diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk
index 1772e71..c8ff4c3 100644
--- a/builds/Resources/Include_bluesim.mk
+++ b/builds/Resources/Include_bluesim.mk
@@ -28,6 +28,7 @@ BSC_C_FLAGS += \
-Xl -v \
-Xc -O1 -Xc++ -O1 \
+
# For Bluespec_2019.05.beta2-debian9stretch-amd64
# you may have to remove the line: -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0
diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 577c182..ea3af92 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -114,6 +114,7 @@ import Trace_Data2 :: *;
interface CoreReq;
method Action start(
+ Bool running,
Addr startpc,
Addr toHostAddr, Addr fromHostAddr
);
@@ -1237,7 +1238,9 @@ module mkCore#(CoreId coreId)(Core);
// Debugger 'halt' request (e.g., GDB '^C' command)
// This is initiated just like an interrupt.
+`ifdef INCLUDE_GDB_CONTROL
renameStage.debug_halt_req;
+`endif
if (show_DM_interactions)
$display ("%0d: %m.rl_debug_halt_req", cur_cycle);
@@ -1327,9 +1330,13 @@ module mkCore#(CoreId coreId)(Core);
interface CoreReq coreReq;
method Action start(
+ Bool running,
Bit#(64) startpc,
Addr toHostAddr, Addr fromHostAddr
);
+`ifdef INCLUDE_GDB_CONTROL
+ if (!running) renameStage.debug_halt_req;
+`endif
fetchStage.start(setAddrUnsafe(almightyCap, startpc)
`ifdef RVFI_DII
, 0
diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv
index 6381749..6a057c9 100644
--- a/src_Core/CPU/MMIOPlatform.bsv
+++ b/src_Core/CPU/MMIOPlatform.bsv
@@ -193,6 +193,10 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
// CRs, we record the AMO resp at processing time
Reg#(MemTaggedData) amoResp <- mkRegU;
+ // For AMOs to the fabric, we end up with read and write responses, and need
+ // to discard the latter. This tracks which of the two we're waiting for.
+ Reg#(Bool) amoWaitWriteResp <- mkRegU;
+
// we increment mtime periodically
Reg#(Bit#(TLog#(CyclesPerTimeInc))) cycle <- mkReg(0);
@@ -836,6 +840,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
let req = MMIOCRq {addr:addr, func:tagged Ld, byteEn:?, data:?};
mmio_fabric_adapter_core_side.request.put (req);
state <= WaitResp;
+ amoWaitWriteResp <= False;
if (verbosity > 0) begin
$display ("MMIOPlatform.rl_mmio_to_fabric_amo_req: addr 0x%0h", addr);
@@ -849,7 +854,11 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
&&& isAmo);
MMIODataPRs dprs <- mmio_fabric_adapter_core_side.response.get;
- if (! dprs.valid) begin
+ if (amoWaitWriteResp) begin
+ // Discard the write response; we're now ready for another request
+ state <= SelectReq;
+ end
+ else if (! dprs.valid) begin
// Access fault
let prs = tagged DataAccess dprs;
cores[reqCore].pRs.enq (prs);
@@ -875,7 +884,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
let prs = tagged DataAccess (MMIODataPRs { valid: True, data: ld_val });
cores[reqCore].pRs.enq (prs);
- state <= SelectReq;
+ // Stay in WaitResp but wait to discard the write response
+ amoWaitWriteResp <= True;
if (verbosity > 1) begin
$display ("MMIO_Platform.rl_mmio_from_fabric_amo_rsp: addr 0x%0h, size %0d, amofunc %0d",
diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv
index d727783..2fbb780 100644
--- a/src_Core/CPU/Proc.bsv
+++ b/src_Core/CPU/Proc.bsv
@@ -233,10 +233,10 @@ module mkProc (Proc_IFC);
// ----------------
// Start the cores running
// Use toHostAddr = 0 if not monitoring tohost
- method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr);
+ method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr);
action
for(Integer i = 0; i < valueof(CoreNum); i = i+1)
- core[i].coreReq.start (startpc, tohostAddr, fromhostAddr);
+ core[i].coreReq.start (running, startpc, tohostAddr, fromhostAddr);
endaction
mmioPlatform.start (tohostAddr, fromhostAddr);
diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv
index a4e62f7..64e2501 100644
--- a/src_Core/CPU/Proc_IFC.bsv
+++ b/src_Core/CPU/Proc_IFC.bsv
@@ -43,7 +43,7 @@ interface Proc_IFC;
// ----------------
// Start the cores running
// Use toHostAddr = 0 if not monitoring tohost
- method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr);
+ method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr);
// ----------------
// SoC fabric connections
diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index cd2a3ba..7d35902 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -200,9 +200,8 @@ module mkCoreW #(Reset dm_power_on_reset)
rule rl_dm_hart0_reset_wait (rg_hart0_reset_delay != 0);
if (rg_hart0_reset_delay == 1) begin
let pc = soc_map_struct.pc_reset_value;
- proc.start (pc, rg_tohost_addr, rg_fromhost_addr);
-
Bool is_running = True;
+ proc.start (is_running, pc, rg_tohost_addr, rg_fromhost_addr);
debug_module.hart0_reset_client.response.put (is_running);
$display ("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h",
cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr);
@@ -398,12 +397,12 @@ module mkCoreW #(Reset dm_power_on_reset)
// ----------------------------------------------------------------
// Start
- method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
+ method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base),
zeroExtend (rangeTop(soc_map.m_plic_addr_range)));
let pc = soc_map_struct.pc_reset_value;
- proc.start (pc, tohost_addr, fromhost_addr);
+ proc.start (is_running, pc, tohost_addr, fromhost_addr);
`ifdef INCLUDE_GDB_CONTROL
// Save for potential future use by rl_dm_hart0_reset
diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv
index f7cfdec..3cf3b97 100644
--- a/src_Core/Core/CoreW_IFC.bsv
+++ b/src_Core/Core/CoreW_IFC.bsv
@@ -61,7 +61,7 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources);
// ----------------------------------------------------------------
// Start
- method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
+ method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
// ----------------------------------------------------------------
// AXI4 Fabric interfaces
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index 6e79f91..876dce6 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -144,7 +144,6 @@ typedef struct {
} Fetch2ToFetch3 deriving(Bits, Eq, FShow);
typedef struct {
- CapMem pc;
CapMem pred_next_pc;
Bool mispred_first_half;
Maybe#(Exception) cause;
@@ -296,8 +295,8 @@ function ActionValue #(Tuple4 #(SupCntX2,
orig_inst: 0,
inst: 0});
MStraddle next_straddle = tagged Invalid;
- // Start parse at parcel 0/1 depending on pc lsbs and pending straddle
- SupCntX2 j = ((getAddr(pc_start) [1:0] == 2'b00 || isValid(pending_straddle)) ? 0 : 1);
+ // Start parse at parcel 0/1 depending on pc lsbs.
+ SupCntX2 j = (getAddr(pc_start) [1:0] == 2'b00 ? 0 : 1);
`ifdef RVFI_DII
j = 0;
`endif
@@ -317,10 +316,10 @@ function ActionValue #(Tuple4 #(SupCntX2,
end
pc = getAddr(s_pc);
inst_kind = Inst_32b;
- orig_inst = { v_x16[0], s_lsbs };
+ orig_inst = { v_x16[j], s_lsbs };
inst = orig_inst;
- j = 1;
- next_pc = getAddr(s_pc) + 4;
+ j = j + 1;
+ next_pc = getAddr(s_pc) + 4;
n_items = 1;
end
else if (is_16b_inst (v_x16 [j])) begin
@@ -427,7 +426,7 @@ module mkFetchStage(FetchStage);
Ehr #(2, MStraddle) ehr_pending_straddle <- mkEhr(tagged Invalid);
// Reg to hold extra instructions from Fetch3 to send to decode the next cycle
Reg #(Vector #(SupSizeX2S1, Inst_Item)) rg_pending_decode <- mkReg(replicate(defaultValue));
- Reg #(SupCntX2S1) rg_pending_n_items <- mkRegU;
+ Reg #(SupCntX2S1) rg_pending_n_items <- mkReg(0);
Reg #(Fetch3ToDecode) rg_pending_f32d <- mkRegU;
// Pipeline Stage FIFOs
@@ -763,7 +762,6 @@ module mkFetchStage(FetchStage);
if (pending_n_items == 0) begin
out = Fetch3ToDecode {
- pc: fetch3In.pc,
pred_next_pc: pred_next_pc,
mispred_first_half: mispred_first_half,
cause: fetch3In.cause,
@@ -813,7 +811,6 @@ module mkFetchStage(FetchStage);
next_pending_n_items = truncate(n_items - fromInteger(valueOf(SupSize)));
rg_pending_decode <= drop(v_items);
rg_pending_f32d <= Fetch3ToDecode {
- pc: v_items[valueOf(SupSize)].pc,
pred_next_pc: out.pred_next_pc,
mispred_first_half: False,
cause: tagged Invalid,
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
index 58f39a4..7f02da0 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
@@ -850,13 +850,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
CapMem fallthrough_pc = addPc(pc, ((orig_inst[1:0] == 2'b11) ? 4 : 2));
-`ifdef INCLUDE_GDB_CONTROL
- if ((i != 0) && (csrf.dcsr_step_bit == 1'b1)) begin
- stop = True;
- debug_step = True;
- end
-`endif
-
// check for wrong path, if wrong path, don't process it, leave to the other rule in next cycle
if(!epochManager.checkEpoch[i].check(main_epoch)) begin
stop = True;
@@ -1124,6 +1117,13 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
if(spec_tag matches tagged Valid .t) begin
spec_bits = spec_bits | (1 << t);
end
+
+`ifdef INCLUDE_GDB_CONTROL
+ if ((i == 0) && (csrf.dcsr_step_bit == 1'b1)) begin
+ stop = True;
+ debug_step = True;
+ end
+`endif
end
end
end
diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile
index cbe69c5..496dae3 100644
--- a/src_SSITH_P3/Makefile
+++ b/src_SSITH_P3/Makefile
@@ -38,12 +38,12 @@ MORE_DEFINES = \
RISCV \
INCLUDE_GDB_CONTROL \
BRVF_TRACE \
- JTAG_TAP
+ XILINX_BSCAN JTAG_TAP
BSC_DEFINES += $(MORE_DEFINES)
BSC_COMPILATION_FLAGS += $(addprefix -D , $(MORE_DEFINES))
# Synth only BSC_COMPILATION_FLAGS
-SYNTH_BSC_OPTIONS = -D XILINX_BSCAN -D XILINX_XCVU9P
+SYNTH_BSC_OPTIONS = -D XILINX_XCVU9P
# Sim only BSC_COMPILATION_FLAGS
SIM_BSC_OPTIONS = -D BSIM
diff --git a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v
index e1880b7..e913064 100644
--- a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v
+++ b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v
@@ -130,17 +130,13 @@ module mkJtagTap(CLK,
// inlined wires
wire [40 : 0] w_dmi_req$wget;
- wire r_dmistat_busy$port1__read,
+ wire r_dmistat_busy$EN_port1__write,
+ r_dmistat_busy$port1__read,
r_dmistat_busy$port2__read,
r_tdo$EN_port0__write,
r_tdo$port0__write_1,
r_tdo$port1__read;
- // register r_dmi
- reg [39 : 0] r_dmi;
- wire [39 : 0] r_dmi$D_IN;
- wire r_dmi$EN;
-
// register r_dmistat_busy
reg r_dmistat_busy;
wire r_dmistat_busy$D_IN, r_dmistat_busy$EN;
@@ -160,11 +156,6 @@ module mkJtagTap(CLK,
wire [17 : 0] r_ir$D_IN;
wire r_ir$EN;
- // register r_state
- reg [3 : 0] r_state;
- wire [3 : 0] r_state$D_IN;
- wire r_state$EN;
-
// register r_tdo
reg r_tdo;
wire r_tdo$D_IN, r_tdo$EN;
@@ -179,6 +170,7 @@ module mkJtagTap(CLK,
// ports of submodule f_dmi_req
wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN;
wire f_dmi_req$dCLR,
+ f_dmi_req$dCLR_RDY,
f_dmi_req$dDEQ,
f_dmi_req$dEMPTY_N,
f_dmi_req$sCLR,
@@ -193,18 +185,32 @@ module mkJtagTap(CLK,
f_dmi_rsp$dDEQ,
f_dmi_rsp$dEMPTY_N,
f_dmi_rsp$sCLR,
+ f_dmi_rsp$sCLR_RDY,
f_dmi_rsp$sENQ,
f_dmi_rsp$sFULL_N;
+ // ports of submodule r_dmi
+ wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT;
+ wire r_dmi$EN;
+
+ // ports of submodule r_initialize
+ wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT;
+
+ // ports of submodule r_initialize2
+ wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT;
+
+ // ports of submodule r_state
+ wire [3 : 0] r_state$D_IN, r_state$Q_OUT;
+ wire r_state$EN;
+
// ports of submodule rst_tck
wire rst_tck$OUT_RST;
// ports of submodule tck_clock
- wire tck_clock$CLK_IN,
- tck_clock$CLK_IN_EN,
- tck_clock$CLK_OUT,
- tck_clock$COND_IN,
- tck_clock$COND_IN_EN;
+ wire tck_clock$IN, tck_clock$OUT;
+
+ // ports of submodule w_tck_crossed
+ wire w_tck_crossed$DOUT;
// rule scheduling signals
wire CAN_FIRE_RL_dmi_request,
@@ -215,7 +221,9 @@ module mkJtagTap(CLK,
CAN_FIRE_RL_dmi_response_ready,
CAN_FIRE_RL_dmi_response_tck,
CAN_FIRE_RL_dmi_start,
- CAN_FIRE_RL_rl_tck,
+ CAN_FIRE_RL_mkConnectionVtoAf,
+ CAN_FIRE_RL_rl_initialize,
+ CAN_FIRE_RL_rl_initialize2,
CAN_FIRE_RL_tick,
CAN_FIRE_dmi_req_ready,
CAN_FIRE_dmi_rsp_data,
@@ -232,7 +240,9 @@ module mkJtagTap(CLK,
WILL_FIRE_RL_dmi_response_ready,
WILL_FIRE_RL_dmi_response_tck,
WILL_FIRE_RL_dmi_start,
- WILL_FIRE_RL_rl_tck,
+ WILL_FIRE_RL_mkConnectionVtoAf,
+ WILL_FIRE_RL_rl_initialize,
+ WILL_FIRE_RL_rl_initialize2,
WILL_FIRE_RL_tick,
WILL_FIRE_dmi_req_ready,
WILL_FIRE_dmi_rsp_data,
@@ -243,24 +253,24 @@ module mkJtagTap(CLK,
WILL_FIRE_jtag_tms;
// remaining internal signals
- reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1,
- v__h2135;
- reg [17 : 0] newir__h3435;
- reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3,
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2;
- wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140,
- v__h2233,
- v__h2601,
- x__h2449,
- x__h2658,
- y__h2659;
- wire [17 : 0] v__h3299, x__h3350, y__h3351;
- wire r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57,
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68,
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72;
+ reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1,
+ v__h2479;
+ reg [17 : 0] newir__h3774;
+ reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3,
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2;
+ wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146,
+ v__h2576,
+ v__h2941,
+ x__h2789,
+ x__h2996,
+ y__h2997;
+ wire [17 : 0] v__h3636, x__h3687, y__h3688;
+ wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63,
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74,
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78;
// oscillator and gates for output clock CLK_jtag_tclk_out
- assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ;
+ assign CLK_jtag_tclk_out = tck_clock$OUT ;
assign CLK_GATE_jtag_tclk_out = 1'b1 ;
// action method jtag_tdi
@@ -311,7 +321,7 @@ module mkJtagTap(CLK,
// submodule f_dmi_busy
FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST),
- .CLK(tck_clock$CLK_OUT),
+ .CLK(tck_clock$OUT),
.ENQ(f_dmi_busy$ENQ),
.DEQ(f_dmi_busy$DEQ),
.CLR(f_dmi_busy$CLR),
@@ -321,7 +331,7 @@ module mkJtagTap(CLK,
// submodule f_dmi_req
SyncFIFOLevel #(.dataWidth(32'd41),
.depth(32'd2),
- .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT),
+ .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT),
.dCLK(CLK),
.sRST(rst_tck$OUT_RST),
.sD_IN(f_dmi_req$sD_IN),
@@ -335,13 +345,13 @@ module mkJtagTap(CLK,
.dCOUNT(),
.sCOUNT(),
.sCLR_RDY(f_dmi_req$sCLR_RDY),
- .dCLR_RDY());
+ .dCLR_RDY(f_dmi_req$dCLR_RDY));
// submodule f_dmi_rsp
SyncFIFOLevel #(.dataWidth(32'd40),
.depth(32'd2),
.indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK),
- .dCLK(tck_clock$CLK_OUT),
+ .dCLK(tck_clock$OUT),
.sRST(RST_N),
.sD_IN(f_dmi_rsp$sD_IN),
.sENQ(f_dmi_rsp$sENQ),
@@ -353,29 +363,46 @@ module mkJtagTap(CLK,
.dEMPTY_N(f_dmi_rsp$dEMPTY_N),
.dCOUNT(),
.sCOUNT(),
- .sCLR_RDY(),
+ .sCLR_RDY(f_dmi_rsp$sCLR_RDY),
.dCLR_RDY(f_dmi_rsp$dCLR_RDY));
+ // submodule r_dmi
+ RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT),
+ .D_IN(r_dmi$D_IN),
+ .EN(r_dmi$EN),
+ .Q_OUT(r_dmi$Q_OUT));
+
+ // submodule r_initialize
+ RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT),
+ .D_IN(r_initialize$D_IN),
+ .EN(r_initialize$EN),
+ .Q_OUT(r_initialize$Q_OUT));
+
+ // submodule r_initialize2
+ RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK),
+ .D_IN(r_initialize2$D_IN),
+ .EN(r_initialize2$EN),
+ .Q_OUT(r_initialize2$Q_OUT));
+
+ // submodule r_state
+ RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT),
+ .D_IN(r_state$D_IN),
+ .EN(r_state$EN),
+ .Q_OUT(r_state$Q_OUT));
+
// submodule rst_tck
- SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT),
- .IN_RST(RST_N),
- .OUT_RST(rst_tck$OUT_RST));
+ SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST));
// submodule tck_clock
- MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK),
- .RST(RST_N),
- .CLK_IN(tck_clock$CLK_IN),
- .COND_IN(tck_clock$COND_IN),
- .CLK_IN_EN(tck_clock$CLK_IN_EN),
- .COND_IN_EN(tck_clock$COND_IN_EN),
- .CLK_VAL_OUT(),
- .COND_OUT(),
- .CLK_GATE_OUT(),
- .CLK_OUT(tck_clock$CLK_OUT));
+ ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT));
- // rule RL_rl_tck
- assign CAN_FIRE_RL_rl_tck = 1'd1 ;
- assign WILL_FIRE_RL_rl_tck = 1'd1 ;
+ // submodule w_tck_crossed
+ SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk),
+ .DOUT(w_tck_crossed$DOUT));
+
+ // rule RL_mkConnectionVtoAf
+ assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ;
+ assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ;
// rule RL_tick
assign CAN_FIRE_RL_tick = 1'd1 ;
@@ -383,7 +410,7 @@ module mkJtagTap(CLK,
// rule RL_dmi_start
assign CAN_FIRE_RL_dmi_start =
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 &&
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 &&
f_dmi_req$sFULL_N &&
f_dmi_busy$FULL_N &&
w_dmi_req$wget[1:0] != 2'd0 ;
@@ -406,9 +433,14 @@ module mkJtagTap(CLK,
f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ;
assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ;
+ // rule RL_rl_initialize
+ assign CAN_FIRE_RL_rl_initialize =
+ r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ;
+ assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ;
+
// rule RL_dmi_reset
assign CAN_FIRE_RL_dmi_reset =
- r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 &&
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 &&
(!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ;
assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ;
@@ -420,35 +452,37 @@ module mkJtagTap(CLK,
assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ;
assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ;
+ // rule RL_rl_initialize2
+ assign CAN_FIRE_RL_rl_initialize2 =
+ f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ;
+ assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ;
+
// inlined wires
assign w_dmi_req$wget = { 1'd0, r_dr } ;
- assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ;
- assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ;
+ assign r_tdo$EN_port0__write =
+ r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ;
+ assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ;
assign r_tdo$port1__read =
r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ;
assign r_dmistat_busy$port1__read =
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 ||
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 ||
r_dmistat_busy ;
+ assign r_dmistat_busy$EN_port1__write =
+ WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ;
assign r_dmistat_busy$port2__read =
- !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ;
-
- // register r_dmi
- assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ;
- assign r_dmi$EN =
- WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 ;
+ !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ;
// register r_dmistat_busy
assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ;
assign r_dmistat_busy$EN = 1'b1 ;
// register r_dr
- always@(r_state or r_dr or v__h2135 or v__h2601)
+ always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941)
begin
- case (r_state)
+ case (r_state$Q_OUT)
4'd0: r_dr$D_IN = r_dr;
- 4'd3: r_dr$D_IN = v__h2135;
- 4'd4: r_dr$D_IN = v__h2601;
+ 4'd3: r_dr$D_IN = v__h2479;
+ 4'd4: r_dr$D_IN = v__h2941;
default: r_dr$D_IN = r_dr;
endcase
end
@@ -456,22 +490,15 @@ module mkJtagTap(CLK,
// register r_drmask
assign r_drmask$D_IN =
- (r_state == 4'd3) ?
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 :
+ (r_state$Q_OUT == 4'd3) ?
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 :
r_drmask ;
assign r_drmask$EN = 1'd1 ;
// register r_ir
- assign r_ir$D_IN = newir__h3435 ;
+ assign r_ir$D_IN = newir__h3774 ;
assign r_ir$EN = 1'd1 ;
- // register r_state
- assign r_state$D_IN =
- jtag_tms ?
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 :
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ;
- assign r_state$EN = 1'd1 ;
-
// register r_tdo
assign r_tdo$D_IN = r_tdo$port1__read ;
assign r_tdo$EN = 1'b1 ;
@@ -479,69 +506,89 @@ module mkJtagTap(CLK,
// submodule f_dmi_busy
assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ;
assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ;
- assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
+ assign f_dmi_busy$CLR =
+ WILL_FIRE_RL_dmi_reset && r_dr[17] ||
+ WILL_FIRE_RL_rl_initialize ;
// submodule f_dmi_req
assign f_dmi_req$sD_IN = w_dmi_req$wget ;
assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ;
assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ;
assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
- assign f_dmi_req$dCLR = 1'b0 ;
+ assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ;
// submodule f_dmi_rsp
assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ;
assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ;
assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ;
- assign f_dmi_rsp$sCLR = 1'b0 ;
+ assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ;
assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
+ // submodule r_dmi
+ assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ;
+ assign r_dmi$EN =
+ WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 ;
+
+ // submodule r_initialize
+ assign r_initialize$D_IN = 1'd0 ;
+ assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ;
+
+ // submodule r_initialize2
+ assign r_initialize2$D_IN = 1'd0 ;
+ assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ;
+
+ // submodule r_state
+ assign r_state$D_IN =
+ jtag_tms ?
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 :
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ;
+ assign r_state$EN = 1'd1 ;
+
// submodule tck_clock
- assign tck_clock$CLK_IN = jtag_tclk ;
- assign tck_clock$COND_IN = 1'b0 ;
- assign tck_clock$CLK_IN_EN = 1'd1 ;
- assign tck_clock$COND_IN_EN = 1'b0 ;
+ assign tck_clock$IN = w_tck_crossed$DOUT ;
// remaining internal signals
- assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 =
+ assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 =
(r_dmistat_busy ||
- r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 &&
f_dmi_busy$EMPTY_N) ?
40'hAAAAAAAAAB :
- r_dmi ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 =
- r_state == 4'd8 && r_ir == 18'b100010100100100100 &&
+ r_dmi$Q_OUT ;
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 =
+ r_state$Q_OUT == 4'd8 && r_ir == 18'b100010100100100100 &&
(r_dr[17] || r_dr[16]) ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 =
- r_state == 4'd8 && r_ir == 18'b000011100100100100 &&
- r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 &&
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 =
+ r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 &&
f_dmi_busy$EMPTY_N ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 =
- r_state == 4'd8 && r_ir == 18'b000011100100100100 &&
- r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 &&
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 =
+ r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 &&
!f_dmi_busy$EMPTY_N ;
- assign v__h2233 = { 22'd960, r_ir } ;
- assign v__h2601 = x__h2658 | y__h2659 ;
- assign v__h3299 = x__h3350 | y__h3351 ;
- assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ;
- assign x__h2658 = { 1'd0, r_dr[39:1] } ;
- assign x__h3350 = { 1'd0, r_ir[17:1] } ;
- assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ;
- assign y__h3351 = jtag_tdi ? 18'd131072 : 18'd0 ;
- always@(r_state or r_ir or v__h3299)
+ assign v__h2576 = { 22'd960, r_ir } ;
+ assign v__h2941 = x__h2996 | y__h2997 ;
+ assign v__h3636 = x__h3687 | y__h3688 ;
+ assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ;
+ assign x__h2996 = { 1'd0, r_dr[39:1] } ;
+ assign x__h3687 = { 1'd0, r_ir[17:1] } ;
+ assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ;
+ assign y__h3688 = jtag_tdi ? 18'd131072 : 18'd0 ;
+ always@(r_state$Q_OUT or r_ir or v__h3636)
begin
- case (r_state)
- 4'd0: newir__h3435 = 18'd1;
- 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir;
- 4'd11: newir__h3435 = v__h3299;
- default: newir__h3435 = r_ir;
+ case (r_state$Q_OUT)
+ 4'd0: newir__h3774 = 18'd1;
+ 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir;
+ 4'd11: newir__h3774 = v__h3636;
+ default: newir__h3774 = r_ir;
endcase
end
always@(r_ir or
- v__h2233 or
- IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 or
- x__h2449)
+ v__h2576 or
+ IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 or
+ x__h2789)
begin
case (r_ir)
18'd0,
@@ -552,18 +599,18 @@ module mkJtagTap(CLK,
18'h00016,
18'h00017,
18'd262143:
- v__h2135 = 40'd0;
- 18'd1: v__h2135 = 40'd4093;
+ v__h2479 = 40'd0;
+ 18'd1: v__h2479 = 40'd4093;
18'b000011100100100100:
- v__h2135 =
- IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140;
- 18'b100010100100100100: v__h2135 = x__h2449;
- default: v__h2135 = v__h2233;
+ v__h2479 =
+ IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146;
+ 18'b100010100100100100: v__h2479 = x__h2789;
+ default: v__h2479 = v__h2576;
endcase
end
- always@(newir__h3435)
+ always@(newir__h3774)
begin
- case (newir__h3435)
+ case (newir__h3774)
18'd0,
18'h00012,
18'h00013,
@@ -572,71 +619,67 @@ module mkJtagTap(CLK,
18'h00016,
18'h00017,
18'd262143:
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1;
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1;
18'd1, 18'b100010100100100100:
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
40'h0080000000;
18'b000011100100100100:
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
40'h8000000000;
- default: CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
+ default: CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
40'h0100000000;
endcase
end
- always@(r_state)
+ always@(r_state$Q_OUT)
begin
- case (r_state)
- 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state;
+ case (r_state$Q_OUT)
+ 4'd0:
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 =
+ r_state$Q_OUT;
4'd1, 4'd8, 4'd15:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2;
- 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9;
- 4'd3, 4'd4:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5;
- 4'd5, 4'd7:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8;
- 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7;
- 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2;
+ 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9;
+ 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5;
+ 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8;
+ 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7;
+ 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0;
4'd10, 4'd11:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12;
4'd12, 4'd14:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15;
- 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15;
+ 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14;
endcase
end
- always@(r_state)
+ always@(r_state$Q_OUT)
begin
- case (r_state)
+ case (r_state$Q_OUT)
4'd0, 4'd1, 4'd8, 4'd15:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1;
- 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1;
+ 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3;
4'd3, 4'd4, 4'd7:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4;
4'd5, 4'd6:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6;
- 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6;
+ 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10;
4'd10, 4'd11, 4'd14:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11;
4'd12, 4'd13:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13;
endcase
end
// handling of inlined registers
- always@(posedge tck_clock$CLK_OUT)
+ always@(posedge tck_clock$OUT)
begin
if (rst_tck$OUT_RST == `BSV_RESET_VALUE)
begin
- r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0;
r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0;
- r_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
- if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN;
if (r_dmistat_busy$EN)
r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN;
- if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN;
end
if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN;
if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN;
@@ -649,12 +692,10 @@ module mkJtagTap(CLK,
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
- r_dmi = 40'hAAAAAAAAAA;
r_dmistat_busy = 1'h0;
r_dr = 40'hAAAAAAAAAA;
r_drmask = 40'hAAAAAAAAAA;
r_ir = 18'h2AAAA;
- r_state = 4'hA;
r_tdo = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
@@ -663,11 +704,11 @@ module mkJtagTap(CLK,
// handling of system tasks
// synopsys translate_off
- always@(negedge tck_clock$CLK_OUT)
+ always@(negedge tck_clock$OUT)
begin
#0;
if (rst_tck$OUT_RST != `BSV_RESET_VALUE)
- if (r_state == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 &&
+ if (r_state$Q_OUT == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 &&
r_ir != 18'h00013 &&
r_ir != 18'h00014 &&
r_ir != 18'h00015 &&
diff --git a/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v
new file mode 100644
index 0000000..65d7430
--- /dev/null
+++ b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v
@@ -0,0 +1,92 @@
+//
+// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
+//
+//
+//
+//
+// Ports:
+// Name I/O size props
+// RST_N_gen_rst O 1 reset
+// CLK I 1 clock
+// RST_N I 1 unused
+//
+// No combinational paths from inputs to outputs
+//
+//
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+ `define BSV_ASSIGNMENT_DELAY
+`endif
+
+`ifdef BSV_POSITIVE_RESET
+ `define BSV_RESET_VALUE 1'b1
+ `define BSV_RESET_EDGE posedge
+`else
+ `define BSV_RESET_VALUE 1'b0
+ `define BSV_RESET_EDGE negedge
+`endif
+
+module mkPowerOnReset(CLK,
+ RST_N,
+
+ RST_N_gen_rst);
+ input CLK;
+ input RST_N;
+
+ // output resets
+ output RST_N_gen_rst;
+
+ // signals for module outputs
+ wire RST_N_gen_rst;
+
+ // ports of submodule ctr
+ wire [7 : 0] ctr$D_IN, ctr$Q_OUT;
+ wire ctr$EN;
+
+ // ports of submodule isInPowerOnReset
+ wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT;
+
+ // ports of submodule rst_ifc
+ wire rst_ifc$OUT;
+
+ // rule scheduling signals
+ wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown;
+
+ // remaining internal signals
+ wire NOT_isInPowerOnReset__read___d5;
+
+ // output resets
+ assign RST_N_gen_rst = rst_ifc$OUT ;
+
+ // submodule ctr
+ RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK),
+ .D_IN(ctr$D_IN),
+ .EN(ctr$EN),
+ .Q_OUT(ctr$Q_OUT));
+
+ // submodule isInPowerOnReset
+ RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK),
+ .D_IN(isInPowerOnReset$D_IN),
+ .EN(isInPowerOnReset$EN),
+ .Q_OUT(isInPowerOnReset$Q_OUT));
+
+ // submodule rst_ifc
+ ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT));
+
+ // rule RL_countDown
+ assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ;
+ assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ;
+
+ // submodule ctr
+ assign ctr$D_IN = ctr$Q_OUT - 8'd1 ;
+ assign ctr$EN = isInPowerOnReset$Q_OUT ;
+
+ // submodule isInPowerOnReset
+ assign isInPowerOnReset$D_IN = 1'd0 ;
+ assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ;
+
+ // remaining internal signals
+ assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ;
+endmodule // mkPowerOnReset
+
diff --git a/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v b/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v
new file mode 100644
index 0000000..4bedc0b
--- /dev/null
+++ b/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v
@@ -0,0 +1,5 @@
+module ASSIGN1(IN, OUT);
+ output OUT;
+ input IN;
+ assign OUT = IN;
+endmodule
diff --git a/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v b/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v
new file mode 100644
index 0000000..1dc1123
--- /dev/null
+++ b/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v
@@ -0,0 +1,87 @@
+
+// Copyright (c) 2000-2012 Bluespec, Inc.
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// $Revision$
+// $Date$
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+ `define BSV_ASSIGNMENT_DELAY
+`endif
+
+`ifdef BSV_POSITIVE_RESET
+ `define BSV_RESET_VALUE 1'b1
+ `define BSV_RESET_EDGE posedge
+`else
+ `define BSV_RESET_VALUE 1'b0
+ `define BSV_RESET_EDGE negedge
+`endif
+
+
+
+module MakeReset0 (
+ CLK,
+ RST,
+ ASSERT_IN,
+ ASSERT_OUT,
+
+ OUT_RST
+ );
+
+ parameter init = 1 ;
+
+ input CLK ;
+ input RST ;
+ input ASSERT_IN ;
+ output ASSERT_OUT ;
+
+ output OUT_RST ;
+
+ reg rst ;
+
+ assign ASSERT_OUT = rst == `BSV_RESET_VALUE ;
+
+ assign OUT_RST = rst ;
+
+ always@(posedge CLK or `BSV_RESET_EDGE RST) begin
+ if (RST == `BSV_RESET_VALUE)
+ rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE;
+ else
+ begin
+ if (ASSERT_IN)
+ rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE;
+ else // if (rst == 1'b0)
+ rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE;
+ end // else: !if(RST == `BSV_RESET_VALUE)
+ end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
+
+
+`ifdef BSV_NO_INITIAL_BLOCKS
+`else // not BSV_NO_INITIAL_BLOCKS
+ // synopsys translate_off
+ initial begin
+ #0 ;
+ rst = ~ `BSV_RESET_VALUE ;
+ end
+ // synopsys translate_on
+`endif // BSV_NO_INITIAL_BLOCKS
+
+endmodule // MakeReset0
diff --git a/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v b/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v
new file mode 100644
index 0000000..9b50bfb
--- /dev/null
+++ b/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v
@@ -0,0 +1,49 @@
+
+// Copyright (c) 2000-2019 Bluespec, Inc.
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// $Revision$
+// $Date$
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+ `define BSV_ASSIGNMENT_DELAY
+`endif
+
+// Basic register with initial value but without reset (not for ASIC synthesis).
+module RegUNInit(CLK, Q_OUT, D_IN, EN);
+
+ parameter width = 1;
+ parameter init = { width {1'b0} } ;
+
+ input CLK;
+ input EN;
+ input [width - 1 : 0] D_IN;
+ output [width - 1 : 0] Q_OUT;
+
+ reg [width - 1 : 0] Q_OUT;
+ initial Q_OUT = init;
+
+ always@(posedge CLK)
+ begin
+ if (EN)
+ Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
+ end
+endmodule
diff --git a/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v b/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v
new file mode 100644
index 0000000..61a23bf
--- /dev/null
+++ b/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v
@@ -0,0 +1,41 @@
+
+// Copyright (c) 2000-2009 Bluespec, Inc.
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// $Revision$
+// $Date$
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+`define BSV_ASSIGNMENT_DELAY
+`endif
+
+
+module SyncWire( DIN, DOUT );
+
+ parameter width = 1;
+
+ input [width - 1 : 0] DIN;
+ output [width - 1 : 0] DOUT;
+
+ assign DOUT = DIN ;
+
+
+endmodule
diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v
index 9cad539..3120e61 100644
--- a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v
+++ b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v
@@ -130,17 +130,13 @@ module mkJtagTap(CLK,
// inlined wires
wire [40 : 0] w_dmi_req$wget;
- wire r_dmistat_busy$port1__read,
+ wire r_dmistat_busy$EN_port1__write,
+ r_dmistat_busy$port1__read,
r_dmistat_busy$port2__read,
r_tdo$EN_port0__write,
r_tdo$port0__write_1,
r_tdo$port1__read;
- // register r_dmi
- reg [39 : 0] r_dmi;
- wire [39 : 0] r_dmi$D_IN;
- wire r_dmi$EN;
-
// register r_dmistat_busy
reg r_dmistat_busy;
wire r_dmistat_busy$D_IN, r_dmistat_busy$EN;
@@ -160,11 +156,6 @@ module mkJtagTap(CLK,
wire [4 : 0] r_ir$D_IN;
wire r_ir$EN;
- // register r_state
- reg [3 : 0] r_state;
- wire [3 : 0] r_state$D_IN;
- wire r_state$EN;
-
// register r_tdo
reg r_tdo;
wire r_tdo$D_IN, r_tdo$EN;
@@ -179,6 +170,7 @@ module mkJtagTap(CLK,
// ports of submodule f_dmi_req
wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN;
wire f_dmi_req$dCLR,
+ f_dmi_req$dCLR_RDY,
f_dmi_req$dDEQ,
f_dmi_req$dEMPTY_N,
f_dmi_req$sCLR,
@@ -193,18 +185,32 @@ module mkJtagTap(CLK,
f_dmi_rsp$dDEQ,
f_dmi_rsp$dEMPTY_N,
f_dmi_rsp$sCLR,
+ f_dmi_rsp$sCLR_RDY,
f_dmi_rsp$sENQ,
f_dmi_rsp$sFULL_N;
+ // ports of submodule r_dmi
+ wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT;
+ wire r_dmi$EN;
+
+ // ports of submodule r_initialize
+ wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT;
+
+ // ports of submodule r_initialize2
+ wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT;
+
+ // ports of submodule r_state
+ wire [3 : 0] r_state$D_IN, r_state$Q_OUT;
+ wire r_state$EN;
+
// ports of submodule rst_tck
wire rst_tck$OUT_RST;
// ports of submodule tck_clock
- wire tck_clock$CLK_IN,
- tck_clock$CLK_IN_EN,
- tck_clock$CLK_OUT,
- tck_clock$COND_IN,
- tck_clock$COND_IN_EN;
+ wire tck_clock$IN, tck_clock$OUT;
+
+ // ports of submodule w_tck_crossed
+ wire w_tck_crossed$DOUT;
// rule scheduling signals
wire CAN_FIRE_RL_dmi_request,
@@ -215,7 +221,9 @@ module mkJtagTap(CLK,
CAN_FIRE_RL_dmi_response_ready,
CAN_FIRE_RL_dmi_response_tck,
CAN_FIRE_RL_dmi_start,
- CAN_FIRE_RL_rl_tck,
+ CAN_FIRE_RL_mkConnectionVtoAf,
+ CAN_FIRE_RL_rl_initialize,
+ CAN_FIRE_RL_rl_initialize2,
CAN_FIRE_RL_tick,
CAN_FIRE_dmi_req_ready,
CAN_FIRE_dmi_rsp_data,
@@ -232,7 +240,9 @@ module mkJtagTap(CLK,
WILL_FIRE_RL_dmi_response_ready,
WILL_FIRE_RL_dmi_response_tck,
WILL_FIRE_RL_dmi_start,
- WILL_FIRE_RL_rl_tck,
+ WILL_FIRE_RL_mkConnectionVtoAf,
+ WILL_FIRE_RL_rl_initialize,
+ WILL_FIRE_RL_rl_initialize2,
WILL_FIRE_RL_tick,
WILL_FIRE_dmi_req_ready,
WILL_FIRE_dmi_rsp_data,
@@ -243,24 +253,24 @@ module mkJtagTap(CLK,
WILL_FIRE_jtag_tms;
// remaining internal signals
- reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1,
- v__h2135;
- reg [4 : 0] newir__h3435;
- reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3,
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2;
- wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140,
- v__h2233,
- v__h2601,
- x__h2449,
- x__h2658,
- y__h2659;
- wire [4 : 0] v__h3299, x__h3350, y__h3351;
- wire r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57,
- r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68,
- r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72;
+ reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1,
+ v__h2479;
+ reg [4 : 0] newir__h3774;
+ reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3,
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2;
+ wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146,
+ v__h2576,
+ v__h2941,
+ x__h2789,
+ x__h2996,
+ y__h2997;
+ wire [4 : 0] v__h3636, x__h3687, y__h3688;
+ wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63,
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74,
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78;
// oscillator and gates for output clock CLK_jtag_tclk_out
- assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ;
+ assign CLK_jtag_tclk_out = tck_clock$OUT ;
assign CLK_GATE_jtag_tclk_out = 1'b1 ;
// action method jtag_tdi
@@ -311,7 +321,7 @@ module mkJtagTap(CLK,
// submodule f_dmi_busy
FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST),
- .CLK(tck_clock$CLK_OUT),
+ .CLK(tck_clock$OUT),
.ENQ(f_dmi_busy$ENQ),
.DEQ(f_dmi_busy$DEQ),
.CLR(f_dmi_busy$CLR),
@@ -321,7 +331,7 @@ module mkJtagTap(CLK,
// submodule f_dmi_req
SyncFIFOLevel #(.dataWidth(32'd41),
.depth(32'd2),
- .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT),
+ .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT),
.dCLK(CLK),
.sRST(rst_tck$OUT_RST),
.sD_IN(f_dmi_req$sD_IN),
@@ -335,13 +345,13 @@ module mkJtagTap(CLK,
.dCOUNT(),
.sCOUNT(),
.sCLR_RDY(f_dmi_req$sCLR_RDY),
- .dCLR_RDY());
+ .dCLR_RDY(f_dmi_req$dCLR_RDY));
// submodule f_dmi_rsp
SyncFIFOLevel #(.dataWidth(32'd40),
.depth(32'd2),
.indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK),
- .dCLK(tck_clock$CLK_OUT),
+ .dCLK(tck_clock$OUT),
.sRST(RST_N),
.sD_IN(f_dmi_rsp$sD_IN),
.sENQ(f_dmi_rsp$sENQ),
@@ -353,29 +363,46 @@ module mkJtagTap(CLK,
.dEMPTY_N(f_dmi_rsp$dEMPTY_N),
.dCOUNT(),
.sCOUNT(),
- .sCLR_RDY(),
+ .sCLR_RDY(f_dmi_rsp$sCLR_RDY),
.dCLR_RDY(f_dmi_rsp$dCLR_RDY));
+ // submodule r_dmi
+ RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT),
+ .D_IN(r_dmi$D_IN),
+ .EN(r_dmi$EN),
+ .Q_OUT(r_dmi$Q_OUT));
+
+ // submodule r_initialize
+ RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT),
+ .D_IN(r_initialize$D_IN),
+ .EN(r_initialize$EN),
+ .Q_OUT(r_initialize$Q_OUT));
+
+ // submodule r_initialize2
+ RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK),
+ .D_IN(r_initialize2$D_IN),
+ .EN(r_initialize2$EN),
+ .Q_OUT(r_initialize2$Q_OUT));
+
+ // submodule r_state
+ RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT),
+ .D_IN(r_state$D_IN),
+ .EN(r_state$EN),
+ .Q_OUT(r_state$Q_OUT));
+
// submodule rst_tck
- SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT),
- .IN_RST(RST_N),
- .OUT_RST(rst_tck$OUT_RST));
+ SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST));
// submodule tck_clock
- MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK),
- .RST(RST_N),
- .CLK_IN(tck_clock$CLK_IN),
- .COND_IN(tck_clock$COND_IN),
- .CLK_IN_EN(tck_clock$CLK_IN_EN),
- .COND_IN_EN(tck_clock$COND_IN_EN),
- .CLK_VAL_OUT(),
- .COND_OUT(),
- .CLK_GATE_OUT(),
- .CLK_OUT(tck_clock$CLK_OUT));
+ ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT));
- // rule RL_rl_tck
- assign CAN_FIRE_RL_rl_tck = 1'd1 ;
- assign WILL_FIRE_RL_rl_tck = 1'd1 ;
+ // submodule w_tck_crossed
+ SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk),
+ .DOUT(w_tck_crossed$DOUT));
+
+ // rule RL_mkConnectionVtoAf
+ assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ;
+ assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ;
// rule RL_tick
assign CAN_FIRE_RL_tick = 1'd1 ;
@@ -383,7 +410,7 @@ module mkJtagTap(CLK,
// rule RL_dmi_start
assign CAN_FIRE_RL_dmi_start =
- r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72 &&
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78 &&
f_dmi_req$sFULL_N &&
f_dmi_busy$FULL_N &&
w_dmi_req$wget[1:0] != 2'd0 ;
@@ -406,9 +433,14 @@ module mkJtagTap(CLK,
f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ;
assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ;
+ // rule RL_rl_initialize
+ assign CAN_FIRE_RL_rl_initialize =
+ r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ;
+ assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ;
+
// rule RL_dmi_reset
assign CAN_FIRE_RL_dmi_reset =
- r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57 &&
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63 &&
(!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ;
assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ;
@@ -420,35 +452,37 @@ module mkJtagTap(CLK,
assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ;
assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ;
+ // rule RL_rl_initialize2
+ assign CAN_FIRE_RL_rl_initialize2 =
+ f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ;
+ assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ;
+
// inlined wires
assign w_dmi_req$wget = { 1'd0, r_dr } ;
- assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ;
- assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ;
+ assign r_tdo$EN_port0__write =
+ r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ;
+ assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ;
assign r_tdo$port1__read =
r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ;
assign r_dmistat_busy$port1__read =
- r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68 ||
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74 ||
r_dmistat_busy ;
+ assign r_dmistat_busy$EN_port1__write =
+ WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ;
assign r_dmistat_busy$port2__read =
- !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ;
-
- // register r_dmi
- assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ;
- assign r_dmi$EN =
- WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 ;
+ !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ;
// register r_dmistat_busy
assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ;
assign r_dmistat_busy$EN = 1'b1 ;
// register r_dr
- always@(r_state or r_dr or v__h2135 or v__h2601)
+ always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941)
begin
- case (r_state)
+ case (r_state$Q_OUT)
4'd0: r_dr$D_IN = r_dr;
- 4'd3: r_dr$D_IN = v__h2135;
- 4'd4: r_dr$D_IN = v__h2601;
+ 4'd3: r_dr$D_IN = v__h2479;
+ 4'd4: r_dr$D_IN = v__h2941;
default: r_dr$D_IN = r_dr;
endcase
end
@@ -456,22 +490,15 @@ module mkJtagTap(CLK,
// register r_drmask
assign r_drmask$D_IN =
- (r_state == 4'd3) ?
- CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 :
+ (r_state$Q_OUT == 4'd3) ?
+ CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 :
r_drmask ;
assign r_drmask$EN = 1'd1 ;
// register r_ir
- assign r_ir$D_IN = newir__h3435 ;
+ assign r_ir$D_IN = newir__h3774 ;
assign r_ir$EN = 1'd1 ;
- // register r_state
- assign r_state$D_IN =
- jtag_tms ?
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 :
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ;
- assign r_state$EN = 1'd1 ;
-
// register r_tdo
assign r_tdo$D_IN = r_tdo$port1__read ;
assign r_tdo$EN = 1'b1 ;
@@ -479,146 +506,165 @@ module mkJtagTap(CLK,
// submodule f_dmi_busy
assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ;
assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ;
- assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
+ assign f_dmi_busy$CLR =
+ WILL_FIRE_RL_dmi_reset && r_dr[17] ||
+ WILL_FIRE_RL_rl_initialize ;
// submodule f_dmi_req
assign f_dmi_req$sD_IN = w_dmi_req$wget ;
assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ;
assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ;
assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
- assign f_dmi_req$dCLR = 1'b0 ;
+ assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ;
// submodule f_dmi_rsp
assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ;
assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ;
assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ;
- assign f_dmi_rsp$sCLR = 1'b0 ;
+ assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ;
assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
+ // submodule r_dmi
+ assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ;
+ assign r_dmi$EN =
+ WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 ;
+
+ // submodule r_initialize
+ assign r_initialize$D_IN = 1'd0 ;
+ assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ;
+
+ // submodule r_initialize2
+ assign r_initialize2$D_IN = 1'd0 ;
+ assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ;
+
+ // submodule r_state
+ assign r_state$D_IN =
+ jtag_tms ?
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 :
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ;
+ assign r_state$EN = 1'd1 ;
+
// submodule tck_clock
- assign tck_clock$CLK_IN = jtag_tclk ;
- assign tck_clock$COND_IN = 1'b0 ;
- assign tck_clock$CLK_IN_EN = 1'd1 ;
- assign tck_clock$COND_IN_EN = 1'b0 ;
+ assign tck_clock$IN = w_tck_crossed$DOUT ;
// remaining internal signals
- assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 =
+ assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 =
(r_dmistat_busy ||
- r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 &&
f_dmi_busy$EMPTY_N) ?
40'hAAAAAAAAAB :
- r_dmi ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57 =
- r_state == 4'd8 && r_ir == 5'h10 && (r_dr[17] || r_dr[16]) ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68 =
- r_state == 4'd8 && r_ir == 5'h11 && r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 &&
+ r_dmi$Q_OUT ;
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63 =
+ r_state$Q_OUT == 4'd8 && r_ir == 5'h10 &&
+ (r_dr[17] || r_dr[16]) ;
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74 =
+ r_state$Q_OUT == 4'd8 && r_ir == 5'h11 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 &&
f_dmi_busy$EMPTY_N ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72 =
- r_state == 4'd8 && r_ir == 5'h11 && r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 &&
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78 =
+ r_state$Q_OUT == 4'd8 && r_ir == 5'h11 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 &&
!f_dmi_busy$EMPTY_N ;
- assign v__h2233 = { 35'd7864320, r_ir } ;
- assign v__h2601 = x__h2658 | y__h2659 ;
- assign v__h3299 = x__h3350 | y__h3351 ;
- assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ;
- assign x__h2658 = { 1'd0, r_dr[39:1] } ;
- assign x__h3350 = { 1'd0, r_ir[4:1] } ;
- assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ;
- assign y__h3351 = jtag_tdi ? 5'd16 : 5'd0 ;
- always@(r_state or r_ir or v__h3299)
+ assign v__h2576 = { 35'd7864320, r_ir } ;
+ assign v__h2941 = x__h2996 | y__h2997 ;
+ assign v__h3636 = x__h3687 | y__h3688 ;
+ assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ;
+ assign x__h2996 = { 1'd0, r_dr[39:1] } ;
+ assign x__h3687 = { 1'd0, r_ir[4:1] } ;
+ assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ;
+ assign y__h3688 = jtag_tdi ? 5'd16 : 5'd0 ;
+ always@(r_state$Q_OUT or r_ir or v__h3636)
begin
- case (r_state)
- 4'd0: newir__h3435 = 5'd1;
- 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir;
- 4'd11: newir__h3435 = v__h3299;
- default: newir__h3435 = r_ir;
+ case (r_state$Q_OUT)
+ 4'd0: newir__h3774 = 5'd1;
+ 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir;
+ 4'd11: newir__h3774 = v__h3636;
+ default: newir__h3774 = r_ir;
endcase
end
always@(r_ir or
- v__h2233 or
- x__h2449 or
- IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140)
+ v__h2576 or
+ x__h2789 or
+ IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146)
begin
case (r_ir)
- 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: v__h2135 = 40'd0;
- 5'd1: v__h2135 = 40'd4093;
- 5'h10: v__h2135 = x__h2449;
+ 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: v__h2479 = 40'd0;
+ 5'd1: v__h2479 = 40'd4093;
+ 5'h10: v__h2479 = x__h2789;
5'h11:
- v__h2135 =
- IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140;
- default: v__h2135 = v__h2233;
+ v__h2479 =
+ IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146;
+ default: v__h2479 = v__h2576;
endcase
end
- always@(newir__h3435)
+ always@(newir__h3774)
begin
- case (newir__h3435)
+ case (newir__h3774)
5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31:
- CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'd1;
+ CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'd1;
5'd1, 5'h10:
- CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 =
+ CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 =
40'h0080000000;
5'h11:
- CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 =
+ CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 =
40'h8000000000;
- default: CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 =
+ default: CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 =
40'h0100000000;
endcase
end
- always@(r_state)
+ always@(r_state$Q_OUT)
begin
- case (r_state)
- 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state;
+ case (r_state$Q_OUT)
+ 4'd0:
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 =
+ r_state$Q_OUT;
4'd1, 4'd8, 4'd15:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2;
- 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9;
- 4'd3, 4'd4:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5;
- 4'd5, 4'd7:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8;
- 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7;
- 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2;
+ 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9;
+ 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5;
+ 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8;
+ 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7;
+ 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0;
4'd10, 4'd11:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12;
4'd12, 4'd14:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15;
- 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15;
+ 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14;
endcase
end
- always@(r_state)
+ always@(r_state$Q_OUT)
begin
- case (r_state)
+ case (r_state$Q_OUT)
4'd0, 4'd1, 4'd8, 4'd15:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1;
- 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1;
+ 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3;
4'd3, 4'd4, 4'd7:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4;
4'd5, 4'd6:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6;
- 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6;
+ 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10;
4'd10, 4'd11, 4'd14:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11;
4'd12, 4'd13:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13;
endcase
end
// handling of inlined registers
- always@(posedge tck_clock$CLK_OUT)
+ always@(posedge tck_clock$OUT)
begin
if (rst_tck$OUT_RST == `BSV_RESET_VALUE)
begin
- r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0;
r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0;
- r_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
- if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN;
if (r_dmistat_busy$EN)
r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN;
- if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN;
end
if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN;
if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN;
@@ -631,12 +677,10 @@ module mkJtagTap(CLK,
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
- r_dmi = 40'hAAAAAAAAAA;
r_dmistat_busy = 1'h0;
r_dr = 40'hAAAAAAAAAA;
r_drmask = 40'hAAAAAAAAAA;
r_ir = 5'h0A;
- r_state = 4'hA;
r_tdo = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
@@ -645,11 +689,12 @@ module mkJtagTap(CLK,
// handling of system tasks
// synopsys translate_off
- always@(negedge tck_clock$CLK_OUT)
+ always@(negedge tck_clock$OUT)
begin
#0;
if (rst_tck$OUT_RST != `BSV_RESET_VALUE)
- if (r_state == 4'd3 && r_ir != 5'd0 && r_ir != 5'h12 && r_ir != 5'h13 &&
+ if (r_state$Q_OUT == 4'd3 && r_ir != 5'd0 && r_ir != 5'h12 &&
+ r_ir != 5'h13 &&
r_ir != 5'h14 &&
r_ir != 5'h15 &&
r_ir != 5'h16 &&
diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v
new file mode 100644
index 0000000..65d7430
--- /dev/null
+++ b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v
@@ -0,0 +1,92 @@
+//
+// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
+//
+//
+//
+//
+// Ports:
+// Name I/O size props
+// RST_N_gen_rst O 1 reset
+// CLK I 1 clock
+// RST_N I 1 unused
+//
+// No combinational paths from inputs to outputs
+//
+//
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+ `define BSV_ASSIGNMENT_DELAY
+`endif
+
+`ifdef BSV_POSITIVE_RESET
+ `define BSV_RESET_VALUE 1'b1
+ `define BSV_RESET_EDGE posedge
+`else
+ `define BSV_RESET_VALUE 1'b0
+ `define BSV_RESET_EDGE negedge
+`endif
+
+module mkPowerOnReset(CLK,
+ RST_N,
+
+ RST_N_gen_rst);
+ input CLK;
+ input RST_N;
+
+ // output resets
+ output RST_N_gen_rst;
+
+ // signals for module outputs
+ wire RST_N_gen_rst;
+
+ // ports of submodule ctr
+ wire [7 : 0] ctr$D_IN, ctr$Q_OUT;
+ wire ctr$EN;
+
+ // ports of submodule isInPowerOnReset
+ wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT;
+
+ // ports of submodule rst_ifc
+ wire rst_ifc$OUT;
+
+ // rule scheduling signals
+ wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown;
+
+ // remaining internal signals
+ wire NOT_isInPowerOnReset__read___d5;
+
+ // output resets
+ assign RST_N_gen_rst = rst_ifc$OUT ;
+
+ // submodule ctr
+ RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK),
+ .D_IN(ctr$D_IN),
+ .EN(ctr$EN),
+ .Q_OUT(ctr$Q_OUT));
+
+ // submodule isInPowerOnReset
+ RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK),
+ .D_IN(isInPowerOnReset$D_IN),
+ .EN(isInPowerOnReset$EN),
+ .Q_OUT(isInPowerOnReset$Q_OUT));
+
+ // submodule rst_ifc
+ ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT));
+
+ // rule RL_countDown
+ assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ;
+ assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ;
+
+ // submodule ctr
+ assign ctr$D_IN = ctr$Q_OUT - 8'd1 ;
+ assign ctr$EN = isInPowerOnReset$Q_OUT ;
+
+ // submodule isInPowerOnReset
+ assign isInPowerOnReset$D_IN = 1'd0 ;
+ assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ;
+
+ // remaining internal signals
+ assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ;
+endmodule // mkPowerOnReset
+
diff --git a/src_SSITH_P3/src_BSV/ClockHacks.bsv b/src_SSITH_P3/src_BSV/ClockHacks.bsv
new file mode 100644
index 0000000..dde2445
--- /dev/null
+++ b/src_SSITH_P3/src_BSV/ClockHacks.bsv
@@ -0,0 +1,117 @@
+
+package ClockHacks;
+
+import Clocks ::*;
+import Connectable ::*;
+
+(* always_ready, always_enabled *)
+interface OutputBit;
+ method Bit#(1) out;
+endinterface
+
+import "BVI" ASSIGN1 =
+module packClock#(Clock clk)(OutputBit);
+
+ default_clock no_clock;
+ default_reset no_reset;
+
+ input_clock clk(IN) = clk;
+
+ method OUT out;
+
+ schedule (out) CF (out);
+
+endmodule
+
+import "BVI" ASSIGN1 =
+module packReset#(Reset rst)(OutputBit);
+
+ default_clock no_clock;
+ default_reset no_reset;
+
+ input_reset rst(IN) = rst;
+
+ method OUT out reset_by(rst);
+
+ schedule (out) CF (out);
+
+endmodule
+
+(* always_ready, always_enabled *)
+interface UnpackedClock;
+ interface Clock clk;
+ method Action in(Bit#(1) x);
+endinterface
+
+import "BVI" ASSIGN1 =
+module unpackClock(UnpackedClock);
+
+ default_clock no_clock;
+ default_reset no_reset;
+
+ output_clock clk(OUT);
+
+ method in(IN) enable((*inhigh*)en) clocked_by(clk);
+
+ schedule (in) CF (in);
+
+endmodule
+
+(* always_ready, always_enabled *)
+interface UnpackedReset;
+ interface Reset rst;
+ method Action in(Bit#(1) x);
+endinterface
+
+import "BVI" ASSIGN1 =
+module unpackReset#(Clock clk)(UnpackedReset);
+
+ default_clock no_clock;
+ default_reset no_reset;
+
+ input_clock clk() = clk;
+ output_reset rst(OUT);
+
+ method in(IN) enable((*inhigh*)en) clocked_by(clk) reset_by(rst);
+
+ schedule (in) CF (in);
+
+endmodule
+
+////////////////////
+
+interface BlockIfc;
+ interface Clock clk;
+ interface Reset rst;
+endinterface
+
+module mkBlock(BlockIfc);
+ let default_clock <- exposeCurrentClock;
+ let default_reset <- exposeCurrentReset;
+
+ interface clk = default_clock;
+ interface rst = default_reset;
+endmodule
+
+module mkTop(Empty);
+
+ let clk_unpack <- unpackClock;
+ let clk = clk_unpack.clk;
+
+ let rst_unpack <- unpackReset(clk);
+ let rst = rst_unpack.rst;
+
+ let a <- mkBlock(clocked_by clk, reset_by rst);
+ let b <- mkBlock(clocked_by clk, reset_by rst);
+
+ let clk_pack <- packClock(b.clk, clocked_by clk);
+ let rst_pack <- packReset(b.rst, clocked_by clk);
+
+ mkConnection(clk_unpack.in, clk_pack.out);
+ mkConnection(rst_unpack.in, rst_pack.out);
+
+endmodule
+
+////////////////////
+
+endpackage : ClockHacks
diff --git a/src_SSITH_P3/src_BSV/JtagTap.bsv b/src_SSITH_P3/src_BSV/JtagTap.bsv
index fe68d51..1efe670 100644
--- a/src_SSITH_P3/src_BSV/JtagTap.bsv
+++ b/src_SSITH_P3/src_BSV/JtagTap.bsv
@@ -3,11 +3,14 @@ package JtagTap;
import BUtils ::*;
import Clocks ::*;
+import Connectable ::*;
import DefaultValue ::*;
import FIFOF ::*;
import FIFOLevel ::*;
import Reserved ::*;
+import PowerOnReset ::*;
+import ClockHacks ::*;
import Giraffe_IFC ::*;
typedef 6 ABITS;
@@ -16,6 +19,10 @@ typedef 6 ABITS;
typedef 6 IR_LENGTH;
`elsif XILINX_XCVU9P
typedef 18 IR_LENGTH;
+`elsif XILINX_XC7K325T
+typedef 6 IR_LENGTH;
+`else
+typedef 5 IR_LENGTH;
`endif
`else
typedef 5 IR_LENGTH;
@@ -34,6 +41,12 @@ Bit#(IR_LENGTH) ir_dtmcs = 'b100010100100100100; // USER3
// 'b000010100100100100; USER1
Bit#(IR_LENGTH) ir_dmi = 'b000011100100100100;
+`elsif XILINX_XC7K325T
+Bit#(IR_LENGTH) ir_dtmcs = 'h22;
+Bit#(IR_LENGTH) ir_dmi = 'h03;
+`else
+Bit#(IR_LENGTH) ir_dtmcs = 'h10;
+Bit#(IR_LENGTH) ir_dmi = 'h11;
`endif
`else
Bit#(IR_LENGTH) ir_dtmcs = 'h10;
@@ -176,15 +189,12 @@ module mkJtagTap(JtagTap_IFC);
Wire#(Bit#(1)) w_tck <- mkDWire(?);
- let tck_clock <- mkUngatedClock(?);
- let tck = tck_clock.new_clk;
+ let tck_clock <- unpackClock;
+ let tck = tck_clock.clk;
+ let w_tck_crossed <- mkNullCrossing(tck, w_tck);
+ mkConnection(w_tck_crossed, tck_clock.in);
- (* no_implicit_conditions, fire_when_enabled *)
- rule rl_tck;
- tck_clock.setClockValue(w_tck);
- endrule
-
- let rst_tck <- mkAsyncResetFromCR(4, tck);
+ let rst_tck <- mkAsyncResetFromCR(0, tck); // value independent of tck
Wire#(Bit#(1)) w_tms <- mkDWire(?, clocked_by tck, reset_by rst_tck);
Wire#(Bit#(1)) w_tdi <- mkDWire(?, clocked_by tck, reset_by rst_tck);
@@ -201,13 +211,16 @@ module mkJtagTap(JtagTap_IFC);
Array#(Reg#(Bit#(1))) r_tdo <- mkCRegU(2, clocked_by tck, reset_by rst_tck);
- Reg#(JtagState) r_state <- mkReg(TEST_LOGIC_RESET, clocked_by tck, reset_by rst_tck);
+ Reg#(JtagState) r_state <- mkRegUNInit(TEST_LOGIC_RESET, clocked_by tck, reset_by rst_tck);
+ Reg#(Bool) r_initialize <- mkRegUNInit(True, clocked_by tck, reset_by rst_tck);
+ Reg#(Bool) r_initialize2 <- mkRegUNInit(True);
+ PulseWire w_initialize <- mkPulseWire( clocked_by tck, reset_by rst_tck);
Reg#(Bit#(IR_LENGTH)) r_ir <- mkRegU(clocked_by tck, reset_by rst_tck);
Reg#(Bit#(DR_LENGTH)) r_dr <- mkRegU(clocked_by tck, reset_by rst_tck);
Reg#(Bit#(DR_LENGTH)) r_drmask <- mkRegU(clocked_by tck, reset_by rst_tck);
- Reg#(DMI) r_dmi <- mkReg(defaultValue, clocked_by tck, reset_by rst_tck);
+ Reg#(DMI) r_dmi <- mkRegUNInit(defaultValue, clocked_by tck, reset_by rst_tck);
Wire#(Tuple3#(Bit#(7),Bit#(32),Bit#(2))) w_dmi_req <- mkWire(clocked_by tck, reset_by rst_tck);
SyncFIFOLevelIfc#(Tuple3#(Bit#(7),Bit#(32),Bit#(2)), 2) f_dmi_req <- mkSyncFIFOLevel(tck, rst_tck, clk);
@@ -216,6 +229,19 @@ module mkJtagTap(JtagTap_IFC);
Array#(Reg#(Bool)) r_dmistat_busy <- mkCReg(2, False, clocked_by tck, reset_by rst_tck);
SyncFIFOLevelIfc#(DMI, 2) f_dmi_rsp <- mkSyncFIFOLevel(clk, rst, tck);
+ rule rl_initialize2(r_initialize2);
+ r_initialize2 <= False;
+
+ f_dmi_req.dClear;
+ f_dmi_rsp.sClear;
+ endrule
+
+ (* no_implicit_conditions, fire_when_enabled *)
+ rule rl_initialize(w_initialize);
+ f_dmi_busy.clear;
+ r_dmistat_busy[1] <= False;
+ endrule
+
(* no_implicit_conditions, fire_when_enabled *)
rule tick;
let newir = r_ir;
@@ -224,6 +250,10 @@ module mkJtagTap(JtagTap_IFC);
if (r_state == TEST_LOGIC_RESET) begin
newir = ir_idcode;
+ if (r_initialize) begin
+ r_initialize <= False;
+ w_initialize.send();
+ end
end
else if (r_state == CAPTURE_DR) begin
if (newir == ir_bypass0 ||
diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv
index bc33d6c..6fb6d87 100644
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -41,6 +41,7 @@ import Cur_Cycle :: *;
import SoC_Map :: *;
import Fabric_Defs :: *;
+import PowerOnReset :: *;
// The basic core
import CoreW_IFC :: *;
@@ -123,8 +124,11 @@ module mkP3_Core (P3_Core_IFC);
// its reset down from here.
// (power-on reset) and the Debug Module's 'hart_reset' control.
+ let default_reset <- exposeCurrentReset();
- let power_on_reset <- exposeCurrentReset;
+ let por_ifc <- mkPowerOnReset();
+ let power_on_reset = por_ifc.gen_rst; // This line and the next
+ //let power_on_reset <- default_reset; //are alternatives.
let dm_power_on_reset = power_on_reset;
// The rest of the system (corew minus the Debug Module) are reset:
@@ -133,13 +137,24 @@ module mkP3_Core (P3_Core_IFC);
`ifdef INCLUDE_GDB_CONTROL
let clk <- exposeCurrentClock;
- Bool initial_reset_val = False;
+ // Setting initial_reset_val to True ensures that if the mkReset is itself in
+ // reset (controlled by mkP3_Core's default reset), its output reset will be
+ // asserted. Thus ndm_reset will be asserted if any of
+ // power_on_reset, default_reset, ndm_reset from debug module
+ // is asserted.
+
+ // Currently initial_reset_val=False -- thus ndm_reset will be asserted only
+ // if any of
+ // power_on_reset, ndm_reset from debug module
+ // is asserted.
+ Bool initial_reset_val = False; // was True;
Integer ndm_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for NDM
let ndm_reset_controller <- mkReset(ndm_reset_duration, initial_reset_val, clk);
let ndm_reset <- mkResetEither (power_on_reset, ndm_reset_controller.new_rst);
`else
- let ndm_reset = power_on_reset;
+ let rstn <- exposeCurrentReset;
+ let ndm_reset <- mkResetEither (power_on_reset, rstn);
`endif
// ================================================================
@@ -167,11 +182,13 @@ module mkP3_Core (P3_Core_IFC);
// NDM reset (reset for non-DebugModule)
Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0);
+ Reg #(Bool) rg_running <- mkRegU;
// Get an NDM-reset request from the Debug Module, assert ndm-reset,
// and then wait for a suitable delay.
rule rl_ndm_reset (rg_ndm_reset_delay == 0);
let x <- corew.ndm_reset_client.request.get;
+ rg_running <= x;
ndm_reset_controller.assertReset;
rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 100); // NOTE: heuristic
@@ -182,9 +199,9 @@ module mkP3_Core (P3_Core_IFC);
// Wait for suitable delay, then send ack response to Debug Module for NDM-reset request
rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0);
if (rg_ndm_reset_delay == 1) begin
- Bool is_running = True;
+ Bool is_running = rg_running;
// Restart the corew
- corew.start (0, 0);
+ corew.start (rg_running, 0, 0);
corew.ndm_reset_client.response.put (is_running);
$display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module",
cur_cycle);
@@ -193,11 +210,13 @@ module mkP3_Core (P3_Core_IFC);
endrule
// ================================================================
- // Start the corew after a PoR
- Reg #(Bool) rg_corew_start_after_por <- mkReg(False);
- rule rl_step_0 (!rg_corew_start_after_por);
- corew.start (0, 0);
- rg_corew_start_after_por <= True;
+ // Start the corew a suitable time after a PoR
+ UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew
+ Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait);
+ rule rl_step_0 (rg_corew_start_after_por != 0);
+ let n = rg_corew_start_after_por - 1;
+ rg_corew_start_after_por <= n;
+ if (n==0) corew.start (True, 0, 0); // initial start leaves proc running
endrule
// ================================================================
@@ -219,7 +238,7 @@ module mkP3_Core (P3_Core_IFC);
BusSender#(Tuple2#(Bit#(32),Bit#(2))) bus_dmi_rsp <- mkBusSender(unpack(0));
`ifdef JTAG_TAP
- let jtagtap <- mkJtagTap;
+ let jtagtap <- mkJtagTap(reset_by power_on_reset);
mkConnection(jtagtap.dmi.req_ready, pack(bus_dmi_req.in.ready));
mkConnection(jtagtap.dmi.req_valid, compose(bus_dmi_req.in.valid, unpack));
diff --git a/src_SSITH_P3/src_BSV/PowerOnReset.bsv b/src_SSITH_P3/src_BSV/PowerOnReset.bsv
new file mode 100644
index 0000000..30bafe2
--- /dev/null
+++ b/src_SSITH_P3/src_BSV/PowerOnReset.bsv
@@ -0,0 +1,51 @@
+package PowerOnReset;
+
+import Clocks::*;
+
+UInt#(8) resetCycles = 10;
+
+import "BVI" RegUNInit =
+module mkRegUNInit#(parameter a init) (Reg#(a))
+ provisos (Bits#(a,sa));
+
+ parameter width = valueOf(sa);
+ parameter init = pack(init);
+
+ default_clock clk(CLK, (*unused*)CLK_GATE);
+ no_reset;
+
+ method Q_OUT _read();
+ method _write(D_IN) enable(EN);
+
+ schedule _read CF _read;
+ schedule _write SBR _write;
+ schedule _read SB _write;
+endmodule
+
+
+
+import "BVI" ASSIGN1 =
+module mkBoolToReset#(Bool xin) (ResetGenIfc);
+ default_clock ();
+ no_reset;
+
+ port IN = xin;
+ output_reset gen_rst(OUT);
+endmodule
+
+(*synthesize*)
+module mkPowerOnReset (ResetGenIfc);
+ Reg#(UInt#(8)) ctr <- mkRegUNInit(resetCycles);
+ Reg#(Bool) isInPowerOnReset <- mkRegUNInit(True);
+
+ rule countDown(isInPowerOnReset);
+ let n = ctr - 1;
+ ctr <= n;
+ if (n==0) isInPowerOnReset <= False;
+ endrule
+
+ let rst_ifc <- mkBoolToReset(!isInPowerOnReset);
+ return rst_ifc;
+endmodule
+
+endpackage
diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml
index ba64067..8a4b2e2 100644
--- a/src_SSITH_P3/xilinx_ip/component.xml
+++ b/src_SSITH_P3/xilinx_ip/component.xml
@@ -729,7 +729,7 @@
viewChecksum
- 63c940c2
+ c8a99f02
@@ -754,7 +754,7 @@
viewChecksum
- 63c940c2
+ 02500583
@@ -2211,6 +2211,16 @@
verilogSource
IMPORTED_FILE
+
+ hdl/RegUNInit.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ hdl/mkPowerOnReset.v
+ verilogSource
+ IMPORTED_FILE
+
hdl/BRAM2.v
verilogSource
@@ -2286,6 +2296,11 @@
verilogSource
IMPORTED_FILE
+
+ hdl/SyncReset0.v
+ verilogSource
+ IMPORTED_FILE
+
hdl/SyncWire.v
verilogSource
@@ -2783,6 +2798,7 @@
hdl/FIFOL1.v
verilogSource
+ CHECKSUM_bfe3b3df
@@ -2822,6 +2838,16 @@
verilogSource
IMPORTED_FILE
+
+ hdl/RegUNInit.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ hdl/mkPowerOnReset.v
+ verilogSource
+ IMPORTED_FILE
+
hdl/BRAM2.v
verilogSource
@@ -2887,6 +2913,11 @@
verilogSource
IMPORTED_FILE
+
+ hdl/SyncReset0.v
+ verilogSource
+ IMPORTED_FILE
+
hdl/SyncWire.v
verilogSource
@@ -3412,23 +3443,28 @@
mkP3_Core_v1_0
package_project
- 1
+ 2
user.org:user:mkP3_Core:1.0
- 2019-04-07T20:09:49Z
+ 2020-02-20T15:03:34Z
/home/charlie/ssith_processor
/home/charlie/ssith_processor
/home/charlie/ssith_processor
+ /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip
+ /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip
+ /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip
+ /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip
+ /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip
- 2017.4
-
+ 2019.1
+
-
-
+
+
diff --git a/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v b/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v
new file mode 100644
index 0000000..9b50bfb
--- /dev/null
+++ b/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v
@@ -0,0 +1,49 @@
+
+// Copyright (c) 2000-2019 Bluespec, Inc.
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// $Revision$
+// $Date$
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+ `define BSV_ASSIGNMENT_DELAY
+`endif
+
+// Basic register with initial value but without reset (not for ASIC synthesis).
+module RegUNInit(CLK, Q_OUT, D_IN, EN);
+
+ parameter width = 1;
+ parameter init = { width {1'b0} } ;
+
+ input CLK;
+ input EN;
+ input [width - 1 : 0] D_IN;
+ output [width - 1 : 0] Q_OUT;
+
+ reg [width - 1 : 0] Q_OUT;
+ initial Q_OUT = init;
+
+ always@(posedge CLK)
+ begin
+ if (EN)
+ Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
+ end
+endmodule
diff --git a/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v b/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v
new file mode 100644
index 0000000..e97c94f
--- /dev/null
+++ b/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v
@@ -0,0 +1,50 @@
+
+// Copyright (c) 2000-2012 Bluespec, Inc.
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// $Revision$
+// $Date$
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+ `define BSV_ASSIGNMENT_DELAY
+`endif
+
+`ifdef BSV_POSITIVE_RESET
+ `define BSV_RESET_VALUE 1'b1
+ `define BSV_RESET_EDGE posedge
+`else
+ `define BSV_RESET_VALUE 1'b0
+ `define BSV_RESET_EDGE negedge
+`endif
+
+
+
+module SyncReset0 (
+ IN_RST,
+ OUT_RST
+ );
+
+ input IN_RST ;
+ output OUT_RST ;
+
+ assign OUT_RST = IN_RST ;
+
+endmodule
diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v
index e1880b7..e913064 100644
--- a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v
+++ b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v
@@ -130,17 +130,13 @@ module mkJtagTap(CLK,
// inlined wires
wire [40 : 0] w_dmi_req$wget;
- wire r_dmistat_busy$port1__read,
+ wire r_dmistat_busy$EN_port1__write,
+ r_dmistat_busy$port1__read,
r_dmistat_busy$port2__read,
r_tdo$EN_port0__write,
r_tdo$port0__write_1,
r_tdo$port1__read;
- // register r_dmi
- reg [39 : 0] r_dmi;
- wire [39 : 0] r_dmi$D_IN;
- wire r_dmi$EN;
-
// register r_dmistat_busy
reg r_dmistat_busy;
wire r_dmistat_busy$D_IN, r_dmistat_busy$EN;
@@ -160,11 +156,6 @@ module mkJtagTap(CLK,
wire [17 : 0] r_ir$D_IN;
wire r_ir$EN;
- // register r_state
- reg [3 : 0] r_state;
- wire [3 : 0] r_state$D_IN;
- wire r_state$EN;
-
// register r_tdo
reg r_tdo;
wire r_tdo$D_IN, r_tdo$EN;
@@ -179,6 +170,7 @@ module mkJtagTap(CLK,
// ports of submodule f_dmi_req
wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN;
wire f_dmi_req$dCLR,
+ f_dmi_req$dCLR_RDY,
f_dmi_req$dDEQ,
f_dmi_req$dEMPTY_N,
f_dmi_req$sCLR,
@@ -193,18 +185,32 @@ module mkJtagTap(CLK,
f_dmi_rsp$dDEQ,
f_dmi_rsp$dEMPTY_N,
f_dmi_rsp$sCLR,
+ f_dmi_rsp$sCLR_RDY,
f_dmi_rsp$sENQ,
f_dmi_rsp$sFULL_N;
+ // ports of submodule r_dmi
+ wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT;
+ wire r_dmi$EN;
+
+ // ports of submodule r_initialize
+ wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT;
+
+ // ports of submodule r_initialize2
+ wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT;
+
+ // ports of submodule r_state
+ wire [3 : 0] r_state$D_IN, r_state$Q_OUT;
+ wire r_state$EN;
+
// ports of submodule rst_tck
wire rst_tck$OUT_RST;
// ports of submodule tck_clock
- wire tck_clock$CLK_IN,
- tck_clock$CLK_IN_EN,
- tck_clock$CLK_OUT,
- tck_clock$COND_IN,
- tck_clock$COND_IN_EN;
+ wire tck_clock$IN, tck_clock$OUT;
+
+ // ports of submodule w_tck_crossed
+ wire w_tck_crossed$DOUT;
// rule scheduling signals
wire CAN_FIRE_RL_dmi_request,
@@ -215,7 +221,9 @@ module mkJtagTap(CLK,
CAN_FIRE_RL_dmi_response_ready,
CAN_FIRE_RL_dmi_response_tck,
CAN_FIRE_RL_dmi_start,
- CAN_FIRE_RL_rl_tck,
+ CAN_FIRE_RL_mkConnectionVtoAf,
+ CAN_FIRE_RL_rl_initialize,
+ CAN_FIRE_RL_rl_initialize2,
CAN_FIRE_RL_tick,
CAN_FIRE_dmi_req_ready,
CAN_FIRE_dmi_rsp_data,
@@ -232,7 +240,9 @@ module mkJtagTap(CLK,
WILL_FIRE_RL_dmi_response_ready,
WILL_FIRE_RL_dmi_response_tck,
WILL_FIRE_RL_dmi_start,
- WILL_FIRE_RL_rl_tck,
+ WILL_FIRE_RL_mkConnectionVtoAf,
+ WILL_FIRE_RL_rl_initialize,
+ WILL_FIRE_RL_rl_initialize2,
WILL_FIRE_RL_tick,
WILL_FIRE_dmi_req_ready,
WILL_FIRE_dmi_rsp_data,
@@ -243,24 +253,24 @@ module mkJtagTap(CLK,
WILL_FIRE_jtag_tms;
// remaining internal signals
- reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1,
- v__h2135;
- reg [17 : 0] newir__h3435;
- reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3,
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2;
- wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140,
- v__h2233,
- v__h2601,
- x__h2449,
- x__h2658,
- y__h2659;
- wire [17 : 0] v__h3299, x__h3350, y__h3351;
- wire r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57,
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68,
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72;
+ reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1,
+ v__h2479;
+ reg [17 : 0] newir__h3774;
+ reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3,
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2;
+ wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146,
+ v__h2576,
+ v__h2941,
+ x__h2789,
+ x__h2996,
+ y__h2997;
+ wire [17 : 0] v__h3636, x__h3687, y__h3688;
+ wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63,
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74,
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78;
// oscillator and gates for output clock CLK_jtag_tclk_out
- assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ;
+ assign CLK_jtag_tclk_out = tck_clock$OUT ;
assign CLK_GATE_jtag_tclk_out = 1'b1 ;
// action method jtag_tdi
@@ -311,7 +321,7 @@ module mkJtagTap(CLK,
// submodule f_dmi_busy
FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST),
- .CLK(tck_clock$CLK_OUT),
+ .CLK(tck_clock$OUT),
.ENQ(f_dmi_busy$ENQ),
.DEQ(f_dmi_busy$DEQ),
.CLR(f_dmi_busy$CLR),
@@ -321,7 +331,7 @@ module mkJtagTap(CLK,
// submodule f_dmi_req
SyncFIFOLevel #(.dataWidth(32'd41),
.depth(32'd2),
- .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT),
+ .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT),
.dCLK(CLK),
.sRST(rst_tck$OUT_RST),
.sD_IN(f_dmi_req$sD_IN),
@@ -335,13 +345,13 @@ module mkJtagTap(CLK,
.dCOUNT(),
.sCOUNT(),
.sCLR_RDY(f_dmi_req$sCLR_RDY),
- .dCLR_RDY());
+ .dCLR_RDY(f_dmi_req$dCLR_RDY));
// submodule f_dmi_rsp
SyncFIFOLevel #(.dataWidth(32'd40),
.depth(32'd2),
.indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK),
- .dCLK(tck_clock$CLK_OUT),
+ .dCLK(tck_clock$OUT),
.sRST(RST_N),
.sD_IN(f_dmi_rsp$sD_IN),
.sENQ(f_dmi_rsp$sENQ),
@@ -353,29 +363,46 @@ module mkJtagTap(CLK,
.dEMPTY_N(f_dmi_rsp$dEMPTY_N),
.dCOUNT(),
.sCOUNT(),
- .sCLR_RDY(),
+ .sCLR_RDY(f_dmi_rsp$sCLR_RDY),
.dCLR_RDY(f_dmi_rsp$dCLR_RDY));
+ // submodule r_dmi
+ RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT),
+ .D_IN(r_dmi$D_IN),
+ .EN(r_dmi$EN),
+ .Q_OUT(r_dmi$Q_OUT));
+
+ // submodule r_initialize
+ RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT),
+ .D_IN(r_initialize$D_IN),
+ .EN(r_initialize$EN),
+ .Q_OUT(r_initialize$Q_OUT));
+
+ // submodule r_initialize2
+ RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK),
+ .D_IN(r_initialize2$D_IN),
+ .EN(r_initialize2$EN),
+ .Q_OUT(r_initialize2$Q_OUT));
+
+ // submodule r_state
+ RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT),
+ .D_IN(r_state$D_IN),
+ .EN(r_state$EN),
+ .Q_OUT(r_state$Q_OUT));
+
// submodule rst_tck
- SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT),
- .IN_RST(RST_N),
- .OUT_RST(rst_tck$OUT_RST));
+ SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST));
// submodule tck_clock
- MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK),
- .RST(RST_N),
- .CLK_IN(tck_clock$CLK_IN),
- .COND_IN(tck_clock$COND_IN),
- .CLK_IN_EN(tck_clock$CLK_IN_EN),
- .COND_IN_EN(tck_clock$COND_IN_EN),
- .CLK_VAL_OUT(),
- .COND_OUT(),
- .CLK_GATE_OUT(),
- .CLK_OUT(tck_clock$CLK_OUT));
+ ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT));
- // rule RL_rl_tck
- assign CAN_FIRE_RL_rl_tck = 1'd1 ;
- assign WILL_FIRE_RL_rl_tck = 1'd1 ;
+ // submodule w_tck_crossed
+ SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk),
+ .DOUT(w_tck_crossed$DOUT));
+
+ // rule RL_mkConnectionVtoAf
+ assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ;
+ assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ;
// rule RL_tick
assign CAN_FIRE_RL_tick = 1'd1 ;
@@ -383,7 +410,7 @@ module mkJtagTap(CLK,
// rule RL_dmi_start
assign CAN_FIRE_RL_dmi_start =
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 &&
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 &&
f_dmi_req$sFULL_N &&
f_dmi_busy$FULL_N &&
w_dmi_req$wget[1:0] != 2'd0 ;
@@ -406,9 +433,14 @@ module mkJtagTap(CLK,
f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ;
assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ;
+ // rule RL_rl_initialize
+ assign CAN_FIRE_RL_rl_initialize =
+ r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ;
+ assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ;
+
// rule RL_dmi_reset
assign CAN_FIRE_RL_dmi_reset =
- r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 &&
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 &&
(!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ;
assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ;
@@ -420,35 +452,37 @@ module mkJtagTap(CLK,
assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ;
assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ;
+ // rule RL_rl_initialize2
+ assign CAN_FIRE_RL_rl_initialize2 =
+ f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ;
+ assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ;
+
// inlined wires
assign w_dmi_req$wget = { 1'd0, r_dr } ;
- assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ;
- assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ;
+ assign r_tdo$EN_port0__write =
+ r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ;
+ assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ;
assign r_tdo$port1__read =
r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ;
assign r_dmistat_busy$port1__read =
- r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 ||
+ r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 ||
r_dmistat_busy ;
+ assign r_dmistat_busy$EN_port1__write =
+ WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ;
assign r_dmistat_busy$port2__read =
- !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ;
-
- // register r_dmi
- assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ;
- assign r_dmi$EN =
- WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 ;
+ !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ;
// register r_dmistat_busy
assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ;
assign r_dmistat_busy$EN = 1'b1 ;
// register r_dr
- always@(r_state or r_dr or v__h2135 or v__h2601)
+ always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941)
begin
- case (r_state)
+ case (r_state$Q_OUT)
4'd0: r_dr$D_IN = r_dr;
- 4'd3: r_dr$D_IN = v__h2135;
- 4'd4: r_dr$D_IN = v__h2601;
+ 4'd3: r_dr$D_IN = v__h2479;
+ 4'd4: r_dr$D_IN = v__h2941;
default: r_dr$D_IN = r_dr;
endcase
end
@@ -456,22 +490,15 @@ module mkJtagTap(CLK,
// register r_drmask
assign r_drmask$D_IN =
- (r_state == 4'd3) ?
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 :
+ (r_state$Q_OUT == 4'd3) ?
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 :
r_drmask ;
assign r_drmask$EN = 1'd1 ;
// register r_ir
- assign r_ir$D_IN = newir__h3435 ;
+ assign r_ir$D_IN = newir__h3774 ;
assign r_ir$EN = 1'd1 ;
- // register r_state
- assign r_state$D_IN =
- jtag_tms ?
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 :
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ;
- assign r_state$EN = 1'd1 ;
-
// register r_tdo
assign r_tdo$D_IN = r_tdo$port1__read ;
assign r_tdo$EN = 1'b1 ;
@@ -479,69 +506,89 @@ module mkJtagTap(CLK,
// submodule f_dmi_busy
assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ;
assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ;
- assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
+ assign f_dmi_busy$CLR =
+ WILL_FIRE_RL_dmi_reset && r_dr[17] ||
+ WILL_FIRE_RL_rl_initialize ;
// submodule f_dmi_req
assign f_dmi_req$sD_IN = w_dmi_req$wget ;
assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ;
assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ;
assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
- assign f_dmi_req$dCLR = 1'b0 ;
+ assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ;
// submodule f_dmi_rsp
assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ;
assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ;
assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ;
- assign f_dmi_rsp$sCLR = 1'b0 ;
+ assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ;
assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ;
+ // submodule r_dmi
+ assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ;
+ assign r_dmi$EN =
+ WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 ;
+
+ // submodule r_initialize
+ assign r_initialize$D_IN = 1'd0 ;
+ assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ;
+
+ // submodule r_initialize2
+ assign r_initialize2$D_IN = 1'd0 ;
+ assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ;
+
+ // submodule r_state
+ assign r_state$D_IN =
+ jtag_tms ?
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 :
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ;
+ assign r_state$EN = 1'd1 ;
+
// submodule tck_clock
- assign tck_clock$CLK_IN = jtag_tclk ;
- assign tck_clock$COND_IN = 1'b0 ;
- assign tck_clock$CLK_IN_EN = 1'd1 ;
- assign tck_clock$COND_IN_EN = 1'b0 ;
+ assign tck_clock$IN = w_tck_crossed$DOUT ;
// remaining internal signals
- assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 =
+ assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 =
(r_dmistat_busy ||
- r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 &&
f_dmi_busy$EMPTY_N) ?
40'hAAAAAAAAAB :
- r_dmi ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 =
- r_state == 4'd8 && r_ir == 18'b100010100100100100 &&
+ r_dmi$Q_OUT ;
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 =
+ r_state$Q_OUT == 4'd8 && r_ir == 18'b100010100100100100 &&
(r_dr[17] || r_dr[16]) ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 =
- r_state == 4'd8 && r_ir == 18'b000011100100100100 &&
- r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 &&
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 =
+ r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 &&
f_dmi_busy$EMPTY_N ;
- assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 =
- r_state == 4'd8 && r_ir == 18'b000011100100100100 &&
- r_dmi[1:0] != 2'd2 &&
- r_dmi[1:0] != 2'd3 &&
+ assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 =
+ r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 &&
+ r_dmi$Q_OUT[1:0] != 2'd2 &&
+ r_dmi$Q_OUT[1:0] != 2'd3 &&
!f_dmi_busy$EMPTY_N ;
- assign v__h2233 = { 22'd960, r_ir } ;
- assign v__h2601 = x__h2658 | y__h2659 ;
- assign v__h3299 = x__h3350 | y__h3351 ;
- assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ;
- assign x__h2658 = { 1'd0, r_dr[39:1] } ;
- assign x__h3350 = { 1'd0, r_ir[17:1] } ;
- assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ;
- assign y__h3351 = jtag_tdi ? 18'd131072 : 18'd0 ;
- always@(r_state or r_ir or v__h3299)
+ assign v__h2576 = { 22'd960, r_ir } ;
+ assign v__h2941 = x__h2996 | y__h2997 ;
+ assign v__h3636 = x__h3687 | y__h3688 ;
+ assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ;
+ assign x__h2996 = { 1'd0, r_dr[39:1] } ;
+ assign x__h3687 = { 1'd0, r_ir[17:1] } ;
+ assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ;
+ assign y__h3688 = jtag_tdi ? 18'd131072 : 18'd0 ;
+ always@(r_state$Q_OUT or r_ir or v__h3636)
begin
- case (r_state)
- 4'd0: newir__h3435 = 18'd1;
- 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir;
- 4'd11: newir__h3435 = v__h3299;
- default: newir__h3435 = r_ir;
+ case (r_state$Q_OUT)
+ 4'd0: newir__h3774 = 18'd1;
+ 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir;
+ 4'd11: newir__h3774 = v__h3636;
+ default: newir__h3774 = r_ir;
endcase
end
always@(r_ir or
- v__h2233 or
- IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 or
- x__h2449)
+ v__h2576 or
+ IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 or
+ x__h2789)
begin
case (r_ir)
18'd0,
@@ -552,18 +599,18 @@ module mkJtagTap(CLK,
18'h00016,
18'h00017,
18'd262143:
- v__h2135 = 40'd0;
- 18'd1: v__h2135 = 40'd4093;
+ v__h2479 = 40'd0;
+ 18'd1: v__h2479 = 40'd4093;
18'b000011100100100100:
- v__h2135 =
- IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140;
- 18'b100010100100100100: v__h2135 = x__h2449;
- default: v__h2135 = v__h2233;
+ v__h2479 =
+ IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146;
+ 18'b100010100100100100: v__h2479 = x__h2789;
+ default: v__h2479 = v__h2576;
endcase
end
- always@(newir__h3435)
+ always@(newir__h3774)
begin
- case (newir__h3435)
+ case (newir__h3774)
18'd0,
18'h00012,
18'h00013,
@@ -572,71 +619,67 @@ module mkJtagTap(CLK,
18'h00016,
18'h00017,
18'd262143:
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1;
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1;
18'd1, 18'b100010100100100100:
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
40'h0080000000;
18'b000011100100100100:
- CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
+ CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
40'h8000000000;
- default: CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
+ default: CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 =
40'h0100000000;
endcase
end
- always@(r_state)
+ always@(r_state$Q_OUT)
begin
- case (r_state)
- 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state;
+ case (r_state$Q_OUT)
+ 4'd0:
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 =
+ r_state$Q_OUT;
4'd1, 4'd8, 4'd15:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2;
- 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9;
- 4'd3, 4'd4:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5;
- 4'd5, 4'd7:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8;
- 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7;
- 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2;
+ 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9;
+ 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5;
+ 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8;
+ 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7;
+ 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0;
4'd10, 4'd11:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12;
4'd12, 4'd14:
- CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15;
- 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14;
+ CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15;
+ 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14;
endcase
end
- always@(r_state)
+ always@(r_state$Q_OUT)
begin
- case (r_state)
+ case (r_state$Q_OUT)
4'd0, 4'd1, 4'd8, 4'd15:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1;
- 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1;
+ 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3;
4'd3, 4'd4, 4'd7:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4;
4'd5, 4'd6:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6;
- 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6;
+ 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10;
4'd10, 4'd11, 4'd14:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11;
4'd12, 4'd13:
- CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13;
+ CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13;
endcase
end
// handling of inlined registers
- always@(posedge tck_clock$CLK_OUT)
+ always@(posedge tck_clock$OUT)
begin
if (rst_tck$OUT_RST == `BSV_RESET_VALUE)
begin
- r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0;
r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0;
- r_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
- if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN;
if (r_dmistat_busy$EN)
r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN;
- if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN;
end
if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN;
if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN;
@@ -649,12 +692,10 @@ module mkJtagTap(CLK,
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
- r_dmi = 40'hAAAAAAAAAA;
r_dmistat_busy = 1'h0;
r_dr = 40'hAAAAAAAAAA;
r_drmask = 40'hAAAAAAAAAA;
r_ir = 18'h2AAAA;
- r_state = 4'hA;
r_tdo = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
@@ -663,11 +704,11 @@ module mkJtagTap(CLK,
// handling of system tasks
// synopsys translate_off
- always@(negedge tck_clock$CLK_OUT)
+ always@(negedge tck_clock$OUT)
begin
#0;
if (rst_tck$OUT_RST != `BSV_RESET_VALUE)
- if (r_state == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 &&
+ if (r_state$Q_OUT == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 &&
r_ir != 18'h00013 &&
r_ir != 18'h00014 &&
r_ir != 18'h00015 &&
diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v
new file mode 100644
index 0000000..65d7430
--- /dev/null
+++ b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v
@@ -0,0 +1,92 @@
+//
+// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
+//
+//
+//
+//
+// Ports:
+// Name I/O size props
+// RST_N_gen_rst O 1 reset
+// CLK I 1 clock
+// RST_N I 1 unused
+//
+// No combinational paths from inputs to outputs
+//
+//
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+ `define BSV_ASSIGNMENT_DELAY
+`endif
+
+`ifdef BSV_POSITIVE_RESET
+ `define BSV_RESET_VALUE 1'b1
+ `define BSV_RESET_EDGE posedge
+`else
+ `define BSV_RESET_VALUE 1'b0
+ `define BSV_RESET_EDGE negedge
+`endif
+
+module mkPowerOnReset(CLK,
+ RST_N,
+
+ RST_N_gen_rst);
+ input CLK;
+ input RST_N;
+
+ // output resets
+ output RST_N_gen_rst;
+
+ // signals for module outputs
+ wire RST_N_gen_rst;
+
+ // ports of submodule ctr
+ wire [7 : 0] ctr$D_IN, ctr$Q_OUT;
+ wire ctr$EN;
+
+ // ports of submodule isInPowerOnReset
+ wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT;
+
+ // ports of submodule rst_ifc
+ wire rst_ifc$OUT;
+
+ // rule scheduling signals
+ wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown;
+
+ // remaining internal signals
+ wire NOT_isInPowerOnReset__read___d5;
+
+ // output resets
+ assign RST_N_gen_rst = rst_ifc$OUT ;
+
+ // submodule ctr
+ RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK),
+ .D_IN(ctr$D_IN),
+ .EN(ctr$EN),
+ .Q_OUT(ctr$Q_OUT));
+
+ // submodule isInPowerOnReset
+ RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK),
+ .D_IN(isInPowerOnReset$D_IN),
+ .EN(isInPowerOnReset$EN),
+ .Q_OUT(isInPowerOnReset$Q_OUT));
+
+ // submodule rst_ifc
+ ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT));
+
+ // rule RL_countDown
+ assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ;
+ assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ;
+
+ // submodule ctr
+ assign ctr$D_IN = ctr$Q_OUT - 8'd1 ;
+ assign ctr$EN = isInPowerOnReset$Q_OUT ;
+
+ // submodule isInPowerOnReset
+ assign isInPowerOnReset$D_IN = 1'd0 ;
+ assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ;
+
+ // remaining internal signals
+ assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ;
+endmodule // mkPowerOnReset
+
diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv
index 218b260..0898d43 100644
--- a/src_Testbench/SoC/SoC_Top.bsv
+++ b/src_Testbench/SoC/SoC_Top.bsv
@@ -343,7 +343,8 @@ module mkSoC_Top #(Reset dm_power_on_reset)
method Action start (Fabric_Addr tohost_addr, Fabric_Addr fromhost_addr);
Bool watch_tohost = (tohost_addr != 0);
mem0_controller.set_watch_tohost (watch_tohost, tohost_addr);
- corew.start (tohost_addr, fromhost_addr);
+ Bool is_running = True;
+ corew.start (is_running, tohost_addr, fromhost_addr);
$display ("%0d: %m.method start (tohost %0h, fromhost %0h)",
cur_cycle, tohost_addr, fromhost_addr);
endmethod