From 41700f69453c3dbaca5fb55a5668864c1a07f161 Mon Sep 17 00:00:00 2001 From: rsnikhil Date: Fri, 13 Mar 2020 15:07:38 -0400 Subject: [PATCH 1/8] Incorporated patches/additions from Joe Stoy after GFE debugging --- .../Verilog_RTL/mkCore.v | 1425 +++++++------- .../Verilog_RTL/mkCoreW.v | 18 +- .../Verilog_RTL/mkFabric_2x3.v | 36 +- .../Verilog_RTL/mkProc.v | 1674 +++++++++-------- .../Verilog_RTL/mkSoC_Top.v | 78 +- builds/Resources/Include_bluesim.mk | 1 + src_Core/CPU/Core.bsv | 9 +- src_Core/CPU/Proc.bsv | 4 +- src_Core/CPU/Proc_IFC.bsv | 2 +- src_Core/Core/CoreW.bsv | 9 +- src_Core/Core/CoreW_IFC.bsv | 2 +- src_SSITH_P3/Makefile | 6 +- src_SSITH_P3/Verilog_RTL/mkCore.v | 1308 ++++++------- src_SSITH_P3/Verilog_RTL/mkCoreW.v | 50 +- src_SSITH_P3/Verilog_RTL/mkJtagTap.v | 369 ++-- src_SSITH_P3/Verilog_RTL/mkP3_Core.v | 118 +- src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v | 92 + src_SSITH_P3/Verilog_RTL/mkProc.v | 1356 ++++++------- src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v | 5 + src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v | 87 + src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v | 50 + src_SSITH_P3/Verilog_RTL_sim/SyncWire.v | 41 + src_SSITH_P3/Verilog_RTL_sim/mkCore.v | 701 +++---- src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v | 50 +- src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v | 369 ++-- src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v | 152 +- src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v | 92 + src_SSITH_P3/Verilog_RTL_sim/mkProc.v | 1364 +++++++------- src_SSITH_P3/src_BSV/ClockHacks.bsv | 117 ++ src_SSITH_P3/src_BSV/JtagTap.bsv | 50 +- src_SSITH_P3/src_BSV/P3_Core.bsv | 43 +- src_SSITH_P3/src_BSV/PowerOnReset.bsv | 51 + src_SSITH_P3/xilinx_ip/component.xml | 132 +- src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v | 5 + src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v | 87 + src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v | 50 + src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v | 50 + src_SSITH_P3/xilinx_ip/hdl/SyncWire.v | 41 + src_SSITH_P3/xilinx_ip/hdl/mkCore.v | 1308 ++++++------- src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v | 50 +- src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v | 369 ++-- src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v | 118 +- src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v | 92 + src_SSITH_P3/xilinx_ip/hdl/mkProc.v | 1356 ++++++------- src_Testbench/SoC/SoC_Top.bsv | 3 +- 45 files changed, 7311 insertions(+), 6079 deletions(-) create mode 100644 src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/SyncWire.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v create mode 100644 src_SSITH_P3/src_BSV/ClockHacks.bsv create mode 100644 src_SSITH_P3/src_BSV/PowerOnReset.bsv create mode 100644 src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/SyncWire.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index 4db820b..d122cc6 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -88,6 +88,7 @@ // RDY_setSEIP O 1 const // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 unused // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -154,6 +155,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -332,6 +334,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4018,7 +4021,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; - wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, + wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; wire MUX_commitStage_rg_serial_num$write_1__SEL_1, @@ -4073,19 +4076,13 @@ module mkCore(CLK, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fs_reg$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_1, - MUX_csrf_ie_vec_1$write_1__SEL_2, - MUX_csrf_ie_vec_1$write_1__VAL_1, + MUX_csrf_ie_vec_1$write_1__VAL_2, MUX_csrf_ie_vec_3$write_1__SEL_1, - MUX_csrf_ie_vec_3$write_1__SEL_2, - MUX_csrf_ie_vec_3$write_1__VAL_1, - MUX_csrf_mpp_reg$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__VAL_1, - MUX_csrf_prev_ie_vec_3$write_1__SEL_1, - MUX_csrf_prev_ie_vec_3$write_1__VAL_1, + MUX_csrf_ie_vec_3$write_1__VAL_2, + MUX_csrf_prev_ie_vec_1$write_1__VAL_2, + MUX_csrf_prev_ie_vec_3$write_1__VAL_2, MUX_csrf_prv_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__VAL_1, + MUX_csrf_spp_reg$write_1__VAL_2, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_flush_reservation$write_1__SEL_1, @@ -4167,20 +4164,20 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77, - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78, + reg [22 : 0] CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75, + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76, CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79, CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q80, CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81, CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q82, CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112, CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q113, - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40, - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41, + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42, + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43, CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110, CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q111, - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42, - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43, + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40, + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41, CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114, CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q115, CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44, @@ -4189,8 +4186,8 @@ module mkCore(CLK, CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q117, CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46, CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q47, - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75, - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76, + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77, + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78, _theResult___fst_sfd__h350720, _theResult___fst_sfd__h359443, _theResult___fst_sfd__h368025, @@ -4268,8 +4265,8 @@ module mkCore(CLK, CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q28, CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95, CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q96, - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29, - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30, + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25, + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26, CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103, CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q104, CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33, @@ -4357,11 +4354,11 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232, + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234, + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, CASE_guard05153_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, CASE_guard05153_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, CASE_guard08267_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, @@ -4370,38 +4367,38 @@ module mkCore(CLK, CASE_guard17336_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, CASE_guard22919_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, CASE_guard22919_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, CASE_guard37808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, CASE_guard47120_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, CASE_guard47120_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, CASE_guard50747_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, CASE_guard50747_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, CASE_guard50848_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, CASE_guard56189_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, CASE_guard59456_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, CASE_guard59456_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, CASE_guard59778_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, CASE_guard68386_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, CASE_guard68614_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, CASE_guard77222_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53, + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, CASE_guard86424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, CASE_guard96446_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, CASE_guard96446_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, CASE_guard98955_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233, + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4678,7 +4675,7 @@ module mkCore(CLK, r1__read__h620737, r1__read__h620854, y__h258435; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q23, + wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91, IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130, @@ -4694,7 +4691,7 @@ module mkCore(CLK, IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166, IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q25, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71, @@ -5110,7 +5107,7 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107, @@ -5246,7 +5243,7 @@ module mkCore(CLK, _theResult___snd_fst_exp__h585834, _theResult___snd_fst_exp__h604269, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64, - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21, + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99, din_inc___2_exp__h526166, din_inc___2_exp__h526201, @@ -5515,7 +5512,7 @@ module mkCore(CLK, IF_sfdin22305_BIT_33_THEN_2_ELSE_0__q67, IF_sfdin50234_BIT_33_THEN_2_ELSE_0__q92, IF_sfdin55340_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q24, + IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22, IF_sfdin68000_BIT_33_THEN_2_ELSE_0__q102, IF_sfdin76608_BIT_33_THEN_2_ELSE_0__q32, IF_sfdin94644_BIT_4_THEN_2_ELSE_0__q148, @@ -5527,7 +5524,7 @@ module mkCore(CLK, IF_theResult___snd45720_BIT_4_THEN_2_ELSE_0__q167, IF_theResult___snd58847_BIT_33_THEN_2_ELSE_0__q94, IF_theResult___snd64125_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q26, + IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24, IF_theResult___snd76637_BIT_33_THEN_2_ELSE_0__q107, IF_theResult___snd85024_BIT_4_THEN_2_ELSE_0__q144, IF_theResult___snd85245_BIT_33_THEN_2_ELSE_0__q37, @@ -5919,7 +5916,7 @@ module mkCore(CLK, NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962, NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017, NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075, - NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_RDY_ETC___d15034, + NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034, NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_deq_ETC___d15187, NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788, NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14981, @@ -5990,7 +5987,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo28, + _dfoo26, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -6145,8 +6142,8 @@ module mkCore(CLK, csrf_prv_reg_read__2956_ULE_1___d14607, csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192, fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551, + fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407, fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617, - fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14165, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305, @@ -6197,7 +6194,7 @@ module mkCore(CLK, r1__read_BIT_20___h662377, r__h619422, r__h620919, - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037, + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037, regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111, regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598, regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612, @@ -6216,7 +6213,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318, regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402, regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412, - rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407, + rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165, rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841, rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975, rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992, @@ -9213,32 +9210,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && - l2Tlb$RDY_toChildren_rsToC_deq && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && + l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9250,16 +9247,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9298,9 +9295,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9600,7 +9597,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_commitTrap[165] && @@ -9649,8 +9646,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && rob$deqPort_0_deq_data[18] ; @@ -9729,7 +9726,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_RDY_ETC___d15034 && + NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034 && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -9878,8 +9875,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9890,8 +9887,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9965,16 +9962,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -9985,8 +9982,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10024,8 +10021,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10122,8 +10119,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10140,8 +10137,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10163,8 +10160,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10311,8 +10308,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -10355,8 +10352,8 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; @@ -10375,8 +10372,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10607,8 +10604,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10652,9 +10649,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && - fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && @@ -10663,8 +10661,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10748,7 +10746,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -10968,27 +10967,15 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; - assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[257:253] == 5'd19 || rob$deqPort_0_deq_data[257:253] == 5'd20) ; - assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -11056,6 +11043,18 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = commitStage_rg_serial_num + y__h723410 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = (k__h675032 == 1'd0 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186) ? { fetchStage$pipelines_0_first[199:195], @@ -11081,18 +11080,6 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11406,7 +11393,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; endcase end - assign MUX_csrf_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || @@ -11414,7 +11401,7 @@ module mkCore(CLK, 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; - assign MUX_csrf_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ? @@ -11425,7 +11412,7 @@ module mkCore(CLK, n__read__h720316 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = n__read__h720316 + { 62'd0, x__h723635 } ; - assign MUX_csrf_mpp_reg$write_1__VAL_1 = + assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ? @@ -11434,14 +11421,14 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__VAL_1 = commitStage_commitTrap[36] ? 64'd0 : trap_val__h709721 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd8 && IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd18 || @@ -11455,7 +11442,7 @@ module mkCore(CLK, 2'd1 : 2'd3 ; assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_spp_reg$write_1__VAL_1 = + assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || @@ -12764,25 +12751,25 @@ module mkCore(CLK, // register csrf_ie_vec_1 assign csrf_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_1 ; + !MUX_csrf_ie_vec_1$write_1__SEL_1 && + MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_ie_vec_3 assign csrf_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_1 ; + !MUX_csrf_ie_vec_3$write_1__SEL_1 && + MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? cause_code__h708698 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = @@ -12795,7 +12782,7 @@ module mkCore(CLK, // register csrf_mcause_interrupt_reg assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = @@ -12861,7 +12848,7 @@ module mkCore(CLK, // register csrf_mepc_csr assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = @@ -12913,13 +12900,13 @@ module mkCore(CLK, // register csrf_mpp_reg assign csrf_mpp_reg$D_IN = - MUX_csrf_mpp_reg$write_1__SEL_1 ? - MUX_csrf_mpp_reg$write_1__VAL_1 : - csrf_prv_reg ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_prv_reg : + MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ; @@ -12939,7 +12926,7 @@ module mkCore(CLK, // register csrf_mtval_csr assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = @@ -12996,23 +12983,23 @@ module mkCore(CLK, // register csrf_prev_ie_vec_1 assign csrf_prev_ie_vec_1$D_IN = - MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : - csrf_ie_vec_1 ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_ie_vec_1 : + MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prev_ie_vec_3 assign csrf_prev_ie_vec_3$D_IN = - MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_3$write_1__VAL_1 : - csrf_ie_vec_3 ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_ie_vec_3 : + MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_prv_reg assign csrf_prv_reg$D_IN = @@ -13067,9 +13054,9 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? cause_code__h708698 : - csrf_rg_tselect$D_IN[3:0] ; + csrf_rg_tdata3$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || @@ -13080,7 +13067,7 @@ module mkCore(CLK, // register csrf_scause_interrupt_reg assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_rg_tselect$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = @@ -13117,7 +13104,7 @@ module mkCore(CLK, // register csrf_sepc_csr assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = @@ -13171,13 +13158,13 @@ module mkCore(CLK, // register csrf_spp_reg assign csrf_spp_reg$D_IN = - MUX_csrf_spp_reg$write_1__SEL_1 ? - MUX_csrf_spp_reg$write_1__VAL_1 : - csrf_prv_reg[0] ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_prv_reg[0] : + MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; @@ -13193,7 +13180,7 @@ module mkCore(CLK, // register csrf_stval_csr assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = @@ -13847,9 +13834,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -17786,7 +17773,7 @@ module mkCore(CLK, .execFpuSimple_rVal1(rVal1__h487144), .execFpuSimple_rVal2(rVal2__h487145), .execFpuSimple(execFpuSimple___d11167)); - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q23 = + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ? _theResult___snd__h358911 : _theResult____h350737 ; @@ -17850,7 +17837,7 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ? _theResult___snd__h458885 : _theResult___snd__h476675 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q25 = + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ? _theResult___snd__h367493 : 57'd0 ; @@ -19024,8 +19011,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 = (guard__h350747 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? @@ -19563,8 +19550,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045 = (_theResult___fst_exp__h603483 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -19574,8 +19561,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581 = (_theResult___fst_exp__h564179 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -19596,8 +19583,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814 = (_theResult___fst_exp__h564179 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -19607,8 +19594,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 = (_theResult___fst_exp__h525326 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -19629,8 +19616,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992 = (_theResult____h658034 == 12'd0 && (csrf_prv_reg == 2'd0 || @@ -20281,8 +20268,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ? 4'd0 : @@ -20838,7 +20825,7 @@ module mkCore(CLK, 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] == + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 9'd386 : { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35[7], @@ -22193,10 +22180,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050 = IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237 = @@ -22226,10 +22213,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 && IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 && (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14165) ; + regRenamingTable$RDY_rename_1_claimRename && + rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165) ; assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && @@ -22292,7 +22279,7 @@ module mkCore(CLK, sfdin__h450234[33] ? 2'd2 : 2'd0 ; assign IF_sfdin55340_BIT_4_THEN_2_ELSE_0__q171 = sfdin__h555340[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q24 = + assign IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22 = sfdin__h358842[33] ? 2'd2 : 2'd0 ; assign IF_sfdin68000_BIT_33_THEN_2_ELSE_0__q102 = sfdin__h468000[33] ? 2'd2 : 2'd0 ; @@ -22316,7 +22303,7 @@ module mkCore(CLK, _theResult___snd__h458847[33] ? 2'd2 : 2'd0 ; assign IF_theResult___snd64125_BIT_4_THEN_2_ELSE_0__q174 = _theResult___snd__h564125[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q26 = + assign IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24 = _theResult___snd__h367455[33] ? 2'd2 : 2'd0 ; assign IF_theResult___snd76637_BIT_33_THEN_2_ELSE_0__q107 = _theResult___snd__h476637[33] ? 2'd2 : 2'd0 ; @@ -23202,7 +23189,7 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125 = (!fetchStage$pipelines_0_canDeq || NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 && + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177 = @@ -23440,12 +23427,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -23538,10 +23525,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073 ; - assign NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_RDY_ETC___d15034 = + assign NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__5002_BIT_25_5003_5_ETC___d15031) ; @@ -23582,7 +23569,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd15 || rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 || @@ -23709,8 +23696,8 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 = - { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21[10], - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21 } ; + { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29[10], + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 } ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^ 12'h800) <= @@ -23719,11 +23706,11 @@ module mkCore(CLK, (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^ 12'h800) < 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22 = + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 + 12'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99[10], @@ -24023,11 +24010,11 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 ; + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235 ; + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 ; assign _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && @@ -24675,7 +24662,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18 || rob$deqPort_0_deq_data[257:253] == 5'd20 ; - assign _dfoo28 = + assign _dfoo26 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || @@ -25218,12 +25205,12 @@ module mkCore(CLK, _theResult___fst_exp__h376614 : _theResult___fst_exp__h377208 ; assign _theResult___fst_exp__h385251 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] == + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] ; + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ; assign _theResult___fst_exp__h385290 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; assign _theResult___fst_exp__h385296 = @@ -26623,7 +26610,7 @@ module mkCore(CLK, _theResult____h350737 : _theResult___snd__h358888 ; assign _theResult___snd__h358888 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q23[54:0], + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0], 2'd0 } ; assign _theResult___snd__h358911 = _theResult____h350737 << @@ -26643,7 +26630,7 @@ module mkCore(CLK, sfd__h343132 : _theResult___snd__h367470 ; assign _theResult___snd__h367470 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q25[54:0], + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0], 2'd0 } ; assign _theResult___snd__h367493 = sfd__h343132 << @@ -27703,7 +27690,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] - 11'd1023 ; assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99 = @@ -28186,9 +28173,9 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788 ; @@ -28339,6 +28326,14 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 ; + assign fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && @@ -28346,12 +28341,6 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 ; - assign fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14165 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -28583,10 +28572,10 @@ module mkCore(CLK, assign fflags_csr__read__h616210 = { 59'd0, csrf_fflags_reg } ; assign frm_csr__read__h616221 = { 61'd0, csrf_frm_reg } ; assign guard__h350747 = - { IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q24[1], + { IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22[1], { sfdin__h358842[32:0], 23'd0 } != 56'd0 } ; assign guard__h359456 = - { IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q26[1], + { IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24[1], { _theResult___snd__h367455[32:0], 23'd0 } != 56'd0 } ; assign guard__h368386 = { IF_sfdin76608_BIT_33_THEN_2_ELSE_0__q32[1], @@ -29156,9 +29145,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign r__h619422 = csrf_fs_reg == 2'b11 ; assign r__h620919 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037 = + assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; assign regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111 = @@ -29579,14 +29568,12 @@ module mkCore(CLK, assign result__h653792 = ~x__h653791 ; assign rg_tdata1__read__h619065 = { r1__read__h620945, csrf_rg_tdata1_data } ; - assign rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14968 = rob$deqPort_0_deq_data[353:290] + 64'd4 ; assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841 = @@ -30526,23 +30513,23 @@ module mkCore(CLK, default: rVal1__h640782 = 64'b0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h396418 = 8'd255; + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h442113 = 8'd255; 3'd2: - _theResult___fst_exp__h396418 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h442113 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h396418 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h442113 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h396418 = 8'd254; - default: _theResult___fst_exp__h396418 = 8'd0; + 3'd4: _theResult___fst_exp__h442113 = 8'd254; + default: _theResult___fst_exp__h442113 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or @@ -30583,6 +30570,25 @@ module mkCore(CLK, default: _theResult___fst_sfd__h350720 = 23'd0; endcase end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h396418 = 8'd255; + 3'd2: + _theResult___fst_exp__h396418 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h396418 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h396418 = 8'd254; + default: _theResult___fst_exp__h396418 = 8'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -30602,25 +30608,6 @@ module mkCore(CLK, default: _theResult___fst_sfd__h396419 = 23'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h442113 = 8'd255; - 3'd2: - _theResult___fst_exp__h442113 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h442113 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h442113 = 8'd254; - default: _theResult___fst_exp__h442113 = 8'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -31025,6 +31012,71 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(guard__h359456 or + _theResult___fst_exp__h367504 or + out_exp__h367949 or _theResult___exp__h367946) + begin + case (guard__h359456) + 2'b0, 2'b01: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 = + _theResult___fst_exp__h367504; + 2'b10: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 = + out_exp__h367949; + 2'b11: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 = + _theResult___exp__h367946; + endcase + end + always@(guard__h359456 or + _theResult___fst_exp__h367504 or _theResult___exp__h367946) + begin + case (guard__h359456) + 2'b0: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 = + _theResult___fst_exp__h367504; + 2'b01, 2'b10, 2'b11: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 = + _theResult___exp__h367946; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 or + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or + _theResult___fst_exp__h367504) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h368024 = + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25; + 3'd1: + _theResult___fst_exp__h368024 = + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26; + 3'd2: + _theResult___fst_exp__h368024 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; + 3'd3: + _theResult___fst_exp__h368024 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; + 3'd4: _theResult___fst_exp__h368024 = _theResult___fst_exp__h367504; + default: _theResult___fst_exp__h368024 = 8'd0; + endcase + end always@(guard__h350747 or _theResult___fst_exp__h358848 or out_exp__h359367 or _theResult___exp__h359364) @@ -31077,58 +31129,6 @@ module mkCore(CLK, default: _theResult___fst_exp__h359442 = 8'd0; endcase end - always@(guard__h359456 or - _theResult___fst_exp__h367504 or - out_exp__h367949 or _theResult___exp__h367946) - begin - case (guard__h359456) - 2'b0, 2'b01: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 = - _theResult___fst_exp__h367504; - 2'b10: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 = - out_exp__h367949; - 2'b11: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 = - _theResult___exp__h367946; - endcase - end - always@(guard__h359456 or - _theResult___fst_exp__h367504 or _theResult___exp__h367946) - begin - case (guard__h359456) - 2'b0: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30 = - _theResult___fst_exp__h367504; - 2'b01, 2'b10, 2'b11: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30 = - _theResult___exp__h367946; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 or - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or - _theResult___fst_exp__h367504) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h368024 = - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29; - 3'd1: - _theResult___fst_exp__h368024 = - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30; - 3'd2: - _theResult___fst_exp__h368024 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; - 3'd3: - _theResult___fst_exp__h368024 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; - 3'd4: _theResult___fst_exp__h368024 = _theResult___fst_exp__h367504; - default: _theResult___fst_exp__h368024 = 8'd0; - endcase - end always@(guard__h368386 or _theResult___fst_exp__h376614 or out_exp__h377133 or _theResult___exp__h377130) @@ -31233,69 +31233,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h385844 = 8'd0; endcase end - always@(guard__h350747 or - sfdin__h358842 or out_sfd__h359368 or _theResult___sfd__h359365) - begin - case (guard__h350747) - 2'b0, 2'b01: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 = - sfdin__h358842[56:34]; - 2'b10: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 = - out_sfd__h359368; - 2'b11: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 = - _theResult___sfd__h359365; - endcase - end - always@(guard__h350747 or sfdin__h358842 or _theResult___sfd__h359365) - begin - case (guard__h350747) - 2'b0: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41 = - sfdin__h358842[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41 = - _theResult___sfd__h359365; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 or - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or - sfdin__h358842) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h359443 = - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40; - 3'd1: - _theResult___fst_sfd__h359443 = - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41; - 3'd2: - _theResult___fst_sfd__h359443 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; - 3'd3: - _theResult___fst_sfd__h359443 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; - 3'd4: _theResult___fst_sfd__h359443 = sfdin__h358842[56:34]; - default: _theResult___fst_sfd__h359443 = 23'd0; - endcase - end always@(guard__h359456 or _theResult___snd__h367455 or out_sfd__h367950 or _theResult___sfd__h367947) begin case (guard__h359456) 2'b0, 2'b01: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 = _theResult___snd__h367455[56:34]; 2'b10: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 = out_sfd__h367950; 2'b11: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 = _theResult___sfd__h367947; endcase end @@ -31304,16 +31254,16 @@ module mkCore(CLK, begin case (guard__h359456) 2'b0: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 = _theResult___snd__h367455[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 = _theResult___sfd__h367947; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 or - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43 or + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 or + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or _theResult___snd__h367455) @@ -31321,10 +31271,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h368025 = - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42; + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40; 3'd1: _theResult___fst_sfd__h368025 = - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43; + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41; 3'd2: _theResult___fst_sfd__h368025 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; @@ -31335,6 +31285,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h368025 = 23'd0; endcase end + always@(guard__h350747 or + sfdin__h358842 or out_sfd__h359368 or _theResult___sfd__h359365) + begin + case (guard__h350747) + 2'b0, 2'b01: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 = + sfdin__h358842[56:34]; + 2'b10: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 = + out_sfd__h359368; + 2'b11: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h359365; + endcase + end + always@(guard__h350747 or sfdin__h358842 or _theResult___sfd__h359365) + begin + case (guard__h350747) + 2'b0: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 = + sfdin__h358842[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h359365; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 or + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or + sfdin__h358842) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h359443 = + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42; + 3'd1: + _theResult___fst_sfd__h359443 = + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43; + 3'd2: + _theResult___fst_sfd__h359443 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; + 3'd3: + _theResult___fst_sfd__h359443 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; + 3'd4: _theResult___fst_sfd__h359443 = sfdin__h358842[56:34]; + default: _theResult___fst_sfd__h359443 = 23'd0; + endcase + end always@(guard__h368386 or sfdin__h376608 or out_sfd__h377134 or _theResult___sfd__h377131) begin @@ -31627,66 +31627,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h377222 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h377222) - 2'b0, 2'b01, 2'b10: - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = - guard__h377222 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or - guard__h377222) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - (guard__h377222 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h377222 == 2'b01 || guard__h377222 == 2'b10 || - guard__h377222 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h368386 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h368386) 2'b0, 2'b01, 2'b10: - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = guard__h368386 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or guard__h368386) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = (guard__h368386 == 2'b0) ? @@ -31703,6 +31665,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h377222 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h377222) + 2'b0, 2'b01, 2'b10: + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + guard__h377222 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or + guard__h377222) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + (guard__h377222 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h377222 == 2'b01 || guard__h377222 == 2'b10 || + guard__h377222 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h377222 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -31741,19 +31741,6 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -31975,69 +31962,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h431541 = 8'd0; endcase end - always@(guard__h396446 or - sfdin__h404539 or out_sfd__h405065 or _theResult___sfd__h405062) - begin - case (guard__h396446) - 2'b0, 2'b01: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 = - sfdin__h404539[56:34]; - 2'b10: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 = - out_sfd__h405065; - 2'b11: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 = - _theResult___sfd__h405062; - endcase - end - always@(guard__h396446 or sfdin__h404539 or _theResult___sfd__h405062) - begin - case (guard__h396446) - 2'b0: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76 = - sfdin__h404539[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h405062; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 or - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or - sfdin__h404539) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h405140 = - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75; - 3'd1: - _theResult___fst_sfd__h405140 = - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76; - 3'd2: - _theResult___fst_sfd__h405140 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; - 3'd3: - _theResult___fst_sfd__h405140 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; - 3'd4: _theResult___fst_sfd__h405140 = sfdin__h404539[56:34]; - default: _theResult___fst_sfd__h405140 = 23'd0; - endcase - end always@(guard__h405153 or _theResult___snd__h413152 or out_sfd__h413647 or _theResult___sfd__h413644) begin case (guard__h405153) 2'b0, 2'b01: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 = _theResult___snd__h413152[56:34]; 2'b10: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 = out_sfd__h413647; 2'b11: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 = _theResult___sfd__h413644; endcase end @@ -32046,16 +31983,16 @@ module mkCore(CLK, begin case (guard__h405153) 2'b0: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 = _theResult___snd__h413152[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 = _theResult___sfd__h413644; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 or - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78 or + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 or + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or _theResult___snd__h413152) @@ -32063,10 +32000,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h413722 = - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77; + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75; 3'd1: _theResult___fst_sfd__h413722 = - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78; + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76; 3'd2: _theResult___fst_sfd__h413722 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; @@ -32077,6 +32014,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h413722 = 23'd0; endcase end + always@(guard__h396446 or + sfdin__h404539 or out_sfd__h405065 or _theResult___sfd__h405062) + begin + case (guard__h396446) + 2'b0, 2'b01: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 = + sfdin__h404539[56:34]; + 2'b10: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 = + out_sfd__h405065; + 2'b11: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h405062; + endcase + end + always@(guard__h396446 or sfdin__h404539 or _theResult___sfd__h405062) + begin + case (guard__h396446) + 2'b0: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 = + sfdin__h404539[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h405062; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 or + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or + sfdin__h404539) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h405140 = + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77; + 3'd1: + _theResult___fst_sfd__h405140 = + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78; + 3'd2: + _theResult___fst_sfd__h405140 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; + 3'd3: + _theResult___fst_sfd__h405140 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; + 3'd4: _theResult___fst_sfd__h405140 = sfdin__h404539[56:34]; + default: _theResult___fst_sfd__h405140 = 23'd0; + endcase + end always@(guard__h414083 or sfdin__h422305 or out_sfd__h422831 or _theResult___sfd__h422828) begin @@ -32926,23 +32913,61 @@ module mkCore(CLK, begin case (guard__h442141) 2'b0, 2'b01, 2'b10: - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + guard__h442141 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or + guard__h442141) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + (guard__h442141 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h442141 != 2'b01 && guard__h442141 != 2'b10 && + guard__h442141 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h442141 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h442141) + 2'b0, 2'b01, 2'b10: + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = guard__h442141 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or guard__h442141) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = (guard__h442141 == 2'b0) ? @@ -32964,23 +32989,23 @@ module mkCore(CLK, begin case (guard__h450848) 2'b0, 2'b01, 2'b10: - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = guard__h450848 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or guard__h450848) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = (guard__h450848 == 2'b0) ? @@ -32997,44 +33022,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h442141 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h442141) - 2'b0, 2'b01, 2'b10: - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h442141 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h442141) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h442141 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h442141 != 2'b01 && guard__h442141 != 2'b10 && - guard__h442141 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end always@(guard__h450848 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -33111,66 +33098,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468614 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h468614) - 2'b0, 2'b01, 2'b10: - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h468614 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h468614) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - (guard__h468614 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h468614 == 2'b01 || guard__h468614 == 2'b10 || - guard__h468614 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end always@(guard__h459778 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (guard__h459778) 2'b0, 2'b01, 2'b10: - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = guard__h459778 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or guard__h459778) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = (guard__h459778 == 2'b0) ? @@ -33187,6 +33136,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end + always@(guard__h468614 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h468614) + 2'b0, 2'b01, 2'b10: + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + guard__h468614 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or + guard__h468614) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + (guard__h468614 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + (guard__h468614 == 2'b01 || guard__h468614 == 2'b10 || + guard__h468614 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end always@(guard__h468614 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -33499,21 +33486,21 @@ module mkCore(CLK, _theResult___exp__h585728; endcase end - always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h586424 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577112) + case (guard__h586424) 2'b0, 2'b01, 2'b10: - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h577112 == 2'b11 && + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h586424 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586424) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33522,12 +33509,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h577112 == 2'b0) ? + (guard__h586424 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h577112 == 2'b01 || guard__h577112 == 2'b10 || - guard__h577112 == 2'b11) && + (guard__h586424 == 2'b01 || guard__h586424 == 2'b10 || + guard__h586424 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33538,21 +33525,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595493) + case (guard__h577112) 2'b0, 2'b01, 2'b10: - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h595493 == 2'b11 && + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h577112 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33561,12 +33548,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h595493 == 2'b0) ? + (guard__h577112 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h595493 == 2'b01 || guard__h595493 == 2'b10 || - guard__h595493 == 2'b11) && + (guard__h577112 == 2'b01 || guard__h577112 == 2'b10 || + guard__h577112 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33577,21 +33564,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h586424 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h586424) + case (guard__h595493) 2'b0, 2'b01, 2'b10: - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h586424 == 2'b11 && + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h595493 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586424) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33600,12 +33587,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h586424 == 2'b0) ? + (guard__h595493 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h586424 == 2'b01 || guard__h586424 == 2'b10 || - guard__h586424 == 2'b11) && + (guard__h595493 == 2'b01 || guard__h595493 == 2'b10 || + guard__h595493 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33655,21 +33642,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595493) + case (guard__h577112) 2'b0, 2'b01, 2'b10: - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h595493 != 2'b11 || + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h577112 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33678,12 +33665,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h595493 == 2'b0) ? + (guard__h577112 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595493 != 2'b01 && guard__h595493 != 2'b10 && - guard__h595493 != 2'b11 || + guard__h577112 != 2'b01 && guard__h577112 != 2'b10 && + guard__h577112 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33694,21 +33681,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577112) + case (guard__h595493) 2'b0, 2'b01, 2'b10: - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h577112 != 2'b11 || + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h595493 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33717,12 +33704,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h577112 == 2'b0) ? + (guard__h595493 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h577112 != 2'b01 && guard__h577112 != 2'b10 && - guard__h577112 != 2'b11 || + guard__h595493 != 2'b01 && guard__h595493 != 2'b10 && + guard__h595493 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -34156,58 +34143,16 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h556189 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h556189) - 2'b0, 2'b01, 2'b10: - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h556189 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556189) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h556189 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h556189 != 2'b01 && guard__h556189 != 2'b10 && - guard__h556189 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h537808 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h537808) 2'b0, 2'b01, 2'b10: - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = guard__h537808 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -34218,12 +34163,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = (guard__h537808 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -34233,6 +34178,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h556189 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h556189) + 2'b0, 2'b01, 2'b10: + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h556189 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556189) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h556189 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h556189 != 2'b01 && guard__h556189 != 2'b10 && + guard__h556189 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -35479,29 +35466,29 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(k__h675032 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin case (k__h675032) 1'd0: - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or @@ -35524,7 +35511,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037 or + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 or @@ -35546,7 +35533,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 || - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037; + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037; endcase end always@(fetchStage$pipelines_0_first or @@ -35610,29 +35597,29 @@ module mkCore(CLK, coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage$pipelines_1_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_1_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin case (fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107) 1'd0: - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235 = + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235 = + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end + always@(fetchStage$pipelines_1_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_1_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or @@ -35736,10 +35723,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = + coreFix_memExe_lsq$enqLdTag[4:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = + coreFix_memExe_lsq$enqStTag[4:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -35747,10 +35734,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = - coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = - coreFix_memExe_lsq$enqStTag[4:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_1_first or @@ -35962,6 +35949,24 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = + 3'd0; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -36176,24 +36181,6 @@ module mkCore(CLK, endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = - 3'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v index 4bb9ec5..4d4b2a0 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v @@ -69,6 +69,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 reg // set_verbosity_logdelay I 64 unused +// start_is_running I 1 unused // start_tohost_addr I 64 reg // start_fromhost_addr I 64 reg // cpu_imem_master_awready I 1 @@ -140,6 +141,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -333,6 +335,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1054,7 +1057,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1167,8 +1171,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h6490; - reg [31 : 0] v__h6484; + reg [31 : 0] v__h6500; + reg [31 : 0] v__h6494; // synopsys translate_on // action method set_verbosity @@ -1793,6 +1797,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2246,6 +2251,7 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; assign proc$start_fromhostAddr = start_fromhost_addr ; + assign proc$start_running = start_is_running ; assign proc$start_startpc = 64'h0000000000001000 ; assign proc$start_tohostAddr = start_tohost_addr ; assign proc$EN_start = EN_start ; @@ -2265,14 +2271,14 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h6490 = $stime; + v__h6500 = $stime; #0; end - v__h6484 = v__h6490 / 32'd10; + v__h6494 = v__h6500 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h6484, + v__h6494, 64'h0000000000001000, start_tohost_addr, start_fromhost_addr); diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v index d5cd23c..a6d7266 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v @@ -3313,17 +3313,17 @@ module mkFabric_2x3(CLK, 8'd0 : x__h12203 ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_0$D_OUT[3:0], 66'd3, @@ -3734,23 +3734,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: @@ -3761,9 +3761,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && @@ -3862,23 +3862,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: @@ -3889,9 +3889,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index 368609d..b77f7ec 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -77,6 +77,7 @@ // debug_module_mem_server_rlast O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 unused // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -159,6 +160,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -377,6 +379,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1285,6 +1288,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_memReq_deq, core_0$RDY_tlbToMem_memReq_first, core_0$RDY_tlbToMem_respLd_enq, + core_0$coreReq_start_running, core_0$mmioToPlatform_cRq_notEmpty, core_0$mmioToPlatform_cRs_first, core_0$recvDoStats_x, @@ -1904,60 +1908,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163686; - reg [31 : 0] v__h163250; - reg [31 : 0] v__h5300; - reg [31 : 0] v__h5473; - reg [31 : 0] v__h5733; - reg [31 : 0] v__h7875; - reg [31 : 0] v__h8090; - reg [31 : 0] v__h2450; - reg [31 : 0] v__h4123; - reg [31 : 0] v__h9260; - reg [31 : 0] v__h9753; - reg [31 : 0] v__h9916; - reg [31 : 0] v__h135207; - reg [31 : 0] v__h135374; - reg [31 : 0] v__h137477; - reg [31 : 0] v__h154821; - reg [31 : 0] v__h134588; - reg [31 : 0] v__h161515; - reg [31 : 0] v__h162023; - reg [31 : 0] v__h2444; - reg [31 : 0] v__h4117; - reg [31 : 0] v__h5294; - reg [31 : 0] v__h5467; - reg [31 : 0] v__h5727; - reg [31 : 0] v__h7869; - reg [31 : 0] v__h8084; - reg [31 : 0] v__h9254; - reg [31 : 0] v__h9747; - reg [31 : 0] v__h9910; - reg [31 : 0] v__h134582; - reg [31 : 0] v__h135201; - reg [31 : 0] v__h135368; - reg [31 : 0] v__h137471; - reg [31 : 0] v__h154815; - reg [31 : 0] v__h161509; - reg [31 : 0] v__h162017; - reg [31 : 0] v__h163244; - reg [31 : 0] v__h163680; + reg [31 : 0] v__h163696; + reg [31 : 0] v__h163258; + reg [31 : 0] v__h5308; + reg [31 : 0] v__h5481; + reg [31 : 0] v__h5741; + reg [31 : 0] v__h7883; + reg [31 : 0] v__h8098; + reg [31 : 0] v__h2458; + reg [31 : 0] v__h4131; + reg [31 : 0] v__h9268; + reg [31 : 0] v__h9761; + reg [31 : 0] v__h9924; + reg [31 : 0] v__h135215; + reg [31 : 0] v__h135382; + reg [31 : 0] v__h137485; + reg [31 : 0] v__h154829; + reg [31 : 0] v__h134596; + reg [31 : 0] v__h161523; + reg [31 : 0] v__h162031; + reg [31 : 0] v__h2452; + reg [31 : 0] v__h4125; + reg [31 : 0] v__h5302; + reg [31 : 0] v__h5475; + reg [31 : 0] v__h5735; + reg [31 : 0] v__h7877; + reg [31 : 0] v__h8092; + reg [31 : 0] v__h9262; + reg [31 : 0] v__h9755; + reg [31 : 0] v__h9918; + reg [31 : 0] v__h134590; + reg [31 : 0] v__h135209; + reg [31 : 0] v__h135376; + reg [31 : 0] v__h137479; + reg [31 : 0] v__h154823; + reg [31 : 0] v__h161517; + reg [31 : 0] v__h162025; + reg [31 : 0] v__h163252; + reg [31 : 0] v__h163690; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26, + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, @@ -1967,39 +1971,39 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, - data64__h148647, - dword__h94449, - ld_data__h132736, - old_dword__h90139, - w1__h48006, - w1__h48011, - w2__h48007, - w2__h48013, - x__h48002; + data64__h148655, + dword__h94457, + ld_data__h132744, + old_dword__h90147, + w1__h48014, + w1__h48019, + w2__h48015, + w2__h48021, + x__h48010; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; - reg [7 : 0] strb8__h148648; + reg [7 : 0] strb8__h148656; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; - reg [2 : 0] x__h61720; - reg [1 : 0] CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; + reg [2 : 0] x__h61728; + reg [1 : 0] CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, + CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, - x__h61727, - x__h82707; + x__h61735, + x__h82715; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - new_cline__h135510; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1597, + new_cline__h135518; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1592, + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408; wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; @@ -2017,89 +2021,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - data__h31730, - failed_testnum__h163293, - line_addr__h102513, - line_addr__h102599, - mask__h90136, - mem_req_rd_addr_araddr__h134808, - mem_req_wr_addr_awaddr__h148732, - mmioPlatform_fromHostQ_data_0__h42577, - mmioPlatform_mtime__h37044, - mmioPlatform_reqData__h48598, - n__read_addr__h61588, - n__read_addr__h61673, - n__read_addr__h80469, - n__read_addr__h80548, - n__read_snd_addr__h124040, - newData__h31811, - newData__h34741, - new_dword__h90140, - op_result__h48614, - op_result__h49144, - op_result__h49149, - op_result__h49154, - op_result__h49159, - op_result__h49165, - op_result__h49172, - op_result__h49178, - result__h48057, - result__h48181, - result__h48209, - result__h48237, - result__h48265, - result__h48293, - result__h48321, - result__h48349, - result__h48377, - result__h48422, - result__h48450, - result__h48478, - result__h48506, - result__h48547, - result__h48575, - result__h48701, - result__h48728, - result__h48755, - result__h48782, - result__h48809, - result__h48836, - result__h48863, - result__h48890, - result__h48934, - result__h48961, - result__h48988, - result__h49015, - result__h49055, - result__h49082, - result__h49199, - result__h49265, - result__h49331, - result__h49397, - result__h49463, - result__h49529, - result__h49595, - result__h49657, - result__h49702, - result__h49768, - result__h49834, - result__h49892, - result__h49937, - w1___1__h48116, - w2___1__h48117, - x1_avValue_data__h40249, - x1_avValue_data__h44935, - x__h31922, - x__h34832, - x__h37192, - x__h40767, - x__h40778, - x__h42860, - x__h42871, - x__h50114, - x__h91302, - y__h91303, - y__h91304; + data__h31738, + failed_testnum__h163301, + line_addr__h102521, + line_addr__h102607, + mask__h90144, + mem_req_rd_addr_araddr__h134816, + mem_req_wr_addr_awaddr__h148740, + mmioPlatform_fromHostQ_data_0__h42585, + mmioPlatform_mtime__h37052, + mmioPlatform_reqData__h48606, + n__read_addr__h61596, + n__read_addr__h61681, + n__read_addr__h80477, + n__read_addr__h80556, + n__read_snd_addr__h124048, + newData__h31819, + newData__h34749, + new_dword__h90148, + op_result__h48622, + op_result__h49152, + op_result__h49157, + op_result__h49162, + op_result__h49167, + op_result__h49173, + op_result__h49180, + op_result__h49186, + result__h48065, + result__h48189, + result__h48217, + result__h48245, + result__h48273, + result__h48301, + result__h48329, + result__h48357, + result__h48385, + result__h48430, + result__h48458, + result__h48486, + result__h48514, + result__h48555, + result__h48583, + result__h48709, + result__h48736, + result__h48763, + result__h48790, + result__h48817, + result__h48844, + result__h48871, + result__h48898, + result__h48942, + result__h48969, + result__h48996, + result__h49023, + result__h49063, + result__h49090, + result__h49207, + result__h49273, + result__h49339, + result__h49405, + result__h49471, + result__h49537, + result__h49603, + result__h49665, + result__h49710, + result__h49776, + result__h49842, + result__h49900, + result__h49945, + w1___1__h48124, + w2___1__h48125, + x1_avValue_data__h40257, + x1_avValue_data__h44943, + x__h31930, + x__h34840, + x__h37200, + x__h40775, + x__h40786, + x__h42868, + x__h42879, + x__h50122, + x__h91310, + y__h91311, + y__h91312; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; @@ -2111,16 +2115,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h31523, - v__h31560, - w18006_BITS_31_TO_0__q7, - w28007_BITS_31_TO_0__q8, - x_data__h30313; + v__h31531, + v__h31568, + w18014_BITS_31_TO_0__q7, + w28015_BITS_31_TO_0__q8, + x_data__h30321; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; - wire [5 : 0] x__h134843, x__h148757; + wire [5 : 0] x__h134851, x__h148765; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; - wire [3 : 0] b__h134515, b__h2344; - wire [2 : 0] n__read_id__h61592, n__read_id__h61677, x__h7705; + wire [3 : 0] b__h134523, b__h2352; + wire [2 : 0] n__read_id__h61600, n__read_id__h61685, x__h7713; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, @@ -2139,8 +2143,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315, - IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664, IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, @@ -2155,8 +2159,8 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019, NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099, NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373, - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715, + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714, NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758, NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763, @@ -2177,33 +2181,33 @@ module mkProc(CLK, NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370, NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477, NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530, mmioPlatform_cycle_47_ULT_99___d348, mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h29938, - mmioPlatform_reqBE_BIT_4___h29898, + mmioPlatform_reqBE_BIT_0___h29946, + mmioPlatform_reqBE_BIT_4___h29906, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61593, - n__read_child__h61678, - n__read_child__h80472, - n__read_child__h80551, - n__read_snd_id__h124041, + n__read_child__h61601, + n__read_child__h61686, + n__read_child__h80480, + n__read_child__h80559, + n__read_snd_id__h124049, propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, - x__h61406, - x__h75220, - x__h80291; + x__h61414, + x__h75228, + x__h80299; // action method start - assign RDY_start = CAN_FIRE_start ; + assign RDY_start = mmioPlatform_state == 2'd0 ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; @@ -2506,6 +2510,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -3183,32 +3188,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3288,14 +3297,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2344 == 4'd0 ; + b__h2352 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2344 != 4'd0 && + b__h2352 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3408,7 +3417,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42860 == 64'd0 || + x__h42868 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3548,7 +3557,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3566,7 +3575,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3584,7 +3593,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3594,7 +3603,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3603,7 +3612,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3614,7 +3623,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3623,7 +3632,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -3631,7 +3640,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -3655,7 +3664,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3672,15 +3681,15 @@ module mkProc(CLK, // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3728,13 +3737,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134515 == 4'd0 ; + b__h134523 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134515 != 4'd0 && + b__h134523 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3838,7 +3847,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30313 } ; + x_data__h30321 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -3878,7 +3887,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31730 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31738 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3903,10 +3912,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102513, + { line_addr__h102521, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102599, + { line_addr__h102607, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3914,14 +3923,14 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1597, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4020,7 +4029,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48002 } ; + x__h48010 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4029,7 +4038,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50114, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50122, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4037,47 +4046,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42860 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42868 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42860 != 64'd0 ; + x__h42868 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 == 64'd0 ; + x__h40775 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 ; + x__h61414 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 ; + x__h80299 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h124040, n__read_snd_id__h124041 } ; + { 1'd1, n__read_snd_addr__h124048, n__read_snd_id__h124049 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4138,11 +4147,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2344 - 4'd1 ; + b__h2352 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2344 ; + b__h2352 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4191,11 +4200,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134515 - 4'd1 ; + b__h134523 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134515 ; + b__h134523 ; // register cfg_verbosity assign cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -4255,7 +4264,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134808, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134816, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4266,13 +4275,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148732, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148740, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148647, strb8__h148648, 1'd1 } ; + { data64__h148655, strb8__h148656, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4284,7 +4293,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135510 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135518 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4315,10 +4324,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4332,15 +4341,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102513 : - line_addr__h102599 ; + line_addr__h102521 : + line_addr__h102607 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4501,7 +4510,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34741 : + newData__h34749 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4510,7 +4519,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h31811 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h31819 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4727,7 +4736,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7705, + x__h7713, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -4827,6 +4836,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -4922,7 +4932,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132736, llc$dma_respLd_first[3] } ; + { ld_data__h132744, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5058,7 +5068,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135510, + { new_cline__h135518, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5134,7 +5144,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94449, 3'd1 } ; + { 4'd0, dword__h94457, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5185,7 +5195,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5215,11 +5225,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5437,47 +5447,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), - .amoExec_current_data(x__h37192), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h31922)); + .amoExec_current_data(x__h37200), + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h31930)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37044), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h34832)); + .amoExec_current_data(mmioPlatform_mtime__h37052), + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h34840)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42577), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h40778)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42585), + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h40786)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h42871)); + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h42879)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40249 } } ; + x1_avValue_data__h40257 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5493,7 +5503,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h31811 <= mmioPlatform_mtime ; + newData__h31819 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5558,7 +5568,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - x__h75220 } ; + x__h75228 } ; assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5567,38 +5577,38 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1592 = + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1597 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1592, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829 = @@ -5737,11 +5747,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42860 == 64'd0 : - x__h40767 == 64'd0, + x__h42868 == 64'd0 : + x__h40775 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44935 } ; + x1_avValue_data__h44943 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -5838,14 +5848,14 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 || IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && @@ -5981,58 +5991,58 @@ module mkProc(CLK, !propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = - { CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, + { CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = - { CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - x__h82707 } ; + x__h82715 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = - { CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = - { CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, - x__h61720, - x__h61727 } ; - assign b__h134515 = + { CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12, + x__h61728, + x__h61735 } ; + assign b__h134523 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2344 = + assign b__h2352 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31730 = + assign data__h31738 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31523, 32'd0 } ; - assign failed_testnum__h163293 = + { v__h31531, 32'd0 } ; + assign failed_testnum__h163301 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102513 = + assign line_addr__h102521 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102599 = + assign line_addr__h102607 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 = - line_addr__h102599 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 = - line_addr__h102513 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90136 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = + line_addr__h102607 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = + line_addr__h102521 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90144 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6057,14 +6067,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134808 = - { llc$to_mem_toM_first[68:11], x__h134843 } ; - assign mem_req_wr_addr_awaddr__h148732 = - { llc$to_mem_toM_first[639:582], x__h148757 } ; + assign mem_req_rd_addr_araddr__h134816 = + { llc$to_mem_toM_first[68:11], x__h134851 } ; + assign mem_req_wr_addr_awaddr__h148740 = + { llc$to_mem_toM_first[639:582], x__h148765 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42577 = + assign mmioPlatform_fromHostQ_data_0__h42585 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6075,18 +6085,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37044 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37052 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34741 ; + mmioPlatform_mtimecmp_0 <= newData__h34749 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h29938 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h29898 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48598 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h29946 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h29906 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48606 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6118,105 +6128,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61588 = + assign n__read_addr__h61596 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61673 = + assign n__read_addr__h61681 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80469 = + assign n__read_addr__h80477 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : 64'd0 ; - assign n__read_addr__h80548 = + assign n__read_addr__h80556 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : 64'd0 ; - assign n__read_child__h61593 = + assign n__read_child__h61601 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61678 = + assign n__read_child__h61686 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80472 = + assign n__read_child__h80480 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; - assign n__read_child__h80551 = + assign n__read_child__h80559 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; - assign n__read_id__h61592 = + assign n__read_id__h61600 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61677 = + assign n__read_id__h61685 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h124040 = + assign n__read_snd_addr__h124048 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h124041 = + assign n__read_snd_id__h124049 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h31811 = + assign newData__h31819 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h31922 : + x__h31930 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34741 = + assign newData__h34749 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h34832 : + x__h34840 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h135510 = + assign new_cline__h135518 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90140 = x__h91302 | y__h91303 ; - assign op_result__h48614 = + assign new_dword__h90148 = x__h91310 | y__h91311 ; + assign op_result__h48622 = IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; - assign op_result__h49144 = w1__h48011 ^ w2__h48013 ; - assign op_result__h49149 = w1__h48011 & w2__h48013 ; - assign op_result__h49154 = w1__h48011 | w2__h48013 ; - assign op_result__h49159 = - (w1__h48011 < w2__h48013) ? w1__h48011 : w2__h48013 ; - assign op_result__h49165 = - (w1__h48011 <= w2__h48013) ? w2__h48013 : w1__h48011 ; - assign op_result__h49172 = + assign op_result__h49152 = w1__h48019 ^ w2__h48021 ; + assign op_result__h49157 = w1__h48019 & w2__h48021 ; + assign op_result__h49162 = w1__h48019 | w2__h48021 ; + assign op_result__h49167 = + (w1__h48019 < w2__h48021) ? w1__h48019 : w2__h48021 ; + assign op_result__h49173 = + (w1__h48019 <= w2__h48021) ? w2__h48021 : w1__h48019 ; + assign op_result__h49180 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w1__h48011 : - w2__h48013 ; - assign op_result__h49178 = + w1__h48019 : + w2__h48021 ; + assign op_result__h49186 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w2__h48013 : - w1__h48011 ; + w2__h48021 : + w1__h48019 ; assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6227,126 +6237,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48057 = + assign result__h48065 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; - assign result__h48181 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48209 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48237 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48265 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48293 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48321 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48349 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48377 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48422 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48450 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48478 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48506 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48547 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48575 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48701 = + assign result__h48189 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48217 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48245 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48273 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48301 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48329 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48357 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48385 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48430 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48458 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48486 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48514 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48555 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48583 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48709 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48728 = + assign result__h48736 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48755 = + assign result__h48763 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48782 = + assign result__h48790 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48809 = + assign result__h48817 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48836 = + assign result__h48844 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48863 = + assign result__h48871 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48890 = + assign result__h48898 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48934 = + assign result__h48942 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48961 = + assign result__h48969 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48988 = + assign result__h48996 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49015 = + assign result__h49023 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49055 = + assign result__h49063 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49082 = + assign result__h49090 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49199 = + assign result__h49207 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49265 = + assign result__h49273 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49331 = + assign result__h49339 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49397 = + assign result__h49405 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49463 = + assign result__h49471 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49529 = + assign result__h49537 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49595 = + assign result__h49603 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49657 = + assign result__h49665 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; - assign result__h49702 = + assign result__h49710 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49768 = + assign result__h49776 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49834 = + assign result__h49842 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49892 = + assign result__h49900 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; - assign result__h49937 = + assign result__h49945 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31523 = mmioPlatform_waitUpperMSIPCRs ? v__h31560 : 32'd0 ; - assign v__h31560 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18006_BITS_31_TO_0__q7 = w1__h48006[31:0] ; - assign w1___1__h48116 = { 32'd0, w1__h48006[31:0] } ; - assign w28007_BITS_31_TO_0__q8 = w2__h48007[31:0] ; - assign w2___1__h48117 = { 32'd0, w2__h48007[31:0] } ; - assign x1_avValue_data__h40249 = + assign v__h31531 = mmioPlatform_waitUpperMSIPCRs ? v__h31568 : 32'd0 ; + assign v__h31568 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18014_BITS_31_TO_0__q7 = w1__h48014[31:0] ; + assign w1___1__h48124 = { 32'd0, w1__h48014[31:0] } ; + assign w28015_BITS_31_TO_0__q8 = w2__h48015[31:0] ; + assign w2___1__h48125 = { 32'd0, w2__h48015[31:0] } ; + assign x1_avValue_data__h40257 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44935 = + assign x1_avValue_data__h44943 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134843 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148757 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37192 = mmioPlatform_mtimecmp_0 ; - assign x__h40767 = + assign x__h134851 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148765 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37200 = mmioPlatform_mtimecmp_0 ; + assign x__h40775 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40778 : + x__h40786 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; - assign x__h42860 = + assign x__h42868 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42871 : + x__h42879 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6355,29 +6365,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50114 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61406 = + assign x__h50122 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61414 = SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; - assign x__h75220 = + assign x__h75228 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; - assign x__h7705 = + assign x__h7713 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80291 = + assign x__h80299 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; - assign x__h91302 = old_dword__h90139 & y__h91304 ; - assign x_data__h30313 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91303 = + assign x__h91310 = old_dword__h90147 & y__h91312 ; + assign x_data__h30321 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91311 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90136 ; - assign y__h91304 = + mask__h90144 ; + assign y__h91312 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -6406,141 +6416,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132736 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132736 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132736 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132736 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132736 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132736 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132736 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132736 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132744 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132744 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132744 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132744 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132744 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132744 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132744 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132744 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148647 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148647 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148647 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148647 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148647 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148647 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148647 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148647 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h148655 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148655 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148655 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148655 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148655 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148655 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148655 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148655 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148648 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148648 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148648 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148648 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148648 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148648 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148648 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148648 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148656 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148656 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148656 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148656 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148656 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148656 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148656 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148656 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48181 or - result__h48209 or - result__h48237 or - result__h48265 or - result__h48293 or - result__h48321 or result__h48349 or result__h48377) + result__h48189 or + result__h48217 or + result__h48245 or + result__h48273 or + result__h48301 or + result__h48329 or result__h48357 or result__h48385) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48181; + result__h48189; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48209; + result__h48217; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48237; + result__h48245; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48265; + result__h48273; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48293; + result__h48301; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48321; + result__h48329; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48349; + result__h48357; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48377; + result__h48385; endcase end always@(mmioPlatform_curReq or - result__h48422 or - result__h48450 or result__h48478 or result__h48506) + result__h48430 or + result__h48458 or result__h48486 or result__h48514) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48422; + result__h48430; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48450; + result__h48458; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48478; + result__h48486; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48506; + result__h48514; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48547 or result__h48575) + always@(mmioPlatform_curReq or result__h48555 or result__h48583) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48547; + result__h48555; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48575; + result__h48583; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -6552,102 +6562,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h48007 = + w2__h48015 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48007 = + w2__h48015 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - w2__h48007 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h48015 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h48007 = + w2__h48015 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w2___1__h48117 or + w2___1__h48125 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48013 = + w2__h48021 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48013 = + w2__h48021 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; - 2'b10: w2__h48013 = w2___1__h48117; + 2'b10: w2__h48021 = w2___1__h48125; 2'b11: - w2__h48013 = + w2__h48021 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_curReq or - result__h48934 or - result__h48961 or result__h48988 or result__h49015) + result__h48942 or + result__h48969 or result__h48996 or result__h49023) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48934; + result__h48942; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48961; + result__h48969; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48988; + result__h48996; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49015; + result__h49023; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48701 or - result__h48728 or - result__h48755 or - result__h48782 or - result__h48809 or - result__h48836 or result__h48863 or result__h48890) + result__h48709 or + result__h48736 or + result__h48763 or + result__h48790 or + result__h48817 or + result__h48844 or result__h48871 or result__h48898) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48701; + result__h48709; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48728; + result__h48736; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48755; + result__h48763; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48782; + result__h48790; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48809; + result__h48817; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48836; + result__h48844; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48863; + result__h48871; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48890; + result__h48898; endcase end - always@(mmioPlatform_curReq or result__h49055 or result__h49082) + always@(mmioPlatform_curReq or result__h49063 or result__h49090) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49055; + result__h49063; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49082; + result__h49090; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -6659,41 +6669,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h48006 = + w1__h48014 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48006 = + w1__h48014 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - w1__h48006 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h48014 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h48006 = + w1__h48014 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w1___1__h48116 or + w1___1__h48124 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48011 = + w1__h48019 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48011 = + w1__h48019 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; - 2'b10: w1__h48011 = w1___1__h48116; + 2'b10: w1__h48019 = w1___1__h48124; 2'b11: - w1__h48011 = + w1__h48019 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w18006_BITS_31_TO_0__q7 or + w18014_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) @@ -6705,7 +6715,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - { {32{w18006_BITS_31_TO_0__q7[31]}}, w18006_BITS_31_TO_0__q7 }; + { {32{w18014_BITS_31_TO_0__q7[31]}}, w18014_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; @@ -6714,7 +6724,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w28007_BITS_31_TO_0__q8 or + w28015_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) @@ -6726,115 +6736,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - { {32{w28007_BITS_31_TO_0__q8[31]}}, w28007_BITS_31_TO_0__q8 }; + { {32{w28015_BITS_31_TO_0__q8[31]}}, w28015_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49178 or - w2__h48013 or - op_result__h48614 or - op_result__h49144 or - op_result__h49149 or - op_result__h49154 or - op_result__h49172 or op_result__h49159 or op_result__h49165) + op_result__h49186 or + w2__h48021 or + op_result__h48622 or + op_result__h49152 or + op_result__h49157 or + op_result__h49162 or + op_result__h49180 or op_result__h49167 or op_result__h49173) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - w2__h48013; + w2__h48021; 4'd1: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h48614; + op_result__h48622; 4'd2: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49144; + op_result__h49152; 4'd3: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49149; + op_result__h49157; 4'd4: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49154; + op_result__h49162; 4'd5: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49172; + op_result__h49180; 4'd7: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49159; + op_result__h49167; 4'd8: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49165; + op_result__h49173; default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49178; + op_result__h49186; endcase end always@(mmioPlatform_curReq or - result__h49657 or - result__h49702 or result__h49768 or result__h49834) + result__h49665 or + result__h49710 or result__h49776 or result__h49842) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49657; + result__h49665; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49702; + result__h49710; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49768; + result__h49776; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49834; + result__h49842; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48057 or - result__h49199 or - result__h49265 or - result__h49331 or - result__h49397 or - result__h49463 or result__h49529 or result__h49595) + result__h48065 or + result__h49207 or + result__h49273 or + result__h49339 or + result__h49405 or + result__h49471 or result__h49537 or result__h49603) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h48057; + result__h48065; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49199; + result__h49207; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49265; + result__h49273; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49331; + result__h49339; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49397; + result__h49405; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49463; + result__h49471; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49529; + result__h49537; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49595; + result__h49603; endcase end - always@(mmioPlatform_curReq or result__h49892 or result__h49937) + always@(mmioPlatform_curReq or result__h49900 or result__h49945) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49892; + result__h49900; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49937; + result__h49945; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -6846,15 +6856,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h48002 = + x__h48010 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; 2'b01: - x__h48002 = + x__h48010 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; 2'b10: - x__h48002 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h48010 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h48002 = + x__h48010 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end @@ -6938,278 +6948,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; endcase end - always@(x__h61406 or n__read_id__h61592 or n__read_id__h61677) + always@(x__h61414 or n__read_id__h61600 or n__read_id__h61685) begin - case (x__h61406) - 1'd0: x__h61720 = n__read_id__h61592; - 1'd1: x__h61720 = n__read_id__h61677; + case (x__h61414) + 1'd0: x__h61728 = n__read_id__h61600; + 1'd1: x__h61728 = n__read_id__h61685; endcase end - always@(x__h61406 or n__read_child__h61593 or n__read_child__h61678) + always@(x__h61414 or n__read_child__h61601 or n__read_child__h61686) begin - case (x__h61406) - 1'd0: x__h61727 = n__read_child__h61593; - 1'd1: x__h61727 = n__read_child__h61678; + case (x__h61414) + 1'd0: x__h61735 = n__read_child__h61601; + 1'd1: x__h61735 = n__read_child__h61686; endcase end - always@(x__h61406 or + always@(x__h61414 or propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = + CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12 = propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; 1'd1: - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = + CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12 = propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; endcase end - always@(x__h61406 or + always@(x__h61414 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; 1'd1: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; endcase end - always@(x__h61406 or + always@(x__h61414 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; 1'd1: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; endcase end - always@(x__h61406 or n__read_addr__h61588 or n__read_addr__h61673) + always@(x__h61414 or n__read_addr__h61596 or n__read_addr__h61681) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = - n__read_addr__h61588; + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15 = + n__read_addr__h61596; 1'd1: - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = - n__read_addr__h61673; + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15 = + n__read_addr__h61681; endcase end - always@(x__h80291 or n__read_child__h80472 or n__read_child__h80551) + always@(x__h80299 or n__read_child__h80480 or n__read_child__h80559) begin - case (x__h80291) - 1'd0: x__h82707 = n__read_child__h80472; - 1'd1: x__h82707 = n__read_child__h80551; + case (x__h80299) + 1'd0: x__h82715 = n__read_child__h80480; + 1'd1: x__h82715 = n__read_child__h80559; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80291 or + always@(x__h80299 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : 2'd0; 1'd1: - CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : 2'd0; endcase end - always@(x__h80291 or + always@(x__h80299 or NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; 1'd1: - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; endcase end - always@(x__h80291 or n__read_addr__h80469 or n__read_addr__h80548) + always@(x__h80299 or n__read_addr__h80477 or n__read_addr__h80556) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = - n__read_addr__h80469; + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26 = + n__read_addr__h80477; 1'd1: - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = - n__read_addr__h80548; + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26 = + n__read_addr__h80556; endcase end @@ -7625,14 +7635,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163686 = $stime; + v__h163696 = $stime; #0; end - v__h163680 = v__h163686 / 32'd10; + v__h163690 = v__h163696 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163680, + v__h163690, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -7653,17 +7663,17 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && + x__h61414 && NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && + x__h61414 && NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && + x__h61414 && NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) @@ -7683,17 +7693,17 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && + x__h80299 && NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && + x__h80299 && NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && + x__h80299 && NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) @@ -7702,14 +7712,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163250 = $stime; + v__h163258 = $stime; #0; end - v__h163244 = v__h163250 / 32'd10; + v__h163252 = v__h163258 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163244, + v__h163252, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7719,7 +7729,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163293); + $display("FAIL %0d", failed_testnum__h163301); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -7727,14 +7737,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5300 = $stime; + v__h5308 = $stime; #0; end - v__h5294 = v__h5300 / 32'd10; + v__h5302 = v__h5308 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5294); + $display("%0d: %m.rl_handle_read_rsps ", v__h5302); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7794,16 +7804,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5473 = $stime; + v__h5481 = $stime; #0; end - v__h5467 = v__h5473 / 32'd10; + v__h5475 = v__h5481 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5467); + v__h5475); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -7907,14 +7917,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5733 = $stime; + v__h5741 = $stime; #0; end - v__h5727 = v__h5733 / 32'd10; + v__h5735 = v__h5741 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5727); + $display("%d: %m.rl_handle_write_req: St request:", v__h5735); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8084,15 +8094,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h7875 = $stime; + v__h7883 = $stime; #0; end - v__h7869 = v__h7875 / 32'd10; + v__h7877 = v__h7883 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h7869); + $display("%0d: ERROR: CreditCounter: overflow", v__h7877); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8142,7 +8152,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7705); + $write("'h%h", x__h7713); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8273,16 +8283,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8090 = $stime; + v__h8098 = $stime; #0; end - v__h8084 = v__h8090 / 32'd10; + v__h8092 = v__h8098 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8084); + v__h8092); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8488,14 +8498,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2450 = $stime; + v__h2458 = $stime; #0; end - v__h2444 = v__h2450 / 32'd10; + v__h2452 = v__h2458 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2444); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2452); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8785,16 +8795,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4123 = $stime; + v__h4131 = $stime; #0; end - v__h4117 = v__h4123 / 32'd10; + v__h4125 = v__h4131 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4117); + v__h4125); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9000,14 +9010,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9260 = $stime; + v__h9268 = $stime; #0; end - v__h9254 = v__h9260 / 32'd10; + v__h9262 = v__h9268 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9254); + $display("%0d: %m.rl_discard_write_rsp", v__h9262); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9044,15 +9054,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9753 = $stime; + v__h9761 = $stime; #0; end - v__h9747 = v__h9753 / 32'd10; + v__h9755 = v__h9761 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9747); + v__h9755); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9092,14 +9102,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h9916 = $stime; + v__h9924 = $stime; #0; end - v__h9910 = v__h9916 / 32'd10; + v__h9918 = v__h9924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h9910); + v__h9918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9319,37 +9329,37 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42868 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42868 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 856, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42868 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40775 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40775 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 848, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40775 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9370,7 +9380,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9384,85 +9394,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h135207 = $stime; + v__h135215 = $stime; #0; end - v__h135201 = v__h135207 / 32'd10; + v__h135209 = v__h135215 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135201, + v__h135209, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135374 = $stime; + v__h135382 = $stime; #0; end - v__h135368 = v__h135374 / 32'd10; + v__h135376 = v__h135382 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135368); + v__h135376); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9524,135 +9534,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137477 = $stime; + v__h137485 = $stime; #0; end - v__h137471 = v__h137477 / 32'd10; + v__h137479 = v__h137485 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137471); + v__h137479); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -10850,169 +10860,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154821 = $stime; + v__h154829 = $stime; #0; end - v__h154815 = v__h154821 / 32'd10; + v__h154823 = v__h154829 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154815); + $display("%0d: ERROR: CreditCounter: overflow", v__h154823); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", mem_req_wr_addr_awaddr__h148732); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_wr_addr_awaddr__h148740); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", data64__h148647); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", data64__h148655); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", strb8__h148648); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", strb8__h148656); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134588 = $stime; + v__h134596 = $stime; #0; end - v__h134582 = v__h134588 / 32'd10; + v__h134590 = v__h134596 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134582, + v__h134590, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11083,159 +11093,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", mem_req_rd_addr_araddr__h134808); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_rd_addr_araddr__h134816); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h161515 = $stime; + v__h161523 = $stime; #0; end - v__h161509 = v__h161515 / 32'd10; + v__h161517 = v__h161523 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161509, + v__h161517, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h162023 = $stime; + v__h162031 = $stime; #0; end - v__h162017 = v__h162023 / 32'd10; + v__h162025 = v__h162031 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h162017); + v__h162025); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v index 9e389f8..17388e5 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v @@ -360,7 +360,8 @@ module mkSoC_Top(RST_N_dm_power_on_reset, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule fabric wire [63 : 0] fabric$v_from_masters_0_araddr, @@ -859,17 +860,14 @@ module mkSoC_Top(RST_N_dm_power_on_reset, WILL_FIRE_to_raw_mem_request_get, WILL_FIRE_to_raw_mem_response_put; - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h11619; - reg [31 : 0] v__h11080; - reg [31 : 0] v__h11328; - reg [31 : 0] v__h11074; - reg [31 : 0] v__h11322; - reg [31 : 0] v__h11613; + reg [31 : 0] v__h11628; + reg [31 : 0] v__h11088; + reg [31 : 0] v__h11336; + reg [31 : 0] v__h11082; + reg [31 : 0] v__h11330; + reg [31 : 0] v__h11622; // synopsys translate_on // action method set_verbosity @@ -1088,6 +1086,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1734,25 +1733,22 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = + assign CAN_FIRE_RL_rl_reset_start_initial = mem0_controller$RDY_server_reset_request_put && uart0$RDY_server_reset_request_put && fabric$RDY_reset && rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && + assign WILL_FIRE_RL_rl_reset_start_initial = + CAN_FIRE_RL_rl_reset_start_initial ; + + // rule RL_rl_reset_complete_initial + assign CAN_FIRE_RL_rl_reset_complete_initial = mem0_controller$RDY_server_reset_response_get && uart0$RDY_server_reset_response_get && + mem0_controller$RDY_set_addr_map && rg_state == 2'd1 ; + assign WILL_FIRE_RL_rl_reset_complete_initial = + CAN_FIRE_RL_rl_reset_complete_initial ; // register rg_state assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; @@ -1791,7 +1787,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + assign boot_rom$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete_initial ; // submodule boot_rom_axi4_deburster assign boot_rom_axi4_deburster$from_master_araddr = @@ -1922,6 +1918,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign corew$set_verbosity_logdelay = set_verbosity_logdelay ; assign corew$set_verbosity_verbosity = set_verbosity_verbosity ; assign corew$start_fromhost_addr = start_fromhost_addr ; + assign corew$start_is_running = 1'd1 ; assign corew$start_tohost_addr = start_tohost_addr ; assign corew$EN_set_verbosity = EN_set_verbosity ; assign corew$EN_start = EN_start ; @@ -2037,7 +2034,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; + assign fabric$EN_reset = CAN_FIRE_RL_rl_reset_start_initial ; assign fabric$EN_set_verbosity = 1'b0 ; // submodule mem0_controller @@ -2106,10 +2103,11 @@ module mkSoC_Top(RST_N_dm_power_on_reset, mem0_controller_axi4_deburster$to_slave_wvalid ; assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; + CAN_FIRE_RL_rl_reset_start_initial ; assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + CAN_FIRE_RL_rl_reset_complete_initial ; + assign mem0_controller$EN_set_addr_map = + CAN_FIRE_RL_rl_reset_complete_initial ; assign mem0_controller$EN_to_raw_mem_request_get = EN_to_raw_mem_request_get ; assign mem0_controller$EN_to_raw_mem_response_put = @@ -2234,9 +2232,11 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + assign uart0$EN_server_reset_request_put = + CAN_FIRE_RL_rl_reset_start_initial ; + assign uart0$EN_server_reset_response_get = + CAN_FIRE_RL_rl_reset_complete_initial ; + assign uart0$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete_initial ; assign uart0$EN_get_to_console_get = EN_get_to_console_get ; assign uart0$EN_put_from_console_put = EN_put_from_console_put ; @@ -2273,36 +2273,36 @@ module mkSoC_Top(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h11619 = $stime; + v__h11628 = $stime; #0; end - v__h11613 = v__h11619 / 32'd10; + v__h11622 = v__h11628 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start (tohost %0h, fromhost %0h)", - v__h11613, + v__h11622, start_tohost_addr, start_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_start_initial) begin - v__h11080 = $stime; + v__h11088 = $stime; #0; end - v__h11074 = v__h11080 / 32'd10; + v__h11082 = v__h11088 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d: %m.rl_reset_start_initial ...", v__h11074); + $display("%0d: %m.rl_reset_start_initial ...", v__h11082); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete_initial) begin - v__h11328 = $stime; + v__h11336 = $stime; #0; end - v__h11322 = v__h11328 / 32'd10; + v__h11330 = v__h11336 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d: %m.rl_reset_complete_initial", v__h11322); + $display("%0d: %m.rl_reset_complete_initial", v__h11330); end // synopsys translate_on endmodule // mkSoC_Top diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk index 1772e71..c8ff4c3 100644 --- a/builds/Resources/Include_bluesim.mk +++ b/builds/Resources/Include_bluesim.mk @@ -28,6 +28,7 @@ BSC_C_FLAGS += \ -Xl -v \ -Xc -O1 -Xc++ -O1 \ + # For Bluespec_2019.05.beta2-debian9stretch-amd64 # you may have to remove the line: -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0 diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 0bb4aac..be88f0d 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -108,6 +108,7 @@ import Trace_Data2 :: *; interface CoreReq; method Action start( + Bool running, Addr startpc, Addr toHostAddr, Addr fromHostAddr ); @@ -1206,7 +1207,9 @@ module mkCore#(CoreId coreId)(Core); // Debugger 'halt' request (e.g., GDB '^C' command) // This is initiated just like an interrupt. +`ifdef INCLUDE_GDB_CONTROL renameStage.debug_halt_req; +`endif if (show_DM_interactions) $display ("%0d: %m.rl_debug_halt_req", cur_cycle); @@ -1296,10 +1299,14 @@ module mkCore#(CoreId coreId)(Core); interface CoreReq coreReq; method Action start( + Bool running, Bit#(64) startpc, Addr toHostAddr, Addr fromHostAddr ); - fetchStage.start(startpc); +`ifdef INCLUDE_GDB_CONTROL + if (!running) renameStage.debug_halt_req; +`endif + fetchStage.start(startpc); started <= True; `ifdef INCLUDE_GDB_CONTROL rg_core_run_state <= CORE_RUNNING; diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index 6cd20d4..515c93e 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -233,10 +233,10 @@ module mkProc (Proc_IFC); // ---------------- // Start the cores running // Use toHostAddr = 0 if not monitoring tohost - method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr); + method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr); action for(Integer i = 0; i < valueof(CoreNum); i = i+1) - core[i].coreReq.start (startpc, tohostAddr, fromhostAddr); + core[i].coreReq.start (running, startpc, tohostAddr, fromhostAddr); endaction mmioPlatform.start (tohostAddr, fromhostAddr); diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index a2d4576..5611260 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -38,7 +38,7 @@ interface Proc_IFC; // ---------------- // Start the cores running // Use toHostAddr = 0 if not monitoring tohost - method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr); + method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr); // ---------------- // SoC fabric connections diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 677dbf3..3b15d5a 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -189,10 +189,9 @@ module mkCoreW #(Reset dm_power_on_reset) rule rl_dm_hart0_reset_wait (rg_hart0_reset_delay != 0); if (rg_hart0_reset_delay == 1) begin - let pc = soc_map_struct.pc_reset_value; - proc.start (pc, rg_tohost_addr, rg_fromhost_addr); - + let pc = soc_map_struct.pc_reset_value; Bool is_running = True; + proc.start (is_running, pc, rg_tohost_addr, rg_fromhost_addr); debug_module.hart0_reset_client.response.put (is_running); $display ("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr); @@ -362,12 +361,12 @@ module mkCoreW #(Reset dm_power_on_reset) // ---------------------------------------------------------------- // Start - method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base), zeroExtend (soc_map.m_plic_addr_lim)); let pc = soc_map_struct.pc_reset_value; - proc.start (pc, tohost_addr, fromhost_addr); + proc.start (is_running, pc, tohost_addr, fromhost_addr); `ifdef INCLUDE_GDB_CONTROL // Save for potential future use by rl_dm_hart0_reset diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv index 21b8928..fbcf5f6 100644 --- a/src_Core/Core/CoreW_IFC.bsv +++ b/src_Core/Core/CoreW_IFC.bsv @@ -54,7 +54,7 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources); // ---------------------------------------------------------------- // Start - method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); // ---------------------------------------------------------------- // AXI4 Fabric interfaces diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile index 13aee7e..9d4462a 100644 --- a/src_SSITH_P3/Makefile +++ b/src_SSITH_P3/Makefile @@ -33,12 +33,12 @@ BSC_COMPILATION_FLAGS += \ -D INCLUDE_GDB_CONTROL \ -D INCLUDE_TANDEM_VERIF \ -D BRVF_TRACE \ - -D JTAG_TAP \ + -D XILINX_BSCAN -D JTAG_TAP # Synth only BSC_COMPILATION_FLAGS -SYNTH_BSC_OPTIONS = -D XILINX_BSCAN -D XILINX_XCVU9P +SYNTH_BSC_OPTIONS = -D XILINX_XCVU9P -# Sim only BSC_COMPILATION_FLAGS +# Sim only BSC_COMPILATION_FLAGS SIM_BSC_OPTIONS = -D BSIM # Only used if we don't have INCLUDE_GDB_CONTROL diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 0452f06..76bc0cb 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -6,7 +6,7 @@ // // Ports: // Name I/O size props -// RDY_coreReq_start O 1 const +// RDY_coreReq_start O 1 // RDY_coreReq_perfReq O 1 reg // coreIndInv_perfResp O 73 // RDY_coreIndInv_perfResp O 1 reg @@ -104,6 +104,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -184,6 +185,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -402,6 +404,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4314,7 +4317,7 @@ module mkCore(CLK, wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, - MUX_l2Tlb$updateVMInfo_1__VAL_1; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, @@ -4464,9 +4467,10 @@ module mkCore(CLK, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, MUX_regRenamingTable$rename_0_getRename_1__SEL_3, - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_2, + MUX_renameStage_rg_m_halt_req$write_1__SEL_3, + MUX_renameStage_rg_m_halt_req$write_1__SEL_6, MUX_rf$write_3_wr_1__PSEL_5, MUX_rf$write_3_wr_1__SEL_1, MUX_rf$write_3_wr_1__SEL_2, @@ -4521,24 +4525,24 @@ module mkCore(CLK, reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4550,20 +4554,20 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84, - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85, + reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82, + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122, CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51, @@ -4572,8 +4576,8 @@ module mkCore(CLK, CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85, _theResult___fst_sfd__h346070, _theResult___fst_sfd__h354793, _theResult___fst_sfd__h363375, @@ -4609,7 +4613,7 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248, + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, @@ -4631,8 +4635,8 @@ module mkCore(CLK, CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, @@ -4698,8 +4702,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21, CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, @@ -4743,7 +4747,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, @@ -4767,22 +4771,22 @@ module mkCore(CLK, CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191, + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, @@ -4790,11 +4794,11 @@ module mkCore(CLK, CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, @@ -4872,19 +4876,19 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080; wire [463 : 0] commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942; wire [457 : 0] rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; wire [393 : 0] IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; wire [181 : 0] fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; @@ -5844,7 +5848,7 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106, x__h181701, x__h713427; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, @@ -6320,7 +6324,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911, - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388, + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388, NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667, NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008, NOT_rob_deqPort_1_deq_data__5354_BIT_25_5355_5_ETC___d15385, @@ -6390,7 +6394,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo22, + _dfoo20, _dfoo24, _dfoo26, _dfoo32, @@ -6535,7 +6539,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909, f_csr_rsps_i_notFull__5799_AND_f_csr_reqs_firs_ETC___d15902, - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093, + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191, @@ -6586,7 +6590,7 @@ module mkCore(CLK, next_deqP___1__h332215, r1__read_BIT_20___h655898, r__h614580, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956, regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037, regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444, @@ -6611,7 +6615,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935, rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15738, - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013, + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, @@ -6630,8 +6634,8 @@ module mkCore(CLK, x__h603386; // action method coreReq_start - assign RDY_coreReq_start = 1'd1 ; - assign CAN_FIRE_coreReq_start = 1'd1 ; + assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; + assign CAN_FIRE_coreReq_start = !renameStage_rg_m_halt_req[4] ; assign WILL_FIRE_coreReq_start = EN_coreReq_start ; // action method coreReq_perfReq @@ -6668,7 +6672,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6688,7 +6692,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9946,7 +9950,8 @@ module mkCore(CLK, f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] && rg_core_run_state == 2'd2 && !f_run_halt_reqs$D_OUT ; - assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ; + assign WILL_FIRE_RL_rl_debug_halt_req = + CAN_FIRE_RL_rl_debug_halt_req && !EN_coreReq_start ; // rule RL_rl_debug_halt_req_already_halted assign CAN_FIRE_RL_rl_debug_halt_req_already_halted = @@ -10371,8 +10376,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10408,7 +10413,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 && + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10443,7 +10448,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 && + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15400 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11412,9 +11417,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11422,19 +11428,21 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_csrInstOrInterruptInflight_canon assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; @@ -11479,7 +11487,8 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_mmio_pRqQ_canonicalize assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ; @@ -11952,16 +11961,17 @@ module mkCore(CLK, WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; - assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst || - WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 = - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 && - csrf_rg_dcsr[2] ; - assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_3 = + WILL_FIRE_RL_renameStage_doRenaming_Trap && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_6 = + EN_coreReq_start && !coreReq_start_running ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && coreFix_memExe_lsq$firstSt[150] ; @@ -12459,6 +12469,12 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738339 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or next_pc__h723452 or csrf_sepc_csr or csrf_mepc_csr) begin @@ -12474,12 +12490,6 @@ module mkCore(CLK, coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 = { 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ; - assign MUX_l2Tlb$updateVMInfo_1__VAL_1 = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], @@ -14811,7 +14821,7 @@ module mkCore(CLK, assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15103,21 +15113,24 @@ module mkCore(CLK, assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; // register renameStage_rg_m_halt_req - always@(WILL_FIRE_RL_rl_debug_resume or + always@(MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_3 or + WILL_FIRE_RL_rl_debug_resume or WILL_FIRE_RL_rl_debug_halt_req or - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or - MUX_renameStage_rg_m_halt_req$write_1__SEL_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; - WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30; - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || - MUX_renameStage_rg_m_halt_req$write_1__SEL_2: - renameStage_rg_m_halt_req$D_IN = 5'd31; - default: renameStage_rg_m_halt_req$D_IN = - 5'b01010 /* unspecified value */ ; - endcase - end + MUX_renameStage_rg_m_halt_req$write_1__SEL_6) + case (1'b1) + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_3: + renameStage_rg_m_halt_req$D_IN = 5'd31; + WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; + WILL_FIRE_RL_rl_debug_halt_req || + MUX_renameStage_rg_m_halt_req$write_1__SEL_6: + renameStage_rg_m_halt_req$D_IN = 5'd30; + default: renameStage_rg_m_halt_req$D_IN = + 5'b01010 /* unspecified value */ ; + endcase assign renameStage_rg_m_halt_req$EN = (WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap) && @@ -15125,6 +15138,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] || + EN_coreReq_start && !coreReq_start_running || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15157,7 +15171,7 @@ module mkCore(CLK, !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data @@ -18150,8 +18164,8 @@ module mkCore(CLK, assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; @@ -18310,8 +18324,8 @@ module mkCore(CLK, MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; assign l2Tlb$updateVMInfo_vmI = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign l2Tlb$EN_updateVMInfo = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_rl_debug_resume ; @@ -20845,8 +20859,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20878,8 +20892,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21439,8 +21453,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21450,8 +21464,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = (_theResult___fst_exp__h519940 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -22132,8 +22146,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || @@ -22158,8 +22172,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? 4'd0 : @@ -24166,10 +24180,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149 = @@ -24183,10 +24197,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 && IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093) ; + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && @@ -25474,9 +25488,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 ; - assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 = + assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25515,7 +25529,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022 = !specTagManager$canClaim || @@ -25549,21 +25563,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, x__h291618 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = @@ -26616,7 +26630,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo22 = + assign _dfoo20 = commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign _dfoo24 = @@ -28089,7 +28103,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 : + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; assign _theResult___fst_exp__h598880 = (_theResult___fst_exp__h598097 == 11'd2047) ? @@ -28220,7 +28234,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 : + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; assign _theResult___fst_sfd__h502289 = (_theResult___fst_exp__h501530 == 11'd2047) ? @@ -28231,7 +28245,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; assign _theResult___fst_sfd__h511940 = (_theResult___fst_exp__h511107 == 11'd2047) ? @@ -28242,7 +28256,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 : + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; assign _theResult___fst_sfd__h520724 = (_theResult___fst_exp__h519940 == 11'd2047) ? @@ -28283,7 +28297,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 : + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; assign _theResult___fst_sfd__h550793 = (_theResult___fst_exp__h549960 == 11'd2047) ? @@ -28294,7 +28308,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 : + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; assign _theResult___fst_sfd__h559577 = (_theResult___fst_exp__h558793 == 11'd2047) ? @@ -30231,12 +30245,14 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609378 = { 56'd0, x__h613036 } ; - assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31048,14 +31064,13 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; assign r__h614580 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31553,13 +31568,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612208 = { r1__read__h614606, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; + assign rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -31582,11 +31596,11 @@ module mkCore(CLK, assign rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 } ; + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; assign rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520 = { rob$deqPort_0_deq_data[181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 } ; + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; assign rs1__h655333 = @@ -33134,6 +33148,23 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33162,23 +33193,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19]) @@ -33555,69 +33569,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h381194 = 8'd0; endcase end - always@(guard__h346097 or - sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0, 2'b01: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - sfdin__h354192[56:34]; - 2'b10: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - out_sfd__h354718; - 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - _theResult___sfd__h354715; - endcase - end - always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - sfdin__h354192[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - _theResult___sfd__h354715; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354192) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47; - 3'd1: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48; - 3'd2: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; - 3'd3: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; - default: _theResult___fst_sfd__h354793 = 23'd0; - endcase - end always@(guard__h354806 or _theResult___snd__h362805 or out_sfd__h363300 or _theResult___sfd__h363297) begin case (guard__h354806) 2'b0, 2'b01: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___snd__h362805[56:34]; 2'b10: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = out_sfd__h363300; 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___sfd__h363297; endcase end @@ -33626,16 +33590,16 @@ module mkCore(CLK, begin case (guard__h354806) 2'b0: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___snd__h362805[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___sfd__h363297; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or _theResult___snd__h362805) @@ -33643,10 +33607,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47; 3'd1: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48; 3'd2: _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; @@ -33657,6 +33621,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h363375 = 23'd0; endcase end + always@(guard__h346097 or + sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0, 2'b01: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354192[56:34]; + 2'b10: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354718; + 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354715; + endcase + end + always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354192[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354715; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or + sfdin__h354192) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49; + 3'd1: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50; + 3'd2: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; + 3'd3: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; + 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; + default: _theResult___fst_sfd__h354793 = 23'd0; + endcase + end always@(guard__h363736 or sfdin__h371958 or out_sfd__h372484 or _theResult___sfd__h372481) begin @@ -33797,66 +33811,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354806 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h354806) - 2'b0, 2'b01, 2'b10: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - guard__h354806 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or - guard__h354806) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354806 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || - guard__h354806 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = (guard__h346097 == 2'b0) ? @@ -33873,6 +33849,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h354806 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h354806) + 2'b0, 2'b01, 2'b10: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354806 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354806) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + (guard__h354806 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || + guard__h354806 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34297,69 +34311,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h426891 = 8'd0; endcase end - always@(guard__h391796 or - sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0, 2'b01: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - sfdin__h399889[56:34]; - 2'b10: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - out_sfd__h400415; - 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - _theResult___sfd__h400412; - endcase - end - always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - sfdin__h399889[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - _theResult___sfd__h400412; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399889) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82; - 3'd1: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83; - 3'd2: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; - 3'd3: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; - default: _theResult___fst_sfd__h400490 = 23'd0; - endcase - end always@(guard__h400503 or _theResult___snd__h408502 or out_sfd__h408997 or _theResult___sfd__h408994) begin case (guard__h400503) 2'b0, 2'b01: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___snd__h408502[56:34]; 2'b10: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = out_sfd__h408997; 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___sfd__h408994; endcase end @@ -34368,16 +34332,16 @@ module mkCore(CLK, begin case (guard__h400503) 2'b0: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___snd__h408502[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___sfd__h408994; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or _theResult___snd__h408502) @@ -34385,10 +34349,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82; 3'd1: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83; 3'd2: _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; @@ -34399,6 +34363,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h409072 = 23'd0; endcase end + always@(guard__h391796 or + sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0, 2'b01: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399889[56:34]; + 2'b10: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400415; + 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400412; + endcase + end + always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399889[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400412; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or + sfdin__h399889) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84; + 3'd1: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85; + 3'd2: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; + 3'd3: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; + 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; + default: _theResult___fst_sfd__h400490 = 23'd0; + endcase + end always@(guard__h409433 or sfdin__h417655 or out_sfd__h418181 or _theResult___sfd__h418178) begin @@ -34734,61 +34748,23 @@ module mkCore(CLK, begin case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or - guard__h418269) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418269 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h418269 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h418269) - 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = guard__h418269 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = (guard__h418269 == 2'b0) ? @@ -34805,6 +34781,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end + always@(guard__h418269 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h418269) + 2'b0, 2'b01, 2'b10: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418269) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + (guard__h418269 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -35821,21 +35835,21 @@ module mkCore(CLK, _theResult___exp__h580342; endcase end - always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581038) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h581038 == 2'b11 && + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571726 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35844,12 +35858,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h581038 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || - guard__h581038 == 2'b11) && + (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || + guard__h571726 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35860,21 +35874,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571726) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h571726 == 2'b11 && + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581038 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35883,12 +35897,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h571726 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || - guard__h571726 == 2'b11) && + (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || + guard__h581038 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36259,57 +36273,15 @@ module mkCore(CLK, _theResult___exp__h589993; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - guard__h532422 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || - guard__h532422 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h590107 or _theResult___fst_exp__h598097 or _theResult___exp__h598777) begin case (guard__h590107) 2'b0: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___fst_exp__h598097; 2'b01, 2'b10, 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___exp__h598777; endcase end @@ -36317,7 +36289,7 @@ module mkCore(CLK, _theResult___fst_exp__h598097 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193) + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36331,7 +36303,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase @@ -36342,13 +36314,13 @@ module mkCore(CLK, begin case (guard__h590107) 2'b0, 2'b01: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___fst_exp__h598097; 2'b10: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = out_exp__h598780; 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___exp__h598777; endcase end @@ -36356,12 +36328,12 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = guard__h541734 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36372,12 +36344,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36387,6 +36359,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h532422 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || + guard__h532422 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -36478,58 +36492,16 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36540,12 +36512,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36555,6 +36527,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -36613,65 +36627,14 @@ module mkCore(CLK, _theResult___sfd__h541039; endcase end - always@(guard__h550803 or - _theResult___snd__h558739 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___snd__h558739[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___sfd__h559474; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558739 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558739[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - 52'd0; - endcase - end - always@(guard__h550803 or - _theResult___snd__h558739 or - out_sfd__h559477 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0, 2'b01: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___snd__h558739[56:5]; - 2'b10: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - out_sfd__h559477; - 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___sfd__h559474; - endcase - end always@(guard__h541734 or sfdin__h549954 or _theResult___sfd__h550690) begin case (guard__h541734) 2'b0: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = sfdin__h549954[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = _theResult___sfd__h550690; endcase end @@ -36679,7 +36642,7 @@ module mkCore(CLK, sfdin__h549954 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209) + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36693,7 +36656,7 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase @@ -36703,16 +36666,67 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = sfdin__h549954[56:5]; 2'b10: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = out_sfd__h550693; 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = _theResult___sfd__h550690; endcase end + always@(guard__h550803 or + _theResult___snd__h558739 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___snd__h558739[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___sfd__h559474; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h558739 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + _theResult___snd__h558739[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + 52'd0; + endcase + end + always@(guard__h550803 or + _theResult___snd__h558739 or + out_sfd__h559477 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0, 2'b01: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___snd__h558739[56:5]; + 2'b10: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + out_sfd__h559477; + 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___sfd__h559474; + endcase + end always@(guard__h502881 or _theResult___fst_exp__h511107 or _theResult___exp__h511836) begin @@ -36815,64 +36829,15 @@ module mkCore(CLK, _theResult___exp__h520620; endcase end - always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h511101[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h511837; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511101 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511101[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - 52'd0; - endcase - end - always@(guard__h502881 or - sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0, 2'b01: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h511101[56:5]; - 2'b10: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h511840; - 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h511837; - endcase - end always@(guard__h493569 or _theResult___snd__h501481 or _theResult___sfd__h502186) begin case (guard__h493569) 2'b0: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___snd__h501481[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___sfd__h502186; endcase end @@ -36880,7 +36845,7 @@ module mkCore(CLK, _theResult___snd__h501481 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217) + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36894,7 +36859,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase @@ -36905,13 +36870,13 @@ module mkCore(CLK, begin case (guard__h493569) 2'b0, 2'b01: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___snd__h501481[56:5]; 2'b10: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = out_sfd__h502189; 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___sfd__h502186; endcase end @@ -36920,10 +36885,10 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___snd__h519886[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___sfd__h520621; endcase end @@ -36931,7 +36896,7 @@ module mkCore(CLK, _theResult___snd__h519886 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219) + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36945,7 +36910,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase @@ -36956,16 +36921,65 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0, 2'b01: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___snd__h519886[56:5]; 2'b10: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = out_sfd__h520624; 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___sfd__h520621; endcase end + always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h511101[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h511837; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h511101 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + sfdin__h511101[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + 52'd0; + endcase + end + always@(guard__h502881 or + sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0, 2'b01: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + sfdin__h511101[56:5]; + 2'b10: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + out_sfd__h511840; + 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + _theResult___sfd__h511837; + endcase + end always@(guard__h571726 or _theResult___snd__h579638 or _theResult___sfd__h580343) begin @@ -38031,10 +38045,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -38042,10 +38056,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -38350,38 +38364,6 @@ module mkCore(CLK, endcase end always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) 12'd1, @@ -38428,12 +38410,44 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = 12'd2303; endcase end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + 4'd15; + endcase + end always@(commitStage_f_rob_data$D_OUT) begin case (commitStage_f_rob_data$D_OUT[97:96]) diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index bb0d3be..607e8ac 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -78,6 +78,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// start_is_running I 1 // start_tohost_addr I 64 // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 @@ -161,6 +162,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -379,6 +381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1401,7 +1404,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1609,12 +1613,12 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5047; - reg [31 : 0] v__h5190; - reg [31 : 0] v__h15930; - reg [31 : 0] v__h5041; - reg [31 : 0] v__h5184; - reg [31 : 0] v__h15924; + reg [31 : 0] v__h5055; + reg [31 : 0] v__h5198; + reg [31 : 0] v__h15940; + reg [31 : 0] v__h5049; + reg [31 : 0] v__h5192; + reg [31 : 0] v__h15934; // synopsys translate_on // remaining internal signals @@ -2523,6 +2527,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2716,22 +2721,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -3359,6 +3364,7 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_proc$start_1__SEL_1 ? rg_fromhost_addr : start_fromhost_addr ; + assign proc$start_running = MUX_proc$start_1__SEL_1 || start_is_running ; assign proc$start_startpc = 64'h0000000070000000 ; assign proc$start_tohostAddr = MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; @@ -3700,15 +3706,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h5047 = $stime; + v__h5055 = $stime; #0; end - v__h5041 = v__h5047 / 32'd10; + v__h5049 = v__h5055 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h5041, + v__h5049, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -3716,17 +3722,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h5190 = $stime; + v__h5198 = $stime; #0; end - v__h5184 = v__h5190 / 32'd10; + v__h5192 = v__h5198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h5184, + v__h5192, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); @@ -3734,15 +3740,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15930 = $stime; + v__h15940 = $stime; #0; end - v__h15924 = v__h15930 / 32'd10; + v__h15934 = v__h15940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15924, + v__h15934, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v index 7ed7f93..e079454 100644 --- a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v @@ -130,17 +130,13 @@ module mkJtagTap(CLK, // inlined wires wire [40 : 0] w_dmi_req$wget; - wire r_dmistat_busy$port1__read, + wire r_dmistat_busy$EN_port1__write, + r_dmistat_busy$port1__read, r_dmistat_busy$port2__read, r_tdo$EN_port0__write, r_tdo$port0__write_1, r_tdo$port1__read; - // register r_dmi - reg [39 : 0] r_dmi; - wire [39 : 0] r_dmi$D_IN; - wire r_dmi$EN; - // register r_dmistat_busy reg r_dmistat_busy; wire r_dmistat_busy$D_IN, r_dmistat_busy$EN; @@ -160,11 +156,6 @@ module mkJtagTap(CLK, wire [17 : 0] r_ir$D_IN; wire r_ir$EN; - // register r_state - reg [3 : 0] r_state; - wire [3 : 0] r_state$D_IN; - wire r_state$EN; - // register r_tdo reg r_tdo; wire r_tdo$D_IN, r_tdo$EN; @@ -179,6 +170,7 @@ module mkJtagTap(CLK, // ports of submodule f_dmi_req wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN; wire f_dmi_req$dCLR, + f_dmi_req$dCLR_RDY, f_dmi_req$dDEQ, f_dmi_req$dEMPTY_N, f_dmi_req$sCLR, @@ -193,18 +185,32 @@ module mkJtagTap(CLK, f_dmi_rsp$dDEQ, f_dmi_rsp$dEMPTY_N, f_dmi_rsp$sCLR, + f_dmi_rsp$sCLR_RDY, f_dmi_rsp$sENQ, f_dmi_rsp$sFULL_N; + // ports of submodule r_dmi + wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT; + wire r_dmi$EN; + + // ports of submodule r_initialize + wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT; + + // ports of submodule r_initialize2 + wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT; + + // ports of submodule r_state + wire [3 : 0] r_state$D_IN, r_state$Q_OUT; + wire r_state$EN; + // ports of submodule rst_tck wire rst_tck$OUT_RST; // ports of submodule tck_clock - wire tck_clock$CLK_IN, - tck_clock$CLK_IN_EN, - tck_clock$CLK_OUT, - tck_clock$COND_IN, - tck_clock$COND_IN_EN; + wire tck_clock$IN, tck_clock$OUT; + + // ports of submodule w_tck_crossed + wire w_tck_crossed$DOUT; // rule scheduling signals wire CAN_FIRE_RL_dmi_request, @@ -215,7 +221,9 @@ module mkJtagTap(CLK, CAN_FIRE_RL_dmi_response_ready, CAN_FIRE_RL_dmi_response_tck, CAN_FIRE_RL_dmi_start, - CAN_FIRE_RL_rl_tck, + CAN_FIRE_RL_mkConnectionVtoAf, + CAN_FIRE_RL_rl_initialize, + CAN_FIRE_RL_rl_initialize2, CAN_FIRE_RL_tick, CAN_FIRE_dmi_req_ready, CAN_FIRE_dmi_rsp_data, @@ -232,7 +240,9 @@ module mkJtagTap(CLK, WILL_FIRE_RL_dmi_response_ready, WILL_FIRE_RL_dmi_response_tck, WILL_FIRE_RL_dmi_start, - WILL_FIRE_RL_rl_tck, + WILL_FIRE_RL_mkConnectionVtoAf, + WILL_FIRE_RL_rl_initialize, + WILL_FIRE_RL_rl_initialize2, WILL_FIRE_RL_tick, WILL_FIRE_dmi_req_ready, WILL_FIRE_dmi_rsp_data, @@ -243,24 +253,24 @@ module mkJtagTap(CLK, WILL_FIRE_jtag_tms; // remaining internal signals - reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, - v__h2135; - reg [17 : 0] newir__h3435; - reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3, - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2; - wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140, - v__h2233, - v__h2601, - x__h2449, - x__h2658, - y__h2659; - wire [17 : 0] v__h3299, x__h3350, y__h3351; - wire r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72; + reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, + v__h2479; + reg [17 : 0] newir__h3774; + reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3, + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2; + wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146, + v__h2576, + v__h2941, + x__h2789, + x__h2996, + y__h2997; + wire [17 : 0] v__h3636, x__h3687, y__h3688; + wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78; // oscillator and gates for output clock CLK_jtag_tclk_out - assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ; + assign CLK_jtag_tclk_out = tck_clock$OUT ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; // action method jtag_tdi @@ -311,7 +321,7 @@ module mkJtagTap(CLK, // submodule f_dmi_busy FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST), - .CLK(tck_clock$CLK_OUT), + .CLK(tck_clock$OUT), .ENQ(f_dmi_busy$ENQ), .DEQ(f_dmi_busy$DEQ), .CLR(f_dmi_busy$CLR), @@ -321,7 +331,7 @@ module mkJtagTap(CLK, // submodule f_dmi_req SyncFIFOLevel #(.dataWidth(32'd41), .depth(32'd2), - .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT), + .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT), .dCLK(CLK), .sRST(rst_tck$OUT_RST), .sD_IN(f_dmi_req$sD_IN), @@ -335,13 +345,13 @@ module mkJtagTap(CLK, .dCOUNT(), .sCOUNT(), .sCLR_RDY(f_dmi_req$sCLR_RDY), - .dCLR_RDY()); + .dCLR_RDY(f_dmi_req$dCLR_RDY)); // submodule f_dmi_rsp SyncFIFOLevel #(.dataWidth(32'd40), .depth(32'd2), .indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK), - .dCLK(tck_clock$CLK_OUT), + .dCLK(tck_clock$OUT), .sRST(RST_N), .sD_IN(f_dmi_rsp$sD_IN), .sENQ(f_dmi_rsp$sENQ), @@ -353,29 +363,46 @@ module mkJtagTap(CLK, .dEMPTY_N(f_dmi_rsp$dEMPTY_N), .dCOUNT(), .sCOUNT(), - .sCLR_RDY(), + .sCLR_RDY(f_dmi_rsp$sCLR_RDY), .dCLR_RDY(f_dmi_rsp$dCLR_RDY)); + // submodule r_dmi + RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT), + .D_IN(r_dmi$D_IN), + .EN(r_dmi$EN), + .Q_OUT(r_dmi$Q_OUT)); + + // submodule r_initialize + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT), + .D_IN(r_initialize$D_IN), + .EN(r_initialize$EN), + .Q_OUT(r_initialize$Q_OUT)); + + // submodule r_initialize2 + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK), + .D_IN(r_initialize2$D_IN), + .EN(r_initialize2$EN), + .Q_OUT(r_initialize2$Q_OUT)); + + // submodule r_state + RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT), + .D_IN(r_state$D_IN), + .EN(r_state$EN), + .Q_OUT(r_state$Q_OUT)); + // submodule rst_tck - SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT), - .IN_RST(RST_N), - .OUT_RST(rst_tck$OUT_RST)); + SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST)); // submodule tck_clock - MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK), - .RST(RST_N), - .CLK_IN(tck_clock$CLK_IN), - .COND_IN(tck_clock$COND_IN), - .CLK_IN_EN(tck_clock$CLK_IN_EN), - .COND_IN_EN(tck_clock$COND_IN_EN), - .CLK_VAL_OUT(), - .COND_OUT(), - .CLK_GATE_OUT(), - .CLK_OUT(tck_clock$CLK_OUT)); + ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT)); - // rule RL_rl_tck - assign CAN_FIRE_RL_rl_tck = 1'd1 ; - assign WILL_FIRE_RL_rl_tck = 1'd1 ; + // submodule w_tck_crossed + SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk), + .DOUT(w_tck_crossed$DOUT)); + + // rule RL_mkConnectionVtoAf + assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; + assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ; // rule RL_tick assign CAN_FIRE_RL_tick = 1'd1 ; @@ -383,7 +410,7 @@ module mkJtagTap(CLK, // rule RL_dmi_start assign CAN_FIRE_RL_dmi_start = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 && f_dmi_req$sFULL_N && f_dmi_busy$FULL_N && w_dmi_req$wget[1:0] != 2'd0 ; @@ -406,9 +433,14 @@ module mkJtagTap(CLK, f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ; assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ; + // rule RL_rl_initialize + assign CAN_FIRE_RL_rl_initialize = + r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ; + // rule RL_dmi_reset assign CAN_FIRE_RL_dmi_reset = - r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 && (!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ; assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ; @@ -420,35 +452,37 @@ module mkJtagTap(CLK, assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ; assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ; + // rule RL_rl_initialize2 + assign CAN_FIRE_RL_rl_initialize2 = + f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ; + // inlined wires assign w_dmi_req$wget = { 1'd0, r_dr } ; - assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ; - assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ; + assign r_tdo$EN_port0__write = + r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ; + assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ; assign r_tdo$port1__read = r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ; assign r_dmistat_busy$port1__read = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 || + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 || r_dmistat_busy ; + assign r_dmistat_busy$EN_port1__write = + WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ; assign r_dmistat_busy$port2__read = - !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ; - - // register r_dmi - assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; - assign r_dmi$EN = - WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 ; + !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ; // register r_dmistat_busy assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ; assign r_dmistat_busy$EN = 1'b1 ; // register r_dr - always@(r_state or r_dr or v__h2135 or v__h2601) + always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941) begin - case (r_state) + case (r_state$Q_OUT) 4'd0: r_dr$D_IN = r_dr; - 4'd3: r_dr$D_IN = v__h2135; - 4'd4: r_dr$D_IN = v__h2601; + 4'd3: r_dr$D_IN = v__h2479; + 4'd4: r_dr$D_IN = v__h2941; default: r_dr$D_IN = r_dr; endcase end @@ -456,22 +490,15 @@ module mkJtagTap(CLK, // register r_drmask assign r_drmask$D_IN = - (r_state == 4'd3) ? - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : + (r_state$Q_OUT == 4'd3) ? + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : r_drmask ; assign r_drmask$EN = 1'd1 ; // register r_ir - assign r_ir$D_IN = newir__h3435 ; + assign r_ir$D_IN = newir__h3774 ; assign r_ir$EN = 1'd1 ; - // register r_state - assign r_state$D_IN = - jtag_tms ? - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 : - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ; - assign r_state$EN = 1'd1 ; - // register r_tdo assign r_tdo$D_IN = r_tdo$port1__read ; assign r_tdo$EN = 1'b1 ; @@ -479,69 +506,89 @@ module mkJtagTap(CLK, // submodule f_dmi_busy assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + assign f_dmi_busy$CLR = + WILL_FIRE_RL_dmi_reset && r_dr[17] || + WILL_FIRE_RL_rl_initialize ; // submodule f_dmi_req assign f_dmi_req$sD_IN = w_dmi_req$wget ; assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ; assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; - assign f_dmi_req$dCLR = 1'b0 ; + assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ; // submodule f_dmi_rsp assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ; assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ; assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_rsp$sCLR = 1'b0 ; + assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ; assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + // submodule r_dmi + assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; + assign r_dmi$EN = + WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 ; + + // submodule r_initialize + assign r_initialize$D_IN = 1'd0 ; + assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ; + + // submodule r_initialize2 + assign r_initialize2$D_IN = 1'd0 ; + assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ; + + // submodule r_state + assign r_state$D_IN = + jtag_tms ? + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 : + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ; + assign r_state$EN = 1'd1 ; + // submodule tck_clock - assign tck_clock$CLK_IN = jtag_tclk ; - assign tck_clock$COND_IN = 1'b0 ; - assign tck_clock$CLK_IN_EN = 1'd1 ; - assign tck_clock$COND_IN_EN = 1'b0 ; + assign tck_clock$IN = w_tck_crossed$DOUT ; // remaining internal signals - assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 = + assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 = (r_dmistat_busy || - r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N) ? 40'hAAAAAAAAAB : - r_dmi ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 = - r_state == 4'd8 && r_ir == 18'b100010100100100100 && + r_dmi$Q_OUT ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b100010100100100100 && (r_dr[17] || r_dr[16]) ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && !f_dmi_busy$EMPTY_N ; - assign v__h2233 = { 22'd960, r_ir } ; - assign v__h2601 = x__h2658 | y__h2659 ; - assign v__h3299 = x__h3350 | y__h3351 ; - assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ; - assign x__h2658 = { 1'd0, r_dr[39:1] } ; - assign x__h3350 = { 1'd0, r_ir[17:1] } ; - assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ; - assign y__h3351 = jtag_tdi ? 18'd131072 : 18'd0 ; - always@(r_state or r_ir or v__h3299) + assign v__h2576 = { 22'd960, r_ir } ; + assign v__h2941 = x__h2996 | y__h2997 ; + assign v__h3636 = x__h3687 | y__h3688 ; + assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ; + assign x__h2996 = { 1'd0, r_dr[39:1] } ; + assign x__h3687 = { 1'd0, r_ir[17:1] } ; + assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ; + assign y__h3688 = jtag_tdi ? 18'd131072 : 18'd0 ; + always@(r_state$Q_OUT or r_ir or v__h3636) begin - case (r_state) - 4'd0: newir__h3435 = 18'd1; - 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir; - 4'd11: newir__h3435 = v__h3299; - default: newir__h3435 = r_ir; + case (r_state$Q_OUT) + 4'd0: newir__h3774 = 18'd1; + 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir; + 4'd11: newir__h3774 = v__h3636; + default: newir__h3774 = r_ir; endcase end always@(r_ir or - v__h2233 or - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 or - x__h2449) + v__h2576 or + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 or + x__h2789) begin case (r_ir) 18'd0, @@ -552,18 +599,18 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - v__h2135 = 40'd0; - 18'd1: v__h2135 = 40'd4093; + v__h2479 = 40'd0; + 18'd1: v__h2479 = 40'd4093; 18'b000011100100100100: - v__h2135 = - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140; - 18'b100010100100100100: v__h2135 = x__h2449; - default: v__h2135 = v__h2233; + v__h2479 = + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146; + 18'b100010100100100100: v__h2479 = x__h2789; + default: v__h2479 = v__h2576; endcase end - always@(newir__h3435) + always@(newir__h3774) begin - case (newir__h3435) + case (newir__h3774) 18'd0, 18'h00012, 18'h00013, @@ -572,71 +619,67 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; 18'd1, 18'b100010100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0080000000; 18'b000011100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h8000000000; - default: CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + default: CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0100000000; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) - 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state; + case (r_state$Q_OUT) + 4'd0: + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = + r_state$Q_OUT; 4'd1, 4'd8, 4'd15: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2; - 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9; - 4'd3, 4'd4: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5; - 4'd5, 4'd7: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8; - 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7; - 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2; + 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9; + 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5; + 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8; + 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7; + 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0; 4'd10, 4'd11: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12; 4'd12, 4'd14: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15; - 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15; + 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) + case (r_state$Q_OUT) 4'd0, 4'd1, 4'd8, 4'd15: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1; - 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1; + 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3; 4'd3, 4'd4, 4'd7: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4; 4'd5, 4'd6: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6; - 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6; + 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10; 4'd10, 4'd11, 4'd14: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11; 4'd12, 4'd13: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13; endcase end // handling of inlined registers - always@(posedge tck_clock$CLK_OUT) + always@(posedge tck_clock$OUT) begin if (rst_tck$OUT_RST == `BSV_RESET_VALUE) begin - r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0; - r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - r_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN; - if (r_dmistat_busy$EN) + if (r_dmistat_busy$EN) r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN; - if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN; end if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN; if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN; @@ -649,12 +692,10 @@ module mkJtagTap(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - r_dmi = 40'hAAAAAAAAAA; r_dmistat_busy = 1'h0; r_dr = 40'hAAAAAAAAAA; r_drmask = 40'hAAAAAAAAAA; r_ir = 18'h2AAAA; - r_state = 4'hA; r_tdo = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS @@ -663,11 +704,11 @@ module mkJtagTap(CLK, // handling of system tasks // synopsys translate_off - always@(negedge tck_clock$CLK_OUT) + always@(negedge tck_clock$OUT) begin #0; if (rst_tck$OUT_RST != `BSV_RESET_VALUE) - if (r_state == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && + if (r_state$Q_OUT == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && r_ir != 18'h00013 && r_ir != 18'h00014 && r_ir != 18'h00015 && diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index b1f7022..53c9fed 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -648,14 +648,19 @@ module mkP3_Core(CLK, wire bus_dmi_rsp_fifof_q_1$EN; // register rg_corew_start_after_por - reg rg_corew_start_after_por; - wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + reg [7 : 0] rg_corew_start_after_por; + wire [7 : 0] rg_corew_start_after_por$D_IN; + wire rg_corew_start_after_por$EN; // register rg_ndm_reset_delay reg [7 : 0] rg_ndm_reset_delay; wire [7 : 0] rg_ndm_reset_delay$D_IN; wire rg_ndm_reset_delay$EN; + // register rg_running + reg rg_running; + wire rg_running$D_IN, rg_running$EN; + // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; wire bus_dmi_req_fifof$CLR, @@ -781,8 +786,10 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, + corew$ndm_reset_client_request_get, corew$ndm_reset_client_response_put, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -804,6 +811,9 @@ module mkP3_Core(CLK, // ports of submodule ndm_reset_controller wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule por_ifc + wire por_ifc$RST_N_gen_rst; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -910,15 +920,15 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1279; - reg [31 : 0] v__h1424; - reg [31 : 0] v__h1273; - reg [31 : 0] v__h1418; + reg [31 : 0] v__h1362; + reg [31 : 0] v__h1510; + reg [31 : 0] v__h1356; + reg [31 : 0] v__h1504; // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; - wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49; + wire IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99, _dfoo1, _dfoo3; @@ -1188,7 +1198,7 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(por_ifc$RST_N_gen_rst), .CLK(CLK), .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), @@ -1237,6 +1247,7 @@ module mkP3_Core(CLK, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1308,7 +1319,7 @@ module mkP3_Core(CLK, .dmi_read_data(corew$dmi_read_data), .RDY_dmi_read_data(corew$RDY_dmi_read_data), .RDY_dmi_write(corew$RDY_dmi_write), - .ndm_reset_client_request_get(), + .ndm_reset_client_request_get(corew$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), @@ -1316,7 +1327,7 @@ module mkP3_Core(CLK, // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), - .RST_N(RST_N), + .RST_N(por_ifc$RST_N_gen_rst), .dmi_req_ready(jtagtap$dmi_req_ready), .dmi_rsp_data(jtagtap$dmi_rsp_data), .dmi_rsp_response(jtagtap$dmi_rsp_response), @@ -1334,7 +1345,7 @@ module mkP3_Core(CLK, .CLK_GATE_jtag_tclk_out()); // submodule ndm_reset - ResetEither ndm_reset(.A_RST(RST_N), + ResetEither ndm_reset(.A_RST(por_ifc$RST_N_gen_rst), .B_RST(ndm_reset_controller$OUT_RST), .RST_OUT(ndm_reset$RST_OUT)); @@ -1346,6 +1357,11 @@ module mkP3_Core(CLK, .ASSERT_OUT(), .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule por_ifc + mkPowerOnReset por_ifc(.CLK(CLK), + .RST_N(RST_N), + .RST_N_gen_rst(por_ifc$RST_N_gen_rst)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1371,7 +1387,8 @@ module mkP3_Core(CLK, // rule RL_rl_step_0 assign CAN_FIRE_RL_rl_step_0 = - corew$RDY_start && !rg_corew_start_after_por ; + (rg_corew_start_after_por != 8'd1 || corew$RDY_start) && + rg_corew_start_after_por != 8'd0 ; assign WILL_FIRE_RL_rl_step_0 = CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; @@ -1422,7 +1439,7 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; + IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu @@ -1434,7 +1451,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; @@ -1526,7 +1543,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1585,7 +1602,7 @@ module mkP3_Core(CLK, WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register rg_corew_start_after_por - assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$D_IN = rg_corew_start_after_por - 8'd1 ; assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; // register rg_ndm_reset_delay @@ -1596,6 +1613,10 @@ module mkP3_Core(CLK, assign rg_ndm_reset_delay$EN = WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; + // register rg_running + assign rg_running$D_IN = corew$ndm_reset_client_request_get ; + assign rg_running$EN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; assign bus_dmi_req_fifof$ENQ = CAN_FIRE_RL_bus_dmi_req_do_enq ; @@ -1660,16 +1681,17 @@ module mkP3_Core(CLK, assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$ndm_reset_client_response_put = rg_running ; assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_is_running = !MUX_corew$start_1__SEL_1 || rg_running ; assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || - WILL_FIRE_RL_rl_step_0 ; + WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1699,7 +1721,7 @@ module mkP3_Core(CLK, assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = + assign IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || @@ -1708,11 +1730,11 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1724,7 +1746,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 8'd100; rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else @@ -1744,6 +1766,7 @@ module mkP3_Core(CLK, if (rg_ndm_reset_delay$EN) rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end + if (rg_running$EN) rg_running <= `BSV_ASSIGNMENT_DELAY rg_running$D_IN; end // synopsys translate_off @@ -1754,8 +1777,9 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_corew_start_after_por = 1'h0; + rg_corew_start_after_por = 8'hAA; rg_ndm_reset_delay = 8'hAA; + rg_running = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1767,30 +1791,34 @@ module mkP3_Core(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - begin - v__h1279 = $stime; - #0; - end - v__h1273 = v__h1279 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1273, - $signed(32'd10)); - if (RST_N != `BSV_RESET_VALUE) - if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1424 = $stime; + v__h1362 = $stime; #0; end - v__h1418 = v__h1424 / 32'd10; + v__h1356 = v__h1362 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1356, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) - $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1418); + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1510 = $stime; + #0; + end + v__h1504 = v__h1510 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1504); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v new file mode 100644 index 0000000..65d7430 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v @@ -0,0 +1,92 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// +// +// +// Ports: +// Name I/O size props +// RST_N_gen_rst O 1 reset +// CLK I 1 clock +// RST_N I 1 unused +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkPowerOnReset(CLK, + RST_N, + + RST_N_gen_rst); + input CLK; + input RST_N; + + // output resets + output RST_N_gen_rst; + + // signals for module outputs + wire RST_N_gen_rst; + + // ports of submodule ctr + wire [7 : 0] ctr$D_IN, ctr$Q_OUT; + wire ctr$EN; + + // ports of submodule isInPowerOnReset + wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT; + + // ports of submodule rst_ifc + wire rst_ifc$OUT; + + // rule scheduling signals + wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown; + + // remaining internal signals + wire NOT_isInPowerOnReset__read___d5; + + // output resets + assign RST_N_gen_rst = rst_ifc$OUT ; + + // submodule ctr + RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK), + .D_IN(ctr$D_IN), + .EN(ctr$EN), + .Q_OUT(ctr$Q_OUT)); + + // submodule isInPowerOnReset + RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK), + .D_IN(isInPowerOnReset$D_IN), + .EN(isInPowerOnReset$EN), + .Q_OUT(isInPowerOnReset$Q_OUT)); + + // submodule rst_ifc + ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT)); + + // rule RL_countDown + assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + + // submodule ctr + assign ctr$D_IN = ctr$Q_OUT - 8'd1 ; + assign ctr$EN = isInPowerOnReset$Q_OUT ; + + // submodule isInPowerOnReset + assign isInPowerOnReset$D_IN = 1'd0 ; + assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ; + + // remaining internal signals + assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ; +endmodule // mkPowerOnReset + diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index dcc8699..0888d5b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -94,6 +94,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -192,6 +193,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -454,6 +456,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1421,6 +1424,7 @@ module mkProc(CLK, core_0$EN_v_to_TV_0_get, core_0$EN_v_to_TV_1_get, core_0$RDY_coreIndInv_terminate, + core_0$RDY_coreReq_start, core_0$RDY_dCacheToParent_fromP_enq, core_0$RDY_dCacheToParent_rqToP_deq, core_0$RDY_dCacheToParent_rqToP_first, @@ -1461,6 +1465,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_respLd_enq, core_0$RDY_v_to_TV_0_get, core_0$RDY_v_to_TV_1_get, + core_0$coreReq_start_running, core_0$hart0_run_halt_server_request_put, core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, @@ -2104,60 +2109,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162844; - reg [31 : 0] v__h162380; - reg [31 : 0] v__h5520; - reg [31 : 0] v__h5693; - reg [31 : 0] v__h5953; - reg [31 : 0] v__h8095; - reg [31 : 0] v__h8310; - reg [31 : 0] v__h2670; - reg [31 : 0] v__h4343; - reg [31 : 0] v__h9480; - reg [31 : 0] v__h9973; - reg [31 : 0] v__h10136; - reg [31 : 0] v__h134337; - reg [31 : 0] v__h134504; - reg [31 : 0] v__h136607; - reg [31 : 0] v__h153951; - reg [31 : 0] v__h133718; - reg [31 : 0] v__h160645; - reg [31 : 0] v__h161153; - reg [31 : 0] v__h2664; - reg [31 : 0] v__h4337; - reg [31 : 0] v__h5514; - reg [31 : 0] v__h5687; - reg [31 : 0] v__h5947; - reg [31 : 0] v__h8089; - reg [31 : 0] v__h8304; - reg [31 : 0] v__h9474; - reg [31 : 0] v__h9967; - reg [31 : 0] v__h10130; - reg [31 : 0] v__h133712; - reg [31 : 0] v__h134331; - reg [31 : 0] v__h134498; - reg [31 : 0] v__h136601; - reg [31 : 0] v__h153945; - reg [31 : 0] v__h160639; - reg [31 : 0] v__h161147; - reg [31 : 0] v__h162374; - reg [31 : 0] v__h162838; + reg [31 : 0] v__h162856; + reg [31 : 0] v__h162388; + reg [31 : 0] v__h5528; + reg [31 : 0] v__h5701; + reg [31 : 0] v__h5961; + reg [31 : 0] v__h8103; + reg [31 : 0] v__h8318; + reg [31 : 0] v__h2678; + reg [31 : 0] v__h4351; + reg [31 : 0] v__h9488; + reg [31 : 0] v__h9981; + reg [31 : 0] v__h10144; + reg [31 : 0] v__h134345; + reg [31 : 0] v__h134512; + reg [31 : 0] v__h136615; + reg [31 : 0] v__h153959; + reg [31 : 0] v__h133726; + reg [31 : 0] v__h160653; + reg [31 : 0] v__h161161; + reg [31 : 0] v__h2672; + reg [31 : 0] v__h4345; + reg [31 : 0] v__h5522; + reg [31 : 0] v__h5695; + reg [31 : 0] v__h5955; + reg [31 : 0] v__h8097; + reg [31 : 0] v__h8312; + reg [31 : 0] v__h9482; + reg [31 : 0] v__h9975; + reg [31 : 0] v__h10138; + reg [31 : 0] v__h133720; + reg [31 : 0] v__h134339; + reg [31 : 0] v__h134506; + reg [31 : 0] v__h136609; + reg [31 : 0] v__h153953; + reg [31 : 0] v__h160647; + reg [31 : 0] v__h161155; + reg [31 : 0] v__h162382; + reg [31 : 0] v__h162850; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, @@ -2167,44 +2172,44 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, - data64__h147777, - dword__h93782, - ld_data__h131939, - old_dword__h89472, - w1__h47861, - w1__h47866, - w2__h47862, - w2__h47868, - x__h47857; + data64__h147785, + dword__h93790, + ld_data__h131947, + old_dword__h89480, + w1__h47869, + w1__h47874, + w2__h47870, + w2__h47876, + x__h47865; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147778; + reg [7 : 0] strb8__h147786; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61575; + reg [2 : 0] x__h61583; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, - x__h61582, - x__h82300; + x__h61590, + x__h82308; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - new_cline__h134640; + new_cline__h134648; wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, @@ -2225,89 +2230,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - data__h31950, - failed_testnum__h162423, - line_addr__h101846, - line_addr__h101932, - mask__h89469, - mem_req_rd_addr_araddr__h133938, - mem_req_wr_addr_awaddr__h147862, - mmioPlatform_fromHostQ_data_0__h42651, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48453, - n__read_addr__h61443, - n__read_addr__h61528, - n__read_addr__h80062, - n__read_addr__h80141, - n__read_snd_addr__h123373, - newData__h32031, - newData__h34961, - new_dword__h89473, - op_result__h48469, - op_result__h48999, - op_result__h49004, - op_result__h49009, - op_result__h49014, - op_result__h49020, - op_result__h49027, - op_result__h49033, - result__h47912, - result__h48036, - result__h48064, - result__h48092, - result__h48120, - result__h48148, - result__h48176, - result__h48204, - result__h48232, - result__h48277, - result__h48305, - result__h48333, - result__h48361, - result__h48402, - result__h48430, - result__h48556, - result__h48583, - result__h48610, - result__h48637, - result__h48664, - result__h48691, - result__h48718, - result__h48745, - result__h48789, - result__h48816, - result__h48843, - result__h48870, - result__h48910, - result__h48937, - result__h49054, - result__h49120, - result__h49186, - result__h49252, - result__h49318, - result__h49384, - result__h49450, - result__h49512, - result__h49557, - result__h49623, - result__h49689, - result__h49747, - result__h49792, - w1___1__h47971, - w2___1__h47972, - x1_avValue_data__h40323, - x1_avValue_data__h44790, - x__h32142, - x__h35052, - x__h37412, - x__h40841, - x__h40852, - x__h42861, - x__h42872, - x__h49969, - x__h90635, - y__h90636, - y__h90637; + data__h31958, + failed_testnum__h162431, + line_addr__h101854, + line_addr__h101940, + mask__h89477, + mem_req_rd_addr_araddr__h133946, + mem_req_wr_addr_awaddr__h147870, + mmioPlatform_fromHostQ_data_0__h42659, + mmioPlatform_mtime__h37272, + mmioPlatform_reqData__h48461, + n__read_addr__h61451, + n__read_addr__h61536, + n__read_addr__h80070, + n__read_addr__h80149, + n__read_snd_addr__h123381, + newData__h32039, + newData__h34969, + new_dword__h89481, + op_result__h48477, + op_result__h49007, + op_result__h49012, + op_result__h49017, + op_result__h49022, + op_result__h49028, + op_result__h49035, + op_result__h49041, + result__h47920, + result__h48044, + result__h48072, + result__h48100, + result__h48128, + result__h48156, + result__h48184, + result__h48212, + result__h48240, + result__h48285, + result__h48313, + result__h48341, + result__h48369, + result__h48410, + result__h48438, + result__h48564, + result__h48591, + result__h48618, + result__h48645, + result__h48672, + result__h48699, + result__h48726, + result__h48753, + result__h48797, + result__h48824, + result__h48851, + result__h48878, + result__h48918, + result__h48945, + result__h49062, + result__h49128, + result__h49194, + result__h49260, + result__h49326, + result__h49392, + result__h49458, + result__h49520, + result__h49565, + result__h49631, + result__h49697, + result__h49755, + result__h49800, + w1___1__h47979, + w2___1__h47980, + x1_avValue_data__h40331, + x1_avValue_data__h44798, + x__h32150, + x__h35060, + x__h37420, + x__h40849, + x__h40860, + x__h42869, + x__h42880, + x__h49977, + x__h90643, + y__h90644, + y__h90645; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; @@ -2319,16 +2324,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w17861_BITS_31_TO_0__q15, - w27862_BITS_31_TO_0__q16, - x_data__h30533; + v__h31751, + v__h31788, + w17869_BITS_31_TO_0__q15, + w27870_BITS_31_TO_0__q16, + x_data__h30541; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; - wire [5 : 0] x__h133973, x__h147887; + wire [5 : 0] x__h133981, x__h147895; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; - wire [3 : 0] b__h133645, b__h2564; - wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; + wire [3 : 0] b__h133653, b__h2572; + wire [2 : 0] n__read_id__h61455, n__read_id__h61540, x__h7933; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, @@ -2390,27 +2395,28 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqBE_BIT_0___h30166, + mmioPlatform_reqBE_BIT_4___h30126, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61448, - n__read_child__h61533, - n__read_child__h80065, - n__read_child__h80144, - n__read_snd_id__h123374, + n__read_child__h61456, + n__read_child__h61541, + n__read_child__h80073, + n__read_child__h80152, + n__read_snd_id__h123382, propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, - x__h61261, - x__h74813, - x__h79884; + x__h61269, + x__h74821, + x__h79892; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; - assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; + assign CAN_FIRE_start = + mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; assign WILL_FIRE_start = EN_start ; // value method master0_m_awvalid @@ -2845,6 +2851,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -2901,7 +2908,7 @@ module mkProc(CLK, .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), .EN_v_to_TV_0_get(core_0$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(core_0$EN_v_to_TV_1_get), - .RDY_coreReq_start(), + .RDY_coreReq_start(core_0$RDY_coreReq_start), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), .RDY_coreIndInv_perfResp(), @@ -3676,14 +3683,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2564 == 4'd0 ; + b__h2572 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2564 != 4'd0 && + b__h2572 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3796,7 +3803,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42861 == 64'd0 || + x__h42869 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -4116,13 +4123,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133645 == 4'd0 ; + b__h133653 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133645 != 4'd0 && + b__h133653 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4226,7 +4233,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30541 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -4266,7 +4273,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31958 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -4291,10 +4298,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101846, + { line_addr__h101854, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101932, + { line_addr__h101940, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4305,11 +4312,11 @@ module mkProc(CLK, { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4408,7 +4415,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47857 } ; + x__h47865 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4417,7 +4424,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49977, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4432,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42869 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42861 != 64'd0 ; + x__h42869 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40841 == 64'd0 ; + x__h40849 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - x__h61261 ; + x__h61269 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - x__h79884 ; + x__h79892 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; + { 1'd1, n__read_snd_addr__h123381, n__read_snd_id__h123382 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4526,11 +4533,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2564 - 4'd1 ; + b__h2572 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2564 ; + b__h2572 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4579,11 +4586,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133645 - 4'd1 ; + b__h133653 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133645 ; + b__h133653 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4646,7 +4653,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133946, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4664,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147870, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147777, strb8__h147778, 1'd1 } ; + { data64__h147785, strb8__h147786, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4682,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134648 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4730,8 +4737,8 @@ module mkProc(CLK, // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101846 : - line_addr__h101932 ; + line_addr__h101854 : + line_addr__h101940 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4892,7 +4899,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34969 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4908,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32039 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5118,7 +5125,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7925, + x__h7933, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -5218,6 +5225,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -5321,7 +5329,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131939, llc$dma_respLd_first[3] } ; + { ld_data__h131947, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5475,7 +5483,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134640, + { new_cline__h134648, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5559,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93782, 3'd1 } ; + { 4'd0, dword__h93790, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5854,47 +5862,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37420), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h32150)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37272), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h35060)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40852)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42659), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h40860)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h42872)); + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h42880)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40323 } } ; + x1_avValue_data__h40331 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5910,7 +5918,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; + newData__h32039 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5975,7 +5983,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - x__h74813 } ; + x__h74821 } ; assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5987,29 +5995,29 @@ module mkProc(CLK, assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? @@ -6154,11 +6162,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42861 == 64'd0 : - x__h40841 == 64'd0, + x__h42869 == 64'd0 : + x__h40849 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44790 } ; + x1_avValue_data__h44798 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6392,58 +6400,58 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = - { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + { CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = - { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + { CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - x__h82300 } ; + x__h82308 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = - { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + { CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = - { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - x__h61575, - x__h61582 } ; - assign b__h133645 = + { CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + x__h61583, + x__h61590 } ; + assign b__h133653 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2564 = + assign b__h2572 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31958 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h162423 = + { v__h31751, 32'd0 } ; + assign failed_testnum__h162431 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101846 = + assign line_addr__h101854 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101932 = + assign line_addr__h101940 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = - line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; + line_addr__h101940 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = - line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89469 = + line_addr__h101854 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89477 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6476,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133938 = - { llc$to_mem_toM_first[68:11], x__h133973 } ; - assign mem_req_wr_addr_awaddr__h147862 = - { llc$to_mem_toM_first[639:582], x__h147887 } ; + assign mem_req_rd_addr_araddr__h133946 = + { llc$to_mem_toM_first[68:11], x__h133981 } ; + assign mem_req_wr_addr_awaddr__h147870 = + { llc$to_mem_toM_first[639:582], x__h147895 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42651 = + assign mmioPlatform_fromHostQ_data_0__h42659 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,18 +6494,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37272 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + mmioPlatform_mtimecmp_0 <= newData__h34969 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30166 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30126 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48461 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6529,105 +6537,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61443 = + assign n__read_addr__h61451 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61528 = + assign n__read_addr__h61536 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80062 = + assign n__read_addr__h80070 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : 64'd0 ; - assign n__read_addr__h80141 = + assign n__read_addr__h80149 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : 64'd0 ; - assign n__read_child__h61448 = + assign n__read_child__h61456 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61533 = + assign n__read_child__h61541 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80065 = + assign n__read_child__h80073 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; - assign n__read_child__h80144 = + assign n__read_child__h80152 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; - assign n__read_id__h61447 = + assign n__read_id__h61455 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61532 = + assign n__read_id__h61540 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123373 = + assign n__read_snd_addr__h123381 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123374 = + assign n__read_snd_id__h123382 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32039 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : + x__h32150 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + assign newData__h34969 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : + x__h35060 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h134640 = + assign new_cline__h134648 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89473 = x__h90635 | y__h90636 ; - assign op_result__h48469 = + assign new_dword__h89481 = x__h90643 | y__h90644 ; + assign op_result__h48477 = IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; - assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; - assign op_result__h49004 = w1__h47866 & w2__h47868 ; - assign op_result__h49009 = w1__h47866 | w2__h47868 ; - assign op_result__h49014 = - (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; - assign op_result__h49020 = - (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; - assign op_result__h49027 = + assign op_result__h49007 = w1__h47874 ^ w2__h47876 ; + assign op_result__h49012 = w1__h47874 & w2__h47876 ; + assign op_result__h49017 = w1__h47874 | w2__h47876 ; + assign op_result__h49022 = + (w1__h47874 < w2__h47876) ? w1__h47874 : w2__h47876 ; + assign op_result__h49028 = + (w1__h47874 <= w2__h47876) ? w2__h47876 : w1__h47874 ; + assign op_result__h49035 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w1__h47866 : - w2__h47868 ; - assign op_result__h49033 = + w1__h47874 : + w2__h47876 ; + assign op_result__h49041 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w2__h47868 : - w1__h47866 ; + w2__h47876 : + w1__h47874 ; assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6638,126 +6646,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47912 = + assign result__h47920 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; - assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48556 = + assign result__h48044 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48072 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48100 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48128 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48156 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48184 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48212 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48240 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48285 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48313 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48341 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48369 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48410 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48438 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48564 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48583 = + assign result__h48591 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48610 = + assign result__h48618 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48637 = + assign result__h48645 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48664 = + assign result__h48672 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48691 = + assign result__h48699 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48718 = + assign result__h48726 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48745 = + assign result__h48753 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48789 = + assign result__h48797 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48816 = + assign result__h48824 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48843 = + assign result__h48851 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48870 = + assign result__h48878 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48910 = + assign result__h48918 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48937 = + assign result__h48945 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49054 = + assign result__h49062 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49120 = + assign result__h49128 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49186 = + assign result__h49194 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49252 = + assign result__h49260 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49318 = + assign result__h49326 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49384 = + assign result__h49392 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49450 = + assign result__h49458 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49512 = + assign result__h49520 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; - assign result__h49557 = + assign result__h49565 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49623 = + assign result__h49631 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49689 = + assign result__h49697 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49747 = + assign result__h49755 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; - assign result__h49792 = + assign result__h49800 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; - assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; - assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; - assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; - assign x1_avValue_data__h40323 = + assign v__h31751 = mmioPlatform_waitUpperMSIPCRs ? v__h31788 : 32'd0 ; + assign v__h31788 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17869_BITS_31_TO_0__q15 = w1__h47869[31:0] ; + assign w1___1__h47979 = { 32'd0, w1__h47869[31:0] } ; + assign w27870_BITS_31_TO_0__q16 = w2__h47870[31:0] ; + assign w2___1__h47980 = { 32'd0, w2__h47870[31:0] } ; + assign x1_avValue_data__h40331 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44790 = + assign x1_avValue_data__h44798 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40841 = + assign x__h133981 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147895 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37420 = mmioPlatform_mtimecmp_0 ; + assign x__h40849 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40852 : + x__h40860 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; - assign x__h42861 = + assign x__h42869 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42872 : + x__h42880 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6774,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61261 = + assign x__h49977 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61269 = SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; - assign x__h74813 = + assign x__h74821 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; - assign x__h7925 = + assign x__h7933 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79884 = + assign x__h79892 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; - assign x__h90635 = old_dword__h89472 & y__h90637 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90636 = + assign x__h90643 = old_dword__h89480 & y__h90645 ; + assign x_data__h30541 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90644 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89469 ; - assign y__h90637 = + mask__h89477 ; + assign y__h90645 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,141 +7009,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h147785 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147785 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147785 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147785 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147785 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147785 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147785 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147785 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131947 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131947 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131947 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131947 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131947 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131947 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131947 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131947 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147786 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147786 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147786 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147786 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147786 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147786 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147786 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147786 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48036 or - result__h48064 or - result__h48092 or - result__h48120 or - result__h48148 or - result__h48176 or result__h48204 or result__h48232) + result__h48044 or + result__h48072 or + result__h48100 or + result__h48128 or + result__h48156 or + result__h48184 or result__h48212 or result__h48240) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48036; + result__h48044; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48064; + result__h48072; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48092; + result__h48100; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48120; + result__h48128; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48148; + result__h48156; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48176; + result__h48184; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48204; + result__h48212; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48232; + result__h48240; endcase end always@(mmioPlatform_curReq or - result__h48277 or - result__h48305 or result__h48333 or result__h48361) + result__h48285 or + result__h48313 or result__h48341 or result__h48369) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48277; + result__h48285; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48305; + result__h48313; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48333; + result__h48341; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48361; + result__h48369; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48402 or result__h48430) + always@(mmioPlatform_curReq or result__h48410 or result__h48438) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48402; + result__h48410; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48430; + result__h48438; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase @@ -7148,103 +7156,103 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - w2__h47862 = + w2__h47870 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w2___1__h47972 or + w2___1__h47980 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; - 2'b10: w2__h47868 = w2___1__h47972; + 2'b10: w2__h47876 = w2___1__h47980; 2'b11: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_curReq or - result__h48556 or - result__h48583 or - result__h48610 or - result__h48637 or - result__h48664 or - result__h48691 or result__h48718 or result__h48745) + result__h48564 or + result__h48591 or + result__h48618 or + result__h48645 or + result__h48672 or + result__h48699 or result__h48726 or result__h48753) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48556; + result__h48564; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48583; + result__h48591; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48610; + result__h48618; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48637; + result__h48645; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48664; + result__h48672; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48691; + result__h48699; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48718; + result__h48726; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48745; + result__h48753; endcase end always@(mmioPlatform_curReq or - result__h48789 or - result__h48816 or result__h48843 or result__h48870) + result__h48797 or + result__h48824 or result__h48851 or result__h48878) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48789; + result__h48797; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48816; + result__h48824; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48843; + result__h48851; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48870; + result__h48878; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48910 or result__h48937) + always@(mmioPlatform_curReq or result__h48918 or result__h48945) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48910; + result__h48918; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48937; + result__h48945; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase @@ -7257,42 +7265,42 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - w1__h47861 = + w1__h47869 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w1___1__h47971 or + w1___1__h47979 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; - 2'b10: w1__h47866 = w1___1__h47971; + 2'b10: w1__h47874 = w1___1__h47979; 2'b11: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w17861_BITS_31_TO_0__q15 or + w17869_BITS_31_TO_0__q15 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) @@ -7304,8 +7312,8 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - { {32{w17861_BITS_31_TO_0__q15[31]}}, - w17861_BITS_31_TO_0__q15 }; + { {32{w17869_BITS_31_TO_0__q15[31]}}, + w17869_BITS_31_TO_0__q15 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; @@ -7314,7 +7322,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w27862_BITS_31_TO_0__q16 or + w27870_BITS_31_TO_0__q16 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) @@ -7326,116 +7334,116 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - { {32{w27862_BITS_31_TO_0__q16[31]}}, - w27862_BITS_31_TO_0__q16 }; + { {32{w27870_BITS_31_TO_0__q16[31]}}, + w27870_BITS_31_TO_0__q16 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49033 or - w2__h47868 or - op_result__h48469 or - op_result__h48999 or - op_result__h49004 or - op_result__h49009 or - op_result__h49027 or op_result__h49014 or op_result__h49020) + op_result__h49041 or + w2__h47876 or + op_result__h48477 or + op_result__h49007 or + op_result__h49012 or + op_result__h49017 or + op_result__h49035 or op_result__h49022 or op_result__h49028) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - w2__h47868; + w2__h47876; 4'd1: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48469; + op_result__h48477; 4'd2: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48999; + op_result__h49007; 4'd3: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49004; + op_result__h49012; 4'd4: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49009; + op_result__h49017; 4'd5: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49027; + op_result__h49035; 4'd7: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49014; + op_result__h49022; 4'd8: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49020; + op_result__h49028; default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49033; + op_result__h49041; endcase end always@(mmioPlatform_curReq or - result__h49512 or - result__h49557 or result__h49623 or result__h49689) + result__h49520 or + result__h49565 or result__h49631 or result__h49697) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49512; + result__h49520; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49557; + result__h49565; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49623; + result__h49631; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49689; + result__h49697; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47912 or - result__h49054 or - result__h49120 or - result__h49186 or - result__h49252 or - result__h49318 or result__h49384 or result__h49450) + result__h47920 or + result__h49062 or + result__h49128 or + result__h49194 or + result__h49260 or + result__h49326 or result__h49392 or result__h49458) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h47912; + result__h47920; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49054; + result__h49062; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49120; + result__h49128; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49186; + result__h49194; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49252; + result__h49260; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49318; + result__h49326; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49384; + result__h49392; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49450; + result__h49458; endcase end - always@(mmioPlatform_curReq or result__h49747 or result__h49792) + always@(mmioPlatform_curReq or result__h49755 or result__h49800) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49747; + result__h49755; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49792; + result__h49800; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase @@ -7448,15 +7456,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; 2'b01: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; 2'b10: - x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47865 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end @@ -7540,278 +7548,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; endcase end - always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) + always@(x__h61269 or n__read_id__h61455 or n__read_id__h61540) begin - case (x__h61261) - 1'd0: x__h61575 = n__read_id__h61447; - 1'd1: x__h61575 = n__read_id__h61532; + case (x__h61269) + 1'd0: x__h61583 = n__read_id__h61455; + 1'd1: x__h61583 = n__read_id__h61540; endcase end - always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) + always@(x__h61269 or n__read_child__h61456 or n__read_child__h61541) begin - case (x__h61261) - 1'd0: x__h61582 = n__read_child__h61448; - 1'd1: x__h61582 = n__read_child__h61533; + case (x__h61269) + 1'd0: x__h61590 = n__read_child__h61456; + 1'd1: x__h61590 = n__read_child__h61541; endcase end - always@(x__h61261 or + always@(x__h61269 or propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; 1'd1: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; endcase end - always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) + always@(x__h61269 or n__read_addr__h61451 or n__read_addr__h61536) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61443; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61451; 1'd1: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61528; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61536; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) + always@(x__h79892 or n__read_child__h80073 or n__read_child__h80152) begin - case (x__h79884) - 1'd0: x__h82300 = n__read_child__h80065; - 1'd1: x__h82300 = n__read_child__h80144; + case (x__h79892) + 1'd0: x__h82308 = n__read_child__h80073; + 1'd1: x__h82308 = n__read_child__h80152; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79884 or + always@(x__h79892 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : 2'd0; 1'd1: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : 2'd0; endcase end - always@(x__h79884 or + always@(x__h79892 or NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; 1'd1: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; endcase end - always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) + always@(x__h79892 or n__read_addr__h80070 or n__read_addr__h80149) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80062; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80070; 1'd1: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80141; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80149; endcase end @@ -8227,14 +8235,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162844 = $stime; + v__h162856 = $stime; #0; end - v__h162838 = v__h162844 / 32'd10; + v__h162850 = v__h162856 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162838, + v__h162850, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8244,14 +8252,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162380 = $stime; + v__h162388 = $stime; #0; end - v__h162374 = v__h162380 / 32'd10; + v__h162382 = v__h162388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162374, + v__h162382, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8261,7 +8269,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162423); + $display("FAIL %0d", failed_testnum__h162431); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8269,14 +8277,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5520 = $stime; + v__h5528 = $stime; #0; end - v__h5514 = v__h5520 / 32'd10; + v__h5522 = v__h5528 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5514); + $display("%0d: %m.rl_handle_read_rsps ", v__h5522); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8336,16 +8344,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5693 = $stime; + v__h5701 = $stime; #0; end - v__h5687 = v__h5693 / 32'd10; + v__h5695 = v__h5701 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5687); + v__h5695); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8449,14 +8457,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5953 = $stime; + v__h5961 = $stime; #0; end - v__h5947 = v__h5953 / 32'd10; + v__h5955 = v__h5961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5947); + $display("%d: %m.rl_handle_write_req: St request:", v__h5955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8626,15 +8634,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h8095 = $stime; + v__h8103 = $stime; #0; end - v__h8089 = v__h8095 / 32'd10; + v__h8097 = v__h8103 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h8089); + $display("%0d: ERROR: CreditCounter: overflow", v__h8097); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8684,7 +8692,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7925); + $write("'h%h", x__h7933); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8815,16 +8823,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8310 = $stime; + v__h8318 = $stime; #0; end - v__h8304 = v__h8310 / 32'd10; + v__h8312 = v__h8318 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8304); + v__h8312); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9030,14 +9038,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2670 = $stime; + v__h2678 = $stime; #0; end - v__h2664 = v__h2670 / 32'd10; + v__h2672 = v__h2678 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2664); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2672); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9327,16 +9335,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4343 = $stime; + v__h4351 = $stime; #0; end - v__h4337 = v__h4343 / 32'd10; + v__h4345 = v__h4351 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4337); + v__h4345); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9542,14 +9550,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9480 = $stime; + v__h9488 = $stime; #0; end - v__h9474 = v__h9480 / 32'd10; + v__h9482 = v__h9488 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9474); + $display("%0d: %m.rl_discard_write_rsp", v__h9482); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9586,15 +9594,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9973 = $stime; + v__h9981 = $stime; #0; end - v__h9967 = v__h9973 / 32'd10; + v__h9975 = v__h9981 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9967); + v__h9975); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9634,14 +9642,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h10136 = $stime; + v__h10144 = $stime; #0; end - v__h10130 = v__h10136 / 32'd10; + v__h10138 = v__h10144 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h10130); + v__h10138); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9828,15 +9836,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h134337 = $stime; + v__h134345 = $stime; #0; end - v__h134331 = v__h134337 / 32'd10; + v__h134339 = v__h134345 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134331, + v__h134339, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9896,15 +9904,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134504 = $stime; + v__h134512 = $stime; #0; end - v__h134498 = v__h134504 / 32'd10; + v__h134506 = v__h134512 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134498); + v__h134506); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10085,16 +10093,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136607 = $stime; + v__h136615 = $stime; #0; end - v__h136601 = v__h136607 / 32'd10; + v__h136609 = v__h136615 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136601); + v__h136609); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11292,14 +11300,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153951 = $stime; + v__h153959 = $stime; #0; end - v__h153945 = v__h153951 / 32'd10; + v__h153953 = v__h153959 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153945); + $display("%0d: ERROR: CreditCounter: overflow", v__h153953); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11323,7 +11331,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_wr_addr_awaddr__h147862); + $write("'h%h", mem_req_wr_addr_awaddr__h147870); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11411,7 +11419,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", data64__h147777); + $write("'h%h", data64__h147785); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11419,7 +11427,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", strb8__h147778); + $write("'h%h", strb8__h147786); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11445,16 +11453,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133718 = $stime; + v__h133726 = $stime; #0; end - v__h133712 = v__h133718 / 32'd10; + v__h133720 = v__h133726 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133712, + v__h133720, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11542,7 +11550,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_rd_addr_araddr__h133938); + $write("'h%h", mem_req_rd_addr_araddr__h133946); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11623,15 +11631,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h160645 = $stime; + v__h160653 = $stime; #0; end - v__h160639 = v__h160645 / 32'd10; + v__h160647 = v__h160653 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160639, + v__h160647, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -11669,15 +11677,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161153 = $stime; + v__h161161 = $stime; #0; end - v__h161147 = v__h161153 / 32'd10; + v__h161155 = v__h161161 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161147); + v__h161155); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v b/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v new file mode 100644 index 0000000..4bedc0b --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v @@ -0,0 +1,5 @@ +module ASSIGN1(IN, OUT); + output OUT; + input IN; + assign OUT = IN; +endmodule diff --git a/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v b/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v new file mode 100644 index 0000000..1dc1123 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v @@ -0,0 +1,87 @@ + +// Copyright (c) 2000-2012 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + + +module MakeReset0 ( + CLK, + RST, + ASSERT_IN, + ASSERT_OUT, + + OUT_RST + ); + + parameter init = 1 ; + + input CLK ; + input RST ; + input ASSERT_IN ; + output ASSERT_OUT ; + + output OUT_RST ; + + reg rst ; + + assign ASSERT_OUT = rst == `BSV_RESET_VALUE ; + + assign OUT_RST = rst ; + + always@(posedge CLK or `BSV_RESET_EDGE RST) begin + if (RST == `BSV_RESET_VALUE) + rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE; + else + begin + if (ASSERT_IN) + rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE; + else // if (rst == 1'b0) + rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE; + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + + +`ifdef BSV_NO_INITIAL_BLOCKS +`else // not BSV_NO_INITIAL_BLOCKS + // synopsys translate_off + initial begin + #0 ; + rst = ~ `BSV_RESET_VALUE ; + end + // synopsys translate_on +`endif // BSV_NO_INITIAL_BLOCKS + +endmodule // MakeReset0 diff --git a/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v b/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v new file mode 100644 index 0000000..c685d10 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v @@ -0,0 +1,50 @@ + +// Copyright (c) 2000-2019 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +// Basic register with initial value but without reset (not for ASIC synthesis). +module RegUNInit(CLK, Q_OUT, D_IN, EN); + + parameter width = 1; + parameter init = { width {1'b0} } ; + + input CLK; + input RST; + input EN; + input [width - 1 : 0] D_IN; + output [width - 1 : 0] Q_OUT; + + reg [width - 1 : 0] Q_OUT; + initial Q_OUT = init; + + always@(posedge CLK) + begin + if (EN) + Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; + end +endmodule diff --git a/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v b/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v new file mode 100644 index 0000000..61a23bf --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v @@ -0,0 +1,41 @@ + +// Copyright (c) 2000-2009 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else +`define BSV_ASSIGNMENT_DELAY +`endif + + +module SyncWire( DIN, DOUT ); + + parameter width = 1; + + input [width - 1 : 0] DIN; + output [width - 1 : 0] DOUT; + + assign DOUT = DIN ; + + +endmodule diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index 97d20b6..ab95b20 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -6,7 +6,7 @@ // // Ports: // Name I/O size props -// RDY_coreReq_start O 1 const +// RDY_coreReq_start O 1 // RDY_coreReq_perfReq O 1 reg // coreIndInv_perfResp O 73 // RDY_coreIndInv_perfResp O 1 reg @@ -104,6 +104,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -184,6 +185,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -402,6 +404,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4510,9 +4513,10 @@ module mkCore(CLK, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, MUX_regRenamingTable$rename_0_getRename_1__SEL_3, - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_2, + MUX_renameStage_rg_m_halt_req$write_1__SEL_3, + MUX_renameStage_rg_m_halt_req$write_1__SEL_6, MUX_rf$write_3_wr_1__PSEL_1, MUX_rf$write_3_wr_1__SEL_1, MUX_rf$write_3_wr_1__SEL_2, @@ -4602,12 +4606,12 @@ module mkCore(CLK, CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q88, CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89, CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q90, - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120, - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121, + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118, + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119, CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50, CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q51, - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118, - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119, + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120, + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121, CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48, CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q49, CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122, @@ -4671,14 +4675,14 @@ module mkCore(CLK, CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q184, CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q185, CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q186, - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189, - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190, + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187, + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188, CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q160, CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q161, - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187, - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188, - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191, - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192, + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191, + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192, + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189, + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190, CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q143, CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619, @@ -4801,8 +4805,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q276, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244, + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243, CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241, CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, @@ -4818,14 +4822,14 @@ module mkCore(CLK, CASE_guard22690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, CASE_guard37351_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, CASE_guard37351_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, CASE_guard46663_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, CASE_guard46663_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard50518_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, CASE_guard50518_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, CASE_guard50619_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, CASE_guard55732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard55732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard59227_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59, @@ -4836,13 +4840,13 @@ module mkCore(CLK, CASE_guard68157_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard76655_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard76993_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, CASE_guard76993_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, CASE_guard85967_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, CASE_guard85967_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, CASE_guard95036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard96217_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, CASE_guard96217_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, @@ -4918,19 +4922,19 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3042; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2240, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16400; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16401; wire [463 : 0] commitStage_f_rob_data_first__5082_BIT_167_518_ETC___d15254; wire [457 : 0] rob_deqPort_0_deq_data__4661_BITS_161_TO_98_46_ETC___d15638; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037; wire [393 : 0] IF_commitStage_f_rob_data_first__5082_BITS_97__ETC___d15253; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3026, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16391; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392; wire [321 : 0] basicExec___d12137, basicExec___d12839; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3017, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16382, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11191, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11204, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11197; @@ -5903,7 +5907,7 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2176, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16427, x__h184591, x__h722372; wire [4 : 0] IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14628, @@ -6387,7 +6391,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13996, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14138, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14156, - NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_RDY_ETC___d15704, + NOT_rob_deqPort_0_canDeq__5662_5663_OR_regRena_ETC___d15704, NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_deq_ETC___d15988, NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320, NOT_rob_deqPort_1_deq_data__5670_BIT_25_5671_5_ETC___d15701, @@ -6618,7 +6622,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14136, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14154, f_csr_rsps_i_notFull__6120_AND_f_csr_reqs_firs_ETC___d16223, - fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338, + fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14467, @@ -6669,7 +6673,7 @@ module mkCore(CLK, next_deqP___1__h336636, r1__read_BIT_20___h663156, r__h620917, - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544, + regRenamingTable_RDY_commit_0_commit__5265_AND_ETC___d15325, regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201, regRenamingTable_RDY_rename_1_getRename__4264__ETC___d14282, regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690, @@ -6698,7 +6702,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180, rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16059, - rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325, + rob_RDY_enqPort_1_enq__4330_AND_NOT_fetchStage_ETC___d14338, tsr_val__h736523, tvm_val__h736525, v__h303709, @@ -6714,8 +6718,8 @@ module mkCore(CLK, x__h608480; // action method coreReq_start - assign RDY_coreReq_start = 1'd1 ; - assign CAN_FIRE_coreReq_start = 1'd1 ; + assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; + assign CAN_FIRE_coreReq_start = !renameStage_rg_m_halt_req[4] ; assign WILL_FIRE_coreReq_start = EN_coreReq_start ; // action method coreReq_perfReq @@ -6752,7 +6756,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16400 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16401 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6772,7 +6776,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q274, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16427 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9965,8 +9969,9 @@ module mkCore(CLK, assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ; // rule RL_setDoFlushBrPred - assign CAN_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_flushBrPred ; - assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_flushBrPred ; + assign CAN_FIRE_RL_setDoFlushBrPred = + flush_brpred && fetchStage$emptyForFlush ; + assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = @@ -9982,8 +9987,8 @@ module mkCore(CLK, assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ; // rule RL_flushBrPred - assign CAN_FIRE_RL_flushBrPred = flush_brpred && fetchStage$emptyForFlush ; - assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_flushBrPred ; + assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; + assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; // rule RL_rl_debug_gpr_read assign CAN_FIRE_RL_rl_debug_gpr_read = @@ -10028,7 +10033,8 @@ module mkCore(CLK, f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] && rg_core_run_state == 2'd2 && !f_run_halt_reqs$D_OUT ; - assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ; + assign WILL_FIRE_RL_rl_debug_halt_req = + CAN_FIRE_RL_rl_debug_halt_req && !EN_coreReq_start ; // rule RL_rl_debug_halt_req_already_halted assign CAN_FIRE_RL_rl_debug_halt_req_already_halted = @@ -10443,8 +10449,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10498,7 +10504,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325 && + regRenamingTable_RDY_commit_0_commit__5265_AND_ETC___d15325 && NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15342 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10533,7 +10539,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_RDY_ETC___d15704 && + NOT_rob_deqPort_0_canDeq__5662_5663_OR_regRena_ETC___d15704 && NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15716 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11527,9 +11533,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13290 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11537,19 +11544,21 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13600 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_csrInstOrInterruptInflight_canon assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; @@ -11594,7 +11603,8 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_mmio_pRqQ_canonicalize assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ; @@ -12067,16 +12077,17 @@ module mkCore(CLK, WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; - assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst || - WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 = - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 && - csrf_rg_dcsr[2] ; - assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_3 = + WILL_FIRE_RL_renameStage_doRenaming_Trap && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_6 = + EN_coreReq_start && !coreReq_start_running ; assign MUX_rf$write_3_wr_1__PSEL_1 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || WILL_FIRE_RL_coreFix_memExe_doRespLdMem ; @@ -15277,21 +15288,24 @@ module mkCore(CLK, assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; // register renameStage_rg_m_halt_req - always@(WILL_FIRE_RL_rl_debug_resume or + always@(MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_3 or + WILL_FIRE_RL_rl_debug_resume or WILL_FIRE_RL_rl_debug_halt_req or - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or - MUX_renameStage_rg_m_halt_req$write_1__SEL_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; - WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30; - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || - MUX_renameStage_rg_m_halt_req$write_1__SEL_2: - renameStage_rg_m_halt_req$D_IN = 5'd31; - default: renameStage_rg_m_halt_req$D_IN = - 5'b01010 /* unspecified value */ ; - endcase - end + MUX_renameStage_rg_m_halt_req$write_1__SEL_6) + case (1'b1) + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_3: + renameStage_rg_m_halt_req$D_IN = 5'd31; + WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; + WILL_FIRE_RL_rl_debug_halt_req || + MUX_renameStage_rg_m_halt_req$write_1__SEL_6: + renameStage_rg_m_halt_req$D_IN = 5'd30; + default: renameStage_rg_m_halt_req$D_IN = + 5'b01010 /* unspecified value */ ; + endcase assign renameStage_rg_m_halt_req$EN = (WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap) && @@ -15299,6 +15313,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && csrf_rg_dcsr[2] || + EN_coreReq_start && !coreReq_start_running || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -16630,18 +16645,18 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = x__h290202 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; + assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] : (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] : 3'd0) ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or @@ -18468,7 +18483,7 @@ module mkCore(CLK, assign fetchStage$EN_train_predictors = coreFix_trainBPQ_1$EMPTY_N || WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ; - assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_flushBrPred ; + assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ; assign fetchStage$EN_perf_setStatus = 1'b0 ; assign fetchStage$EN_perf_req = 1'b0 ; assign fetchStage$EN_perf_resp = 1'b0 ; @@ -21604,8 +21619,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10049 = (_theResult___fst_exp__h603026 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21615,8 +21630,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10585 = (_theResult___fst_exp__h563722 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -24330,10 +24345,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14214 = IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14411 = @@ -24347,10 +24362,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14301 && IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14093 && (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14328 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338) ; + rob_RDY_enqPort_1_enq__4330_AND_NOT_fetchStage_ETC___d14338) ; assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14628 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && @@ -24702,7 +24717,7 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd11) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; assign NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14958 = NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14951 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && @@ -24724,7 +24739,7 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd14) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; assign NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15331 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -25693,9 +25708,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13985 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14154 ; - assign NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_RDY_ETC___d15704 = + assign NOT_rob_deqPort_0_canDeq__5662_5663_OR_regRena_ETC___d15704 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25734,7 +25749,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14267 = !specTagManager$canClaim || @@ -25768,21 +25783,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, x__h295972 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16427 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16382 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16391 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16382, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16400 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16391, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16401 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10246 = @@ -28158,7 +28173,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 : + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 ; assign _theResult___fst_exp__h564505 = (_theResult___fst_exp__h563722 == 11'd2047) ? @@ -28284,7 +28299,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 : + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 ; assign _theResult___fst_exp__h595025 = (_theResult___fst_exp__h594193 == 11'd2047) ? @@ -28314,7 +28329,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 : + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 ; assign _theResult___fst_exp__h603809 = (_theResult___fst_exp__h603026 == 11'd2047) ? @@ -29752,7 +29767,7 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd11 || !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 ; assign commitStage_f_rob_data_first__5082_BIT_167_518_ETC___d15254 = { commitStage_f_rob_data$D_OUT[167:166], commitStage_f_rob_data$D_OUT[166] ? @@ -30568,12 +30583,14 @@ module mkCore(CLK, fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; assign fcsr_csr__read__h615715 = { 56'd0, x__h619373 } ; - assign fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14334) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31385,14 +31402,13 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign r__h620917 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__5265_AND_ETC___d15325 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320 ; assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31921,13 +31937,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h618545 = { r1__read__h620943, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320 ; + assign rob_RDY_enqPort_1_enq__4330_AND_NOT_fetchStage_ETC___d14338 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14334) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4661_BITS_161_TO_98_46_ETC___d15638 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -33498,23 +33513,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33543,6 +33541,23 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19]) @@ -35403,70 +35418,18 @@ module mkCore(CLK, default: _theResult___fst_exp__h477007 = 8'd0; endcase end - always@(guard__h450619 or - _theResult___snd__h458618 or - out_sfd__h459113 or _theResult___sfd__h459110) - begin - case (guard__h450619) - 2'b0, 2'b01: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = - _theResult___snd__h458618[56:34]; - 2'b10: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = - out_sfd__h459113; - 2'b11: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = - _theResult___sfd__h459110; - endcase - end - always@(guard__h450619 or - _theResult___snd__h458618 or _theResult___sfd__h459110) - begin - case (guard__h450619) - 2'b0: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 = - _theResult___snd__h458618[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 = - _theResult___sfd__h459110; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 or - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 or - _theResult___snd__h458618) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h459188 = - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118; - 3'd1: - _theResult___fst_sfd__h459188 = - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119; - 3'd2: - _theResult___fst_sfd__h459188 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860; - 3'd3: - _theResult___fst_sfd__h459188 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862; - 3'd4: _theResult___fst_sfd__h459188 = _theResult___snd__h458618[56:34]; - default: _theResult___fst_sfd__h459188 = 23'd0; - endcase - end always@(guard__h441912 or sfdin__h450005 or out_sfd__h450531 or _theResult___sfd__h450528) begin case (guard__h441912) 2'b0, 2'b01: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 = sfdin__h450005[56:34]; 2'b10: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 = out_sfd__h450531; 2'b11: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 = _theResult___sfd__h450528; endcase end @@ -35474,16 +35437,16 @@ module mkCore(CLK, begin case (guard__h441912) 2'b0: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119 = sfdin__h450005[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119 = _theResult___sfd__h450528; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 or - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 or + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 or + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843 or sfdin__h450005) @@ -35491,10 +35454,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h450606 = - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118; 3'd1: _theResult___fst_sfd__h450606 = - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119; 3'd2: _theResult___fst_sfd__h450606 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841; @@ -35505,6 +35468,58 @@ module mkCore(CLK, default: _theResult___fst_sfd__h450606 = 23'd0; endcase end + always@(guard__h450619 or + _theResult___snd__h458618 or + out_sfd__h459113 or _theResult___sfd__h459110) + begin + case (guard__h450619) + 2'b0, 2'b01: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 = + _theResult___snd__h458618[56:34]; + 2'b10: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 = + out_sfd__h459113; + 2'b11: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 = + _theResult___sfd__h459110; + endcase + end + always@(guard__h450619 or + _theResult___snd__h458618 or _theResult___sfd__h459110) + begin + case (guard__h450619) + 2'b0: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121 = + _theResult___snd__h458618[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121 = + _theResult___sfd__h459110; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 or + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 or + _theResult___snd__h458618) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h459188 = + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120; + 3'd1: + _theResult___fst_sfd__h459188 = + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121; + 3'd2: + _theResult___fst_sfd__h459188 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860; + 3'd3: + _theResult___fst_sfd__h459188 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862; + 3'd4: _theResult___fst_sfd__h459188 = _theResult___snd__h458618[56:34]; + default: _theResult___fst_sfd__h459188 = 23'd0; + endcase + end always@(guard__h459549 or sfdin__h467771 or out_sfd__h468297 or _theResult___sfd__h468294) begin @@ -35612,61 +35627,23 @@ module mkCore(CLK, begin case (guard__h441912) 2'b0, 2'b01, 2'b10: - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h441912 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h441912) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - (guard__h441912 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h441912 != 2'b01 && guard__h441912 != 2'b10 && - guard__h441912 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h441912 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h441912) - 2'b0, 2'b01, 2'b10: - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = guard__h441912 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or guard__h441912) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = (guard__h441912 == 2'b0) ? @@ -35688,23 +35665,23 @@ module mkCore(CLK, begin case (guard__h450619) 2'b0, 2'b01, 2'b10: - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = guard__h450619 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or guard__h450619) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128; + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = (guard__h450619 == 2'b0) ? @@ -35721,6 +35698,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end + always@(guard__h441912 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h441912) + 2'b0, 2'b01, 2'b10: + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h441912 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h441912) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + (guard__h441912 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h441912 != 2'b01 && guard__h441912 != 2'b10 && + guard__h441912 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end always@(guard__h450619 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -36341,21 +36356,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595036 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576655 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595036) + case (guard__h576655) 2'b0, 2'b01, 2'b10: - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h595036 != 2'b11 || + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h576655 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595036) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576655) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36364,12 +36379,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h595036 == 2'b0) ? + (guard__h576655 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595036 != 2'b01 && guard__h595036 != 2'b10 && - guard__h595036 != 2'b11 || + guard__h576655 != 2'b01 && guard__h576655 != 2'b10 && + guard__h576655 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36380,21 +36395,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h576655 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576655) + case (guard__h595036) 2'b0, 2'b01, 2'b10: - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h576655 != 2'b11 || + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h595036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576655) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36403,12 +36418,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h576655 == 2'b0) ? + (guard__h595036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h576655 != 2'b01 && guard__h576655 != 2'b10 && - guard__h576655 != 2'b11 || + guard__h595036 != 2'b01 && guard__h595036 != 2'b10 && + guard__h595036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36521,66 +36536,15 @@ module mkCore(CLK, _theResult___exp__h555618; endcase end - always@(guard__h585967 or - _theResult___fst_exp__h594193 or _theResult___exp__h594922) - begin - case (guard__h585967) - 2'b0: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187 = - _theResult___fst_exp__h594193; - 2'b01, 2'b10, 2'b11: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187 = - _theResult___exp__h594922; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h594193 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 or - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - _theResult___fst_exp__h594193; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - 11'd0; - endcase - end - always@(guard__h585967 or - _theResult___fst_exp__h594193 or - out_exp__h594925 or _theResult___exp__h594922) - begin - case (guard__h585967) - 2'b0, 2'b01: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 = - _theResult___fst_exp__h594193; - 2'b10: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 = - out_exp__h594925; - 2'b11: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 = - _theResult___exp__h594922; - endcase - end always@(guard__h555732 or _theResult___fst_exp__h563722 or _theResult___exp__h564402) begin case (guard__h555732) 2'b0: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187 = _theResult___fst_exp__h563722; 2'b01, 2'b10, 2'b11: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187 = _theResult___exp__h564402; endcase end @@ -36588,7 +36552,7 @@ module mkCore(CLK, _theResult___fst_exp__h563722 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682 or - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189) + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36602,7 +36566,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = 11'd0; endcase @@ -36613,13 +36577,13 @@ module mkCore(CLK, begin case (guard__h555732) 2'b0, 2'b01: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = _theResult___fst_exp__h563722; 2'b10: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = out_exp__h564405; 2'b11: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = _theResult___exp__h564402; endcase end @@ -36628,10 +36592,10 @@ module mkCore(CLK, begin case (guard__h595036) 2'b0: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189 = _theResult___fst_exp__h603026; 2'b01, 2'b10, 2'b11: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189 = _theResult___exp__h603706; endcase end @@ -36639,7 +36603,7 @@ module mkCore(CLK, _theResult___fst_exp__h603026 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912 or - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191) + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36653,7 +36617,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = 11'd0; endcase @@ -36664,16 +36628,67 @@ module mkCore(CLK, begin case (guard__h595036) 2'b0, 2'b01: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 = _theResult___fst_exp__h603026; 2'b10: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 = out_exp__h603709; 2'b11: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 = _theResult___exp__h603706; endcase end + always@(guard__h585967 or + _theResult___fst_exp__h594193 or _theResult___exp__h594922) + begin + case (guard__h585967) + 2'b0: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191 = + _theResult___fst_exp__h594193; + 2'b01, 2'b10, 2'b11: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191 = + _theResult___exp__h594922; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h594193 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 or + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + _theResult___fst_exp__h594193; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + 11'd0; + endcase + end + always@(guard__h585967 or + _theResult___fst_exp__h594193 or + out_exp__h594925 or _theResult___exp__h594922) + begin + case (guard__h585967) + 2'b0, 2'b01: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 = + _theResult___fst_exp__h594193; + 2'b10: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 = + out_exp__h594925; + 2'b11: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 = + _theResult___exp__h594922; + endcase + end always@(guard__h537351 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h537351) @@ -38471,26 +38486,26 @@ module mkCore(CLK, begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = - !csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = + csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = - !csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = - !csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = + csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = + csrf_rg_dcsr[12]; endcase end always@(csrf_prv_reg or csrf_rg_dcsr) begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = - csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = + !csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = - csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = - csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = + !csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = + !csrf_rg_dcsr[12]; endcase end always@(rob$deqPort_0_deq_data) @@ -38944,15 +38959,6 @@ module mkCore(CLK, 3'd0; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -39166,6 +39172,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9999 or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9289 or diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index bb0d3be..607e8ac 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -78,6 +78,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// start_is_running I 1 // start_tohost_addr I 64 // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 @@ -161,6 +162,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -379,6 +381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1401,7 +1404,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1609,12 +1613,12 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5047; - reg [31 : 0] v__h5190; - reg [31 : 0] v__h15930; - reg [31 : 0] v__h5041; - reg [31 : 0] v__h5184; - reg [31 : 0] v__h15924; + reg [31 : 0] v__h5055; + reg [31 : 0] v__h5198; + reg [31 : 0] v__h15940; + reg [31 : 0] v__h5049; + reg [31 : 0] v__h5192; + reg [31 : 0] v__h15934; // synopsys translate_on // remaining internal signals @@ -2523,6 +2527,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2716,22 +2721,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -3359,6 +3364,7 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_proc$start_1__SEL_1 ? rg_fromhost_addr : start_fromhost_addr ; + assign proc$start_running = MUX_proc$start_1__SEL_1 || start_is_running ; assign proc$start_startpc = 64'h0000000070000000 ; assign proc$start_tohostAddr = MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; @@ -3700,15 +3706,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h5047 = $stime; + v__h5055 = $stime; #0; end - v__h5041 = v__h5047 / 32'd10; + v__h5049 = v__h5055 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h5041, + v__h5049, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -3716,17 +3722,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h5190 = $stime; + v__h5198 = $stime; #0; end - v__h5184 = v__h5190 / 32'd10; + v__h5192 = v__h5198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h5184, + v__h5192, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); @@ -3734,15 +3740,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15930 = $stime; + v__h15940 = $stime; #0; end - v__h15924 = v__h15930 / 32'd10; + v__h15934 = v__h15940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15924, + v__h15934, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v index add4077..64142bb 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v @@ -130,17 +130,13 @@ module mkJtagTap(CLK, // inlined wires wire [40 : 0] w_dmi_req$wget; - wire r_dmistat_busy$port1__read, + wire r_dmistat_busy$EN_port1__write, + r_dmistat_busy$port1__read, r_dmistat_busy$port2__read, r_tdo$EN_port0__write, r_tdo$port0__write_1, r_tdo$port1__read; - // register r_dmi - reg [39 : 0] r_dmi; - wire [39 : 0] r_dmi$D_IN; - wire r_dmi$EN; - // register r_dmistat_busy reg r_dmistat_busy; wire r_dmistat_busy$D_IN, r_dmistat_busy$EN; @@ -160,11 +156,6 @@ module mkJtagTap(CLK, wire [4 : 0] r_ir$D_IN; wire r_ir$EN; - // register r_state - reg [3 : 0] r_state; - wire [3 : 0] r_state$D_IN; - wire r_state$EN; - // register r_tdo reg r_tdo; wire r_tdo$D_IN, r_tdo$EN; @@ -179,6 +170,7 @@ module mkJtagTap(CLK, // ports of submodule f_dmi_req wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN; wire f_dmi_req$dCLR, + f_dmi_req$dCLR_RDY, f_dmi_req$dDEQ, f_dmi_req$dEMPTY_N, f_dmi_req$sCLR, @@ -193,18 +185,32 @@ module mkJtagTap(CLK, f_dmi_rsp$dDEQ, f_dmi_rsp$dEMPTY_N, f_dmi_rsp$sCLR, + f_dmi_rsp$sCLR_RDY, f_dmi_rsp$sENQ, f_dmi_rsp$sFULL_N; + // ports of submodule r_dmi + wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT; + wire r_dmi$EN; + + // ports of submodule r_initialize + wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT; + + // ports of submodule r_initialize2 + wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT; + + // ports of submodule r_state + wire [3 : 0] r_state$D_IN, r_state$Q_OUT; + wire r_state$EN; + // ports of submodule rst_tck wire rst_tck$OUT_RST; // ports of submodule tck_clock - wire tck_clock$CLK_IN, - tck_clock$CLK_IN_EN, - tck_clock$CLK_OUT, - tck_clock$COND_IN, - tck_clock$COND_IN_EN; + wire tck_clock$IN, tck_clock$OUT; + + // ports of submodule w_tck_crossed + wire w_tck_crossed$DOUT; // rule scheduling signals wire CAN_FIRE_RL_dmi_request, @@ -215,7 +221,9 @@ module mkJtagTap(CLK, CAN_FIRE_RL_dmi_response_ready, CAN_FIRE_RL_dmi_response_tck, CAN_FIRE_RL_dmi_start, - CAN_FIRE_RL_rl_tck, + CAN_FIRE_RL_mkConnectionVtoAf, + CAN_FIRE_RL_rl_initialize, + CAN_FIRE_RL_rl_initialize2, CAN_FIRE_RL_tick, CAN_FIRE_dmi_req_ready, CAN_FIRE_dmi_rsp_data, @@ -232,7 +240,9 @@ module mkJtagTap(CLK, WILL_FIRE_RL_dmi_response_ready, WILL_FIRE_RL_dmi_response_tck, WILL_FIRE_RL_dmi_start, - WILL_FIRE_RL_rl_tck, + WILL_FIRE_RL_mkConnectionVtoAf, + WILL_FIRE_RL_rl_initialize, + WILL_FIRE_RL_rl_initialize2, WILL_FIRE_RL_tick, WILL_FIRE_dmi_req_ready, WILL_FIRE_dmi_rsp_data, @@ -243,24 +253,24 @@ module mkJtagTap(CLK, WILL_FIRE_jtag_tms; // remaining internal signals - reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1, - v__h2135; - reg [4 : 0] newir__h3435; - reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3, - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2; - wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140, - v__h2233, - v__h2601, - x__h2449, - x__h2658, - y__h2659; - wire [4 : 0] v__h3299, x__h3350, y__h3351; - wire r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57, - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68, - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72; + reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1, + v__h2479; + reg [4 : 0] newir__h3774; + reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3, + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2; + wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146, + v__h2576, + v__h2941, + x__h2789, + x__h2996, + y__h2997; + wire [4 : 0] v__h3636, x__h3687, y__h3688; + wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78; // oscillator and gates for output clock CLK_jtag_tclk_out - assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ; + assign CLK_jtag_tclk_out = tck_clock$OUT ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; // action method jtag_tdi @@ -311,7 +321,7 @@ module mkJtagTap(CLK, // submodule f_dmi_busy FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST), - .CLK(tck_clock$CLK_OUT), + .CLK(tck_clock$OUT), .ENQ(f_dmi_busy$ENQ), .DEQ(f_dmi_busy$DEQ), .CLR(f_dmi_busy$CLR), @@ -321,7 +331,7 @@ module mkJtagTap(CLK, // submodule f_dmi_req SyncFIFOLevel #(.dataWidth(32'd41), .depth(32'd2), - .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT), + .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT), .dCLK(CLK), .sRST(rst_tck$OUT_RST), .sD_IN(f_dmi_req$sD_IN), @@ -335,13 +345,13 @@ module mkJtagTap(CLK, .dCOUNT(), .sCOUNT(), .sCLR_RDY(f_dmi_req$sCLR_RDY), - .dCLR_RDY()); + .dCLR_RDY(f_dmi_req$dCLR_RDY)); // submodule f_dmi_rsp SyncFIFOLevel #(.dataWidth(32'd40), .depth(32'd2), .indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK), - .dCLK(tck_clock$CLK_OUT), + .dCLK(tck_clock$OUT), .sRST(RST_N), .sD_IN(f_dmi_rsp$sD_IN), .sENQ(f_dmi_rsp$sENQ), @@ -353,29 +363,46 @@ module mkJtagTap(CLK, .dEMPTY_N(f_dmi_rsp$dEMPTY_N), .dCOUNT(), .sCOUNT(), - .sCLR_RDY(), + .sCLR_RDY(f_dmi_rsp$sCLR_RDY), .dCLR_RDY(f_dmi_rsp$dCLR_RDY)); + // submodule r_dmi + RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT), + .D_IN(r_dmi$D_IN), + .EN(r_dmi$EN), + .Q_OUT(r_dmi$Q_OUT)); + + // submodule r_initialize + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT), + .D_IN(r_initialize$D_IN), + .EN(r_initialize$EN), + .Q_OUT(r_initialize$Q_OUT)); + + // submodule r_initialize2 + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK), + .D_IN(r_initialize2$D_IN), + .EN(r_initialize2$EN), + .Q_OUT(r_initialize2$Q_OUT)); + + // submodule r_state + RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT), + .D_IN(r_state$D_IN), + .EN(r_state$EN), + .Q_OUT(r_state$Q_OUT)); + // submodule rst_tck - SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT), - .IN_RST(RST_N), - .OUT_RST(rst_tck$OUT_RST)); + SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST)); // submodule tck_clock - MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK), - .RST(RST_N), - .CLK_IN(tck_clock$CLK_IN), - .COND_IN(tck_clock$COND_IN), - .CLK_IN_EN(tck_clock$CLK_IN_EN), - .COND_IN_EN(tck_clock$COND_IN_EN), - .CLK_VAL_OUT(), - .COND_OUT(), - .CLK_GATE_OUT(), - .CLK_OUT(tck_clock$CLK_OUT)); + ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT)); - // rule RL_rl_tck - assign CAN_FIRE_RL_rl_tck = 1'd1 ; - assign WILL_FIRE_RL_rl_tck = 1'd1 ; + // submodule w_tck_crossed + SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk), + .DOUT(w_tck_crossed$DOUT)); + + // rule RL_mkConnectionVtoAf + assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; + assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ; // rule RL_tick assign CAN_FIRE_RL_tick = 1'd1 ; @@ -383,7 +410,7 @@ module mkJtagTap(CLK, // rule RL_dmi_start assign CAN_FIRE_RL_dmi_start = - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78 && f_dmi_req$sFULL_N && f_dmi_busy$FULL_N && w_dmi_req$wget[1:0] != 2'd0 ; @@ -406,9 +433,14 @@ module mkJtagTap(CLK, f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ; assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ; + // rule RL_rl_initialize + assign CAN_FIRE_RL_rl_initialize = + r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ; + // rule RL_dmi_reset assign CAN_FIRE_RL_dmi_reset = - r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63 && (!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ; assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ; @@ -420,35 +452,37 @@ module mkJtagTap(CLK, assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ; assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ; + // rule RL_rl_initialize2 + assign CAN_FIRE_RL_rl_initialize2 = + f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ; + // inlined wires assign w_dmi_req$wget = { 1'd0, r_dr } ; - assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ; - assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ; + assign r_tdo$EN_port0__write = + r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ; + assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ; assign r_tdo$port1__read = r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ; assign r_dmistat_busy$port1__read = - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68 || + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74 || r_dmistat_busy ; + assign r_dmistat_busy$EN_port1__write = + WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ; assign r_dmistat_busy$port2__read = - !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ; - - // register r_dmi - assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; - assign r_dmi$EN = - WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 ; + !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ; // register r_dmistat_busy assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ; assign r_dmistat_busy$EN = 1'b1 ; // register r_dr - always@(r_state or r_dr or v__h2135 or v__h2601) + always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941) begin - case (r_state) + case (r_state$Q_OUT) 4'd0: r_dr$D_IN = r_dr; - 4'd3: r_dr$D_IN = v__h2135; - 4'd4: r_dr$D_IN = v__h2601; + 4'd3: r_dr$D_IN = v__h2479; + 4'd4: r_dr$D_IN = v__h2941; default: r_dr$D_IN = r_dr; endcase end @@ -456,22 +490,15 @@ module mkJtagTap(CLK, // register r_drmask assign r_drmask$D_IN = - (r_state == 4'd3) ? - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 : + (r_state$Q_OUT == 4'd3) ? + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 : r_drmask ; assign r_drmask$EN = 1'd1 ; // register r_ir - assign r_ir$D_IN = newir__h3435 ; + assign r_ir$D_IN = newir__h3774 ; assign r_ir$EN = 1'd1 ; - // register r_state - assign r_state$D_IN = - jtag_tms ? - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 : - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ; - assign r_state$EN = 1'd1 ; - // register r_tdo assign r_tdo$D_IN = r_tdo$port1__read ; assign r_tdo$EN = 1'b1 ; @@ -479,146 +506,165 @@ module mkJtagTap(CLK, // submodule f_dmi_busy assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + assign f_dmi_busy$CLR = + WILL_FIRE_RL_dmi_reset && r_dr[17] || + WILL_FIRE_RL_rl_initialize ; // submodule f_dmi_req assign f_dmi_req$sD_IN = w_dmi_req$wget ; assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ; assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; - assign f_dmi_req$dCLR = 1'b0 ; + assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ; // submodule f_dmi_rsp assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ; assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ; assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_rsp$sCLR = 1'b0 ; + assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ; assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + // submodule r_dmi + assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; + assign r_dmi$EN = + WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 ; + + // submodule r_initialize + assign r_initialize$D_IN = 1'd0 ; + assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ; + + // submodule r_initialize2 + assign r_initialize2$D_IN = 1'd0 ; + assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ; + + // submodule r_state + assign r_state$D_IN = + jtag_tms ? + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 : + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ; + assign r_state$EN = 1'd1 ; + // submodule tck_clock - assign tck_clock$CLK_IN = jtag_tclk ; - assign tck_clock$COND_IN = 1'b0 ; - assign tck_clock$CLK_IN_EN = 1'd1 ; - assign tck_clock$COND_IN_EN = 1'b0 ; + assign tck_clock$IN = w_tck_crossed$DOUT ; // remaining internal signals - assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 = + assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 = (r_dmistat_busy || - r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N) ? 40'hAAAAAAAAAB : - r_dmi ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57 = - r_state == 4'd8 && r_ir == 5'h10 && (r_dr[17] || r_dr[16]) ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68 = - r_state == 4'd8 && r_ir == 5'h11 && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63 = + r_state$Q_OUT == 4'd8 && r_ir == 5'h10 && + (r_dr[17] || r_dr[16]) ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74 = + r_state$Q_OUT == 4'd8 && r_ir == 5'h11 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72 = - r_state == 4'd8 && r_ir == 5'h11 && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78 = + r_state$Q_OUT == 4'd8 && r_ir == 5'h11 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && !f_dmi_busy$EMPTY_N ; - assign v__h2233 = { 35'd7864320, r_ir } ; - assign v__h2601 = x__h2658 | y__h2659 ; - assign v__h3299 = x__h3350 | y__h3351 ; - assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ; - assign x__h2658 = { 1'd0, r_dr[39:1] } ; - assign x__h3350 = { 1'd0, r_ir[4:1] } ; - assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ; - assign y__h3351 = jtag_tdi ? 5'd16 : 5'd0 ; - always@(r_state or r_ir or v__h3299) + assign v__h2576 = { 35'd7864320, r_ir } ; + assign v__h2941 = x__h2996 | y__h2997 ; + assign v__h3636 = x__h3687 | y__h3688 ; + assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ; + assign x__h2996 = { 1'd0, r_dr[39:1] } ; + assign x__h3687 = { 1'd0, r_ir[4:1] } ; + assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ; + assign y__h3688 = jtag_tdi ? 5'd16 : 5'd0 ; + always@(r_state$Q_OUT or r_ir or v__h3636) begin - case (r_state) - 4'd0: newir__h3435 = 5'd1; - 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir; - 4'd11: newir__h3435 = v__h3299; - default: newir__h3435 = r_ir; + case (r_state$Q_OUT) + 4'd0: newir__h3774 = 5'd1; + 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir; + 4'd11: newir__h3774 = v__h3636; + default: newir__h3774 = r_ir; endcase end always@(r_ir or - v__h2233 or - x__h2449 or - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140) + v__h2576 or + x__h2789 or + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146) begin case (r_ir) - 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: v__h2135 = 40'd0; - 5'd1: v__h2135 = 40'd4093; - 5'h10: v__h2135 = x__h2449; + 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: v__h2479 = 40'd0; + 5'd1: v__h2479 = 40'd4093; + 5'h10: v__h2479 = x__h2789; 5'h11: - v__h2135 = - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140; - default: v__h2135 = v__h2233; + v__h2479 = + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146; + default: v__h2479 = v__h2576; endcase end - always@(newir__h3435) + always@(newir__h3774) begin - case (newir__h3435) + case (newir__h3774) 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'd1; + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'd1; 5'd1, 5'h10: - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'h0080000000; 5'h11: - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'h8000000000; - default: CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = + default: CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'h0100000000; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) - 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state; + case (r_state$Q_OUT) + 4'd0: + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = + r_state$Q_OUT; 4'd1, 4'd8, 4'd15: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2; - 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9; - 4'd3, 4'd4: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5; - 4'd5, 4'd7: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8; - 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7; - 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2; + 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9; + 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5; + 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8; + 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7; + 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0; 4'd10, 4'd11: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12; 4'd12, 4'd14: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15; - 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15; + 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) + case (r_state$Q_OUT) 4'd0, 4'd1, 4'd8, 4'd15: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1; - 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1; + 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3; 4'd3, 4'd4, 4'd7: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4; 4'd5, 4'd6: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6; - 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6; + 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10; 4'd10, 4'd11, 4'd14: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11; 4'd12, 4'd13: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13; endcase end // handling of inlined registers - always@(posedge tck_clock$CLK_OUT) + always@(posedge tck_clock$OUT) begin if (rst_tck$OUT_RST == `BSV_RESET_VALUE) begin - r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0; - r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - r_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN; - if (r_dmistat_busy$EN) + if (r_dmistat_busy$EN) r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN; - if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN; end if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN; if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN; @@ -631,12 +677,10 @@ module mkJtagTap(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - r_dmi = 40'hAAAAAAAAAA; r_dmistat_busy = 1'h0; r_dr = 40'hAAAAAAAAAA; r_drmask = 40'hAAAAAAAAAA; r_ir = 5'h0A; - r_state = 4'hA; r_tdo = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS @@ -645,11 +689,12 @@ module mkJtagTap(CLK, // handling of system tasks // synopsys translate_off - always@(negedge tck_clock$CLK_OUT) + always@(negedge tck_clock$OUT) begin #0; if (rst_tck$OUT_RST != `BSV_RESET_VALUE) - if (r_state == 4'd3 && r_ir != 5'd0 && r_ir != 5'h12 && r_ir != 5'h13 && + if (r_state$Q_OUT == 4'd3 && r_ir != 5'd0 && r_ir != 5'h12 && + r_ir != 5'h13 && r_ir != 5'h14 && r_ir != 5'h15 && r_ir != 5'h16 && diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v index b1f7022..4f1d8af 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v @@ -648,14 +648,19 @@ module mkP3_Core(CLK, wire bus_dmi_rsp_fifof_q_1$EN; // register rg_corew_start_after_por - reg rg_corew_start_after_por; - wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + reg [7 : 0] rg_corew_start_after_por; + wire [7 : 0] rg_corew_start_after_por$D_IN; + wire rg_corew_start_after_por$EN; // register rg_ndm_reset_delay reg [7 : 0] rg_ndm_reset_delay; wire [7 : 0] rg_ndm_reset_delay$D_IN; wire rg_ndm_reset_delay$EN; + // register rg_running + reg rg_running; + wire rg_running$D_IN, rg_running$EN; + // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; wire bus_dmi_req_fifof$CLR, @@ -781,8 +786,10 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, + corew$ndm_reset_client_request_get, corew$ndm_reset_client_response_put, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -804,6 +811,9 @@ module mkP3_Core(CLK, // ports of submodule ndm_reset_controller wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule por_ifc + wire por_ifc$RST_N_gen_rst; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -896,7 +906,7 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2, - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1, + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2; wire [7 : 0] MUX_rg_ndm_reset_delay$write_1__VAL_1; @@ -910,15 +920,15 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1279; - reg [31 : 0] v__h1424; - reg [31 : 0] v__h1273; - reg [31 : 0] v__h1418; + reg [31 : 0] v__h1362; + reg [31 : 0] v__h1510; + reg [31 : 0] v__h1356; + reg [31 : 0] v__h1504; // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; - wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49; + wire IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99, _dfoo1, _dfoo3; @@ -1188,7 +1198,7 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(por_ifc$RST_N_gen_rst), .CLK(CLK), .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), @@ -1237,6 +1247,7 @@ module mkP3_Core(CLK, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1308,7 +1319,7 @@ module mkP3_Core(CLK, .dmi_read_data(corew$dmi_read_data), .RDY_dmi_read_data(corew$RDY_dmi_read_data), .RDY_dmi_write(corew$RDY_dmi_write), - .ndm_reset_client_request_get(), + .ndm_reset_client_request_get(corew$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), @@ -1316,7 +1327,7 @@ module mkP3_Core(CLK, // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), - .RST_N(RST_N), + .RST_N(por_ifc$RST_N_gen_rst), .dmi_req_ready(jtagtap$dmi_req_ready), .dmi_rsp_data(jtagtap$dmi_rsp_data), .dmi_rsp_response(jtagtap$dmi_rsp_response), @@ -1334,7 +1345,7 @@ module mkP3_Core(CLK, .CLK_GATE_jtag_tclk_out()); // submodule ndm_reset - ResetEither ndm_reset(.A_RST(RST_N), + ResetEither ndm_reset(.A_RST(por_ifc$RST_N_gen_rst), .B_RST(ndm_reset_controller$OUT_RST), .RST_OUT(ndm_reset$RST_OUT)); @@ -1346,6 +1357,11 @@ module mkP3_Core(CLK, .ASSERT_OUT(), .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule por_ifc + mkPowerOnReset por_ifc(.CLK(CLK), + .RST_N(RST_N), + .RST_N_gen_rst(por_ifc$RST_N_gen_rst)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1371,7 +1387,8 @@ module mkP3_Core(CLK, // rule RL_rl_step_0 assign CAN_FIRE_RL_rl_step_0 = - corew$RDY_start && !rg_corew_start_after_por ; + (rg_corew_start_after_por != 8'd1 || corew$RDY_start) && + rg_corew_start_after_por != 8'd0 ; assign WILL_FIRE_RL_rl_step_0 = CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; @@ -1422,7 +1439,7 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; + IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu @@ -1434,7 +1451,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; @@ -1478,15 +1495,15 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 ; + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ; @@ -1495,16 +1512,16 @@ module mkP3_Core(CLK, assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 = bus_dmi_rsp_fifof_cntr_r + 2'd1 ; assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 = - (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : - bus_dmi_rsp_fifof_q_1 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 ? MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 : MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 = + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = + (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : + bus_dmi_rsp_fifof_q_1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 = (bus_dmi_rsp_fifof_cntr_r == 2'd2) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : 34'd0 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 = { 32'hAAAAAAAA, @@ -1526,7 +1543,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1553,25 +1570,25 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_0$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register bus_dmi_rsp_fifof_q_1 always@(MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 or - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 or + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 or MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 or - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 or WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr) begin case (1'b1) // synopsys parallel_case MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1; + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1; MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2; + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2; WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr: bus_dmi_rsp_fifof_q_1$D_IN = 34'd0; default: bus_dmi_rsp_fifof_q_1$D_IN = @@ -1579,13 +1596,13 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_1$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register rg_corew_start_after_por - assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$D_IN = rg_corew_start_after_por - 8'd1 ; assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; // register rg_ndm_reset_delay @@ -1596,6 +1613,10 @@ module mkP3_Core(CLK, assign rg_ndm_reset_delay$EN = WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; + // register rg_running + assign rg_running$D_IN = corew$ndm_reset_client_request_get ; + assign rg_running$EN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; assign bus_dmi_req_fifof$ENQ = CAN_FIRE_RL_bus_dmi_req_do_enq ; @@ -1660,16 +1681,17 @@ module mkP3_Core(CLK, assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$ndm_reset_client_response_put = rg_running ; assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_is_running = !MUX_corew$start_1__SEL_1 || rg_running ; assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || - WILL_FIRE_RL_rl_step_0 ; + WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1699,7 +1721,7 @@ module mkP3_Core(CLK, assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = + assign IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || @@ -1708,11 +1730,11 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1724,7 +1746,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 8'd100; rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else @@ -1744,6 +1766,7 @@ module mkP3_Core(CLK, if (rg_ndm_reset_delay$EN) rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end + if (rg_running$EN) rg_running <= `BSV_ASSIGNMENT_DELAY rg_running$D_IN; end // synopsys translate_off @@ -1754,8 +1777,9 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_corew_start_after_por = 1'h0; + rg_corew_start_after_por = 8'hAA; rg_ndm_reset_delay = 8'hAA; + rg_running = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1767,30 +1791,34 @@ module mkP3_Core(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - begin - v__h1279 = $stime; - #0; - end - v__h1273 = v__h1279 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1273, - $signed(32'd10)); - if (RST_N != `BSV_RESET_VALUE) - if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1424 = $stime; + v__h1362 = $stime; #0; end - v__h1418 = v__h1424 / 32'd10; + v__h1356 = v__h1362 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1356, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) - $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1418); + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1510 = $stime; + #0; + end + v__h1504 = v__h1510 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1504); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v new file mode 100644 index 0000000..65d7430 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v @@ -0,0 +1,92 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// +// +// +// Ports: +// Name I/O size props +// RST_N_gen_rst O 1 reset +// CLK I 1 clock +// RST_N I 1 unused +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkPowerOnReset(CLK, + RST_N, + + RST_N_gen_rst); + input CLK; + input RST_N; + + // output resets + output RST_N_gen_rst; + + // signals for module outputs + wire RST_N_gen_rst; + + // ports of submodule ctr + wire [7 : 0] ctr$D_IN, ctr$Q_OUT; + wire ctr$EN; + + // ports of submodule isInPowerOnReset + wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT; + + // ports of submodule rst_ifc + wire rst_ifc$OUT; + + // rule scheduling signals + wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown; + + // remaining internal signals + wire NOT_isInPowerOnReset__read___d5; + + // output resets + assign RST_N_gen_rst = rst_ifc$OUT ; + + // submodule ctr + RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK), + .D_IN(ctr$D_IN), + .EN(ctr$EN), + .Q_OUT(ctr$Q_OUT)); + + // submodule isInPowerOnReset + RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK), + .D_IN(isInPowerOnReset$D_IN), + .EN(isInPowerOnReset$EN), + .Q_OUT(isInPowerOnReset$Q_OUT)); + + // submodule rst_ifc + ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT)); + + // rule RL_countDown + assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + + // submodule ctr + assign ctr$D_IN = ctr$Q_OUT - 8'd1 ; + assign ctr$EN = isInPowerOnReset$Q_OUT ; + + // submodule isInPowerOnReset + assign isInPowerOnReset$D_IN = 1'd0 ; + assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ; + + // remaining internal signals + assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ; +endmodule // mkPowerOnReset + diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index 6ec567d..6af5681 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -94,6 +94,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -192,6 +193,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -454,6 +456,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1421,6 +1424,7 @@ module mkProc(CLK, core_0$EN_v_to_TV_0_get, core_0$EN_v_to_TV_1_get, core_0$RDY_coreIndInv_terminate, + core_0$RDY_coreReq_start, core_0$RDY_dCacheToParent_fromP_enq, core_0$RDY_dCacheToParent_rqToP_deq, core_0$RDY_dCacheToParent_rqToP_first, @@ -1461,6 +1465,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_respLd_enq, core_0$RDY_v_to_TV_0_get, core_0$RDY_v_to_TV_1_get, + core_0$coreReq_start_running, core_0$hart0_run_halt_server_request_put, core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, @@ -2104,60 +2109,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163582; - reg [31 : 0] v__h163118; - reg [31 : 0] v__h5520; - reg [31 : 0] v__h5693; - reg [31 : 0] v__h5953; - reg [31 : 0] v__h8095; - reg [31 : 0] v__h8310; - reg [31 : 0] v__h2670; - reg [31 : 0] v__h4343; - reg [31 : 0] v__h9480; - reg [31 : 0] v__h9973; - reg [31 : 0] v__h10136; - reg [31 : 0] v__h135075; - reg [31 : 0] v__h135242; - reg [31 : 0] v__h137345; - reg [31 : 0] v__h154689; - reg [31 : 0] v__h134456; - reg [31 : 0] v__h161383; - reg [31 : 0] v__h161891; - reg [31 : 0] v__h2664; - reg [31 : 0] v__h4337; - reg [31 : 0] v__h5514; - reg [31 : 0] v__h5687; - reg [31 : 0] v__h5947; - reg [31 : 0] v__h8089; - reg [31 : 0] v__h8304; - reg [31 : 0] v__h9474; - reg [31 : 0] v__h9967; - reg [31 : 0] v__h10130; - reg [31 : 0] v__h134450; - reg [31 : 0] v__h135069; - reg [31 : 0] v__h135236; - reg [31 : 0] v__h137339; - reg [31 : 0] v__h154683; - reg [31 : 0] v__h161377; - reg [31 : 0] v__h161885; - reg [31 : 0] v__h163112; - reg [31 : 0] v__h163576; + reg [31 : 0] v__h163594; + reg [31 : 0] v__h163126; + reg [31 : 0] v__h5528; + reg [31 : 0] v__h5701; + reg [31 : 0] v__h5961; + reg [31 : 0] v__h8103; + reg [31 : 0] v__h8318; + reg [31 : 0] v__h2678; + reg [31 : 0] v__h4351; + reg [31 : 0] v__h9488; + reg [31 : 0] v__h9981; + reg [31 : 0] v__h10144; + reg [31 : 0] v__h135083; + reg [31 : 0] v__h135250; + reg [31 : 0] v__h137353; + reg [31 : 0] v__h154697; + reg [31 : 0] v__h134464; + reg [31 : 0] v__h161391; + reg [31 : 0] v__h161899; + reg [31 : 0] v__h2672; + reg [31 : 0] v__h4345; + reg [31 : 0] v__h5522; + reg [31 : 0] v__h5695; + reg [31 : 0] v__h5955; + reg [31 : 0] v__h8097; + reg [31 : 0] v__h8312; + reg [31 : 0] v__h9482; + reg [31 : 0] v__h9975; + reg [31 : 0] v__h10138; + reg [31 : 0] v__h134458; + reg [31 : 0] v__h135077; + reg [31 : 0] v__h135244; + reg [31 : 0] v__h137347; + reg [31 : 0] v__h154691; + reg [31 : 0] v__h161385; + reg [31 : 0] v__h161893; + reg [31 : 0] v__h163120; + reg [31 : 0] v__h163588; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34, + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, @@ -2167,44 +2172,44 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, - data64__h148515, - dword__h94382, - ld_data__h132631, - old_dword__h90072, - w1__h48093, - w1__h48098, - w2__h48094, - w2__h48100, - x__h48089; + data64__h148523, + dword__h94390, + ld_data__h132639, + old_dword__h90080, + w1__h48101, + w1__h48106, + w2__h48102, + w2__h48108, + x__h48097; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h148516; + reg [7 : 0] strb8__h148524; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61807; + reg [2 : 0] x__h61815; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; + CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, + CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20, SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, - x__h61814, - x__h82716; + x__h61822, + x__h82724; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - new_cline__h135378; + new_cline__h135386; wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, @@ -2225,89 +2230,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - data__h31950, - failed_testnum__h163161, - line_addr__h102446, - line_addr__h102532, - mask__h90069, - mem_req_rd_addr_araddr__h134676, - mem_req_wr_addr_awaddr__h148600, - mmioPlatform_fromHostQ_data_0__h42745, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48685, - n__read_addr__h61675, - n__read_addr__h61760, - n__read_addr__h80478, - n__read_addr__h80557, - n__read_snd_addr__h123973, - newData__h32031, - newData__h34961, - new_dword__h90073, - op_result__h48701, - op_result__h49231, - op_result__h49236, - op_result__h49241, - op_result__h49246, - op_result__h49252, - op_result__h49259, - op_result__h49265, - result__h48144, - result__h48268, - result__h48296, - result__h48324, - result__h48352, - result__h48380, - result__h48408, - result__h48436, - result__h48464, - result__h48509, - result__h48537, - result__h48565, - result__h48593, - result__h48634, - result__h48662, - result__h48788, - result__h48815, - result__h48842, - result__h48869, - result__h48896, - result__h48923, - result__h48950, - result__h48977, - result__h49021, - result__h49048, - result__h49075, - result__h49102, - result__h49142, - result__h49169, - result__h49286, - result__h49352, - result__h49418, - result__h49484, - result__h49550, - result__h49616, - result__h49682, - result__h49744, - result__h49789, - result__h49855, - result__h49921, - result__h49979, - result__h50024, - w1___1__h48203, - w2___1__h48204, - x1_avValue_data__h40417, - x1_avValue_data__h45022, - x__h32142, - x__h35052, - x__h37412, - x__h40935, - x__h40946, - x__h43001, - x__h43012, - x__h50201, - x__h91235, - y__h91236, - y__h91237; + data__h31958, + failed_testnum__h163169, + line_addr__h102454, + line_addr__h102540, + mask__h90077, + mem_req_rd_addr_araddr__h134684, + mem_req_wr_addr_awaddr__h148608, + mmioPlatform_fromHostQ_data_0__h42753, + mmioPlatform_mtime__h37272, + mmioPlatform_reqData__h48693, + n__read_addr__h61683, + n__read_addr__h61768, + n__read_addr__h80486, + n__read_addr__h80565, + n__read_snd_addr__h123981, + newData__h32039, + newData__h34969, + new_dword__h90081, + op_result__h48709, + op_result__h49239, + op_result__h49244, + op_result__h49249, + op_result__h49254, + op_result__h49260, + op_result__h49267, + op_result__h49273, + result__h48152, + result__h48276, + result__h48304, + result__h48332, + result__h48360, + result__h48388, + result__h48416, + result__h48444, + result__h48472, + result__h48517, + result__h48545, + result__h48573, + result__h48601, + result__h48642, + result__h48670, + result__h48796, + result__h48823, + result__h48850, + result__h48877, + result__h48904, + result__h48931, + result__h48958, + result__h48985, + result__h49029, + result__h49056, + result__h49083, + result__h49110, + result__h49150, + result__h49177, + result__h49294, + result__h49360, + result__h49426, + result__h49492, + result__h49558, + result__h49624, + result__h49690, + result__h49752, + result__h49797, + result__h49863, + result__h49929, + result__h49987, + result__h50032, + w1___1__h48211, + w2___1__h48212, + x1_avValue_data__h40425, + x1_avValue_data__h45030, + x__h32150, + x__h35060, + x__h37420, + x__h40943, + x__h40954, + x__h43009, + x__h43020, + x__h50209, + x__h91243, + y__h91244, + y__h91245; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; @@ -2319,16 +2324,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w18093_BITS_31_TO_0__q15, - w28094_BITS_31_TO_0__q16, - x_data__h30533; + v__h31751, + v__h31788, + w18101_BITS_31_TO_0__q15, + w28102_BITS_31_TO_0__q16, + x_data__h30541; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; - wire [5 : 0] x__h134711, x__h148625; + wire [5 : 0] x__h134719, x__h148633; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; - wire [3 : 0] b__h134383, b__h2564; - wire [2 : 0] n__read_id__h61679, n__read_id__h61764, x__h7925; + wire [3 : 0] b__h134391, b__h2572; + wire [2 : 0] n__read_id__h61687, n__read_id__h61772, x__h7933; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, @@ -2390,27 +2395,28 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqBE_BIT_0___h30166, + mmioPlatform_reqBE_BIT_4___h30126, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61680, - n__read_child__h61765, - n__read_child__h80481, - n__read_child__h80560, - n__read_snd_id__h123974, + n__read_child__h61688, + n__read_child__h61773, + n__read_child__h80489, + n__read_child__h80568, + n__read_snd_id__h123982, propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, - x__h61493, - x__h75229, - x__h80300; + x__h61501, + x__h75237, + x__h80308; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; - assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; + assign CAN_FIRE_start = + mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; assign WILL_FIRE_start = EN_start ; // value method master0_m_awvalid @@ -2845,6 +2851,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -2901,7 +2908,7 @@ module mkProc(CLK, .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), .EN_v_to_TV_0_get(core_0$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(core_0$EN_v_to_TV_1_get), - .RDY_coreReq_start(), + .RDY_coreReq_start(core_0$RDY_coreReq_start), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), .RDY_coreIndInv_perfResp(), @@ -3676,14 +3683,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2564 == 4'd0 ; + b__h2572 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2564 != 4'd0 && + b__h2572 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3796,7 +3803,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h43001 == 64'd0 || + x__h43009 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -4116,13 +4123,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134383 == 4'd0 ; + b__h134391 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134383 != 4'd0 && + b__h134391 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4226,7 +4233,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30541 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -4266,7 +4273,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31958 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -4291,10 +4298,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102446, + { line_addr__h102454, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102532, + { line_addr__h102540, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4305,11 +4312,11 @@ module mkProc(CLK, { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4408,7 +4415,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48089 } ; + x__h48097 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4417,7 +4424,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50201, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50209, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4432,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43001 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43009 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h43001 != 64'd0 ; + x__h43009 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40935 == 64'd0 ; + x__h40943 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61493 ; + x__h61501 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23, SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80300 ; + x__h80308 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123973, n__read_snd_id__h123974 } ; + { 1'd1, n__read_snd_addr__h123981, n__read_snd_id__h123982 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4526,11 +4533,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2564 - 4'd1 ; + b__h2572 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2564 ; + b__h2572 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4579,11 +4586,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134383 - 4'd1 ; + b__h134391 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134383 ; + b__h134391 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4646,7 +4653,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134676, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134684, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4664,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148600, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148608, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148515, strb8__h148516, 1'd1 } ; + { data64__h148523, strb8__h148524, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4682,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135378 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135386 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4730,8 +4737,8 @@ module mkProc(CLK, // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102446 : - line_addr__h102532 ; + line_addr__h102454 : + line_addr__h102540 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4892,7 +4899,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34969 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4908,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32039 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5118,7 +5125,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7925, + x__h7933, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -5218,6 +5225,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -5321,7 +5329,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132631, llc$dma_respLd_first[3] } ; + { ld_data__h132639, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5475,7 +5483,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135378, + { new_cline__h135386, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5559,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94382, 3'd1 } ; + { 4'd0, dword__h94390, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5854,47 +5862,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37420), + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h32150)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37272), + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h35060)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42745), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40946)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42753), + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h40954)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h43012)); + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h43020)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40417 } } ; + x1_avValue_data__h40425 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5910,7 +5918,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; + newData__h32039 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5975,7 +5983,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - x__h75229 } ; + x__h75237 } ; assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5987,29 +5995,29 @@ module mkProc(CLK, assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? @@ -6154,11 +6162,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h43001 == 64'd0 : - x__h40935 == 64'd0, + x__h43009 == 64'd0 : + x__h40943 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h45022 } ; + x1_avValue_data__h45030 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6392,58 +6400,58 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = - { CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, + { CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = - { CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + { CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - x__h82716 } ; + x__h82724 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = - { CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + { CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = - { CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, - x__h61807, - x__h61814 } ; - assign b__h134383 = + { CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20, + x__h61815, + x__h61822 } ; + assign b__h134391 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2564 = + assign b__h2572 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31958 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h163161 = + { v__h31751, 32'd0 } ; + assign failed_testnum__h163169 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102446 = + assign line_addr__h102454 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102532 = + assign line_addr__h102540 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = - line_addr__h102532 == llc_mem_server_rg_cacheline_cache_addr ; + line_addr__h102540 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = - line_addr__h102446 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90069 = + line_addr__h102454 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90077 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6476,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134676 = - { llc$to_mem_toM_first[68:11], x__h134711 } ; - assign mem_req_wr_addr_awaddr__h148600 = - { llc$to_mem_toM_first[639:582], x__h148625 } ; + assign mem_req_rd_addr_araddr__h134684 = + { llc$to_mem_toM_first[68:11], x__h134719 } ; + assign mem_req_wr_addr_awaddr__h148608 = + { llc$to_mem_toM_first[639:582], x__h148633 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42745 = + assign mmioPlatform_fromHostQ_data_0__h42753 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,18 +6494,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37272 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + mmioPlatform_mtimecmp_0 <= newData__h34969 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48685 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30166 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30126 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48693 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6529,105 +6537,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61675 = + assign n__read_addr__h61683 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61760 = + assign n__read_addr__h61768 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80478 = + assign n__read_addr__h80486 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : 64'd0 ; - assign n__read_addr__h80557 = + assign n__read_addr__h80565 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : 64'd0 ; - assign n__read_child__h61680 = + assign n__read_child__h61688 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61765 = + assign n__read_child__h61773 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80481 = + assign n__read_child__h80489 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; - assign n__read_child__h80560 = + assign n__read_child__h80568 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; - assign n__read_id__h61679 = + assign n__read_id__h61687 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61764 = + assign n__read_id__h61772 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123973 = + assign n__read_snd_addr__h123981 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123974 = + assign n__read_snd_id__h123982 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32039 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : + x__h32150 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + assign newData__h34969 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : + x__h35060 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h135378 = + assign new_cline__h135386 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90073 = x__h91235 | y__h91236 ; - assign op_result__h48701 = + assign new_dword__h90081 = x__h91243 | y__h91244 ; + assign op_result__h48709 = IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; - assign op_result__h49231 = w1__h48098 ^ w2__h48100 ; - assign op_result__h49236 = w1__h48098 & w2__h48100 ; - assign op_result__h49241 = w1__h48098 | w2__h48100 ; - assign op_result__h49246 = - (w1__h48098 < w2__h48100) ? w1__h48098 : w2__h48100 ; - assign op_result__h49252 = - (w1__h48098 <= w2__h48100) ? w2__h48100 : w1__h48098 ; - assign op_result__h49259 = + assign op_result__h49239 = w1__h48106 ^ w2__h48108 ; + assign op_result__h49244 = w1__h48106 & w2__h48108 ; + assign op_result__h49249 = w1__h48106 | w2__h48108 ; + assign op_result__h49254 = + (w1__h48106 < w2__h48108) ? w1__h48106 : w2__h48108 ; + assign op_result__h49260 = + (w1__h48106 <= w2__h48108) ? w2__h48108 : w1__h48106 ; + assign op_result__h49267 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w1__h48098 : - w2__h48100 ; - assign op_result__h49265 = + w1__h48106 : + w2__h48108 ; + assign op_result__h49273 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w2__h48100 : - w1__h48098 ; + w2__h48108 : + w1__h48106 ; assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6638,126 +6646,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48144 = + assign result__h48152 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; - assign result__h48268 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48296 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48324 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48352 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48380 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48408 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48436 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48464 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48509 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48537 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48565 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48593 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48634 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48662 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48788 = + assign result__h48276 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48304 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48332 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48360 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48388 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48416 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48444 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48472 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48517 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48545 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48573 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48601 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48642 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48670 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48796 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48815 = + assign result__h48823 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48842 = + assign result__h48850 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48869 = + assign result__h48877 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48896 = + assign result__h48904 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48923 = + assign result__h48931 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48950 = + assign result__h48958 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48977 = + assign result__h48985 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h49021 = + assign result__h49029 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h49048 = + assign result__h49056 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h49075 = + assign result__h49083 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49102 = + assign result__h49110 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49142 = + assign result__h49150 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49169 = + assign result__h49177 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49286 = + assign result__h49294 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49352 = + assign result__h49360 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49418 = + assign result__h49426 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49484 = + assign result__h49492 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49550 = + assign result__h49558 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49616 = + assign result__h49624 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49682 = + assign result__h49690 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49744 = + assign result__h49752 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; - assign result__h49789 = + assign result__h49797 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49855 = + assign result__h49863 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49921 = + assign result__h49929 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49979 = + assign result__h49987 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; - assign result__h50024 = + assign result__h50032 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18093_BITS_31_TO_0__q15 = w1__h48093[31:0] ; - assign w1___1__h48203 = { 32'd0, w1__h48093[31:0] } ; - assign w28094_BITS_31_TO_0__q16 = w2__h48094[31:0] ; - assign w2___1__h48204 = { 32'd0, w2__h48094[31:0] } ; - assign x1_avValue_data__h40417 = + assign v__h31751 = mmioPlatform_waitUpperMSIPCRs ? v__h31788 : 32'd0 ; + assign v__h31788 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18101_BITS_31_TO_0__q15 = w1__h48101[31:0] ; + assign w1___1__h48211 = { 32'd0, w1__h48101[31:0] } ; + assign w28102_BITS_31_TO_0__q16 = w2__h48102[31:0] ; + assign w2___1__h48212 = { 32'd0, w2__h48102[31:0] } ; + assign x1_avValue_data__h40425 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h45022 = + assign x1_avValue_data__h45030 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134711 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148625 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40935 = + assign x__h134719 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148633 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37420 = mmioPlatform_mtimecmp_0 ; + assign x__h40943 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40946 : + x__h40954 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; - assign x__h43001 = + assign x__h43009 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h43012 : + x__h43020 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6774,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50201 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61493 = + assign x__h50209 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61501 = SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; - assign x__h75229 = + assign x__h75237 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; - assign x__h7925 = + assign x__h7933 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80300 = + assign x__h80308 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; - assign x__h91235 = old_dword__h90072 & y__h91237 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91236 = + assign x__h91243 = old_dword__h90080 & y__h91245 ; + assign x_data__h30541 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91244 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90069 ; - assign y__h91237 = + mask__h90077 ; + assign y__h91245 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,141 +7009,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148515 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148515 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148515 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148515 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148515 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148515 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148515 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148515 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h148523 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148523 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148523 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148523 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148523 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148523 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148523 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148523 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132631 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132631 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132631 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132631 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132631 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132631 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132631 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132631 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132639 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132639 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132639 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132639 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132639 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132639 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132639 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132639 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148516 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148516 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148516 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148516 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148516 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148516 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148516 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148516 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148524 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148524 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148524 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148524 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148524 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148524 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148524 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148524 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48268 or - result__h48296 or - result__h48324 or - result__h48352 or - result__h48380 or - result__h48408 or result__h48436 or result__h48464) + result__h48276 or + result__h48304 or + result__h48332 or + result__h48360 or + result__h48388 or + result__h48416 or result__h48444 or result__h48472) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48268; + result__h48276; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48296; + result__h48304; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48324; + result__h48332; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48352; + result__h48360; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48380; + result__h48388; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48408; + result__h48416; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48436; + result__h48444; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48464; + result__h48472; endcase end always@(mmioPlatform_curReq or - result__h48509 or - result__h48537 or result__h48565 or result__h48593) + result__h48517 or + result__h48545 or result__h48573 or result__h48601) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48509; + result__h48517; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48537; + result__h48545; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48565; + result__h48573; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48593; + result__h48601; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48634 or result__h48662) + always@(mmioPlatform_curReq or result__h48642 or result__h48670) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48634; + result__h48642; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48662; + result__h48670; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase @@ -7148,103 +7156,103 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h48094 = + w2__h48102 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48094 = + w2__h48102 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - w2__h48094 = + w2__h48102 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h48094 = + w2__h48102 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w2___1__h48204 or + w2___1__h48212 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48100 = + w2__h48108 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48100 = + w2__h48108 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; - 2'b10: w2__h48100 = w2___1__h48204; + 2'b10: w2__h48108 = w2___1__h48212; 2'b11: - w2__h48100 = + w2__h48108 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_curReq or - result__h48788 or - result__h48815 or - result__h48842 or - result__h48869 or - result__h48896 or - result__h48923 or result__h48950 or result__h48977) + result__h48796 or + result__h48823 or + result__h48850 or + result__h48877 or + result__h48904 or + result__h48931 or result__h48958 or result__h48985) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48788; + result__h48796; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48815; + result__h48823; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48842; + result__h48850; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48869; + result__h48877; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48896; + result__h48904; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48923; + result__h48931; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48950; + result__h48958; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48977; + result__h48985; endcase end always@(mmioPlatform_curReq or - result__h49021 or - result__h49048 or result__h49075 or result__h49102) + result__h49029 or + result__h49056 or result__h49083 or result__h49110) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49021; + result__h49029; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49048; + result__h49056; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49075; + result__h49083; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49102; + result__h49110; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h49142 or result__h49169) + always@(mmioPlatform_curReq or result__h49150 or result__h49177) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49142; + result__h49150; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49169; + result__h49177; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase @@ -7257,42 +7265,42 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h48093 = + w1__h48101 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48093 = + w1__h48101 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - w1__h48093 = + w1__h48101 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h48093 = + w1__h48101 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w1___1__h48203 or + w1___1__h48211 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48098 = + w1__h48106 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48098 = + w1__h48106 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; - 2'b10: w1__h48098 = w1___1__h48203; + 2'b10: w1__h48106 = w1___1__h48211; 2'b11: - w1__h48098 = + w1__h48106 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w18093_BITS_31_TO_0__q15 or + w18101_BITS_31_TO_0__q15 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) @@ -7304,8 +7312,8 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - { {32{w18093_BITS_31_TO_0__q15[31]}}, - w18093_BITS_31_TO_0__q15 }; + { {32{w18101_BITS_31_TO_0__q15[31]}}, + w18101_BITS_31_TO_0__q15 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; @@ -7314,7 +7322,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w28094_BITS_31_TO_0__q16 or + w28102_BITS_31_TO_0__q16 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) @@ -7326,116 +7334,116 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - { {32{w28094_BITS_31_TO_0__q16[31]}}, - w28094_BITS_31_TO_0__q16 }; + { {32{w28102_BITS_31_TO_0__q16[31]}}, + w28102_BITS_31_TO_0__q16 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49265 or - w2__h48100 or - op_result__h48701 or - op_result__h49231 or - op_result__h49236 or - op_result__h49241 or - op_result__h49259 or op_result__h49246 or op_result__h49252) + op_result__h49273 or + w2__h48108 or + op_result__h48709 or + op_result__h49239 or + op_result__h49244 or + op_result__h49249 or + op_result__h49267 or op_result__h49254 or op_result__h49260) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - w2__h48100; + w2__h48108; 4'd1: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h48701; + op_result__h48709; 4'd2: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49231; + op_result__h49239; 4'd3: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49236; + op_result__h49244; 4'd4: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49241; + op_result__h49249; 4'd5: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49259; + op_result__h49267; 4'd7: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49246; + op_result__h49254; 4'd8: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49252; + op_result__h49260; default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49265; + op_result__h49273; endcase end always@(mmioPlatform_curReq or - result__h49744 or - result__h49789 or result__h49855 or result__h49921) + result__h49752 or + result__h49797 or result__h49863 or result__h49929) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49744; + result__h49752; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49789; + result__h49797; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49855; + result__h49863; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49921; + result__h49929; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48144 or - result__h49286 or - result__h49352 or - result__h49418 or - result__h49484 or - result__h49550 or result__h49616 or result__h49682) + result__h48152 or + result__h49294 or + result__h49360 or + result__h49426 or + result__h49492 or + result__h49558 or result__h49624 or result__h49690) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h48144; + result__h48152; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49286; + result__h49294; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49352; + result__h49360; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49418; + result__h49426; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49484; + result__h49492; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49550; + result__h49558; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49616; + result__h49624; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49682; + result__h49690; endcase end - always@(mmioPlatform_curReq or result__h49979 or result__h50024) + always@(mmioPlatform_curReq or result__h49987 or result__h50032) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49979; + result__h49987; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h50024; + result__h50032; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase @@ -7448,15 +7456,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h48089 = + x__h48097 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; 2'b01: - x__h48089 = + x__h48097 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; 2'b10: - x__h48089 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h48097 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h48089 = + x__h48097 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end @@ -7540,278 +7548,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; endcase end - always@(x__h61493 or n__read_id__h61679 or n__read_id__h61764) + always@(x__h61501 or n__read_id__h61687 or n__read_id__h61772) begin - case (x__h61493) - 1'd0: x__h61807 = n__read_id__h61679; - 1'd1: x__h61807 = n__read_id__h61764; + case (x__h61501) + 1'd0: x__h61815 = n__read_id__h61687; + 1'd1: x__h61815 = n__read_id__h61772; endcase end - always@(x__h61493 or n__read_child__h61680 or n__read_child__h61765) + always@(x__h61501 or n__read_child__h61688 or n__read_child__h61773) begin - case (x__h61493) - 1'd0: x__h61814 = n__read_child__h61680; - 1'd1: x__h61814 = n__read_child__h61765; + case (x__h61501) + 1'd0: x__h61822 = n__read_child__h61688; + 1'd1: x__h61822 = n__read_child__h61773; endcase end - always@(x__h61493 or + always@(x__h61501 or propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = + CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20 = propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; 1'd1: - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = + CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20 = propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; endcase end - always@(x__h61493 or + always@(x__h61501 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; 1'd1: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; endcase end - always@(x__h61493 or + always@(x__h61501 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; 1'd1: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; endcase end - always@(x__h61493 or n__read_addr__h61675 or n__read_addr__h61760) + always@(x__h61501 or n__read_addr__h61683 or n__read_addr__h61768) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = - n__read_addr__h61675; + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23 = + n__read_addr__h61683; 1'd1: - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = - n__read_addr__h61760; + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23 = + n__read_addr__h61768; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80300 or n__read_child__h80481 or n__read_child__h80560) + always@(x__h80308 or n__read_child__h80489 or n__read_child__h80568) begin - case (x__h80300) - 1'd0: x__h82716 = n__read_child__h80481; - 1'd1: x__h82716 = n__read_child__h80560; + case (x__h80308) + 1'd0: x__h82724 = n__read_child__h80489; + 1'd1: x__h82724 = n__read_child__h80568; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80300 or + always@(x__h80308 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : 2'd0; 1'd1: - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : 2'd0; endcase end - always@(x__h80300 or + always@(x__h80308 or NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; 1'd1: - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; endcase end - always@(x__h80300 or n__read_addr__h80478 or n__read_addr__h80557) + always@(x__h80308 or n__read_addr__h80486 or n__read_addr__h80565) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = - n__read_addr__h80478; + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34 = + n__read_addr__h80486; 1'd1: - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = - n__read_addr__h80557; + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34 = + n__read_addr__h80565; endcase end @@ -8227,14 +8235,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163582 = $stime; + v__h163594 = $stime; #0; end - v__h163576 = v__h163582 / 32'd10; + v__h163588 = v__h163594 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163576, + v__h163588, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8245,7 +8253,7 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61493 && + x__h61501 && (!propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8256,7 +8264,7 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80300 && + x__h80308 && (!propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8266,14 +8274,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163118 = $stime; + v__h163126 = $stime; #0; end - v__h163112 = v__h163118 / 32'd10; + v__h163120 = v__h163126 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163112, + v__h163120, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8283,7 +8291,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163161); + $display("FAIL %0d", failed_testnum__h163169); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8291,14 +8299,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5520 = $stime; + v__h5528 = $stime; #0; end - v__h5514 = v__h5520 / 32'd10; + v__h5522 = v__h5528 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5514); + $display("%0d: %m.rl_handle_read_rsps ", v__h5522); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8358,16 +8366,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5693 = $stime; + v__h5701 = $stime; #0; end - v__h5687 = v__h5693 / 32'd10; + v__h5695 = v__h5701 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5687); + v__h5695); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8471,14 +8479,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5953 = $stime; + v__h5961 = $stime; #0; end - v__h5947 = v__h5953 / 32'd10; + v__h5955 = v__h5961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5947); + $display("%d: %m.rl_handle_write_req: St request:", v__h5955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8648,15 +8656,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h8095 = $stime; + v__h8103 = $stime; #0; end - v__h8089 = v__h8095 / 32'd10; + v__h8097 = v__h8103 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h8089); + $display("%0d: ERROR: CreditCounter: overflow", v__h8097); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8706,7 +8714,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7925); + $write("'h%h", x__h7933); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8837,16 +8845,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8310 = $stime; + v__h8318 = $stime; #0; end - v__h8304 = v__h8310 / 32'd10; + v__h8312 = v__h8318 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8304); + v__h8312); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9052,14 +9060,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2670 = $stime; + v__h2678 = $stime; #0; end - v__h2664 = v__h2670 / 32'd10; + v__h2672 = v__h2678 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2664); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2672); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9349,16 +9357,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4343 = $stime; + v__h4351 = $stime; #0; end - v__h4337 = v__h4343 / 32'd10; + v__h4345 = v__h4351 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4337); + v__h4345); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9564,14 +9572,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9480 = $stime; + v__h9488 = $stime; #0; end - v__h9474 = v__h9480 / 32'd10; + v__h9482 = v__h9488 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9474); + $display("%0d: %m.rl_discard_write_rsp", v__h9482); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9608,15 +9616,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9973 = $stime; + v__h9981 = $stime; #0; end - v__h9967 = v__h9973 / 32'd10; + v__h9975 = v__h9981 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9967); + v__h9975); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9656,14 +9664,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h10136 = $stime; + v__h10144 = $stime; #0; end - v__h10130 = v__h10136 / 32'd10; + v__h10138 = v__h10144 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h10130); + v__h10138); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9861,13 +9869,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43001 != 64'd0) + x__h43009 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40935 != 64'd0) + x__h40943 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9887,15 +9895,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h135075 = $stime; + v__h135083 = $stime; #0; end - v__h135069 = v__h135075 / 32'd10; + v__h135077 = v__h135083 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135069, + v__h135077, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9955,15 +9963,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135242 = $stime; + v__h135250 = $stime; #0; end - v__h135236 = v__h135242 / 32'd10; + v__h135244 = v__h135250 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135236); + v__h135244); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10144,16 +10152,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137345 = $stime; + v__h137353 = $stime; #0; end - v__h137339 = v__h137345 / 32'd10; + v__h137347 = v__h137353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137339); + v__h137347); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11351,14 +11359,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154689 = $stime; + v__h154697 = $stime; #0; end - v__h154683 = v__h154689 / 32'd10; + v__h154691 = v__h154697 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154683); + $display("%0d: ERROR: CreditCounter: overflow", v__h154691); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11382,7 +11390,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_wr_addr_awaddr__h148600); + $write("'h%h", mem_req_wr_addr_awaddr__h148608); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11470,7 +11478,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", data64__h148515); + $write("'h%h", data64__h148523); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11478,7 +11486,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", strb8__h148516); + $write("'h%h", strb8__h148524); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11504,16 +11512,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134456 = $stime; + v__h134464 = $stime; #0; end - v__h134450 = v__h134456 / 32'd10; + v__h134458 = v__h134464 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134450, + v__h134458, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11601,7 +11609,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_rd_addr_araddr__h134676); + $write("'h%h", mem_req_rd_addr_araddr__h134684); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11682,15 +11690,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h161383 = $stime; + v__h161391 = $stime; #0; end - v__h161377 = v__h161383 / 32'd10; + v__h161385 = v__h161391 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161377, + v__h161385, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -11728,15 +11736,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161891 = $stime; + v__h161899 = $stime; #0; end - v__h161885 = v__h161891 / 32'd10; + v__h161893 = v__h161899 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161885); + v__h161893); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/src_BSV/ClockHacks.bsv b/src_SSITH_P3/src_BSV/ClockHacks.bsv new file mode 100644 index 0000000..dde2445 --- /dev/null +++ b/src_SSITH_P3/src_BSV/ClockHacks.bsv @@ -0,0 +1,117 @@ + +package ClockHacks; + +import Clocks ::*; +import Connectable ::*; + +(* always_ready, always_enabled *) +interface OutputBit; + method Bit#(1) out; +endinterface + +import "BVI" ASSIGN1 = +module packClock#(Clock clk)(OutputBit); + + default_clock no_clock; + default_reset no_reset; + + input_clock clk(IN) = clk; + + method OUT out; + + schedule (out) CF (out); + +endmodule + +import "BVI" ASSIGN1 = +module packReset#(Reset rst)(OutputBit); + + default_clock no_clock; + default_reset no_reset; + + input_reset rst(IN) = rst; + + method OUT out reset_by(rst); + + schedule (out) CF (out); + +endmodule + +(* always_ready, always_enabled *) +interface UnpackedClock; + interface Clock clk; + method Action in(Bit#(1) x); +endinterface + +import "BVI" ASSIGN1 = +module unpackClock(UnpackedClock); + + default_clock no_clock; + default_reset no_reset; + + output_clock clk(OUT); + + method in(IN) enable((*inhigh*)en) clocked_by(clk); + + schedule (in) CF (in); + +endmodule + +(* always_ready, always_enabled *) +interface UnpackedReset; + interface Reset rst; + method Action in(Bit#(1) x); +endinterface + +import "BVI" ASSIGN1 = +module unpackReset#(Clock clk)(UnpackedReset); + + default_clock no_clock; + default_reset no_reset; + + input_clock clk() = clk; + output_reset rst(OUT); + + method in(IN) enable((*inhigh*)en) clocked_by(clk) reset_by(rst); + + schedule (in) CF (in); + +endmodule + +//////////////////// + +interface BlockIfc; + interface Clock clk; + interface Reset rst; +endinterface + +module mkBlock(BlockIfc); + let default_clock <- exposeCurrentClock; + let default_reset <- exposeCurrentReset; + + interface clk = default_clock; + interface rst = default_reset; +endmodule + +module mkTop(Empty); + + let clk_unpack <- unpackClock; + let clk = clk_unpack.clk; + + let rst_unpack <- unpackReset(clk); + let rst = rst_unpack.rst; + + let a <- mkBlock(clocked_by clk, reset_by rst); + let b <- mkBlock(clocked_by clk, reset_by rst); + + let clk_pack <- packClock(b.clk, clocked_by clk); + let rst_pack <- packReset(b.rst, clocked_by clk); + + mkConnection(clk_unpack.in, clk_pack.out); + mkConnection(rst_unpack.in, rst_pack.out); + +endmodule + +//////////////////// + +endpackage : ClockHacks diff --git a/src_SSITH_P3/src_BSV/JtagTap.bsv b/src_SSITH_P3/src_BSV/JtagTap.bsv index fe68d51..1efe670 100644 --- a/src_SSITH_P3/src_BSV/JtagTap.bsv +++ b/src_SSITH_P3/src_BSV/JtagTap.bsv @@ -3,11 +3,14 @@ package JtagTap; import BUtils ::*; import Clocks ::*; +import Connectable ::*; import DefaultValue ::*; import FIFOF ::*; import FIFOLevel ::*; import Reserved ::*; +import PowerOnReset ::*; +import ClockHacks ::*; import Giraffe_IFC ::*; typedef 6 ABITS; @@ -16,6 +19,10 @@ typedef 6 ABITS; typedef 6 IR_LENGTH; `elsif XILINX_XCVU9P typedef 18 IR_LENGTH; +`elsif XILINX_XC7K325T +typedef 6 IR_LENGTH; +`else +typedef 5 IR_LENGTH; `endif `else typedef 5 IR_LENGTH; @@ -34,6 +41,12 @@ Bit#(IR_LENGTH) ir_dtmcs = 'b100010100100100100; // USER3 // 'b000010100100100100; USER1 Bit#(IR_LENGTH) ir_dmi = 'b000011100100100100; +`elsif XILINX_XC7K325T +Bit#(IR_LENGTH) ir_dtmcs = 'h22; +Bit#(IR_LENGTH) ir_dmi = 'h03; +`else +Bit#(IR_LENGTH) ir_dtmcs = 'h10; +Bit#(IR_LENGTH) ir_dmi = 'h11; `endif `else Bit#(IR_LENGTH) ir_dtmcs = 'h10; @@ -176,15 +189,12 @@ module mkJtagTap(JtagTap_IFC); Wire#(Bit#(1)) w_tck <- mkDWire(?); - let tck_clock <- mkUngatedClock(?); - let tck = tck_clock.new_clk; + let tck_clock <- unpackClock; + let tck = tck_clock.clk; + let w_tck_crossed <- mkNullCrossing(tck, w_tck); + mkConnection(w_tck_crossed, tck_clock.in); - (* no_implicit_conditions, fire_when_enabled *) - rule rl_tck; - tck_clock.setClockValue(w_tck); - endrule - - let rst_tck <- mkAsyncResetFromCR(4, tck); + let rst_tck <- mkAsyncResetFromCR(0, tck); // value independent of tck Wire#(Bit#(1)) w_tms <- mkDWire(?, clocked_by tck, reset_by rst_tck); Wire#(Bit#(1)) w_tdi <- mkDWire(?, clocked_by tck, reset_by rst_tck); @@ -201,13 +211,16 @@ module mkJtagTap(JtagTap_IFC); Array#(Reg#(Bit#(1))) r_tdo <- mkCRegU(2, clocked_by tck, reset_by rst_tck); - Reg#(JtagState) r_state <- mkReg(TEST_LOGIC_RESET, clocked_by tck, reset_by rst_tck); + Reg#(JtagState) r_state <- mkRegUNInit(TEST_LOGIC_RESET, clocked_by tck, reset_by rst_tck); + Reg#(Bool) r_initialize <- mkRegUNInit(True, clocked_by tck, reset_by rst_tck); + Reg#(Bool) r_initialize2 <- mkRegUNInit(True); + PulseWire w_initialize <- mkPulseWire( clocked_by tck, reset_by rst_tck); Reg#(Bit#(IR_LENGTH)) r_ir <- mkRegU(clocked_by tck, reset_by rst_tck); Reg#(Bit#(DR_LENGTH)) r_dr <- mkRegU(clocked_by tck, reset_by rst_tck); Reg#(Bit#(DR_LENGTH)) r_drmask <- mkRegU(clocked_by tck, reset_by rst_tck); - Reg#(DMI) r_dmi <- mkReg(defaultValue, clocked_by tck, reset_by rst_tck); + Reg#(DMI) r_dmi <- mkRegUNInit(defaultValue, clocked_by tck, reset_by rst_tck); Wire#(Tuple3#(Bit#(7),Bit#(32),Bit#(2))) w_dmi_req <- mkWire(clocked_by tck, reset_by rst_tck); SyncFIFOLevelIfc#(Tuple3#(Bit#(7),Bit#(32),Bit#(2)), 2) f_dmi_req <- mkSyncFIFOLevel(tck, rst_tck, clk); @@ -216,6 +229,19 @@ module mkJtagTap(JtagTap_IFC); Array#(Reg#(Bool)) r_dmistat_busy <- mkCReg(2, False, clocked_by tck, reset_by rst_tck); SyncFIFOLevelIfc#(DMI, 2) f_dmi_rsp <- mkSyncFIFOLevel(clk, rst, tck); + rule rl_initialize2(r_initialize2); + r_initialize2 <= False; + + f_dmi_req.dClear; + f_dmi_rsp.sClear; + endrule + + (* no_implicit_conditions, fire_when_enabled *) + rule rl_initialize(w_initialize); + f_dmi_busy.clear; + r_dmistat_busy[1] <= False; + endrule + (* no_implicit_conditions, fire_when_enabled *) rule tick; let newir = r_ir; @@ -224,6 +250,10 @@ module mkJtagTap(JtagTap_IFC); if (r_state == TEST_LOGIC_RESET) begin newir = ir_idcode; + if (r_initialize) begin + r_initialize <= False; + w_initialize.send(); + end end else if (r_state == CAPTURE_DR) begin if (newir == ir_bypass0 || diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 3f05153..da97bd6 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -36,7 +36,8 @@ import Cur_Cycle :: *; // ================================================================ // Project imports -import SoC_Map :: *; +import SoC_Map :: *; +import PowerOnReset :: *; // The basic core import CoreW_IFC :: *; @@ -121,8 +122,11 @@ module mkP3_Core (P3_Core_IFC); // its reset down from here. // (power-on reset) and the Debug Module's 'hart_reset' control. + let default_reset <- exposeCurrentReset(); - let power_on_reset <- exposeCurrentReset; + let por_ifc <- mkPowerOnReset(); + let power_on_reset = por_ifc.gen_rst; // This line and the next + //let power_on_reset <- default_reset; //are alternatives. let dm_power_on_reset = power_on_reset; // The rest of the system (corew minus the Debug Module) are reset: @@ -131,13 +135,24 @@ module mkP3_Core (P3_Core_IFC); `ifdef INCLUDE_GDB_CONTROL let clk <- exposeCurrentClock; - Bool initial_reset_val = False; + // Setting initial_reset_val to True ensures that if the mkReset is itself in + // reset (controlled by mkP3_Core's default reset), its output reset will be + // asserted. Thus ndm_reset will be asserted if any of + // power_on_reset, default_reset, ndm_reset from debug module + // is asserted. + + // Currently initial_reset_val=False -- thus ndm_reset will be asserted only + // if any of + // power_on_reset, ndm_reset from debug module + // is asserted. + Bool initial_reset_val = False; // was True; Integer ndm_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for NDM let ndm_reset_controller <- mkReset(ndm_reset_duration, initial_reset_val, clk); let ndm_reset <- mkResetEither (power_on_reset, ndm_reset_controller.new_rst); `else - let ndm_reset = power_on_reset; + let rstn <- exposeCurrentReset; + let ndm_reset <- mkResetEither (power_on_reset, rstn); `endif // ================================================================ @@ -165,11 +180,13 @@ module mkP3_Core (P3_Core_IFC); // NDM reset (reset for non-DebugModule) Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0); + Reg #(Bool) rg_running <- mkRegU; // Get an NDM-reset request from the Debug Module, assert ndm-reset, // and then wait for a suitable delay. rule rl_ndm_reset (rg_ndm_reset_delay == 0); let x <- corew.ndm_reset_client.request.get; + rg_running <= x; ndm_reset_controller.assertReset; rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 100); // NOTE: heuristic @@ -180,9 +197,9 @@ module mkP3_Core (P3_Core_IFC); // Wait for suitable delay, then send ack response to Debug Module for NDM-reset request rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0); if (rg_ndm_reset_delay == 1) begin - Bool is_running = True; + Bool is_running = rg_running; // Restart the corew - corew.start (0, 0); + corew.start (rg_running, 0, 0); corew.ndm_reset_client.response.put (is_running); $display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", cur_cycle); @@ -191,11 +208,13 @@ module mkP3_Core (P3_Core_IFC); endrule // ================================================================ - // Start the corew after a PoR - Reg #(Bool) rg_corew_start_after_por <- mkReg(False); - rule rl_step_0 (!rg_corew_start_after_por); - corew.start (0, 0); - rg_corew_start_after_por <= True; + // Start the corew a suitable time after a PoR + UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew + Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait); + rule rl_step_0 (rg_corew_start_after_por != 0); + let n = rg_corew_start_after_por - 1; + rg_corew_start_after_por <= n; + if (n==0) corew.start (True, 0, 0); // initial start leaves proc running endrule // ================================================================ @@ -217,7 +236,7 @@ module mkP3_Core (P3_Core_IFC); BusSender#(Tuple2#(Bit#(32),Bit#(2))) bus_dmi_rsp <- mkBusSender(unpack(0)); `ifdef JTAG_TAP - let jtagtap <- mkJtagTap; + let jtagtap <- mkJtagTap(reset_by power_on_reset); mkConnection(jtagtap.dmi.req_ready, pack(bus_dmi_req.in.ready)); mkConnection(jtagtap.dmi.req_valid, compose(bus_dmi_req.in.valid, unpack)); diff --git a/src_SSITH_P3/src_BSV/PowerOnReset.bsv b/src_SSITH_P3/src_BSV/PowerOnReset.bsv new file mode 100644 index 0000000..30bafe2 --- /dev/null +++ b/src_SSITH_P3/src_BSV/PowerOnReset.bsv @@ -0,0 +1,51 @@ +package PowerOnReset; + +import Clocks::*; + +UInt#(8) resetCycles = 10; + +import "BVI" RegUNInit = +module mkRegUNInit#(parameter a init) (Reg#(a)) + provisos (Bits#(a,sa)); + + parameter width = valueOf(sa); + parameter init = pack(init); + + default_clock clk(CLK, (*unused*)CLK_GATE); + no_reset; + + method Q_OUT _read(); + method _write(D_IN) enable(EN); + + schedule _read CF _read; + schedule _write SBR _write; + schedule _read SB _write; +endmodule + + + +import "BVI" ASSIGN1 = +module mkBoolToReset#(Bool xin) (ResetGenIfc); + default_clock (); + no_reset; + + port IN = xin; + output_reset gen_rst(OUT); +endmodule + +(*synthesize*) +module mkPowerOnReset (ResetGenIfc); + Reg#(UInt#(8)) ctr <- mkRegUNInit(resetCycles); + Reg#(Bool) isInPowerOnReset <- mkRegUNInit(True); + + rule countDown(isInPowerOnReset); + let n = ctr - 1; + ctr <= n; + if (n==0) isInPowerOnReset <= False; + endrule + + let rst_ifc <- mkBoolToReset(!isInPowerOnReset); + return rst_ifc; +endmodule + +endpackage diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index 63770e1..6760f41 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -165,14 +165,6 @@ master0_awready - - - WID - - - master0_wid - - WDATA @@ -495,14 +487,6 @@ master1_awready - - - WID - - - master1_wid - - WDATA @@ -801,7 +785,7 @@ viewChecksum - 63c940c2 + c8a99f02 @@ -826,7 +810,7 @@ viewChecksum - 63c940c2 + 02500583 @@ -1080,23 +1064,6 @@ - - master0_wid - - out - - 3 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - master0_wdata @@ -1737,23 +1704,6 @@ - - master1_wid - - out - - 3 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - master1_wdata @@ -2405,6 +2355,21 @@ USED_IN_implementation USED_IN_synthesis + + hdl/ASSIGN1.v + verilogSource + IMPORTED_FILE + + + hdl/RegUNInit.v + verilogSource + IMPORTED_FILE + + + hdl/mkPowerOnReset.v + verilogSource + IMPORTED_FILE + hdl/BRAM2.v verilogSource @@ -2470,6 +2435,16 @@ verilogSource IMPORTED_FILE + + hdl/SyncReset0.v + verilogSource + IMPORTED_FILE + + + hdl/SyncWire.v + verilogSource + IMPORTED_FILE + hdl/mkAluDispToRegFifo.v verilogSource @@ -2785,6 +2760,11 @@ verilogSource IMPORTED_FILE + + hdl/mkTrace_Data2_to_Trace_Data.v + verilogSource + IMPORTED_FILE + hdl/mkTV_Xactor.v verilogSource @@ -2932,6 +2912,7 @@ hdl/FIFOL1.v verilogSource + CHECKSUM_bfe3b3df @@ -2966,6 +2947,21 @@ xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/ASSIGN1.v + verilogSource + IMPORTED_FILE + + + hdl/RegUNInit.v + verilogSource + IMPORTED_FILE + + + hdl/mkPowerOnReset.v + verilogSource + IMPORTED_FILE + hdl/BRAM2.v verilogSource @@ -3031,6 +3027,16 @@ verilogSource IMPORTED_FILE + + hdl/SyncReset0.v + verilogSource + IMPORTED_FILE + + + hdl/SyncWire.v + verilogSource + IMPORTED_FILE + hdl/mkAluDispToRegFifo.v verilogSource @@ -3346,6 +3352,11 @@ verilogSource IMPORTED_FILE + + hdl/mkTrace_Data2_to_Trace_Data.v + verilogSource + IMPORTED_FILE + hdl/mkTV_Xactor.v verilogSource @@ -3551,23 +3562,28 @@ mkP3_Core_v1_0 package_project - 1 + 2 user.org:user:mkP3_Core:1.0 - 2019-04-07T20:09:49Z + 2020-02-20T15:03:34Z /home/charlie/ssith_processor /home/charlie/ssith_processor /home/charlie/ssith_processor + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip - 2017.4 - + 2019.1 + - - + + diff --git a/src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v b/src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v new file mode 100644 index 0000000..4bedc0b --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v @@ -0,0 +1,5 @@ +module ASSIGN1(IN, OUT); + output OUT; + input IN; + assign OUT = IN; +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v b/src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v new file mode 100644 index 0000000..1dc1123 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v @@ -0,0 +1,87 @@ + +// Copyright (c) 2000-2012 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + + +module MakeReset0 ( + CLK, + RST, + ASSERT_IN, + ASSERT_OUT, + + OUT_RST + ); + + parameter init = 1 ; + + input CLK ; + input RST ; + input ASSERT_IN ; + output ASSERT_OUT ; + + output OUT_RST ; + + reg rst ; + + assign ASSERT_OUT = rst == `BSV_RESET_VALUE ; + + assign OUT_RST = rst ; + + always@(posedge CLK or `BSV_RESET_EDGE RST) begin + if (RST == `BSV_RESET_VALUE) + rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE; + else + begin + if (ASSERT_IN) + rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE; + else // if (rst == 1'b0) + rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE; + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + + +`ifdef BSV_NO_INITIAL_BLOCKS +`else // not BSV_NO_INITIAL_BLOCKS + // synopsys translate_off + initial begin + #0 ; + rst = ~ `BSV_RESET_VALUE ; + end + // synopsys translate_on +`endif // BSV_NO_INITIAL_BLOCKS + +endmodule // MakeReset0 diff --git a/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v b/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v new file mode 100644 index 0000000..c685d10 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v @@ -0,0 +1,50 @@ + +// Copyright (c) 2000-2019 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +// Basic register with initial value but without reset (not for ASIC synthesis). +module RegUNInit(CLK, Q_OUT, D_IN, EN); + + parameter width = 1; + parameter init = { width {1'b0} } ; + + input CLK; + input RST; + input EN; + input [width - 1 : 0] D_IN; + output [width - 1 : 0] Q_OUT; + + reg [width - 1 : 0] Q_OUT; + initial Q_OUT = init; + + always@(posedge CLK) + begin + if (EN) + Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; + end +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v b/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v new file mode 100644 index 0000000..e97c94f --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v @@ -0,0 +1,50 @@ + +// Copyright (c) 2000-2012 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + + +module SyncReset0 ( + IN_RST, + OUT_RST + ); + + input IN_RST ; + output OUT_RST ; + + assign OUT_RST = IN_RST ; + +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/SyncWire.v b/src_SSITH_P3/xilinx_ip/hdl/SyncWire.v new file mode 100644 index 0000000..61a23bf --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/SyncWire.v @@ -0,0 +1,41 @@ + +// Copyright (c) 2000-2009 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else +`define BSV_ASSIGNMENT_DELAY +`endif + + +module SyncWire( DIN, DOUT ); + + parameter width = 1; + + input [width - 1 : 0] DIN; + output [width - 1 : 0] DOUT; + + assign DOUT = DIN ; + + +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 0452f06..76bc0cb 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -6,7 +6,7 @@ // // Ports: // Name I/O size props -// RDY_coreReq_start O 1 const +// RDY_coreReq_start O 1 // RDY_coreReq_perfReq O 1 reg // coreIndInv_perfResp O 73 // RDY_coreIndInv_perfResp O 1 reg @@ -104,6 +104,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -184,6 +185,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -402,6 +404,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4314,7 +4317,7 @@ module mkCore(CLK, wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, - MUX_l2Tlb$updateVMInfo_1__VAL_1; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, @@ -4464,9 +4467,10 @@ module mkCore(CLK, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, MUX_regRenamingTable$rename_0_getRename_1__SEL_3, - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_2, + MUX_renameStage_rg_m_halt_req$write_1__SEL_3, + MUX_renameStage_rg_m_halt_req$write_1__SEL_6, MUX_rf$write_3_wr_1__PSEL_5, MUX_rf$write_3_wr_1__SEL_1, MUX_rf$write_3_wr_1__SEL_2, @@ -4521,24 +4525,24 @@ module mkCore(CLK, reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4550,20 +4554,20 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84, - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85, + reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82, + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122, CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51, @@ -4572,8 +4576,8 @@ module mkCore(CLK, CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85, _theResult___fst_sfd__h346070, _theResult___fst_sfd__h354793, _theResult___fst_sfd__h363375, @@ -4609,7 +4613,7 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248, + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, @@ -4631,8 +4635,8 @@ module mkCore(CLK, CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, @@ -4698,8 +4702,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21, CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, @@ -4743,7 +4747,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, @@ -4767,22 +4771,22 @@ module mkCore(CLK, CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191, + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, @@ -4790,11 +4794,11 @@ module mkCore(CLK, CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, @@ -4872,19 +4876,19 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080; wire [463 : 0] commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942; wire [457 : 0] rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; wire [393 : 0] IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; wire [181 : 0] fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; @@ -5844,7 +5848,7 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106, x__h181701, x__h713427; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, @@ -6320,7 +6324,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911, - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388, + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388, NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667, NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008, NOT_rob_deqPort_1_deq_data__5354_BIT_25_5355_5_ETC___d15385, @@ -6390,7 +6394,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo22, + _dfoo20, _dfoo24, _dfoo26, _dfoo32, @@ -6535,7 +6539,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909, f_csr_rsps_i_notFull__5799_AND_f_csr_reqs_firs_ETC___d15902, - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093, + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191, @@ -6586,7 +6590,7 @@ module mkCore(CLK, next_deqP___1__h332215, r1__read_BIT_20___h655898, r__h614580, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956, regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037, regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444, @@ -6611,7 +6615,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935, rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15738, - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013, + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, @@ -6630,8 +6634,8 @@ module mkCore(CLK, x__h603386; // action method coreReq_start - assign RDY_coreReq_start = 1'd1 ; - assign CAN_FIRE_coreReq_start = 1'd1 ; + assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; + assign CAN_FIRE_coreReq_start = !renameStage_rg_m_halt_req[4] ; assign WILL_FIRE_coreReq_start = EN_coreReq_start ; // action method coreReq_perfReq @@ -6668,7 +6672,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6688,7 +6692,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9946,7 +9950,8 @@ module mkCore(CLK, f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] && rg_core_run_state == 2'd2 && !f_run_halt_reqs$D_OUT ; - assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ; + assign WILL_FIRE_RL_rl_debug_halt_req = + CAN_FIRE_RL_rl_debug_halt_req && !EN_coreReq_start ; // rule RL_rl_debug_halt_req_already_halted assign CAN_FIRE_RL_rl_debug_halt_req_already_halted = @@ -10371,8 +10376,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10408,7 +10413,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 && + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10443,7 +10448,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 && + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15400 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11412,9 +11417,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11422,19 +11428,21 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_csrInstOrInterruptInflight_canon assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; @@ -11479,7 +11487,8 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_mmio_pRqQ_canonicalize assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ; @@ -11952,16 +11961,17 @@ module mkCore(CLK, WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; - assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst || - WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 = - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 && - csrf_rg_dcsr[2] ; - assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_3 = + WILL_FIRE_RL_renameStage_doRenaming_Trap && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_6 = + EN_coreReq_start && !coreReq_start_running ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && coreFix_memExe_lsq$firstSt[150] ; @@ -12459,6 +12469,12 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738339 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or next_pc__h723452 or csrf_sepc_csr or csrf_mepc_csr) begin @@ -12474,12 +12490,6 @@ module mkCore(CLK, coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 = { 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ; - assign MUX_l2Tlb$updateVMInfo_1__VAL_1 = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], @@ -14811,7 +14821,7 @@ module mkCore(CLK, assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15103,21 +15113,24 @@ module mkCore(CLK, assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; // register renameStage_rg_m_halt_req - always@(WILL_FIRE_RL_rl_debug_resume or + always@(MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_3 or + WILL_FIRE_RL_rl_debug_resume or WILL_FIRE_RL_rl_debug_halt_req or - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or - MUX_renameStage_rg_m_halt_req$write_1__SEL_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; - WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30; - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || - MUX_renameStage_rg_m_halt_req$write_1__SEL_2: - renameStage_rg_m_halt_req$D_IN = 5'd31; - default: renameStage_rg_m_halt_req$D_IN = - 5'b01010 /* unspecified value */ ; - endcase - end + MUX_renameStage_rg_m_halt_req$write_1__SEL_6) + case (1'b1) + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_3: + renameStage_rg_m_halt_req$D_IN = 5'd31; + WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; + WILL_FIRE_RL_rl_debug_halt_req || + MUX_renameStage_rg_m_halt_req$write_1__SEL_6: + renameStage_rg_m_halt_req$D_IN = 5'd30; + default: renameStage_rg_m_halt_req$D_IN = + 5'b01010 /* unspecified value */ ; + endcase assign renameStage_rg_m_halt_req$EN = (WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap) && @@ -15125,6 +15138,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] || + EN_coreReq_start && !coreReq_start_running || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15157,7 +15171,7 @@ module mkCore(CLK, !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data @@ -18150,8 +18164,8 @@ module mkCore(CLK, assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; @@ -18310,8 +18324,8 @@ module mkCore(CLK, MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; assign l2Tlb$updateVMInfo_vmI = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign l2Tlb$EN_updateVMInfo = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_rl_debug_resume ; @@ -20845,8 +20859,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20878,8 +20892,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21439,8 +21453,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21450,8 +21464,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = (_theResult___fst_exp__h519940 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -22132,8 +22146,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || @@ -22158,8 +22172,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? 4'd0 : @@ -24166,10 +24180,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149 = @@ -24183,10 +24197,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 && IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093) ; + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && @@ -25474,9 +25488,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 ; - assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 = + assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25515,7 +25529,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022 = !specTagManager$canClaim || @@ -25549,21 +25563,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, x__h291618 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = @@ -26616,7 +26630,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo22 = + assign _dfoo20 = commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign _dfoo24 = @@ -28089,7 +28103,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 : + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; assign _theResult___fst_exp__h598880 = (_theResult___fst_exp__h598097 == 11'd2047) ? @@ -28220,7 +28234,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 : + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; assign _theResult___fst_sfd__h502289 = (_theResult___fst_exp__h501530 == 11'd2047) ? @@ -28231,7 +28245,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; assign _theResult___fst_sfd__h511940 = (_theResult___fst_exp__h511107 == 11'd2047) ? @@ -28242,7 +28256,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 : + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; assign _theResult___fst_sfd__h520724 = (_theResult___fst_exp__h519940 == 11'd2047) ? @@ -28283,7 +28297,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 : + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; assign _theResult___fst_sfd__h550793 = (_theResult___fst_exp__h549960 == 11'd2047) ? @@ -28294,7 +28308,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 : + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; assign _theResult___fst_sfd__h559577 = (_theResult___fst_exp__h558793 == 11'd2047) ? @@ -30231,12 +30245,14 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609378 = { 56'd0, x__h613036 } ; - assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31048,14 +31064,13 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; assign r__h614580 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31553,13 +31568,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612208 = { r1__read__h614606, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; + assign rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -31582,11 +31596,11 @@ module mkCore(CLK, assign rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 } ; + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; assign rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520 = { rob$deqPort_0_deq_data[181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 } ; + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; assign rs1__h655333 = @@ -33134,6 +33148,23 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33162,23 +33193,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19]) @@ -33555,69 +33569,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h381194 = 8'd0; endcase end - always@(guard__h346097 or - sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0, 2'b01: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - sfdin__h354192[56:34]; - 2'b10: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - out_sfd__h354718; - 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - _theResult___sfd__h354715; - endcase - end - always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - sfdin__h354192[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - _theResult___sfd__h354715; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354192) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47; - 3'd1: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48; - 3'd2: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; - 3'd3: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; - default: _theResult___fst_sfd__h354793 = 23'd0; - endcase - end always@(guard__h354806 or _theResult___snd__h362805 or out_sfd__h363300 or _theResult___sfd__h363297) begin case (guard__h354806) 2'b0, 2'b01: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___snd__h362805[56:34]; 2'b10: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = out_sfd__h363300; 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___sfd__h363297; endcase end @@ -33626,16 +33590,16 @@ module mkCore(CLK, begin case (guard__h354806) 2'b0: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___snd__h362805[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___sfd__h363297; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or _theResult___snd__h362805) @@ -33643,10 +33607,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47; 3'd1: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48; 3'd2: _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; @@ -33657,6 +33621,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h363375 = 23'd0; endcase end + always@(guard__h346097 or + sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0, 2'b01: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354192[56:34]; + 2'b10: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354718; + 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354715; + endcase + end + always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354192[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354715; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or + sfdin__h354192) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49; + 3'd1: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50; + 3'd2: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; + 3'd3: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; + 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; + default: _theResult___fst_sfd__h354793 = 23'd0; + endcase + end always@(guard__h363736 or sfdin__h371958 or out_sfd__h372484 or _theResult___sfd__h372481) begin @@ -33797,66 +33811,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354806 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h354806) - 2'b0, 2'b01, 2'b10: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - guard__h354806 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or - guard__h354806) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354806 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || - guard__h354806 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = (guard__h346097 == 2'b0) ? @@ -33873,6 +33849,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h354806 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h354806) + 2'b0, 2'b01, 2'b10: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354806 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354806) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + (guard__h354806 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || + guard__h354806 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34297,69 +34311,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h426891 = 8'd0; endcase end - always@(guard__h391796 or - sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0, 2'b01: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - sfdin__h399889[56:34]; - 2'b10: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - out_sfd__h400415; - 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - _theResult___sfd__h400412; - endcase - end - always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - sfdin__h399889[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - _theResult___sfd__h400412; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399889) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82; - 3'd1: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83; - 3'd2: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; - 3'd3: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; - default: _theResult___fst_sfd__h400490 = 23'd0; - endcase - end always@(guard__h400503 or _theResult___snd__h408502 or out_sfd__h408997 or _theResult___sfd__h408994) begin case (guard__h400503) 2'b0, 2'b01: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___snd__h408502[56:34]; 2'b10: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = out_sfd__h408997; 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___sfd__h408994; endcase end @@ -34368,16 +34332,16 @@ module mkCore(CLK, begin case (guard__h400503) 2'b0: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___snd__h408502[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___sfd__h408994; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or _theResult___snd__h408502) @@ -34385,10 +34349,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82; 3'd1: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83; 3'd2: _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; @@ -34399,6 +34363,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h409072 = 23'd0; endcase end + always@(guard__h391796 or + sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0, 2'b01: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399889[56:34]; + 2'b10: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400415; + 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400412; + endcase + end + always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399889[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400412; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or + sfdin__h399889) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84; + 3'd1: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85; + 3'd2: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; + 3'd3: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; + 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; + default: _theResult___fst_sfd__h400490 = 23'd0; + endcase + end always@(guard__h409433 or sfdin__h417655 or out_sfd__h418181 or _theResult___sfd__h418178) begin @@ -34734,61 +34748,23 @@ module mkCore(CLK, begin case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or - guard__h418269) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418269 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h418269 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h418269) - 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = guard__h418269 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = (guard__h418269 == 2'b0) ? @@ -34805,6 +34781,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end + always@(guard__h418269 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h418269) + 2'b0, 2'b01, 2'b10: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418269) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + (guard__h418269 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -35821,21 +35835,21 @@ module mkCore(CLK, _theResult___exp__h580342; endcase end - always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581038) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h581038 == 2'b11 && + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571726 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35844,12 +35858,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h581038 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || - guard__h581038 == 2'b11) && + (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || + guard__h571726 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35860,21 +35874,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571726) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h571726 == 2'b11 && + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581038 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35883,12 +35897,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h571726 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || - guard__h571726 == 2'b11) && + (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || + guard__h581038 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36259,57 +36273,15 @@ module mkCore(CLK, _theResult___exp__h589993; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - guard__h532422 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || - guard__h532422 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h590107 or _theResult___fst_exp__h598097 or _theResult___exp__h598777) begin case (guard__h590107) 2'b0: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___fst_exp__h598097; 2'b01, 2'b10, 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___exp__h598777; endcase end @@ -36317,7 +36289,7 @@ module mkCore(CLK, _theResult___fst_exp__h598097 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193) + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36331,7 +36303,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase @@ -36342,13 +36314,13 @@ module mkCore(CLK, begin case (guard__h590107) 2'b0, 2'b01: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___fst_exp__h598097; 2'b10: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = out_exp__h598780; 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___exp__h598777; endcase end @@ -36356,12 +36328,12 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = guard__h541734 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36372,12 +36344,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36387,6 +36359,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h532422 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || + guard__h532422 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -36478,58 +36492,16 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36540,12 +36512,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36555,6 +36527,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -36613,65 +36627,14 @@ module mkCore(CLK, _theResult___sfd__h541039; endcase end - always@(guard__h550803 or - _theResult___snd__h558739 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___snd__h558739[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___sfd__h559474; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558739 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558739[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - 52'd0; - endcase - end - always@(guard__h550803 or - _theResult___snd__h558739 or - out_sfd__h559477 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0, 2'b01: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___snd__h558739[56:5]; - 2'b10: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - out_sfd__h559477; - 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___sfd__h559474; - endcase - end always@(guard__h541734 or sfdin__h549954 or _theResult___sfd__h550690) begin case (guard__h541734) 2'b0: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = sfdin__h549954[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = _theResult___sfd__h550690; endcase end @@ -36679,7 +36642,7 @@ module mkCore(CLK, sfdin__h549954 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209) + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36693,7 +36656,7 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase @@ -36703,16 +36666,67 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = sfdin__h549954[56:5]; 2'b10: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = out_sfd__h550693; 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = _theResult___sfd__h550690; endcase end + always@(guard__h550803 or + _theResult___snd__h558739 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___snd__h558739[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___sfd__h559474; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h558739 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + _theResult___snd__h558739[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + 52'd0; + endcase + end + always@(guard__h550803 or + _theResult___snd__h558739 or + out_sfd__h559477 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0, 2'b01: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___snd__h558739[56:5]; + 2'b10: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + out_sfd__h559477; + 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___sfd__h559474; + endcase + end always@(guard__h502881 or _theResult___fst_exp__h511107 or _theResult___exp__h511836) begin @@ -36815,64 +36829,15 @@ module mkCore(CLK, _theResult___exp__h520620; endcase end - always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h511101[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h511837; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511101 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511101[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - 52'd0; - endcase - end - always@(guard__h502881 or - sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0, 2'b01: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h511101[56:5]; - 2'b10: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h511840; - 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h511837; - endcase - end always@(guard__h493569 or _theResult___snd__h501481 or _theResult___sfd__h502186) begin case (guard__h493569) 2'b0: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___snd__h501481[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___sfd__h502186; endcase end @@ -36880,7 +36845,7 @@ module mkCore(CLK, _theResult___snd__h501481 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217) + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36894,7 +36859,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase @@ -36905,13 +36870,13 @@ module mkCore(CLK, begin case (guard__h493569) 2'b0, 2'b01: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___snd__h501481[56:5]; 2'b10: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = out_sfd__h502189; 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___sfd__h502186; endcase end @@ -36920,10 +36885,10 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___snd__h519886[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___sfd__h520621; endcase end @@ -36931,7 +36896,7 @@ module mkCore(CLK, _theResult___snd__h519886 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219) + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36945,7 +36910,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase @@ -36956,16 +36921,65 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0, 2'b01: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___snd__h519886[56:5]; 2'b10: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = out_sfd__h520624; 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___sfd__h520621; endcase end + always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h511101[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h511837; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h511101 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + sfdin__h511101[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + 52'd0; + endcase + end + always@(guard__h502881 or + sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0, 2'b01: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + sfdin__h511101[56:5]; + 2'b10: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + out_sfd__h511840; + 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + _theResult___sfd__h511837; + endcase + end always@(guard__h571726 or _theResult___snd__h579638 or _theResult___sfd__h580343) begin @@ -38031,10 +38045,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -38042,10 +38056,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -38350,38 +38364,6 @@ module mkCore(CLK, endcase end always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) 12'd1, @@ -38428,12 +38410,44 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = 12'd2303; endcase end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + 4'd15; + endcase + end always@(commitStage_f_rob_data$D_OUT) begin case (commitStage_f_rob_data$D_OUT[97:96]) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index bb0d3be..607e8ac 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -78,6 +78,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// start_is_running I 1 // start_tohost_addr I 64 // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 @@ -161,6 +162,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -379,6 +381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1401,7 +1404,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1609,12 +1613,12 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5047; - reg [31 : 0] v__h5190; - reg [31 : 0] v__h15930; - reg [31 : 0] v__h5041; - reg [31 : 0] v__h5184; - reg [31 : 0] v__h15924; + reg [31 : 0] v__h5055; + reg [31 : 0] v__h5198; + reg [31 : 0] v__h15940; + reg [31 : 0] v__h5049; + reg [31 : 0] v__h5192; + reg [31 : 0] v__h15934; // synopsys translate_on // remaining internal signals @@ -2523,6 +2527,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2716,22 +2721,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -3359,6 +3364,7 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_proc$start_1__SEL_1 ? rg_fromhost_addr : start_fromhost_addr ; + assign proc$start_running = MUX_proc$start_1__SEL_1 || start_is_running ; assign proc$start_startpc = 64'h0000000070000000 ; assign proc$start_tohostAddr = MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; @@ -3700,15 +3706,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h5047 = $stime; + v__h5055 = $stime; #0; end - v__h5041 = v__h5047 / 32'd10; + v__h5049 = v__h5055 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h5041, + v__h5049, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -3716,17 +3722,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h5190 = $stime; + v__h5198 = $stime; #0; end - v__h5184 = v__h5190 / 32'd10; + v__h5192 = v__h5198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h5184, + v__h5192, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); @@ -3734,15 +3740,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15930 = $stime; + v__h15940 = $stime; #0; end - v__h15924 = v__h15930 / 32'd10; + v__h15934 = v__h15940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15924, + v__h15934, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v index 7ed7f93..e079454 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v @@ -130,17 +130,13 @@ module mkJtagTap(CLK, // inlined wires wire [40 : 0] w_dmi_req$wget; - wire r_dmistat_busy$port1__read, + wire r_dmistat_busy$EN_port1__write, + r_dmistat_busy$port1__read, r_dmistat_busy$port2__read, r_tdo$EN_port0__write, r_tdo$port0__write_1, r_tdo$port1__read; - // register r_dmi - reg [39 : 0] r_dmi; - wire [39 : 0] r_dmi$D_IN; - wire r_dmi$EN; - // register r_dmistat_busy reg r_dmistat_busy; wire r_dmistat_busy$D_IN, r_dmistat_busy$EN; @@ -160,11 +156,6 @@ module mkJtagTap(CLK, wire [17 : 0] r_ir$D_IN; wire r_ir$EN; - // register r_state - reg [3 : 0] r_state; - wire [3 : 0] r_state$D_IN; - wire r_state$EN; - // register r_tdo reg r_tdo; wire r_tdo$D_IN, r_tdo$EN; @@ -179,6 +170,7 @@ module mkJtagTap(CLK, // ports of submodule f_dmi_req wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN; wire f_dmi_req$dCLR, + f_dmi_req$dCLR_RDY, f_dmi_req$dDEQ, f_dmi_req$dEMPTY_N, f_dmi_req$sCLR, @@ -193,18 +185,32 @@ module mkJtagTap(CLK, f_dmi_rsp$dDEQ, f_dmi_rsp$dEMPTY_N, f_dmi_rsp$sCLR, + f_dmi_rsp$sCLR_RDY, f_dmi_rsp$sENQ, f_dmi_rsp$sFULL_N; + // ports of submodule r_dmi + wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT; + wire r_dmi$EN; + + // ports of submodule r_initialize + wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT; + + // ports of submodule r_initialize2 + wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT; + + // ports of submodule r_state + wire [3 : 0] r_state$D_IN, r_state$Q_OUT; + wire r_state$EN; + // ports of submodule rst_tck wire rst_tck$OUT_RST; // ports of submodule tck_clock - wire tck_clock$CLK_IN, - tck_clock$CLK_IN_EN, - tck_clock$CLK_OUT, - tck_clock$COND_IN, - tck_clock$COND_IN_EN; + wire tck_clock$IN, tck_clock$OUT; + + // ports of submodule w_tck_crossed + wire w_tck_crossed$DOUT; // rule scheduling signals wire CAN_FIRE_RL_dmi_request, @@ -215,7 +221,9 @@ module mkJtagTap(CLK, CAN_FIRE_RL_dmi_response_ready, CAN_FIRE_RL_dmi_response_tck, CAN_FIRE_RL_dmi_start, - CAN_FIRE_RL_rl_tck, + CAN_FIRE_RL_mkConnectionVtoAf, + CAN_FIRE_RL_rl_initialize, + CAN_FIRE_RL_rl_initialize2, CAN_FIRE_RL_tick, CAN_FIRE_dmi_req_ready, CAN_FIRE_dmi_rsp_data, @@ -232,7 +240,9 @@ module mkJtagTap(CLK, WILL_FIRE_RL_dmi_response_ready, WILL_FIRE_RL_dmi_response_tck, WILL_FIRE_RL_dmi_start, - WILL_FIRE_RL_rl_tck, + WILL_FIRE_RL_mkConnectionVtoAf, + WILL_FIRE_RL_rl_initialize, + WILL_FIRE_RL_rl_initialize2, WILL_FIRE_RL_tick, WILL_FIRE_dmi_req_ready, WILL_FIRE_dmi_rsp_data, @@ -243,24 +253,24 @@ module mkJtagTap(CLK, WILL_FIRE_jtag_tms; // remaining internal signals - reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, - v__h2135; - reg [17 : 0] newir__h3435; - reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3, - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2; - wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140, - v__h2233, - v__h2601, - x__h2449, - x__h2658, - y__h2659; - wire [17 : 0] v__h3299, x__h3350, y__h3351; - wire r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72; + reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, + v__h2479; + reg [17 : 0] newir__h3774; + reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3, + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2; + wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146, + v__h2576, + v__h2941, + x__h2789, + x__h2996, + y__h2997; + wire [17 : 0] v__h3636, x__h3687, y__h3688; + wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78; // oscillator and gates for output clock CLK_jtag_tclk_out - assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ; + assign CLK_jtag_tclk_out = tck_clock$OUT ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; // action method jtag_tdi @@ -311,7 +321,7 @@ module mkJtagTap(CLK, // submodule f_dmi_busy FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST), - .CLK(tck_clock$CLK_OUT), + .CLK(tck_clock$OUT), .ENQ(f_dmi_busy$ENQ), .DEQ(f_dmi_busy$DEQ), .CLR(f_dmi_busy$CLR), @@ -321,7 +331,7 @@ module mkJtagTap(CLK, // submodule f_dmi_req SyncFIFOLevel #(.dataWidth(32'd41), .depth(32'd2), - .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT), + .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT), .dCLK(CLK), .sRST(rst_tck$OUT_RST), .sD_IN(f_dmi_req$sD_IN), @@ -335,13 +345,13 @@ module mkJtagTap(CLK, .dCOUNT(), .sCOUNT(), .sCLR_RDY(f_dmi_req$sCLR_RDY), - .dCLR_RDY()); + .dCLR_RDY(f_dmi_req$dCLR_RDY)); // submodule f_dmi_rsp SyncFIFOLevel #(.dataWidth(32'd40), .depth(32'd2), .indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK), - .dCLK(tck_clock$CLK_OUT), + .dCLK(tck_clock$OUT), .sRST(RST_N), .sD_IN(f_dmi_rsp$sD_IN), .sENQ(f_dmi_rsp$sENQ), @@ -353,29 +363,46 @@ module mkJtagTap(CLK, .dEMPTY_N(f_dmi_rsp$dEMPTY_N), .dCOUNT(), .sCOUNT(), - .sCLR_RDY(), + .sCLR_RDY(f_dmi_rsp$sCLR_RDY), .dCLR_RDY(f_dmi_rsp$dCLR_RDY)); + // submodule r_dmi + RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT), + .D_IN(r_dmi$D_IN), + .EN(r_dmi$EN), + .Q_OUT(r_dmi$Q_OUT)); + + // submodule r_initialize + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT), + .D_IN(r_initialize$D_IN), + .EN(r_initialize$EN), + .Q_OUT(r_initialize$Q_OUT)); + + // submodule r_initialize2 + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK), + .D_IN(r_initialize2$D_IN), + .EN(r_initialize2$EN), + .Q_OUT(r_initialize2$Q_OUT)); + + // submodule r_state + RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT), + .D_IN(r_state$D_IN), + .EN(r_state$EN), + .Q_OUT(r_state$Q_OUT)); + // submodule rst_tck - SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT), - .IN_RST(RST_N), - .OUT_RST(rst_tck$OUT_RST)); + SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST)); // submodule tck_clock - MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK), - .RST(RST_N), - .CLK_IN(tck_clock$CLK_IN), - .COND_IN(tck_clock$COND_IN), - .CLK_IN_EN(tck_clock$CLK_IN_EN), - .COND_IN_EN(tck_clock$COND_IN_EN), - .CLK_VAL_OUT(), - .COND_OUT(), - .CLK_GATE_OUT(), - .CLK_OUT(tck_clock$CLK_OUT)); + ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT)); - // rule RL_rl_tck - assign CAN_FIRE_RL_rl_tck = 1'd1 ; - assign WILL_FIRE_RL_rl_tck = 1'd1 ; + // submodule w_tck_crossed + SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk), + .DOUT(w_tck_crossed$DOUT)); + + // rule RL_mkConnectionVtoAf + assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; + assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ; // rule RL_tick assign CAN_FIRE_RL_tick = 1'd1 ; @@ -383,7 +410,7 @@ module mkJtagTap(CLK, // rule RL_dmi_start assign CAN_FIRE_RL_dmi_start = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 && f_dmi_req$sFULL_N && f_dmi_busy$FULL_N && w_dmi_req$wget[1:0] != 2'd0 ; @@ -406,9 +433,14 @@ module mkJtagTap(CLK, f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ; assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ; + // rule RL_rl_initialize + assign CAN_FIRE_RL_rl_initialize = + r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ; + // rule RL_dmi_reset assign CAN_FIRE_RL_dmi_reset = - r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 && (!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ; assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ; @@ -420,35 +452,37 @@ module mkJtagTap(CLK, assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ; assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ; + // rule RL_rl_initialize2 + assign CAN_FIRE_RL_rl_initialize2 = + f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ; + // inlined wires assign w_dmi_req$wget = { 1'd0, r_dr } ; - assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ; - assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ; + assign r_tdo$EN_port0__write = + r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ; + assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ; assign r_tdo$port1__read = r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ; assign r_dmistat_busy$port1__read = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 || + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 || r_dmistat_busy ; + assign r_dmistat_busy$EN_port1__write = + WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ; assign r_dmistat_busy$port2__read = - !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ; - - // register r_dmi - assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; - assign r_dmi$EN = - WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 ; + !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ; // register r_dmistat_busy assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ; assign r_dmistat_busy$EN = 1'b1 ; // register r_dr - always@(r_state or r_dr or v__h2135 or v__h2601) + always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941) begin - case (r_state) + case (r_state$Q_OUT) 4'd0: r_dr$D_IN = r_dr; - 4'd3: r_dr$D_IN = v__h2135; - 4'd4: r_dr$D_IN = v__h2601; + 4'd3: r_dr$D_IN = v__h2479; + 4'd4: r_dr$D_IN = v__h2941; default: r_dr$D_IN = r_dr; endcase end @@ -456,22 +490,15 @@ module mkJtagTap(CLK, // register r_drmask assign r_drmask$D_IN = - (r_state == 4'd3) ? - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : + (r_state$Q_OUT == 4'd3) ? + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : r_drmask ; assign r_drmask$EN = 1'd1 ; // register r_ir - assign r_ir$D_IN = newir__h3435 ; + assign r_ir$D_IN = newir__h3774 ; assign r_ir$EN = 1'd1 ; - // register r_state - assign r_state$D_IN = - jtag_tms ? - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 : - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ; - assign r_state$EN = 1'd1 ; - // register r_tdo assign r_tdo$D_IN = r_tdo$port1__read ; assign r_tdo$EN = 1'b1 ; @@ -479,69 +506,89 @@ module mkJtagTap(CLK, // submodule f_dmi_busy assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + assign f_dmi_busy$CLR = + WILL_FIRE_RL_dmi_reset && r_dr[17] || + WILL_FIRE_RL_rl_initialize ; // submodule f_dmi_req assign f_dmi_req$sD_IN = w_dmi_req$wget ; assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ; assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; - assign f_dmi_req$dCLR = 1'b0 ; + assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ; // submodule f_dmi_rsp assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ; assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ; assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_rsp$sCLR = 1'b0 ; + assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ; assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + // submodule r_dmi + assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; + assign r_dmi$EN = + WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 ; + + // submodule r_initialize + assign r_initialize$D_IN = 1'd0 ; + assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ; + + // submodule r_initialize2 + assign r_initialize2$D_IN = 1'd0 ; + assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ; + + // submodule r_state + assign r_state$D_IN = + jtag_tms ? + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 : + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ; + assign r_state$EN = 1'd1 ; + // submodule tck_clock - assign tck_clock$CLK_IN = jtag_tclk ; - assign tck_clock$COND_IN = 1'b0 ; - assign tck_clock$CLK_IN_EN = 1'd1 ; - assign tck_clock$COND_IN_EN = 1'b0 ; + assign tck_clock$IN = w_tck_crossed$DOUT ; // remaining internal signals - assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 = + assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 = (r_dmistat_busy || - r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N) ? 40'hAAAAAAAAAB : - r_dmi ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 = - r_state == 4'd8 && r_ir == 18'b100010100100100100 && + r_dmi$Q_OUT ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b100010100100100100 && (r_dr[17] || r_dr[16]) ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && !f_dmi_busy$EMPTY_N ; - assign v__h2233 = { 22'd960, r_ir } ; - assign v__h2601 = x__h2658 | y__h2659 ; - assign v__h3299 = x__h3350 | y__h3351 ; - assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ; - assign x__h2658 = { 1'd0, r_dr[39:1] } ; - assign x__h3350 = { 1'd0, r_ir[17:1] } ; - assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ; - assign y__h3351 = jtag_tdi ? 18'd131072 : 18'd0 ; - always@(r_state or r_ir or v__h3299) + assign v__h2576 = { 22'd960, r_ir } ; + assign v__h2941 = x__h2996 | y__h2997 ; + assign v__h3636 = x__h3687 | y__h3688 ; + assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ; + assign x__h2996 = { 1'd0, r_dr[39:1] } ; + assign x__h3687 = { 1'd0, r_ir[17:1] } ; + assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ; + assign y__h3688 = jtag_tdi ? 18'd131072 : 18'd0 ; + always@(r_state$Q_OUT or r_ir or v__h3636) begin - case (r_state) - 4'd0: newir__h3435 = 18'd1; - 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir; - 4'd11: newir__h3435 = v__h3299; - default: newir__h3435 = r_ir; + case (r_state$Q_OUT) + 4'd0: newir__h3774 = 18'd1; + 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir; + 4'd11: newir__h3774 = v__h3636; + default: newir__h3774 = r_ir; endcase end always@(r_ir or - v__h2233 or - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 or - x__h2449) + v__h2576 or + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 or + x__h2789) begin case (r_ir) 18'd0, @@ -552,18 +599,18 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - v__h2135 = 40'd0; - 18'd1: v__h2135 = 40'd4093; + v__h2479 = 40'd0; + 18'd1: v__h2479 = 40'd4093; 18'b000011100100100100: - v__h2135 = - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140; - 18'b100010100100100100: v__h2135 = x__h2449; - default: v__h2135 = v__h2233; + v__h2479 = + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146; + 18'b100010100100100100: v__h2479 = x__h2789; + default: v__h2479 = v__h2576; endcase end - always@(newir__h3435) + always@(newir__h3774) begin - case (newir__h3435) + case (newir__h3774) 18'd0, 18'h00012, 18'h00013, @@ -572,71 +619,67 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; 18'd1, 18'b100010100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0080000000; 18'b000011100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h8000000000; - default: CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + default: CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0100000000; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) - 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state; + case (r_state$Q_OUT) + 4'd0: + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = + r_state$Q_OUT; 4'd1, 4'd8, 4'd15: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2; - 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9; - 4'd3, 4'd4: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5; - 4'd5, 4'd7: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8; - 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7; - 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2; + 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9; + 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5; + 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8; + 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7; + 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0; 4'd10, 4'd11: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12; 4'd12, 4'd14: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15; - 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15; + 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) + case (r_state$Q_OUT) 4'd0, 4'd1, 4'd8, 4'd15: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1; - 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1; + 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3; 4'd3, 4'd4, 4'd7: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4; 4'd5, 4'd6: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6; - 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6; + 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10; 4'd10, 4'd11, 4'd14: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11; 4'd12, 4'd13: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13; endcase end // handling of inlined registers - always@(posedge tck_clock$CLK_OUT) + always@(posedge tck_clock$OUT) begin if (rst_tck$OUT_RST == `BSV_RESET_VALUE) begin - r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0; - r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - r_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN; - if (r_dmistat_busy$EN) + if (r_dmistat_busy$EN) r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN; - if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN; end if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN; if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN; @@ -649,12 +692,10 @@ module mkJtagTap(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - r_dmi = 40'hAAAAAAAAAA; r_dmistat_busy = 1'h0; r_dr = 40'hAAAAAAAAAA; r_drmask = 40'hAAAAAAAAAA; r_ir = 18'h2AAAA; - r_state = 4'hA; r_tdo = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS @@ -663,11 +704,11 @@ module mkJtagTap(CLK, // handling of system tasks // synopsys translate_off - always@(negedge tck_clock$CLK_OUT) + always@(negedge tck_clock$OUT) begin #0; if (rst_tck$OUT_RST != `BSV_RESET_VALUE) - if (r_state == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && + if (r_state$Q_OUT == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && r_ir != 18'h00013 && r_ir != 18'h00014 && r_ir != 18'h00015 && diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index b1f7022..53c9fed 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -648,14 +648,19 @@ module mkP3_Core(CLK, wire bus_dmi_rsp_fifof_q_1$EN; // register rg_corew_start_after_por - reg rg_corew_start_after_por; - wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + reg [7 : 0] rg_corew_start_after_por; + wire [7 : 0] rg_corew_start_after_por$D_IN; + wire rg_corew_start_after_por$EN; // register rg_ndm_reset_delay reg [7 : 0] rg_ndm_reset_delay; wire [7 : 0] rg_ndm_reset_delay$D_IN; wire rg_ndm_reset_delay$EN; + // register rg_running + reg rg_running; + wire rg_running$D_IN, rg_running$EN; + // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; wire bus_dmi_req_fifof$CLR, @@ -781,8 +786,10 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, + corew$ndm_reset_client_request_get, corew$ndm_reset_client_response_put, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -804,6 +811,9 @@ module mkP3_Core(CLK, // ports of submodule ndm_reset_controller wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule por_ifc + wire por_ifc$RST_N_gen_rst; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -910,15 +920,15 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1279; - reg [31 : 0] v__h1424; - reg [31 : 0] v__h1273; - reg [31 : 0] v__h1418; + reg [31 : 0] v__h1362; + reg [31 : 0] v__h1510; + reg [31 : 0] v__h1356; + reg [31 : 0] v__h1504; // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; - wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49; + wire IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99, _dfoo1, _dfoo3; @@ -1188,7 +1198,7 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(por_ifc$RST_N_gen_rst), .CLK(CLK), .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), @@ -1237,6 +1247,7 @@ module mkP3_Core(CLK, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1308,7 +1319,7 @@ module mkP3_Core(CLK, .dmi_read_data(corew$dmi_read_data), .RDY_dmi_read_data(corew$RDY_dmi_read_data), .RDY_dmi_write(corew$RDY_dmi_write), - .ndm_reset_client_request_get(), + .ndm_reset_client_request_get(corew$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), @@ -1316,7 +1327,7 @@ module mkP3_Core(CLK, // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), - .RST_N(RST_N), + .RST_N(por_ifc$RST_N_gen_rst), .dmi_req_ready(jtagtap$dmi_req_ready), .dmi_rsp_data(jtagtap$dmi_rsp_data), .dmi_rsp_response(jtagtap$dmi_rsp_response), @@ -1334,7 +1345,7 @@ module mkP3_Core(CLK, .CLK_GATE_jtag_tclk_out()); // submodule ndm_reset - ResetEither ndm_reset(.A_RST(RST_N), + ResetEither ndm_reset(.A_RST(por_ifc$RST_N_gen_rst), .B_RST(ndm_reset_controller$OUT_RST), .RST_OUT(ndm_reset$RST_OUT)); @@ -1346,6 +1357,11 @@ module mkP3_Core(CLK, .ASSERT_OUT(), .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule por_ifc + mkPowerOnReset por_ifc(.CLK(CLK), + .RST_N(RST_N), + .RST_N_gen_rst(por_ifc$RST_N_gen_rst)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1371,7 +1387,8 @@ module mkP3_Core(CLK, // rule RL_rl_step_0 assign CAN_FIRE_RL_rl_step_0 = - corew$RDY_start && !rg_corew_start_after_por ; + (rg_corew_start_after_por != 8'd1 || corew$RDY_start) && + rg_corew_start_after_por != 8'd0 ; assign WILL_FIRE_RL_rl_step_0 = CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; @@ -1422,7 +1439,7 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; + IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu @@ -1434,7 +1451,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; @@ -1526,7 +1543,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1585,7 +1602,7 @@ module mkP3_Core(CLK, WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register rg_corew_start_after_por - assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$D_IN = rg_corew_start_after_por - 8'd1 ; assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; // register rg_ndm_reset_delay @@ -1596,6 +1613,10 @@ module mkP3_Core(CLK, assign rg_ndm_reset_delay$EN = WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; + // register rg_running + assign rg_running$D_IN = corew$ndm_reset_client_request_get ; + assign rg_running$EN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; assign bus_dmi_req_fifof$ENQ = CAN_FIRE_RL_bus_dmi_req_do_enq ; @@ -1660,16 +1681,17 @@ module mkP3_Core(CLK, assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$ndm_reset_client_response_put = rg_running ; assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_is_running = !MUX_corew$start_1__SEL_1 || rg_running ; assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || - WILL_FIRE_RL_rl_step_0 ; + WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1699,7 +1721,7 @@ module mkP3_Core(CLK, assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = + assign IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || @@ -1708,11 +1730,11 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1724,7 +1746,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 8'd100; rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else @@ -1744,6 +1766,7 @@ module mkP3_Core(CLK, if (rg_ndm_reset_delay$EN) rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end + if (rg_running$EN) rg_running <= `BSV_ASSIGNMENT_DELAY rg_running$D_IN; end // synopsys translate_off @@ -1754,8 +1777,9 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_corew_start_after_por = 1'h0; + rg_corew_start_after_por = 8'hAA; rg_ndm_reset_delay = 8'hAA; + rg_running = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1767,30 +1791,34 @@ module mkP3_Core(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - begin - v__h1279 = $stime; - #0; - end - v__h1273 = v__h1279 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1273, - $signed(32'd10)); - if (RST_N != `BSV_RESET_VALUE) - if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1424 = $stime; + v__h1362 = $stime; #0; end - v__h1418 = v__h1424 / 32'd10; + v__h1356 = v__h1362 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1356, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) - $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1418); + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1510 = $stime; + #0; + end + v__h1504 = v__h1510 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1504); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v new file mode 100644 index 0000000..65d7430 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v @@ -0,0 +1,92 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// +// +// +// Ports: +// Name I/O size props +// RST_N_gen_rst O 1 reset +// CLK I 1 clock +// RST_N I 1 unused +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkPowerOnReset(CLK, + RST_N, + + RST_N_gen_rst); + input CLK; + input RST_N; + + // output resets + output RST_N_gen_rst; + + // signals for module outputs + wire RST_N_gen_rst; + + // ports of submodule ctr + wire [7 : 0] ctr$D_IN, ctr$Q_OUT; + wire ctr$EN; + + // ports of submodule isInPowerOnReset + wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT; + + // ports of submodule rst_ifc + wire rst_ifc$OUT; + + // rule scheduling signals + wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown; + + // remaining internal signals + wire NOT_isInPowerOnReset__read___d5; + + // output resets + assign RST_N_gen_rst = rst_ifc$OUT ; + + // submodule ctr + RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK), + .D_IN(ctr$D_IN), + .EN(ctr$EN), + .Q_OUT(ctr$Q_OUT)); + + // submodule isInPowerOnReset + RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK), + .D_IN(isInPowerOnReset$D_IN), + .EN(isInPowerOnReset$EN), + .Q_OUT(isInPowerOnReset$Q_OUT)); + + // submodule rst_ifc + ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT)); + + // rule RL_countDown + assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + + // submodule ctr + assign ctr$D_IN = ctr$Q_OUT - 8'd1 ; + assign ctr$EN = isInPowerOnReset$Q_OUT ; + + // submodule isInPowerOnReset + assign isInPowerOnReset$D_IN = 1'd0 ; + assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ; + + // remaining internal signals + assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ; +endmodule // mkPowerOnReset + diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index dcc8699..0888d5b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -94,6 +94,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -192,6 +193,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -454,6 +456,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1421,6 +1424,7 @@ module mkProc(CLK, core_0$EN_v_to_TV_0_get, core_0$EN_v_to_TV_1_get, core_0$RDY_coreIndInv_terminate, + core_0$RDY_coreReq_start, core_0$RDY_dCacheToParent_fromP_enq, core_0$RDY_dCacheToParent_rqToP_deq, core_0$RDY_dCacheToParent_rqToP_first, @@ -1461,6 +1465,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_respLd_enq, core_0$RDY_v_to_TV_0_get, core_0$RDY_v_to_TV_1_get, + core_0$coreReq_start_running, core_0$hart0_run_halt_server_request_put, core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, @@ -2104,60 +2109,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162844; - reg [31 : 0] v__h162380; - reg [31 : 0] v__h5520; - reg [31 : 0] v__h5693; - reg [31 : 0] v__h5953; - reg [31 : 0] v__h8095; - reg [31 : 0] v__h8310; - reg [31 : 0] v__h2670; - reg [31 : 0] v__h4343; - reg [31 : 0] v__h9480; - reg [31 : 0] v__h9973; - reg [31 : 0] v__h10136; - reg [31 : 0] v__h134337; - reg [31 : 0] v__h134504; - reg [31 : 0] v__h136607; - reg [31 : 0] v__h153951; - reg [31 : 0] v__h133718; - reg [31 : 0] v__h160645; - reg [31 : 0] v__h161153; - reg [31 : 0] v__h2664; - reg [31 : 0] v__h4337; - reg [31 : 0] v__h5514; - reg [31 : 0] v__h5687; - reg [31 : 0] v__h5947; - reg [31 : 0] v__h8089; - reg [31 : 0] v__h8304; - reg [31 : 0] v__h9474; - reg [31 : 0] v__h9967; - reg [31 : 0] v__h10130; - reg [31 : 0] v__h133712; - reg [31 : 0] v__h134331; - reg [31 : 0] v__h134498; - reg [31 : 0] v__h136601; - reg [31 : 0] v__h153945; - reg [31 : 0] v__h160639; - reg [31 : 0] v__h161147; - reg [31 : 0] v__h162374; - reg [31 : 0] v__h162838; + reg [31 : 0] v__h162856; + reg [31 : 0] v__h162388; + reg [31 : 0] v__h5528; + reg [31 : 0] v__h5701; + reg [31 : 0] v__h5961; + reg [31 : 0] v__h8103; + reg [31 : 0] v__h8318; + reg [31 : 0] v__h2678; + reg [31 : 0] v__h4351; + reg [31 : 0] v__h9488; + reg [31 : 0] v__h9981; + reg [31 : 0] v__h10144; + reg [31 : 0] v__h134345; + reg [31 : 0] v__h134512; + reg [31 : 0] v__h136615; + reg [31 : 0] v__h153959; + reg [31 : 0] v__h133726; + reg [31 : 0] v__h160653; + reg [31 : 0] v__h161161; + reg [31 : 0] v__h2672; + reg [31 : 0] v__h4345; + reg [31 : 0] v__h5522; + reg [31 : 0] v__h5695; + reg [31 : 0] v__h5955; + reg [31 : 0] v__h8097; + reg [31 : 0] v__h8312; + reg [31 : 0] v__h9482; + reg [31 : 0] v__h9975; + reg [31 : 0] v__h10138; + reg [31 : 0] v__h133720; + reg [31 : 0] v__h134339; + reg [31 : 0] v__h134506; + reg [31 : 0] v__h136609; + reg [31 : 0] v__h153953; + reg [31 : 0] v__h160647; + reg [31 : 0] v__h161155; + reg [31 : 0] v__h162382; + reg [31 : 0] v__h162850; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, @@ -2167,44 +2172,44 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, - data64__h147777, - dword__h93782, - ld_data__h131939, - old_dword__h89472, - w1__h47861, - w1__h47866, - w2__h47862, - w2__h47868, - x__h47857; + data64__h147785, + dword__h93790, + ld_data__h131947, + old_dword__h89480, + w1__h47869, + w1__h47874, + w2__h47870, + w2__h47876, + x__h47865; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147778; + reg [7 : 0] strb8__h147786; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61575; + reg [2 : 0] x__h61583; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, - x__h61582, - x__h82300; + x__h61590, + x__h82308; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - new_cline__h134640; + new_cline__h134648; wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, @@ -2225,89 +2230,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - data__h31950, - failed_testnum__h162423, - line_addr__h101846, - line_addr__h101932, - mask__h89469, - mem_req_rd_addr_araddr__h133938, - mem_req_wr_addr_awaddr__h147862, - mmioPlatform_fromHostQ_data_0__h42651, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48453, - n__read_addr__h61443, - n__read_addr__h61528, - n__read_addr__h80062, - n__read_addr__h80141, - n__read_snd_addr__h123373, - newData__h32031, - newData__h34961, - new_dword__h89473, - op_result__h48469, - op_result__h48999, - op_result__h49004, - op_result__h49009, - op_result__h49014, - op_result__h49020, - op_result__h49027, - op_result__h49033, - result__h47912, - result__h48036, - result__h48064, - result__h48092, - result__h48120, - result__h48148, - result__h48176, - result__h48204, - result__h48232, - result__h48277, - result__h48305, - result__h48333, - result__h48361, - result__h48402, - result__h48430, - result__h48556, - result__h48583, - result__h48610, - result__h48637, - result__h48664, - result__h48691, - result__h48718, - result__h48745, - result__h48789, - result__h48816, - result__h48843, - result__h48870, - result__h48910, - result__h48937, - result__h49054, - result__h49120, - result__h49186, - result__h49252, - result__h49318, - result__h49384, - result__h49450, - result__h49512, - result__h49557, - result__h49623, - result__h49689, - result__h49747, - result__h49792, - w1___1__h47971, - w2___1__h47972, - x1_avValue_data__h40323, - x1_avValue_data__h44790, - x__h32142, - x__h35052, - x__h37412, - x__h40841, - x__h40852, - x__h42861, - x__h42872, - x__h49969, - x__h90635, - y__h90636, - y__h90637; + data__h31958, + failed_testnum__h162431, + line_addr__h101854, + line_addr__h101940, + mask__h89477, + mem_req_rd_addr_araddr__h133946, + mem_req_wr_addr_awaddr__h147870, + mmioPlatform_fromHostQ_data_0__h42659, + mmioPlatform_mtime__h37272, + mmioPlatform_reqData__h48461, + n__read_addr__h61451, + n__read_addr__h61536, + n__read_addr__h80070, + n__read_addr__h80149, + n__read_snd_addr__h123381, + newData__h32039, + newData__h34969, + new_dword__h89481, + op_result__h48477, + op_result__h49007, + op_result__h49012, + op_result__h49017, + op_result__h49022, + op_result__h49028, + op_result__h49035, + op_result__h49041, + result__h47920, + result__h48044, + result__h48072, + result__h48100, + result__h48128, + result__h48156, + result__h48184, + result__h48212, + result__h48240, + result__h48285, + result__h48313, + result__h48341, + result__h48369, + result__h48410, + result__h48438, + result__h48564, + result__h48591, + result__h48618, + result__h48645, + result__h48672, + result__h48699, + result__h48726, + result__h48753, + result__h48797, + result__h48824, + result__h48851, + result__h48878, + result__h48918, + result__h48945, + result__h49062, + result__h49128, + result__h49194, + result__h49260, + result__h49326, + result__h49392, + result__h49458, + result__h49520, + result__h49565, + result__h49631, + result__h49697, + result__h49755, + result__h49800, + w1___1__h47979, + w2___1__h47980, + x1_avValue_data__h40331, + x1_avValue_data__h44798, + x__h32150, + x__h35060, + x__h37420, + x__h40849, + x__h40860, + x__h42869, + x__h42880, + x__h49977, + x__h90643, + y__h90644, + y__h90645; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; @@ -2319,16 +2324,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w17861_BITS_31_TO_0__q15, - w27862_BITS_31_TO_0__q16, - x_data__h30533; + v__h31751, + v__h31788, + w17869_BITS_31_TO_0__q15, + w27870_BITS_31_TO_0__q16, + x_data__h30541; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; - wire [5 : 0] x__h133973, x__h147887; + wire [5 : 0] x__h133981, x__h147895; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; - wire [3 : 0] b__h133645, b__h2564; - wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; + wire [3 : 0] b__h133653, b__h2572; + wire [2 : 0] n__read_id__h61455, n__read_id__h61540, x__h7933; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, @@ -2390,27 +2395,28 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqBE_BIT_0___h30166, + mmioPlatform_reqBE_BIT_4___h30126, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61448, - n__read_child__h61533, - n__read_child__h80065, - n__read_child__h80144, - n__read_snd_id__h123374, + n__read_child__h61456, + n__read_child__h61541, + n__read_child__h80073, + n__read_child__h80152, + n__read_snd_id__h123382, propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, - x__h61261, - x__h74813, - x__h79884; + x__h61269, + x__h74821, + x__h79892; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; - assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; + assign CAN_FIRE_start = + mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; assign WILL_FIRE_start = EN_start ; // value method master0_m_awvalid @@ -2845,6 +2851,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -2901,7 +2908,7 @@ module mkProc(CLK, .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), .EN_v_to_TV_0_get(core_0$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(core_0$EN_v_to_TV_1_get), - .RDY_coreReq_start(), + .RDY_coreReq_start(core_0$RDY_coreReq_start), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), .RDY_coreIndInv_perfResp(), @@ -3676,14 +3683,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2564 == 4'd0 ; + b__h2572 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2564 != 4'd0 && + b__h2572 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3796,7 +3803,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42861 == 64'd0 || + x__h42869 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -4116,13 +4123,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133645 == 4'd0 ; + b__h133653 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133645 != 4'd0 && + b__h133653 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4226,7 +4233,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30541 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -4266,7 +4273,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31958 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -4291,10 +4298,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101846, + { line_addr__h101854, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101932, + { line_addr__h101940, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4305,11 +4312,11 @@ module mkProc(CLK, { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4408,7 +4415,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47857 } ; + x__h47865 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4417,7 +4424,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49977, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4432,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42869 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42861 != 64'd0 ; + x__h42869 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40841 == 64'd0 ; + x__h40849 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - x__h61261 ; + x__h61269 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - x__h79884 ; + x__h79892 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; + { 1'd1, n__read_snd_addr__h123381, n__read_snd_id__h123382 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4526,11 +4533,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2564 - 4'd1 ; + b__h2572 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2564 ; + b__h2572 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4579,11 +4586,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133645 - 4'd1 ; + b__h133653 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133645 ; + b__h133653 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4646,7 +4653,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133946, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4664,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147870, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147777, strb8__h147778, 1'd1 } ; + { data64__h147785, strb8__h147786, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4682,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134648 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4730,8 +4737,8 @@ module mkProc(CLK, // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101846 : - line_addr__h101932 ; + line_addr__h101854 : + line_addr__h101940 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4892,7 +4899,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34969 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4908,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32039 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5118,7 +5125,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7925, + x__h7933, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -5218,6 +5225,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -5321,7 +5329,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131939, llc$dma_respLd_first[3] } ; + { ld_data__h131947, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5475,7 +5483,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134640, + { new_cline__h134648, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5559,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93782, 3'd1 } ; + { 4'd0, dword__h93790, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5854,47 +5862,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37420), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h32150)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37272), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h35060)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40852)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42659), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h40860)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h42872)); + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h42880)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40323 } } ; + x1_avValue_data__h40331 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5910,7 +5918,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; + newData__h32039 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5975,7 +5983,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - x__h74813 } ; + x__h74821 } ; assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5987,29 +5995,29 @@ module mkProc(CLK, assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? @@ -6154,11 +6162,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42861 == 64'd0 : - x__h40841 == 64'd0, + x__h42869 == 64'd0 : + x__h40849 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44790 } ; + x1_avValue_data__h44798 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6392,58 +6400,58 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = - { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + { CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = - { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + { CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - x__h82300 } ; + x__h82308 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = - { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + { CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = - { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - x__h61575, - x__h61582 } ; - assign b__h133645 = + { CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + x__h61583, + x__h61590 } ; + assign b__h133653 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2564 = + assign b__h2572 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31958 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h162423 = + { v__h31751, 32'd0 } ; + assign failed_testnum__h162431 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101846 = + assign line_addr__h101854 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101932 = + assign line_addr__h101940 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = - line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; + line_addr__h101940 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = - line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89469 = + line_addr__h101854 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89477 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6476,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133938 = - { llc$to_mem_toM_first[68:11], x__h133973 } ; - assign mem_req_wr_addr_awaddr__h147862 = - { llc$to_mem_toM_first[639:582], x__h147887 } ; + assign mem_req_rd_addr_araddr__h133946 = + { llc$to_mem_toM_first[68:11], x__h133981 } ; + assign mem_req_wr_addr_awaddr__h147870 = + { llc$to_mem_toM_first[639:582], x__h147895 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42651 = + assign mmioPlatform_fromHostQ_data_0__h42659 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,18 +6494,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37272 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + mmioPlatform_mtimecmp_0 <= newData__h34969 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30166 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30126 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48461 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6529,105 +6537,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61443 = + assign n__read_addr__h61451 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61528 = + assign n__read_addr__h61536 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80062 = + assign n__read_addr__h80070 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : 64'd0 ; - assign n__read_addr__h80141 = + assign n__read_addr__h80149 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : 64'd0 ; - assign n__read_child__h61448 = + assign n__read_child__h61456 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61533 = + assign n__read_child__h61541 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80065 = + assign n__read_child__h80073 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; - assign n__read_child__h80144 = + assign n__read_child__h80152 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; - assign n__read_id__h61447 = + assign n__read_id__h61455 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61532 = + assign n__read_id__h61540 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123373 = + assign n__read_snd_addr__h123381 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123374 = + assign n__read_snd_id__h123382 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32039 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : + x__h32150 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + assign newData__h34969 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : + x__h35060 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h134640 = + assign new_cline__h134648 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89473 = x__h90635 | y__h90636 ; - assign op_result__h48469 = + assign new_dword__h89481 = x__h90643 | y__h90644 ; + assign op_result__h48477 = IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; - assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; - assign op_result__h49004 = w1__h47866 & w2__h47868 ; - assign op_result__h49009 = w1__h47866 | w2__h47868 ; - assign op_result__h49014 = - (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; - assign op_result__h49020 = - (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; - assign op_result__h49027 = + assign op_result__h49007 = w1__h47874 ^ w2__h47876 ; + assign op_result__h49012 = w1__h47874 & w2__h47876 ; + assign op_result__h49017 = w1__h47874 | w2__h47876 ; + assign op_result__h49022 = + (w1__h47874 < w2__h47876) ? w1__h47874 : w2__h47876 ; + assign op_result__h49028 = + (w1__h47874 <= w2__h47876) ? w2__h47876 : w1__h47874 ; + assign op_result__h49035 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w1__h47866 : - w2__h47868 ; - assign op_result__h49033 = + w1__h47874 : + w2__h47876 ; + assign op_result__h49041 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w2__h47868 : - w1__h47866 ; + w2__h47876 : + w1__h47874 ; assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6638,126 +6646,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47912 = + assign result__h47920 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; - assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48556 = + assign result__h48044 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48072 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48100 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48128 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48156 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48184 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48212 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48240 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48285 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48313 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48341 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48369 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48410 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48438 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48564 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48583 = + assign result__h48591 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48610 = + assign result__h48618 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48637 = + assign result__h48645 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48664 = + assign result__h48672 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48691 = + assign result__h48699 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48718 = + assign result__h48726 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48745 = + assign result__h48753 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48789 = + assign result__h48797 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48816 = + assign result__h48824 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48843 = + assign result__h48851 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48870 = + assign result__h48878 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48910 = + assign result__h48918 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48937 = + assign result__h48945 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49054 = + assign result__h49062 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49120 = + assign result__h49128 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49186 = + assign result__h49194 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49252 = + assign result__h49260 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49318 = + assign result__h49326 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49384 = + assign result__h49392 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49450 = + assign result__h49458 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49512 = + assign result__h49520 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; - assign result__h49557 = + assign result__h49565 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49623 = + assign result__h49631 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49689 = + assign result__h49697 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49747 = + assign result__h49755 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; - assign result__h49792 = + assign result__h49800 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; - assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; - assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; - assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; - assign x1_avValue_data__h40323 = + assign v__h31751 = mmioPlatform_waitUpperMSIPCRs ? v__h31788 : 32'd0 ; + assign v__h31788 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17869_BITS_31_TO_0__q15 = w1__h47869[31:0] ; + assign w1___1__h47979 = { 32'd0, w1__h47869[31:0] } ; + assign w27870_BITS_31_TO_0__q16 = w2__h47870[31:0] ; + assign w2___1__h47980 = { 32'd0, w2__h47870[31:0] } ; + assign x1_avValue_data__h40331 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44790 = + assign x1_avValue_data__h44798 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40841 = + assign x__h133981 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147895 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37420 = mmioPlatform_mtimecmp_0 ; + assign x__h40849 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40852 : + x__h40860 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; - assign x__h42861 = + assign x__h42869 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42872 : + x__h42880 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6774,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61261 = + assign x__h49977 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61269 = SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; - assign x__h74813 = + assign x__h74821 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; - assign x__h7925 = + assign x__h7933 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79884 = + assign x__h79892 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; - assign x__h90635 = old_dword__h89472 & y__h90637 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90636 = + assign x__h90643 = old_dword__h89480 & y__h90645 ; + assign x_data__h30541 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90644 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89469 ; - assign y__h90637 = + mask__h89477 ; + assign y__h90645 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,141 +7009,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h147785 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147785 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147785 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147785 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147785 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147785 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147785 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147785 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131947 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131947 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131947 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131947 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131947 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131947 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131947 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131947 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147786 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147786 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147786 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147786 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147786 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147786 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147786 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147786 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48036 or - result__h48064 or - result__h48092 or - result__h48120 or - result__h48148 or - result__h48176 or result__h48204 or result__h48232) + result__h48044 or + result__h48072 or + result__h48100 or + result__h48128 or + result__h48156 or + result__h48184 or result__h48212 or result__h48240) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48036; + result__h48044; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48064; + result__h48072; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48092; + result__h48100; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48120; + result__h48128; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48148; + result__h48156; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48176; + result__h48184; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48204; + result__h48212; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48232; + result__h48240; endcase end always@(mmioPlatform_curReq or - result__h48277 or - result__h48305 or result__h48333 or result__h48361) + result__h48285 or + result__h48313 or result__h48341 or result__h48369) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48277; + result__h48285; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48305; + result__h48313; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48333; + result__h48341; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48361; + result__h48369; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48402 or result__h48430) + always@(mmioPlatform_curReq or result__h48410 or result__h48438) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48402; + result__h48410; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48430; + result__h48438; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase @@ -7148,103 +7156,103 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - w2__h47862 = + w2__h47870 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w2___1__h47972 or + w2___1__h47980 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; - 2'b10: w2__h47868 = w2___1__h47972; + 2'b10: w2__h47876 = w2___1__h47980; 2'b11: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_curReq or - result__h48556 or - result__h48583 or - result__h48610 or - result__h48637 or - result__h48664 or - result__h48691 or result__h48718 or result__h48745) + result__h48564 or + result__h48591 or + result__h48618 or + result__h48645 or + result__h48672 or + result__h48699 or result__h48726 or result__h48753) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48556; + result__h48564; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48583; + result__h48591; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48610; + result__h48618; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48637; + result__h48645; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48664; + result__h48672; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48691; + result__h48699; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48718; + result__h48726; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48745; + result__h48753; endcase end always@(mmioPlatform_curReq or - result__h48789 or - result__h48816 or result__h48843 or result__h48870) + result__h48797 or + result__h48824 or result__h48851 or result__h48878) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48789; + result__h48797; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48816; + result__h48824; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48843; + result__h48851; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48870; + result__h48878; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48910 or result__h48937) + always@(mmioPlatform_curReq or result__h48918 or result__h48945) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48910; + result__h48918; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48937; + result__h48945; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase @@ -7257,42 +7265,42 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - w1__h47861 = + w1__h47869 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w1___1__h47971 or + w1___1__h47979 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; - 2'b10: w1__h47866 = w1___1__h47971; + 2'b10: w1__h47874 = w1___1__h47979; 2'b11: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w17861_BITS_31_TO_0__q15 or + w17869_BITS_31_TO_0__q15 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) @@ -7304,8 +7312,8 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - { {32{w17861_BITS_31_TO_0__q15[31]}}, - w17861_BITS_31_TO_0__q15 }; + { {32{w17869_BITS_31_TO_0__q15[31]}}, + w17869_BITS_31_TO_0__q15 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; @@ -7314,7 +7322,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w27862_BITS_31_TO_0__q16 or + w27870_BITS_31_TO_0__q16 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) @@ -7326,116 +7334,116 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - { {32{w27862_BITS_31_TO_0__q16[31]}}, - w27862_BITS_31_TO_0__q16 }; + { {32{w27870_BITS_31_TO_0__q16[31]}}, + w27870_BITS_31_TO_0__q16 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49033 or - w2__h47868 or - op_result__h48469 or - op_result__h48999 or - op_result__h49004 or - op_result__h49009 or - op_result__h49027 or op_result__h49014 or op_result__h49020) + op_result__h49041 or + w2__h47876 or + op_result__h48477 or + op_result__h49007 or + op_result__h49012 or + op_result__h49017 or + op_result__h49035 or op_result__h49022 or op_result__h49028) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - w2__h47868; + w2__h47876; 4'd1: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48469; + op_result__h48477; 4'd2: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48999; + op_result__h49007; 4'd3: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49004; + op_result__h49012; 4'd4: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49009; + op_result__h49017; 4'd5: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49027; + op_result__h49035; 4'd7: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49014; + op_result__h49022; 4'd8: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49020; + op_result__h49028; default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49033; + op_result__h49041; endcase end always@(mmioPlatform_curReq or - result__h49512 or - result__h49557 or result__h49623 or result__h49689) + result__h49520 or + result__h49565 or result__h49631 or result__h49697) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49512; + result__h49520; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49557; + result__h49565; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49623; + result__h49631; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49689; + result__h49697; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47912 or - result__h49054 or - result__h49120 or - result__h49186 or - result__h49252 or - result__h49318 or result__h49384 or result__h49450) + result__h47920 or + result__h49062 or + result__h49128 or + result__h49194 or + result__h49260 or + result__h49326 or result__h49392 or result__h49458) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h47912; + result__h47920; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49054; + result__h49062; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49120; + result__h49128; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49186; + result__h49194; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49252; + result__h49260; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49318; + result__h49326; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49384; + result__h49392; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49450; + result__h49458; endcase end - always@(mmioPlatform_curReq or result__h49747 or result__h49792) + always@(mmioPlatform_curReq or result__h49755 or result__h49800) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49747; + result__h49755; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49792; + result__h49800; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase @@ -7448,15 +7456,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; 2'b01: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; 2'b10: - x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47865 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end @@ -7540,278 +7548,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; endcase end - always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) + always@(x__h61269 or n__read_id__h61455 or n__read_id__h61540) begin - case (x__h61261) - 1'd0: x__h61575 = n__read_id__h61447; - 1'd1: x__h61575 = n__read_id__h61532; + case (x__h61269) + 1'd0: x__h61583 = n__read_id__h61455; + 1'd1: x__h61583 = n__read_id__h61540; endcase end - always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) + always@(x__h61269 or n__read_child__h61456 or n__read_child__h61541) begin - case (x__h61261) - 1'd0: x__h61582 = n__read_child__h61448; - 1'd1: x__h61582 = n__read_child__h61533; + case (x__h61269) + 1'd0: x__h61590 = n__read_child__h61456; + 1'd1: x__h61590 = n__read_child__h61541; endcase end - always@(x__h61261 or + always@(x__h61269 or propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; 1'd1: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; endcase end - always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) + always@(x__h61269 or n__read_addr__h61451 or n__read_addr__h61536) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61443; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61451; 1'd1: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61528; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61536; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) + always@(x__h79892 or n__read_child__h80073 or n__read_child__h80152) begin - case (x__h79884) - 1'd0: x__h82300 = n__read_child__h80065; - 1'd1: x__h82300 = n__read_child__h80144; + case (x__h79892) + 1'd0: x__h82308 = n__read_child__h80073; + 1'd1: x__h82308 = n__read_child__h80152; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79884 or + always@(x__h79892 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : 2'd0; 1'd1: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : 2'd0; endcase end - always@(x__h79884 or + always@(x__h79892 or NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; 1'd1: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; endcase end - always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) + always@(x__h79892 or n__read_addr__h80070 or n__read_addr__h80149) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80062; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80070; 1'd1: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80141; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80149; endcase end @@ -8227,14 +8235,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162844 = $stime; + v__h162856 = $stime; #0; end - v__h162838 = v__h162844 / 32'd10; + v__h162850 = v__h162856 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162838, + v__h162850, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8244,14 +8252,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162380 = $stime; + v__h162388 = $stime; #0; end - v__h162374 = v__h162380 / 32'd10; + v__h162382 = v__h162388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162374, + v__h162382, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8261,7 +8269,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162423); + $display("FAIL %0d", failed_testnum__h162431); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8269,14 +8277,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5520 = $stime; + v__h5528 = $stime; #0; end - v__h5514 = v__h5520 / 32'd10; + v__h5522 = v__h5528 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5514); + $display("%0d: %m.rl_handle_read_rsps ", v__h5522); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8336,16 +8344,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5693 = $stime; + v__h5701 = $stime; #0; end - v__h5687 = v__h5693 / 32'd10; + v__h5695 = v__h5701 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5687); + v__h5695); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8449,14 +8457,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5953 = $stime; + v__h5961 = $stime; #0; end - v__h5947 = v__h5953 / 32'd10; + v__h5955 = v__h5961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5947); + $display("%d: %m.rl_handle_write_req: St request:", v__h5955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8626,15 +8634,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h8095 = $stime; + v__h8103 = $stime; #0; end - v__h8089 = v__h8095 / 32'd10; + v__h8097 = v__h8103 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h8089); + $display("%0d: ERROR: CreditCounter: overflow", v__h8097); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8684,7 +8692,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7925); + $write("'h%h", x__h7933); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8815,16 +8823,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8310 = $stime; + v__h8318 = $stime; #0; end - v__h8304 = v__h8310 / 32'd10; + v__h8312 = v__h8318 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8304); + v__h8312); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9030,14 +9038,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2670 = $stime; + v__h2678 = $stime; #0; end - v__h2664 = v__h2670 / 32'd10; + v__h2672 = v__h2678 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2664); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2672); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9327,16 +9335,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4343 = $stime; + v__h4351 = $stime; #0; end - v__h4337 = v__h4343 / 32'd10; + v__h4345 = v__h4351 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4337); + v__h4345); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9542,14 +9550,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9480 = $stime; + v__h9488 = $stime; #0; end - v__h9474 = v__h9480 / 32'd10; + v__h9482 = v__h9488 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9474); + $display("%0d: %m.rl_discard_write_rsp", v__h9482); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9586,15 +9594,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9973 = $stime; + v__h9981 = $stime; #0; end - v__h9967 = v__h9973 / 32'd10; + v__h9975 = v__h9981 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9967); + v__h9975); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9634,14 +9642,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h10136 = $stime; + v__h10144 = $stime; #0; end - v__h10130 = v__h10136 / 32'd10; + v__h10138 = v__h10144 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h10130); + v__h10138); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9828,15 +9836,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h134337 = $stime; + v__h134345 = $stime; #0; end - v__h134331 = v__h134337 / 32'd10; + v__h134339 = v__h134345 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134331, + v__h134339, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9896,15 +9904,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134504 = $stime; + v__h134512 = $stime; #0; end - v__h134498 = v__h134504 / 32'd10; + v__h134506 = v__h134512 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134498); + v__h134506); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10085,16 +10093,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136607 = $stime; + v__h136615 = $stime; #0; end - v__h136601 = v__h136607 / 32'd10; + v__h136609 = v__h136615 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136601); + v__h136609); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11292,14 +11300,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153951 = $stime; + v__h153959 = $stime; #0; end - v__h153945 = v__h153951 / 32'd10; + v__h153953 = v__h153959 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153945); + $display("%0d: ERROR: CreditCounter: overflow", v__h153953); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11323,7 +11331,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_wr_addr_awaddr__h147862); + $write("'h%h", mem_req_wr_addr_awaddr__h147870); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11411,7 +11419,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", data64__h147777); + $write("'h%h", data64__h147785); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11419,7 +11427,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", strb8__h147778); + $write("'h%h", strb8__h147786); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11445,16 +11453,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133718 = $stime; + v__h133726 = $stime; #0; end - v__h133712 = v__h133718 / 32'd10; + v__h133720 = v__h133726 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133712, + v__h133720, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11542,7 +11550,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_rd_addr_araddr__h133938); + $write("'h%h", mem_req_rd_addr_araddr__h133946); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11623,15 +11631,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h160645 = $stime; + v__h160653 = $stime; #0; end - v__h160639 = v__h160645 / 32'd10; + v__h160647 = v__h160653 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160639, + v__h160647, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -11669,15 +11677,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161153 = $stime; + v__h161161 = $stime; #0; end - v__h161147 = v__h161153 / 32'd10; + v__h161155 = v__h161161 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161147); + v__h161155); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index 0015cc0..31227b4 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -324,7 +324,8 @@ module mkSoC_Top #(Reset dm_power_on_reset) method Action start (Fabric_Addr tohost_addr, Fabric_Addr fromhost_addr); Bool watch_tohost = (tohost_addr != 0); mem0_controller.set_watch_tohost (watch_tohost, tohost_addr); - corew.start (tohost_addr, fromhost_addr); + Bool is_running = True; + corew.start (is_running, tohost_addr, fromhost_addr); $display ("%0d: %m.method start (tohost %0h, fromhost %0h)", cur_cycle, tohost_addr, fromhost_addr); endmethod From a6a227ed6601bd9f2d6129cf85a9b04413ad6f63 Mon Sep 17 00:00:00 2001 From: rsnikhil Date: Fri, 13 Mar 2020 15:07:38 -0400 Subject: [PATCH 2/8] Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...) Amendment: RegUNInit.v updated, removing an extraneous RST line. --- .../Verilog_RTL/mkCore.v | 1425 +++++++------- .../Verilog_RTL/mkCoreW.v | 18 +- .../Verilog_RTL/mkFabric_2x3.v | 36 +- .../Verilog_RTL/mkProc.v | 1674 +++++++++-------- .../Verilog_RTL/mkSoC_Top.v | 78 +- builds/Resources/Include_bluesim.mk | 1 + src_Core/CPU/Core.bsv | 9 +- src_Core/CPU/Proc.bsv | 4 +- src_Core/CPU/Proc_IFC.bsv | 2 +- src_Core/Core/CoreW.bsv | 9 +- src_Core/Core/CoreW_IFC.bsv | 2 +- src_SSITH_P3/Makefile | 6 +- src_SSITH_P3/Verilog_RTL/mkCore.v | 1308 ++++++------- src_SSITH_P3/Verilog_RTL/mkCoreW.v | 50 +- src_SSITH_P3/Verilog_RTL/mkJtagTap.v | 369 ++-- src_SSITH_P3/Verilog_RTL/mkP3_Core.v | 118 +- src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v | 92 + src_SSITH_P3/Verilog_RTL/mkProc.v | 1356 ++++++------- src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v | 5 + src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v | 87 + src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v | 49 + src_SSITH_P3/Verilog_RTL_sim/SyncWire.v | 41 + src_SSITH_P3/Verilog_RTL_sim/mkCore.v | 701 +++---- src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v | 50 +- src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v | 369 ++-- src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v | 152 +- src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v | 92 + src_SSITH_P3/Verilog_RTL_sim/mkProc.v | 1364 +++++++------- src_SSITH_P3/src_BSV/ClockHacks.bsv | 117 ++ src_SSITH_P3/src_BSV/JtagTap.bsv | 50 +- src_SSITH_P3/src_BSV/P3_Core.bsv | 43 +- src_SSITH_P3/src_BSV/PowerOnReset.bsv | 51 + src_SSITH_P3/xilinx_ip/component.xml | 132 +- src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v | 5 + src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v | 87 + src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v | 49 + src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v | 50 + src_SSITH_P3/xilinx_ip/hdl/SyncWire.v | 41 + src_SSITH_P3/xilinx_ip/hdl/mkCore.v | 1308 ++++++------- src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v | 50 +- src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v | 369 ++-- src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v | 118 +- src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v | 92 + src_SSITH_P3/xilinx_ip/hdl/mkProc.v | 1356 ++++++------- src_Testbench/SoC/SoC_Top.bsv | 3 +- 45 files changed, 7309 insertions(+), 6079 deletions(-) create mode 100644 src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/SyncWire.v create mode 100644 src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v create mode 100644 src_SSITH_P3/src_BSV/ClockHacks.bsv create mode 100644 src_SSITH_P3/src_BSV/PowerOnReset.bsv create mode 100644 src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/SyncWire.v create mode 100644 src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index 4db820b..d122cc6 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -88,6 +88,7 @@ // RDY_setSEIP O 1 const // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 unused // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -154,6 +155,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -332,6 +334,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4018,7 +4021,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; - wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, + wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; wire MUX_commitStage_rg_serial_num$write_1__SEL_1, @@ -4073,19 +4076,13 @@ module mkCore(CLK, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fs_reg$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_1, - MUX_csrf_ie_vec_1$write_1__SEL_2, - MUX_csrf_ie_vec_1$write_1__VAL_1, + MUX_csrf_ie_vec_1$write_1__VAL_2, MUX_csrf_ie_vec_3$write_1__SEL_1, - MUX_csrf_ie_vec_3$write_1__SEL_2, - MUX_csrf_ie_vec_3$write_1__VAL_1, - MUX_csrf_mpp_reg$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__VAL_1, - MUX_csrf_prev_ie_vec_3$write_1__SEL_1, - MUX_csrf_prev_ie_vec_3$write_1__VAL_1, + MUX_csrf_ie_vec_3$write_1__VAL_2, + MUX_csrf_prev_ie_vec_1$write_1__VAL_2, + MUX_csrf_prev_ie_vec_3$write_1__VAL_2, MUX_csrf_prv_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__VAL_1, + MUX_csrf_spp_reg$write_1__VAL_2, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_flush_reservation$write_1__SEL_1, @@ -4167,20 +4164,20 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77, - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78, + reg [22 : 0] CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75, + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76, CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79, CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q80, CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81, CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q82, CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112, CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q113, - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40, - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41, + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42, + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43, CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110, CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q111, - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42, - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43, + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40, + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41, CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114, CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q115, CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44, @@ -4189,8 +4186,8 @@ module mkCore(CLK, CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q117, CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46, CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q47, - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75, - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76, + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77, + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78, _theResult___fst_sfd__h350720, _theResult___fst_sfd__h359443, _theResult___fst_sfd__h368025, @@ -4268,8 +4265,8 @@ module mkCore(CLK, CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q28, CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95, CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q96, - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29, - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30, + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25, + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26, CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103, CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q104, CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33, @@ -4357,11 +4354,11 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232, + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234, + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, CASE_guard05153_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, CASE_guard05153_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, CASE_guard08267_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, @@ -4370,38 +4367,38 @@ module mkCore(CLK, CASE_guard17336_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, CASE_guard22919_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, CASE_guard22919_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, CASE_guard37808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, CASE_guard47120_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, CASE_guard47120_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, CASE_guard50747_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, CASE_guard50747_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, CASE_guard50848_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, CASE_guard56189_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, CASE_guard59456_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, CASE_guard59456_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, CASE_guard59778_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, CASE_guard68386_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, CASE_guard68614_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, CASE_guard77222_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53, + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, CASE_guard86424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, CASE_guard96446_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, CASE_guard96446_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, CASE_guard98955_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233, + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4678,7 +4675,7 @@ module mkCore(CLK, r1__read__h620737, r1__read__h620854, y__h258435; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q23, + wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91, IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130, @@ -4694,7 +4691,7 @@ module mkCore(CLK, IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166, IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q25, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71, @@ -5110,7 +5107,7 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107, @@ -5246,7 +5243,7 @@ module mkCore(CLK, _theResult___snd_fst_exp__h585834, _theResult___snd_fst_exp__h604269, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64, - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21, + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99, din_inc___2_exp__h526166, din_inc___2_exp__h526201, @@ -5515,7 +5512,7 @@ module mkCore(CLK, IF_sfdin22305_BIT_33_THEN_2_ELSE_0__q67, IF_sfdin50234_BIT_33_THEN_2_ELSE_0__q92, IF_sfdin55340_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q24, + IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22, IF_sfdin68000_BIT_33_THEN_2_ELSE_0__q102, IF_sfdin76608_BIT_33_THEN_2_ELSE_0__q32, IF_sfdin94644_BIT_4_THEN_2_ELSE_0__q148, @@ -5527,7 +5524,7 @@ module mkCore(CLK, IF_theResult___snd45720_BIT_4_THEN_2_ELSE_0__q167, IF_theResult___snd58847_BIT_33_THEN_2_ELSE_0__q94, IF_theResult___snd64125_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q26, + IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24, IF_theResult___snd76637_BIT_33_THEN_2_ELSE_0__q107, IF_theResult___snd85024_BIT_4_THEN_2_ELSE_0__q144, IF_theResult___snd85245_BIT_33_THEN_2_ELSE_0__q37, @@ -5919,7 +5916,7 @@ module mkCore(CLK, NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962, NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017, NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075, - NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_RDY_ETC___d15034, + NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034, NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_deq_ETC___d15187, NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788, NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14981, @@ -5990,7 +5987,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo28, + _dfoo26, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -6145,8 +6142,8 @@ module mkCore(CLK, csrf_prv_reg_read__2956_ULE_1___d14607, csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192, fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551, + fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407, fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617, - fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14165, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305, @@ -6197,7 +6194,7 @@ module mkCore(CLK, r1__read_BIT_20___h662377, r__h619422, r__h620919, - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037, + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037, regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111, regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598, regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612, @@ -6216,7 +6213,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318, regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402, regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412, - rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407, + rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165, rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841, rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975, rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992, @@ -9213,32 +9210,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && - l2Tlb$RDY_toChildren_rsToC_deq && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && + l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9250,16 +9247,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9298,9 +9295,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9600,7 +9597,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_commitTrap[165] && @@ -9649,8 +9646,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && rob$deqPort_0_deq_data[18] ; @@ -9729,7 +9726,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_RDY_ETC___d15034 && + NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034 && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -9878,8 +9875,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9890,8 +9887,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9965,16 +9962,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -9985,8 +9982,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10024,8 +10021,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10122,8 +10119,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10140,8 +10137,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10163,8 +10160,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10311,8 +10308,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -10355,8 +10352,8 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; @@ -10375,8 +10372,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10607,8 +10604,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10652,9 +10649,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && - fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && @@ -10663,8 +10661,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10748,7 +10746,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -10968,27 +10967,15 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; - assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[257:253] == 5'd19 || rob$deqPort_0_deq_data[257:253] == 5'd20) ; - assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -11056,6 +11043,18 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = commitStage_rg_serial_num + y__h723410 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = (k__h675032 == 1'd0 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186) ? { fetchStage$pipelines_0_first[199:195], @@ -11081,18 +11080,6 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11406,7 +11393,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; endcase end - assign MUX_csrf_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || @@ -11414,7 +11401,7 @@ module mkCore(CLK, 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; - assign MUX_csrf_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ? @@ -11425,7 +11412,7 @@ module mkCore(CLK, n__read__h720316 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = n__read__h720316 + { 62'd0, x__h723635 } ; - assign MUX_csrf_mpp_reg$write_1__VAL_1 = + assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ? @@ -11434,14 +11421,14 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__VAL_1 = commitStage_commitTrap[36] ? 64'd0 : trap_val__h709721 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd8 && IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd18 || @@ -11455,7 +11442,7 @@ module mkCore(CLK, 2'd1 : 2'd3 ; assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_spp_reg$write_1__VAL_1 = + assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || @@ -12764,25 +12751,25 @@ module mkCore(CLK, // register csrf_ie_vec_1 assign csrf_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_1 ; + !MUX_csrf_ie_vec_1$write_1__SEL_1 && + MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_ie_vec_3 assign csrf_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_1 ; + !MUX_csrf_ie_vec_3$write_1__SEL_1 && + MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? cause_code__h708698 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = @@ -12795,7 +12782,7 @@ module mkCore(CLK, // register csrf_mcause_interrupt_reg assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = @@ -12861,7 +12848,7 @@ module mkCore(CLK, // register csrf_mepc_csr assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = @@ -12913,13 +12900,13 @@ module mkCore(CLK, // register csrf_mpp_reg assign csrf_mpp_reg$D_IN = - MUX_csrf_mpp_reg$write_1__SEL_1 ? - MUX_csrf_mpp_reg$write_1__VAL_1 : - csrf_prv_reg ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_prv_reg : + MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ; @@ -12939,7 +12926,7 @@ module mkCore(CLK, // register csrf_mtval_csr assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = @@ -12996,23 +12983,23 @@ module mkCore(CLK, // register csrf_prev_ie_vec_1 assign csrf_prev_ie_vec_1$D_IN = - MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : - csrf_ie_vec_1 ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_ie_vec_1 : + MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prev_ie_vec_3 assign csrf_prev_ie_vec_3$D_IN = - MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_3$write_1__VAL_1 : - csrf_ie_vec_3 ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_ie_vec_3 : + MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_prv_reg assign csrf_prv_reg$D_IN = @@ -13067,9 +13054,9 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? cause_code__h708698 : - csrf_rg_tselect$D_IN[3:0] ; + csrf_rg_tdata3$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || @@ -13080,7 +13067,7 @@ module mkCore(CLK, // register csrf_scause_interrupt_reg assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_rg_tselect$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = @@ -13117,7 +13104,7 @@ module mkCore(CLK, // register csrf_sepc_csr assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = @@ -13171,13 +13158,13 @@ module mkCore(CLK, // register csrf_spp_reg assign csrf_spp_reg$D_IN = - MUX_csrf_spp_reg$write_1__SEL_1 ? - MUX_csrf_spp_reg$write_1__VAL_1 : - csrf_prv_reg[0] ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_prv_reg[0] : + MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; @@ -13193,7 +13180,7 @@ module mkCore(CLK, // register csrf_stval_csr assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = @@ -13847,9 +13834,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -17786,7 +17773,7 @@ module mkCore(CLK, .execFpuSimple_rVal1(rVal1__h487144), .execFpuSimple_rVal2(rVal2__h487145), .execFpuSimple(execFpuSimple___d11167)); - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q23 = + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ? _theResult___snd__h358911 : _theResult____h350737 ; @@ -17850,7 +17837,7 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ? _theResult___snd__h458885 : _theResult___snd__h476675 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q25 = + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ? _theResult___snd__h367493 : 57'd0 ; @@ -19024,8 +19011,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 = (guard__h350747 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? @@ -19563,8 +19550,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045 = (_theResult___fst_exp__h603483 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -19574,8 +19561,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581 = (_theResult___fst_exp__h564179 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -19596,8 +19583,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814 = (_theResult___fst_exp__h564179 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -19607,8 +19594,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 = (_theResult___fst_exp__h525326 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -19629,8 +19616,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992 = (_theResult____h658034 == 12'd0 && (csrf_prv_reg == 2'd0 || @@ -20281,8 +20268,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ? 4'd0 : @@ -20838,7 +20825,7 @@ module mkCore(CLK, 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] == + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 9'd386 : { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35[7], @@ -22193,10 +22180,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050 = IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237 = @@ -22226,10 +22213,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 && IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 && (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14165) ; + regRenamingTable$RDY_rename_1_claimRename && + rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165) ; assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && @@ -22292,7 +22279,7 @@ module mkCore(CLK, sfdin__h450234[33] ? 2'd2 : 2'd0 ; assign IF_sfdin55340_BIT_4_THEN_2_ELSE_0__q171 = sfdin__h555340[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q24 = + assign IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22 = sfdin__h358842[33] ? 2'd2 : 2'd0 ; assign IF_sfdin68000_BIT_33_THEN_2_ELSE_0__q102 = sfdin__h468000[33] ? 2'd2 : 2'd0 ; @@ -22316,7 +22303,7 @@ module mkCore(CLK, _theResult___snd__h458847[33] ? 2'd2 : 2'd0 ; assign IF_theResult___snd64125_BIT_4_THEN_2_ELSE_0__q174 = _theResult___snd__h564125[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q26 = + assign IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24 = _theResult___snd__h367455[33] ? 2'd2 : 2'd0 ; assign IF_theResult___snd76637_BIT_33_THEN_2_ELSE_0__q107 = _theResult___snd__h476637[33] ? 2'd2 : 2'd0 ; @@ -23202,7 +23189,7 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125 = (!fetchStage$pipelines_0_canDeq || NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 && + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177 = @@ -23440,12 +23427,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -23538,10 +23525,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073 ; - assign NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_RDY_ETC___d15034 = + assign NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__5002_BIT_25_5003_5_ETC___d15031) ; @@ -23582,7 +23569,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd15 || rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 || @@ -23709,8 +23696,8 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 = - { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21[10], - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21 } ; + { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29[10], + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 } ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^ 12'h800) <= @@ -23719,11 +23706,11 @@ module mkCore(CLK, (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^ 12'h800) < 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22 = + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 + 12'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99[10], @@ -24023,11 +24010,11 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 ; + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235 ; + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 ; assign _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && @@ -24675,7 +24662,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18 || rob$deqPort_0_deq_data[257:253] == 5'd20 ; - assign _dfoo28 = + assign _dfoo26 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || @@ -25218,12 +25205,12 @@ module mkCore(CLK, _theResult___fst_exp__h376614 : _theResult___fst_exp__h377208 ; assign _theResult___fst_exp__h385251 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] == + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] ; + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ; assign _theResult___fst_exp__h385290 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q22[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; assign _theResult___fst_exp__h385296 = @@ -26623,7 +26610,7 @@ module mkCore(CLK, _theResult____h350737 : _theResult___snd__h358888 ; assign _theResult___snd__h358888 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q23[54:0], + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0], 2'd0 } ; assign _theResult___snd__h358911 = _theResult____h350737 << @@ -26643,7 +26630,7 @@ module mkCore(CLK, sfd__h343132 : _theResult___snd__h367470 ; assign _theResult___snd__h367470 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q25[54:0], + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0], 2'd0 } ; assign _theResult___snd__h367493 = sfd__h343132 << @@ -27703,7 +27690,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q21 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] - 11'd1023 ; assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99 = @@ -28186,9 +28173,9 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788 ; @@ -28339,6 +28326,14 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 ; + assign fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && @@ -28346,12 +28341,6 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 ; - assign fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14165 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -28583,10 +28572,10 @@ module mkCore(CLK, assign fflags_csr__read__h616210 = { 59'd0, csrf_fflags_reg } ; assign frm_csr__read__h616221 = { 61'd0, csrf_frm_reg } ; assign guard__h350747 = - { IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q24[1], + { IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22[1], { sfdin__h358842[32:0], 23'd0 } != 56'd0 } ; assign guard__h359456 = - { IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q26[1], + { IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24[1], { _theResult___snd__h367455[32:0], 23'd0 } != 56'd0 } ; assign guard__h368386 = { IF_sfdin76608_BIT_33_THEN_2_ELSE_0__q32[1], @@ -29156,9 +29145,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign r__h619422 = csrf_fs_reg == 2'b11 ; assign r__h620919 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037 = + assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; assign regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111 = @@ -29579,14 +29568,12 @@ module mkCore(CLK, assign result__h653792 = ~x__h653791 ; assign rg_tdata1__read__h619065 = { r1__read__h620945, csrf_rg_tdata1_data } ; - assign rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14968 = rob$deqPort_0_deq_data[353:290] + 64'd4 ; assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841 = @@ -30526,23 +30513,23 @@ module mkCore(CLK, default: rVal1__h640782 = 64'b0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h396418 = 8'd255; + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h442113 = 8'd255; 3'd2: - _theResult___fst_exp__h396418 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h442113 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h396418 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h442113 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h396418 = 8'd254; - default: _theResult___fst_exp__h396418 = 8'd0; + 3'd4: _theResult___fst_exp__h442113 = 8'd254; + default: _theResult___fst_exp__h442113 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or @@ -30583,6 +30570,25 @@ module mkCore(CLK, default: _theResult___fst_sfd__h350720 = 23'd0; endcase end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h396418 = 8'd255; + 3'd2: + _theResult___fst_exp__h396418 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h396418 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h396418 = 8'd254; + default: _theResult___fst_exp__h396418 = 8'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -30602,25 +30608,6 @@ module mkCore(CLK, default: _theResult___fst_sfd__h396419 = 23'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h442113 = 8'd255; - 3'd2: - _theResult___fst_exp__h442113 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h442113 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h442113 = 8'd254; - default: _theResult___fst_exp__h442113 = 8'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -31025,6 +31012,71 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(guard__h359456 or + _theResult___fst_exp__h367504 or + out_exp__h367949 or _theResult___exp__h367946) + begin + case (guard__h359456) + 2'b0, 2'b01: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 = + _theResult___fst_exp__h367504; + 2'b10: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 = + out_exp__h367949; + 2'b11: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 = + _theResult___exp__h367946; + endcase + end + always@(guard__h359456 or + _theResult___fst_exp__h367504 or _theResult___exp__h367946) + begin + case (guard__h359456) + 2'b0: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 = + _theResult___fst_exp__h367504; + 2'b01, 2'b10, 2'b11: + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 = + _theResult___exp__h367946; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 or + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or + _theResult___fst_exp__h367504) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_exp__h368024 = + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25; + 3'd1: + _theResult___fst_exp__h368024 = + CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26; + 3'd2: + _theResult___fst_exp__h368024 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; + 3'd3: + _theResult___fst_exp__h368024 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; + 3'd4: _theResult___fst_exp__h368024 = _theResult___fst_exp__h367504; + default: _theResult___fst_exp__h368024 = 8'd0; + endcase + end always@(guard__h350747 or _theResult___fst_exp__h358848 or out_exp__h359367 or _theResult___exp__h359364) @@ -31077,58 +31129,6 @@ module mkCore(CLK, default: _theResult___fst_exp__h359442 = 8'd0; endcase end - always@(guard__h359456 or - _theResult___fst_exp__h367504 or - out_exp__h367949 or _theResult___exp__h367946) - begin - case (guard__h359456) - 2'b0, 2'b01: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 = - _theResult___fst_exp__h367504; - 2'b10: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 = - out_exp__h367949; - 2'b11: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 = - _theResult___exp__h367946; - endcase - end - always@(guard__h359456 or - _theResult___fst_exp__h367504 or _theResult___exp__h367946) - begin - case (guard__h359456) - 2'b0: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30 = - _theResult___fst_exp__h367504; - 2'b01, 2'b10, 2'b11: - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30 = - _theResult___exp__h367946; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29 or - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or - _theResult___fst_exp__h367504) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_exp__h368024 = - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q29; - 3'd1: - _theResult___fst_exp__h368024 = - CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q30; - 3'd2: - _theResult___fst_exp__h368024 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; - 3'd3: - _theResult___fst_exp__h368024 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; - 3'd4: _theResult___fst_exp__h368024 = _theResult___fst_exp__h367504; - default: _theResult___fst_exp__h368024 = 8'd0; - endcase - end always@(guard__h368386 or _theResult___fst_exp__h376614 or out_exp__h377133 or _theResult___exp__h377130) @@ -31233,69 +31233,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h385844 = 8'd0; endcase end - always@(guard__h350747 or - sfdin__h358842 or out_sfd__h359368 or _theResult___sfd__h359365) - begin - case (guard__h350747) - 2'b0, 2'b01: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 = - sfdin__h358842[56:34]; - 2'b10: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 = - out_sfd__h359368; - 2'b11: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 = - _theResult___sfd__h359365; - endcase - end - always@(guard__h350747 or sfdin__h358842 or _theResult___sfd__h359365) - begin - case (guard__h350747) - 2'b0: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41 = - sfdin__h358842[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41 = - _theResult___sfd__h359365; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40 or - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or - sfdin__h358842) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h359443 = - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q40; - 3'd1: - _theResult___fst_sfd__h359443 = - CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q41; - 3'd2: - _theResult___fst_sfd__h359443 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; - 3'd3: - _theResult___fst_sfd__h359443 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; - 3'd4: _theResult___fst_sfd__h359443 = sfdin__h358842[56:34]; - default: _theResult___fst_sfd__h359443 = 23'd0; - endcase - end always@(guard__h359456 or _theResult___snd__h367455 or out_sfd__h367950 or _theResult___sfd__h367947) begin case (guard__h359456) 2'b0, 2'b01: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 = _theResult___snd__h367455[56:34]; 2'b10: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 = out_sfd__h367950; 2'b11: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 = _theResult___sfd__h367947; endcase end @@ -31304,16 +31254,16 @@ module mkCore(CLK, begin case (guard__h359456) 2'b0: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 = _theResult___snd__h367455[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43 = + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 = _theResult___sfd__h367947; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42 or - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43 or + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 or + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or _theResult___snd__h367455) @@ -31321,10 +31271,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h368025 = - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q42; + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40; 3'd1: _theResult___fst_sfd__h368025 = - CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q43; + CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41; 3'd2: _theResult___fst_sfd__h368025 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; @@ -31335,6 +31285,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h368025 = 23'd0; endcase end + always@(guard__h350747 or + sfdin__h358842 or out_sfd__h359368 or _theResult___sfd__h359365) + begin + case (guard__h350747) + 2'b0, 2'b01: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 = + sfdin__h358842[56:34]; + 2'b10: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 = + out_sfd__h359368; + 2'b11: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h359365; + endcase + end + always@(guard__h350747 or sfdin__h358842 or _theResult___sfd__h359365) + begin + case (guard__h350747) + 2'b0: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 = + sfdin__h358842[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h359365; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 or + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or + sfdin__h358842) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h359443 = + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42; + 3'd1: + _theResult___fst_sfd__h359443 = + CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43; + 3'd2: + _theResult___fst_sfd__h359443 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; + 3'd3: + _theResult___fst_sfd__h359443 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; + 3'd4: _theResult___fst_sfd__h359443 = sfdin__h358842[56:34]; + default: _theResult___fst_sfd__h359443 = 23'd0; + endcase + end always@(guard__h368386 or sfdin__h376608 or out_sfd__h377134 or _theResult___sfd__h377131) begin @@ -31627,66 +31627,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h377222 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h377222) - 2'b0, 2'b01, 2'b10: - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = - guard__h377222 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or - guard__h377222) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - (guard__h377222 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h377222 == 2'b01 || guard__h377222 == 2'b10 || - guard__h377222 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h368386 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h368386) 2'b0, 2'b01, 2'b10: - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = guard__h368386 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or guard__h368386) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; + CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = (guard__h368386 == 2'b0) ? @@ -31703,6 +31665,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h377222 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h377222) + 2'b0, 2'b01, 2'b10: + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + guard__h377222 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or + guard__h377222) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + (guard__h377222 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h377222 == 2'b01 || guard__h377222 == 2'b10 || + guard__h377222 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h377222 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -31741,19 +31741,6 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -31975,69 +31962,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h431541 = 8'd0; endcase end - always@(guard__h396446 or - sfdin__h404539 or out_sfd__h405065 or _theResult___sfd__h405062) - begin - case (guard__h396446) - 2'b0, 2'b01: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 = - sfdin__h404539[56:34]; - 2'b10: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 = - out_sfd__h405065; - 2'b11: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 = - _theResult___sfd__h405062; - endcase - end - always@(guard__h396446 or sfdin__h404539 or _theResult___sfd__h405062) - begin - case (guard__h396446) - 2'b0: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76 = - sfdin__h404539[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h405062; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75 or - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or - sfdin__h404539) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h405140 = - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q75; - 3'd1: - _theResult___fst_sfd__h405140 = - CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q76; - 3'd2: - _theResult___fst_sfd__h405140 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; - 3'd3: - _theResult___fst_sfd__h405140 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; - 3'd4: _theResult___fst_sfd__h405140 = sfdin__h404539[56:34]; - default: _theResult___fst_sfd__h405140 = 23'd0; - endcase - end always@(guard__h405153 or _theResult___snd__h413152 or out_sfd__h413647 or _theResult___sfd__h413644) begin case (guard__h405153) 2'b0, 2'b01: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 = _theResult___snd__h413152[56:34]; 2'b10: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 = out_sfd__h413647; 2'b11: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 = _theResult___sfd__h413644; endcase end @@ -32046,16 +31983,16 @@ module mkCore(CLK, begin case (guard__h405153) 2'b0: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 = _theResult___snd__h413152[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78 = + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 = _theResult___sfd__h413644; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77 or - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78 or + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 or + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or _theResult___snd__h413152) @@ -32063,10 +32000,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h413722 = - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q77; + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75; 3'd1: _theResult___fst_sfd__h413722 = - CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q78; + CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76; 3'd2: _theResult___fst_sfd__h413722 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; @@ -32077,6 +32014,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h413722 = 23'd0; endcase end + always@(guard__h396446 or + sfdin__h404539 or out_sfd__h405065 or _theResult___sfd__h405062) + begin + case (guard__h396446) + 2'b0, 2'b01: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 = + sfdin__h404539[56:34]; + 2'b10: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 = + out_sfd__h405065; + 2'b11: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h405062; + endcase + end + always@(guard__h396446 or sfdin__h404539 or _theResult___sfd__h405062) + begin + case (guard__h396446) + 2'b0: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 = + sfdin__h404539[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h405062; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 or + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or + sfdin__h404539) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h405140 = + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77; + 3'd1: + _theResult___fst_sfd__h405140 = + CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78; + 3'd2: + _theResult___fst_sfd__h405140 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; + 3'd3: + _theResult___fst_sfd__h405140 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; + 3'd4: _theResult___fst_sfd__h405140 = sfdin__h404539[56:34]; + default: _theResult___fst_sfd__h405140 = 23'd0; + endcase + end always@(guard__h414083 or sfdin__h422305 or out_sfd__h422831 or _theResult___sfd__h422828) begin @@ -32926,23 +32913,61 @@ module mkCore(CLK, begin case (guard__h442141) 2'b0, 2'b01, 2'b10: - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + guard__h442141 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or + guard__h442141) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + (guard__h442141 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h442141 != 2'b01 && guard__h442141 != 2'b10 && + guard__h442141 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h442141 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h442141) + 2'b0, 2'b01, 2'b10: + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = guard__h442141 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or guard__h442141) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; + CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = (guard__h442141 == 2'b0) ? @@ -32964,23 +32989,23 @@ module mkCore(CLK, begin case (guard__h450848) 2'b0, 2'b01, 2'b10: - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = guard__h450848 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or guard__h450848) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = (guard__h450848 == 2'b0) ? @@ -32997,44 +33022,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h442141 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h442141) - 2'b0, 2'b01, 2'b10: - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h442141 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h442141) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h442141 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h442141 != 2'b01 && guard__h442141 != 2'b10 && - guard__h442141 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end always@(guard__h450848 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -33111,66 +33098,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468614 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h468614) - 2'b0, 2'b01, 2'b10: - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h468614 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h468614) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - (guard__h468614 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h468614 == 2'b01 || guard__h468614 == 2'b10 || - guard__h468614 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end always@(guard__h459778 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (guard__h459778) 2'b0, 2'b01, 2'b10: - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = guard__h459778 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or guard__h459778) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; + CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = (guard__h459778 == 2'b0) ? @@ -33187,6 +33136,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end + always@(guard__h468614 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h468614) + 2'b0, 2'b01, 2'b10: + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + guard__h468614 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or + guard__h468614) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + (guard__h468614 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + (guard__h468614 == 2'b01 || guard__h468614 == 2'b10 || + guard__h468614 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end always@(guard__h468614 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -33499,21 +33486,21 @@ module mkCore(CLK, _theResult___exp__h585728; endcase end - always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h586424 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577112) + case (guard__h586424) 2'b0, 2'b01, 2'b10: - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h577112 == 2'b11 && + CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h586424 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586424) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33522,12 +33509,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h577112 == 2'b0) ? + (guard__h586424 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h577112 == 2'b01 || guard__h577112 == 2'b10 || - guard__h577112 == 2'b11) && + (guard__h586424 == 2'b01 || guard__h586424 == 2'b10 || + guard__h586424 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33538,21 +33525,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595493) + case (guard__h577112) 2'b0, 2'b01, 2'b10: - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h595493 == 2'b11 && + CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h577112 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33561,12 +33548,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h595493 == 2'b0) ? + (guard__h577112 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h595493 == 2'b01 || guard__h595493 == 2'b10 || - guard__h595493 == 2'b11) && + (guard__h577112 == 2'b01 || guard__h577112 == 2'b10 || + guard__h577112 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33577,21 +33564,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h586424 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h586424) + case (guard__h595493) 2'b0, 2'b01, 2'b10: - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h586424 == 2'b11 && + CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h595493 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586424) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33600,12 +33587,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h586424 == 2'b0) ? + (guard__h595493 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h586424 == 2'b01 || guard__h586424 == 2'b10 || - guard__h586424 == 2'b11) && + (guard__h595493 == 2'b01 || guard__h595493 == 2'b10 || + guard__h595493 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33655,21 +33642,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595493) + case (guard__h577112) 2'b0, 2'b01, 2'b10: - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h595493 != 2'b11 || + CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h577112 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33678,12 +33665,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h595493 == 2'b0) ? + (guard__h577112 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595493 != 2'b01 && guard__h595493 != 2'b10 && - guard__h595493 != 2'b11 || + guard__h577112 != 2'b01 && guard__h577112 != 2'b10 && + guard__h577112 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33694,21 +33681,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577112) + case (guard__h595493) 2'b0, 2'b01, 2'b10: - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h577112 != 2'b11 || + CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h595493 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33717,12 +33704,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h577112 == 2'b0) ? + (guard__h595493 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h577112 != 2'b01 && guard__h577112 != 2'b10 && - guard__h577112 != 2'b11 || + guard__h595493 != 2'b01 && guard__h595493 != 2'b10 && + guard__h595493 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -34156,58 +34143,16 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h556189 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h556189) - 2'b0, 2'b01, 2'b10: - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h556189 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556189) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h556189 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h556189 != 2'b01 && guard__h556189 != 2'b10 && - guard__h556189 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h537808 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h537808) 2'b0, 2'b01, 2'b10: - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = guard__h537808 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -34218,12 +34163,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = (guard__h537808 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -34233,6 +34178,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h556189 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h556189) + 2'b0, 2'b01, 2'b10: + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h556189 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556189) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h556189 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h556189 != 2'b01 && guard__h556189 != 2'b10 && + guard__h556189 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -35479,29 +35466,29 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(k__h675032 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin case (k__h675032) 1'd0: - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or @@ -35524,7 +35511,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037 or + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 or @@ -35546,7 +35533,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 || - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14037; + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037; endcase end always@(fetchStage$pipelines_0_first or @@ -35610,29 +35597,29 @@ module mkCore(CLK, coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage$pipelines_1_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_1_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin case (fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107) 1'd0: - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235 = + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q235 = + CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end + always@(fetchStage$pipelines_1_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_1_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or @@ -35736,10 +35723,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = + coreFix_memExe_lsq$enqLdTag[4:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = + coreFix_memExe_lsq$enqStTag[4:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -35747,10 +35734,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = - coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = - coreFix_memExe_lsq$enqStTag[4:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_1_first or @@ -35962,6 +35949,24 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = + 3'd0; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -36176,24 +36181,6 @@ module mkCore(CLK, endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = - 3'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v index 4bb9ec5..4d4b2a0 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v @@ -69,6 +69,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 reg // set_verbosity_logdelay I 64 unused +// start_is_running I 1 unused // start_tohost_addr I 64 reg // start_fromhost_addr I 64 reg // cpu_imem_master_awready I 1 @@ -140,6 +141,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -333,6 +335,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1054,7 +1057,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1167,8 +1171,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h6490; - reg [31 : 0] v__h6484; + reg [31 : 0] v__h6500; + reg [31 : 0] v__h6494; // synopsys translate_on // action method set_verbosity @@ -1793,6 +1797,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2246,6 +2251,7 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; assign proc$start_fromhostAddr = start_fromhost_addr ; + assign proc$start_running = start_is_running ; assign proc$start_startpc = 64'h0000000000001000 ; assign proc$start_tohostAddr = start_tohost_addr ; assign proc$EN_start = EN_start ; @@ -2265,14 +2271,14 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h6490 = $stime; + v__h6500 = $stime; #0; end - v__h6484 = v__h6490 / 32'd10; + v__h6494 = v__h6500 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h6484, + v__h6494, 64'h0000000000001000, start_tohost_addr, start_fromhost_addr); diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v index d5cd23c..a6d7266 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v @@ -3313,17 +3313,17 @@ module mkFabric_2x3(CLK, 8'd0 : x__h12203 ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_0$D_OUT[3:0], 66'd3, @@ -3734,23 +3734,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: @@ -3761,9 +3761,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && @@ -3862,23 +3862,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: @@ -3889,9 +3889,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index 368609d..b77f7ec 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -77,6 +77,7 @@ // debug_module_mem_server_rlast O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 unused // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -159,6 +160,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -377,6 +379,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1285,6 +1288,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_memReq_deq, core_0$RDY_tlbToMem_memReq_first, core_0$RDY_tlbToMem_respLd_enq, + core_0$coreReq_start_running, core_0$mmioToPlatform_cRq_notEmpty, core_0$mmioToPlatform_cRs_first, core_0$recvDoStats_x, @@ -1904,60 +1908,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163686; - reg [31 : 0] v__h163250; - reg [31 : 0] v__h5300; - reg [31 : 0] v__h5473; - reg [31 : 0] v__h5733; - reg [31 : 0] v__h7875; - reg [31 : 0] v__h8090; - reg [31 : 0] v__h2450; - reg [31 : 0] v__h4123; - reg [31 : 0] v__h9260; - reg [31 : 0] v__h9753; - reg [31 : 0] v__h9916; - reg [31 : 0] v__h135207; - reg [31 : 0] v__h135374; - reg [31 : 0] v__h137477; - reg [31 : 0] v__h154821; - reg [31 : 0] v__h134588; - reg [31 : 0] v__h161515; - reg [31 : 0] v__h162023; - reg [31 : 0] v__h2444; - reg [31 : 0] v__h4117; - reg [31 : 0] v__h5294; - reg [31 : 0] v__h5467; - reg [31 : 0] v__h5727; - reg [31 : 0] v__h7869; - reg [31 : 0] v__h8084; - reg [31 : 0] v__h9254; - reg [31 : 0] v__h9747; - reg [31 : 0] v__h9910; - reg [31 : 0] v__h134582; - reg [31 : 0] v__h135201; - reg [31 : 0] v__h135368; - reg [31 : 0] v__h137471; - reg [31 : 0] v__h154815; - reg [31 : 0] v__h161509; - reg [31 : 0] v__h162017; - reg [31 : 0] v__h163244; - reg [31 : 0] v__h163680; + reg [31 : 0] v__h163696; + reg [31 : 0] v__h163258; + reg [31 : 0] v__h5308; + reg [31 : 0] v__h5481; + reg [31 : 0] v__h5741; + reg [31 : 0] v__h7883; + reg [31 : 0] v__h8098; + reg [31 : 0] v__h2458; + reg [31 : 0] v__h4131; + reg [31 : 0] v__h9268; + reg [31 : 0] v__h9761; + reg [31 : 0] v__h9924; + reg [31 : 0] v__h135215; + reg [31 : 0] v__h135382; + reg [31 : 0] v__h137485; + reg [31 : 0] v__h154829; + reg [31 : 0] v__h134596; + reg [31 : 0] v__h161523; + reg [31 : 0] v__h162031; + reg [31 : 0] v__h2452; + reg [31 : 0] v__h4125; + reg [31 : 0] v__h5302; + reg [31 : 0] v__h5475; + reg [31 : 0] v__h5735; + reg [31 : 0] v__h7877; + reg [31 : 0] v__h8092; + reg [31 : 0] v__h9262; + reg [31 : 0] v__h9755; + reg [31 : 0] v__h9918; + reg [31 : 0] v__h134590; + reg [31 : 0] v__h135209; + reg [31 : 0] v__h135376; + reg [31 : 0] v__h137479; + reg [31 : 0] v__h154823; + reg [31 : 0] v__h161517; + reg [31 : 0] v__h162025; + reg [31 : 0] v__h163252; + reg [31 : 0] v__h163690; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26, + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, @@ -1967,39 +1971,39 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, - data64__h148647, - dword__h94449, - ld_data__h132736, - old_dword__h90139, - w1__h48006, - w1__h48011, - w2__h48007, - w2__h48013, - x__h48002; + data64__h148655, + dword__h94457, + ld_data__h132744, + old_dword__h90147, + w1__h48014, + w1__h48019, + w2__h48015, + w2__h48021, + x__h48010; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; - reg [7 : 0] strb8__h148648; + reg [7 : 0] strb8__h148656; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; - reg [2 : 0] x__h61720; - reg [1 : 0] CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; + reg [2 : 0] x__h61728; + reg [1 : 0] CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, + CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, - x__h61727, - x__h82707; + x__h61735, + x__h82715; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - new_cline__h135510; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1597, + new_cline__h135518; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1592, + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408; wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; @@ -2017,89 +2021,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - data__h31730, - failed_testnum__h163293, - line_addr__h102513, - line_addr__h102599, - mask__h90136, - mem_req_rd_addr_araddr__h134808, - mem_req_wr_addr_awaddr__h148732, - mmioPlatform_fromHostQ_data_0__h42577, - mmioPlatform_mtime__h37044, - mmioPlatform_reqData__h48598, - n__read_addr__h61588, - n__read_addr__h61673, - n__read_addr__h80469, - n__read_addr__h80548, - n__read_snd_addr__h124040, - newData__h31811, - newData__h34741, - new_dword__h90140, - op_result__h48614, - op_result__h49144, - op_result__h49149, - op_result__h49154, - op_result__h49159, - op_result__h49165, - op_result__h49172, - op_result__h49178, - result__h48057, - result__h48181, - result__h48209, - result__h48237, - result__h48265, - result__h48293, - result__h48321, - result__h48349, - result__h48377, - result__h48422, - result__h48450, - result__h48478, - result__h48506, - result__h48547, - result__h48575, - result__h48701, - result__h48728, - result__h48755, - result__h48782, - result__h48809, - result__h48836, - result__h48863, - result__h48890, - result__h48934, - result__h48961, - result__h48988, - result__h49015, - result__h49055, - result__h49082, - result__h49199, - result__h49265, - result__h49331, - result__h49397, - result__h49463, - result__h49529, - result__h49595, - result__h49657, - result__h49702, - result__h49768, - result__h49834, - result__h49892, - result__h49937, - w1___1__h48116, - w2___1__h48117, - x1_avValue_data__h40249, - x1_avValue_data__h44935, - x__h31922, - x__h34832, - x__h37192, - x__h40767, - x__h40778, - x__h42860, - x__h42871, - x__h50114, - x__h91302, - y__h91303, - y__h91304; + data__h31738, + failed_testnum__h163301, + line_addr__h102521, + line_addr__h102607, + mask__h90144, + mem_req_rd_addr_araddr__h134816, + mem_req_wr_addr_awaddr__h148740, + mmioPlatform_fromHostQ_data_0__h42585, + mmioPlatform_mtime__h37052, + mmioPlatform_reqData__h48606, + n__read_addr__h61596, + n__read_addr__h61681, + n__read_addr__h80477, + n__read_addr__h80556, + n__read_snd_addr__h124048, + newData__h31819, + newData__h34749, + new_dword__h90148, + op_result__h48622, + op_result__h49152, + op_result__h49157, + op_result__h49162, + op_result__h49167, + op_result__h49173, + op_result__h49180, + op_result__h49186, + result__h48065, + result__h48189, + result__h48217, + result__h48245, + result__h48273, + result__h48301, + result__h48329, + result__h48357, + result__h48385, + result__h48430, + result__h48458, + result__h48486, + result__h48514, + result__h48555, + result__h48583, + result__h48709, + result__h48736, + result__h48763, + result__h48790, + result__h48817, + result__h48844, + result__h48871, + result__h48898, + result__h48942, + result__h48969, + result__h48996, + result__h49023, + result__h49063, + result__h49090, + result__h49207, + result__h49273, + result__h49339, + result__h49405, + result__h49471, + result__h49537, + result__h49603, + result__h49665, + result__h49710, + result__h49776, + result__h49842, + result__h49900, + result__h49945, + w1___1__h48124, + w2___1__h48125, + x1_avValue_data__h40257, + x1_avValue_data__h44943, + x__h31930, + x__h34840, + x__h37200, + x__h40775, + x__h40786, + x__h42868, + x__h42879, + x__h50122, + x__h91310, + y__h91311, + y__h91312; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; @@ -2111,16 +2115,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h31523, - v__h31560, - w18006_BITS_31_TO_0__q7, - w28007_BITS_31_TO_0__q8, - x_data__h30313; + v__h31531, + v__h31568, + w18014_BITS_31_TO_0__q7, + w28015_BITS_31_TO_0__q8, + x_data__h30321; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; - wire [5 : 0] x__h134843, x__h148757; + wire [5 : 0] x__h134851, x__h148765; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; - wire [3 : 0] b__h134515, b__h2344; - wire [2 : 0] n__read_id__h61592, n__read_id__h61677, x__h7705; + wire [3 : 0] b__h134523, b__h2352; + wire [2 : 0] n__read_id__h61600, n__read_id__h61685, x__h7713; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, @@ -2139,8 +2143,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315, - IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664, IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, @@ -2155,8 +2159,8 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019, NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099, NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373, - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715, + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714, NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758, NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763, @@ -2177,33 +2181,33 @@ module mkProc(CLK, NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370, NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477, NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530, mmioPlatform_cycle_47_ULT_99___d348, mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h29938, - mmioPlatform_reqBE_BIT_4___h29898, + mmioPlatform_reqBE_BIT_0___h29946, + mmioPlatform_reqBE_BIT_4___h29906, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61593, - n__read_child__h61678, - n__read_child__h80472, - n__read_child__h80551, - n__read_snd_id__h124041, + n__read_child__h61601, + n__read_child__h61686, + n__read_child__h80480, + n__read_child__h80559, + n__read_snd_id__h124049, propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, - x__h61406, - x__h75220, - x__h80291; + x__h61414, + x__h75228, + x__h80299; // action method start - assign RDY_start = CAN_FIRE_start ; + assign RDY_start = mmioPlatform_state == 2'd0 ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; @@ -2506,6 +2510,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -3183,32 +3188,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3288,14 +3297,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2344 == 4'd0 ; + b__h2352 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2344 != 4'd0 && + b__h2352 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3408,7 +3417,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42860 == 64'd0 || + x__h42868 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3548,7 +3557,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3566,7 +3575,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3584,7 +3593,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3594,7 +3603,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3603,7 +3612,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3614,7 +3623,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3623,7 +3632,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -3631,7 +3640,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -3655,7 +3664,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3672,15 +3681,15 @@ module mkProc(CLK, // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3728,13 +3737,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134515 == 4'd0 ; + b__h134523 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134515 != 4'd0 && + b__h134523 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3838,7 +3847,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30313 } ; + x_data__h30321 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -3878,7 +3887,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31730 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31738 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3903,10 +3912,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102513, + { line_addr__h102521, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102599, + { line_addr__h102607, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3914,14 +3923,14 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1597, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4020,7 +4029,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48002 } ; + x__h48010 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4029,7 +4038,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50114, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50122, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4037,47 +4046,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42860 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42868 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42860 != 64'd0 ; + x__h42868 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 == 64'd0 ; + x__h40775 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 ; + x__h61414 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 ; + x__h80299 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h124040, n__read_snd_id__h124041 } ; + { 1'd1, n__read_snd_addr__h124048, n__read_snd_id__h124049 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4138,11 +4147,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2344 - 4'd1 ; + b__h2352 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2344 ; + b__h2352 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4191,11 +4200,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134515 - 4'd1 ; + b__h134523 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134515 ; + b__h134523 ; // register cfg_verbosity assign cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -4255,7 +4264,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134808, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134816, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4266,13 +4275,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148732, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148740, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148647, strb8__h148648, 1'd1 } ; + { data64__h148655, strb8__h148656, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4284,7 +4293,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135510 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135518 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4315,10 +4324,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4332,15 +4341,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102513 : - line_addr__h102599 ; + line_addr__h102521 : + line_addr__h102607 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4501,7 +4510,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34741 : + newData__h34749 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4510,7 +4519,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h31811 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h31819 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4727,7 +4736,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7705, + x__h7713, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -4827,6 +4836,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -4922,7 +4932,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132736, llc$dma_respLd_first[3] } ; + { ld_data__h132744, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5058,7 +5068,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135510, + { new_cline__h135518, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5134,7 +5144,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94449, 3'd1 } ; + { 4'd0, dword__h94457, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5185,7 +5195,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5215,11 +5225,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5437,47 +5447,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), - .amoExec_current_data(x__h37192), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h31922)); + .amoExec_current_data(x__h37200), + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h31930)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37044), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h34832)); + .amoExec_current_data(mmioPlatform_mtime__h37052), + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h34840)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42577), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h40778)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42585), + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h40786)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29906 && + mmioPlatform_reqBE_BIT_0___h29946, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h42871)); + .amoExec_in_data(mmioPlatform_reqData__h48606), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 && + !mmioPlatform_reqBE_BIT_0___h29946), + .amoExec(x__h42879)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40249 } } ; + x1_avValue_data__h40257 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5493,7 +5503,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h31811 <= mmioPlatform_mtime ; + newData__h31819 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5558,7 +5568,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - x__h75220 } ; + x__h75228 } ; assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5567,38 +5577,38 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1592 = + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1597 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1592, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90140 : + new_dword__h90148 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__677_THE_ETC___d1682 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829 = @@ -5737,11 +5747,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42860 == 64'd0 : - x__h40767 == 64'd0, + x__h42868 == 64'd0 : + x__h40775 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44935 } ; + x1_avValue_data__h44943 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -5838,14 +5848,14 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 || IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__662_ETC___d1665 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && @@ -5981,58 +5991,58 @@ module mkProc(CLK, !propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = - { CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, + { CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = - { CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - x__h82707 } ; + x__h82715 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = - { CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = - { CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, - x__h61720, - x__h61727 } ; - assign b__h134515 = + { CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12, + x__h61728, + x__h61735 } ; + assign b__h134523 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2344 = + assign b__h2352 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31730 = + assign data__h31738 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31523, 32'd0 } ; - assign failed_testnum__h163293 = + { v__h31531, 32'd0 } ; + assign failed_testnum__h163301 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102513 = + assign line_addr__h102521 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102599 = + assign line_addr__h102607 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1609 = - line_addr__h102599 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1531 = - line_addr__h102513 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90136 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = + line_addr__h102607 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = + line_addr__h102521 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90144 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6057,14 +6067,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134808 = - { llc$to_mem_toM_first[68:11], x__h134843 } ; - assign mem_req_wr_addr_awaddr__h148732 = - { llc$to_mem_toM_first[639:582], x__h148757 } ; + assign mem_req_rd_addr_araddr__h134816 = + { llc$to_mem_toM_first[68:11], x__h134851 } ; + assign mem_req_wr_addr_awaddr__h148740 = + { llc$to_mem_toM_first[639:582], x__h148765 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42577 = + assign mmioPlatform_fromHostQ_data_0__h42585 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6075,18 +6085,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37044 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37052 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34741 ; + mmioPlatform_mtimecmp_0 <= newData__h34749 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h29938 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h29898 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48598 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h29946 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h29906 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48606 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6118,105 +6128,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61588 = + assign n__read_addr__h61596 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61673 = + assign n__read_addr__h61681 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80469 = + assign n__read_addr__h80477 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : 64'd0 ; - assign n__read_addr__h80548 = + assign n__read_addr__h80556 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : 64'd0 ; - assign n__read_child__h61593 = + assign n__read_child__h61601 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61678 = + assign n__read_child__h61686 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80472 = + assign n__read_child__h80480 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; - assign n__read_child__h80551 = + assign n__read_child__h80559 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; - assign n__read_id__h61592 = + assign n__read_id__h61600 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61677 = + assign n__read_id__h61685 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h124040 = + assign n__read_snd_addr__h124048 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h124041 = + assign n__read_snd_id__h124049 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h31811 = + assign newData__h31819 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h31922 : + x__h31930 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34741 = + assign newData__h34749 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h34832 : + x__h34840 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h135510 = + assign new_cline__h135518 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90140 = x__h91302 | y__h91303 ; - assign op_result__h48614 = + assign new_dword__h90148 = x__h91310 | y__h91311 ; + assign op_result__h48622 = IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; - assign op_result__h49144 = w1__h48011 ^ w2__h48013 ; - assign op_result__h49149 = w1__h48011 & w2__h48013 ; - assign op_result__h49154 = w1__h48011 | w2__h48013 ; - assign op_result__h49159 = - (w1__h48011 < w2__h48013) ? w1__h48011 : w2__h48013 ; - assign op_result__h49165 = - (w1__h48011 <= w2__h48013) ? w2__h48013 : w1__h48011 ; - assign op_result__h49172 = + assign op_result__h49152 = w1__h48019 ^ w2__h48021 ; + assign op_result__h49157 = w1__h48019 & w2__h48021 ; + assign op_result__h49162 = w1__h48019 | w2__h48021 ; + assign op_result__h49167 = + (w1__h48019 < w2__h48021) ? w1__h48019 : w2__h48021 ; + assign op_result__h49173 = + (w1__h48019 <= w2__h48021) ? w2__h48021 : w1__h48019 ; + assign op_result__h49180 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w1__h48011 : - w2__h48013 ; - assign op_result__h49178 = + w1__h48019 : + w2__h48021 ; + assign op_result__h49186 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w2__h48013 : - w1__h48011 ; + w2__h48021 : + w1__h48019 ; assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6227,126 +6237,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48057 = + assign result__h48065 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; - assign result__h48181 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48209 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48237 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48265 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48293 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48321 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48349 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48377 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48422 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48450 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48478 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48506 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48547 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48575 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48701 = + assign result__h48189 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48217 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48245 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48273 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48301 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48329 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48357 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48385 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48430 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48458 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48486 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48514 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48555 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48583 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48709 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48728 = + assign result__h48736 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48755 = + assign result__h48763 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48782 = + assign result__h48790 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48809 = + assign result__h48817 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48836 = + assign result__h48844 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48863 = + assign result__h48871 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48890 = + assign result__h48898 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48934 = + assign result__h48942 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48961 = + assign result__h48969 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48988 = + assign result__h48996 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49015 = + assign result__h49023 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49055 = + assign result__h49063 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49082 = + assign result__h49090 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49199 = + assign result__h49207 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49265 = + assign result__h49273 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49331 = + assign result__h49339 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49397 = + assign result__h49405 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49463 = + assign result__h49471 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49529 = + assign result__h49537 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49595 = + assign result__h49603 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49657 = + assign result__h49665 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; - assign result__h49702 = + assign result__h49710 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49768 = + assign result__h49776 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49834 = + assign result__h49842 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49892 = + assign result__h49900 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; - assign result__h49937 = + assign result__h49945 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31523 = mmioPlatform_waitUpperMSIPCRs ? v__h31560 : 32'd0 ; - assign v__h31560 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18006_BITS_31_TO_0__q7 = w1__h48006[31:0] ; - assign w1___1__h48116 = { 32'd0, w1__h48006[31:0] } ; - assign w28007_BITS_31_TO_0__q8 = w2__h48007[31:0] ; - assign w2___1__h48117 = { 32'd0, w2__h48007[31:0] } ; - assign x1_avValue_data__h40249 = + assign v__h31531 = mmioPlatform_waitUpperMSIPCRs ? v__h31568 : 32'd0 ; + assign v__h31568 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18014_BITS_31_TO_0__q7 = w1__h48014[31:0] ; + assign w1___1__h48124 = { 32'd0, w1__h48014[31:0] } ; + assign w28015_BITS_31_TO_0__q8 = w2__h48015[31:0] ; + assign w2___1__h48125 = { 32'd0, w2__h48015[31:0] } ; + assign x1_avValue_data__h40257 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44935 = + assign x1_avValue_data__h44943 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134843 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148757 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37192 = mmioPlatform_mtimecmp_0 ; - assign x__h40767 = + assign x__h134851 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148765 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37200 = mmioPlatform_mtimecmp_0 ; + assign x__h40775 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40778 : + x__h40786 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; - assign x__h42860 = + assign x__h42868 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42871 : + x__h42879 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6355,29 +6365,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50114 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61406 = + assign x__h50122 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61414 = SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; - assign x__h75220 = + assign x__h75228 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; - assign x__h7705 = + assign x__h7713 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80291 = + assign x__h80299 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; - assign x__h91302 = old_dword__h90139 & y__h91304 ; - assign x_data__h30313 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91303 = + assign x__h91310 = old_dword__h90147 & y__h91312 ; + assign x_data__h30321 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91311 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90136 ; - assign y__h91304 = + mask__h90144 ; + assign y__h91312 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -6406,141 +6416,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132736 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132736 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132736 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132736 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132736 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132736 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132736 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132736 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132744 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132744 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132744 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132744 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132744 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132744 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132744 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132744 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148647 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148647 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148647 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148647 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148647 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148647 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148647 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148647 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h148655 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148655 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148655 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148655 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148655 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148655 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148655 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148655 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148648 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148648 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148648 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148648 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148648 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148648 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148648 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148648 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148656 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148656 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148656 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148656 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148656 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148656 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148656 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148656 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48181 or - result__h48209 or - result__h48237 or - result__h48265 or - result__h48293 or - result__h48321 or result__h48349 or result__h48377) + result__h48189 or + result__h48217 or + result__h48245 or + result__h48273 or + result__h48301 or + result__h48329 or result__h48357 or result__h48385) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48181; + result__h48189; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48209; + result__h48217; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48237; + result__h48245; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48265; + result__h48273; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48293; + result__h48301; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48321; + result__h48329; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48349; + result__h48357; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48377; + result__h48385; endcase end always@(mmioPlatform_curReq or - result__h48422 or - result__h48450 or result__h48478 or result__h48506) + result__h48430 or + result__h48458 or result__h48486 or result__h48514) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48422; + result__h48430; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48450; + result__h48458; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48478; + result__h48486; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48506; + result__h48514; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48547 or result__h48575) + always@(mmioPlatform_curReq or result__h48555 or result__h48583) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48547; + result__h48555; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48575; + result__h48583; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -6552,102 +6562,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h48007 = + w2__h48015 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48007 = + w2__h48015 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - w2__h48007 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h48015 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h48007 = + w2__h48015 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w2___1__h48117 or + w2___1__h48125 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48013 = + w2__h48021 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48013 = + w2__h48021 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; - 2'b10: w2__h48013 = w2___1__h48117; + 2'b10: w2__h48021 = w2___1__h48125; 2'b11: - w2__h48013 = + w2__h48021 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_curReq or - result__h48934 or - result__h48961 or result__h48988 or result__h49015) + result__h48942 or + result__h48969 or result__h48996 or result__h49023) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48934; + result__h48942; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48961; + result__h48969; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48988; + result__h48996; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49015; + result__h49023; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48701 or - result__h48728 or - result__h48755 or - result__h48782 or - result__h48809 or - result__h48836 or result__h48863 or result__h48890) + result__h48709 or + result__h48736 or + result__h48763 or + result__h48790 or + result__h48817 or + result__h48844 or result__h48871 or result__h48898) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48701; + result__h48709; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48728; + result__h48736; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48755; + result__h48763; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48782; + result__h48790; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48809; + result__h48817; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48836; + result__h48844; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48863; + result__h48871; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48890; + result__h48898; endcase end - always@(mmioPlatform_curReq or result__h49055 or result__h49082) + always@(mmioPlatform_curReq or result__h49063 or result__h49090) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49055; + result__h49063; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49082; + result__h49090; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -6659,41 +6669,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h48006 = + w1__h48014 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48006 = + w1__h48014 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - w1__h48006 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h48014 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h48006 = + w1__h48014 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w1___1__h48116 or + w1___1__h48124 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48011 = + w1__h48019 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48011 = + w1__h48019 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; - 2'b10: w1__h48011 = w1___1__h48116; + 2'b10: w1__h48019 = w1___1__h48124; 2'b11: - w1__h48011 = + w1__h48019 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w18006_BITS_31_TO_0__q7 or + w18014_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) @@ -6705,7 +6715,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - { {32{w18006_BITS_31_TO_0__q7[31]}}, w18006_BITS_31_TO_0__q7 }; + { {32{w18014_BITS_31_TO_0__q7[31]}}, w18014_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; @@ -6714,7 +6724,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w28007_BITS_31_TO_0__q8 or + w28015_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) @@ -6726,115 +6736,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - { {32{w28007_BITS_31_TO_0__q8[31]}}, w28007_BITS_31_TO_0__q8 }; + { {32{w28015_BITS_31_TO_0__q8[31]}}, w28015_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49178 or - w2__h48013 or - op_result__h48614 or - op_result__h49144 or - op_result__h49149 or - op_result__h49154 or - op_result__h49172 or op_result__h49159 or op_result__h49165) + op_result__h49186 or + w2__h48021 or + op_result__h48622 or + op_result__h49152 or + op_result__h49157 or + op_result__h49162 or + op_result__h49180 or op_result__h49167 or op_result__h49173) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - w2__h48013; + w2__h48021; 4'd1: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h48614; + op_result__h48622; 4'd2: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49144; + op_result__h49152; 4'd3: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49149; + op_result__h49157; 4'd4: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49154; + op_result__h49162; 4'd5: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49172; + op_result__h49180; 4'd7: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49159; + op_result__h49167; 4'd8: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49165; + op_result__h49173; default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49178; + op_result__h49186; endcase end always@(mmioPlatform_curReq or - result__h49657 or - result__h49702 or result__h49768 or result__h49834) + result__h49665 or + result__h49710 or result__h49776 or result__h49842) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49657; + result__h49665; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49702; + result__h49710; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49768; + result__h49776; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49834; + result__h49842; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48057 or - result__h49199 or - result__h49265 or - result__h49331 or - result__h49397 or - result__h49463 or result__h49529 or result__h49595) + result__h48065 or + result__h49207 or + result__h49273 or + result__h49339 or + result__h49405 or + result__h49471 or result__h49537 or result__h49603) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h48057; + result__h48065; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49199; + result__h49207; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49265; + result__h49273; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49331; + result__h49339; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49397; + result__h49405; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49463; + result__h49471; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49529; + result__h49537; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49595; + result__h49603; endcase end - always@(mmioPlatform_curReq or result__h49892 or result__h49937) + always@(mmioPlatform_curReq or result__h49900 or result__h49945) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49892; + result__h49900; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49937; + result__h49945; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -6846,15 +6856,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h48002 = + x__h48010 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; 2'b01: - x__h48002 = + x__h48010 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; 2'b10: - x__h48002 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h48010 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h48002 = + x__h48010 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end @@ -6938,278 +6948,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; endcase end - always@(x__h61406 or n__read_id__h61592 or n__read_id__h61677) + always@(x__h61414 or n__read_id__h61600 or n__read_id__h61685) begin - case (x__h61406) - 1'd0: x__h61720 = n__read_id__h61592; - 1'd1: x__h61720 = n__read_id__h61677; + case (x__h61414) + 1'd0: x__h61728 = n__read_id__h61600; + 1'd1: x__h61728 = n__read_id__h61685; endcase end - always@(x__h61406 or n__read_child__h61593 or n__read_child__h61678) + always@(x__h61414 or n__read_child__h61601 or n__read_child__h61686) begin - case (x__h61406) - 1'd0: x__h61727 = n__read_child__h61593; - 1'd1: x__h61727 = n__read_child__h61678; + case (x__h61414) + 1'd0: x__h61735 = n__read_child__h61601; + 1'd1: x__h61735 = n__read_child__h61686; endcase end - always@(x__h61406 or + always@(x__h61414 or propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = + CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12 = propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; 1'd1: - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = + CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12 = propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; endcase end - always@(x__h61406 or + always@(x__h61414 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; 1'd1: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; endcase end - always@(x__h61406 or + always@(x__h61414 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; 1'd1: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; endcase end - always@(x__h61406 or n__read_addr__h61588 or n__read_addr__h61673) + always@(x__h61414 or n__read_addr__h61596 or n__read_addr__h61681) begin - case (x__h61406) + case (x__h61414) 1'd0: - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = - n__read_addr__h61588; + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15 = + n__read_addr__h61596; 1'd1: - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = - n__read_addr__h61673; + CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15 = + n__read_addr__h61681; endcase end - always@(x__h80291 or n__read_child__h80472 or n__read_child__h80551) + always@(x__h80299 or n__read_child__h80480 or n__read_child__h80559) begin - case (x__h80291) - 1'd0: x__h82707 = n__read_child__h80472; - 1'd1: x__h82707 = n__read_child__h80551; + case (x__h80299) + 1'd0: x__h82715 = n__read_child__h80480; + 1'd1: x__h82715 = n__read_child__h80559; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80291 or + always@(x__h80299 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80291 or + always@(x__h80299 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : 2'd0; 1'd1: - CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : 2'd0; endcase end - always@(x__h80291 or + always@(x__h80299 or NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; 1'd1: - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; endcase end - always@(x__h80291 or n__read_addr__h80469 or n__read_addr__h80548) + always@(x__h80299 or n__read_addr__h80477 or n__read_addr__h80556) begin - case (x__h80291) + case (x__h80299) 1'd0: - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = - n__read_addr__h80469; + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26 = + n__read_addr__h80477; 1'd1: - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = - n__read_addr__h80548; + CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26 = + n__read_addr__h80556; endcase end @@ -7625,14 +7635,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163686 = $stime; + v__h163696 = $stime; #0; end - v__h163680 = v__h163686 / 32'd10; + v__h163690 = v__h163696 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163680, + v__h163690, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -7653,17 +7663,17 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && + x__h61414 && NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && + x__h61414 && NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && + x__h61414 && NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) @@ -7683,17 +7693,17 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && + x__h80299 && NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && + x__h80299 && NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && + x__h80299 && NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) @@ -7702,14 +7712,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163250 = $stime; + v__h163258 = $stime; #0; end - v__h163244 = v__h163250 / 32'd10; + v__h163252 = v__h163258 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163244, + v__h163252, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7719,7 +7729,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163293); + $display("FAIL %0d", failed_testnum__h163301); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -7727,14 +7737,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5300 = $stime; + v__h5308 = $stime; #0; end - v__h5294 = v__h5300 / 32'd10; + v__h5302 = v__h5308 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5294); + $display("%0d: %m.rl_handle_read_rsps ", v__h5302); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7794,16 +7804,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5473 = $stime; + v__h5481 = $stime; #0; end - v__h5467 = v__h5473 / 32'd10; + v__h5475 = v__h5481 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5467); + v__h5475); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -7907,14 +7917,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5733 = $stime; + v__h5741 = $stime; #0; end - v__h5727 = v__h5733 / 32'd10; + v__h5735 = v__h5741 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5727); + $display("%d: %m.rl_handle_write_req: St request:", v__h5735); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8084,15 +8094,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h7875 = $stime; + v__h7883 = $stime; #0; end - v__h7869 = v__h7875 / 32'd10; + v__h7877 = v__h7883 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h7869); + $display("%0d: ERROR: CreditCounter: overflow", v__h7877); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8142,7 +8152,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7705); + $write("'h%h", x__h7713); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8273,16 +8283,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8090 = $stime; + v__h8098 = $stime; #0; end - v__h8084 = v__h8090 / 32'd10; + v__h8092 = v__h8098 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8084); + v__h8092); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8488,14 +8498,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2450 = $stime; + v__h2458 = $stime; #0; end - v__h2444 = v__h2450 / 32'd10; + v__h2452 = v__h2458 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2444); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2452); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8785,16 +8795,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4123 = $stime; + v__h4131 = $stime; #0; end - v__h4117 = v__h4123 / 32'd10; + v__h4125 = v__h4131 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4117); + v__h4125); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9000,14 +9010,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9260 = $stime; + v__h9268 = $stime; #0; end - v__h9254 = v__h9260 / 32'd10; + v__h9262 = v__h9268 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9254); + $display("%0d: %m.rl_discard_write_rsp", v__h9262); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9044,15 +9054,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9753 = $stime; + v__h9761 = $stime; #0; end - v__h9747 = v__h9753 / 32'd10; + v__h9755 = v__h9761 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9747); + v__h9755); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9092,14 +9102,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h9916 = $stime; + v__h9924 = $stime; #0; end - v__h9910 = v__h9916 / 32'd10; + v__h9918 = v__h9924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h9910); + v__h9918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9319,37 +9329,37 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42868 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42868 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 856, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42868 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40775 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40775 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 848, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40775 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9370,7 +9380,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__708_ETC___d1715 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9384,85 +9394,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h135207 = $stime; + v__h135215 = $stime; #0; end - v__h135201 = v__h135207 / 32'd10; + v__h135209 = v__h135215 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135201, + v__h135209, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135374 = $stime; + v__h135382 = $stime; #0; end - v__h135368 = v__h135374 / 32'd10; + v__h135376 = v__h135382 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135368); + v__h135376); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9524,135 +9534,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137477 = $stime; + v__h137485 = $stime; #0; end - v__h137471 = v__h137477 / 32'd10; + v__h137479 = v__h137485 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137471); + v__h137479); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -10850,169 +10860,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154821 = $stime; + v__h154829 = $stime; #0; end - v__h154815 = v__h154821 / 32'd10; + v__h154823 = v__h154829 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154815); + $display("%0d: ERROR: CreditCounter: overflow", v__h154823); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", mem_req_wr_addr_awaddr__h148732); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_wr_addr_awaddr__h148740); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", data64__h148647); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", data64__h148655); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", strb8__h148648); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", strb8__h148656); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134588 = $stime; + v__h134596 = $stime; #0; end - v__h134582 = v__h134588 / 32'd10; + v__h134590 = v__h134596 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134582, + v__h134590, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11083,159 +11093,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) - $write("'h%h", mem_req_rd_addr_araddr__h134808); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_rd_addr_araddr__h134816); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h161515 = $stime; + v__h161523 = $stime; #0; end - v__h161509 = v__h161515 / 32'd10; + v__h161517 = v__h161523 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161509, + v__h161517, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__782_U_ETC___d1799) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h162023 = $stime; + v__h162031 = $stime; #0; end - v__h162017 = v__h162023 / 32'd10; + v__h162025 = v__h162031 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h162017); + v__h162025); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v index 9e389f8..17388e5 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v @@ -360,7 +360,8 @@ module mkSoC_Top(RST_N_dm_power_on_reset, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule fabric wire [63 : 0] fabric$v_from_masters_0_araddr, @@ -859,17 +860,14 @@ module mkSoC_Top(RST_N_dm_power_on_reset, WILL_FIRE_to_raw_mem_request_get, WILL_FIRE_to_raw_mem_response_put; - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h11619; - reg [31 : 0] v__h11080; - reg [31 : 0] v__h11328; - reg [31 : 0] v__h11074; - reg [31 : 0] v__h11322; - reg [31 : 0] v__h11613; + reg [31 : 0] v__h11628; + reg [31 : 0] v__h11088; + reg [31 : 0] v__h11336; + reg [31 : 0] v__h11082; + reg [31 : 0] v__h11330; + reg [31 : 0] v__h11622; // synopsys translate_on // action method set_verbosity @@ -1088,6 +1086,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1734,25 +1733,22 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = + assign CAN_FIRE_RL_rl_reset_start_initial = mem0_controller$RDY_server_reset_request_put && uart0$RDY_server_reset_request_put && fabric$RDY_reset && rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && + assign WILL_FIRE_RL_rl_reset_start_initial = + CAN_FIRE_RL_rl_reset_start_initial ; + + // rule RL_rl_reset_complete_initial + assign CAN_FIRE_RL_rl_reset_complete_initial = mem0_controller$RDY_server_reset_response_get && uart0$RDY_server_reset_response_get && + mem0_controller$RDY_set_addr_map && rg_state == 2'd1 ; + assign WILL_FIRE_RL_rl_reset_complete_initial = + CAN_FIRE_RL_rl_reset_complete_initial ; // register rg_state assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; @@ -1791,7 +1787,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + assign boot_rom$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete_initial ; // submodule boot_rom_axi4_deburster assign boot_rom_axi4_deburster$from_master_araddr = @@ -1922,6 +1918,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign corew$set_verbosity_logdelay = set_verbosity_logdelay ; assign corew$set_verbosity_verbosity = set_verbosity_verbosity ; assign corew$start_fromhost_addr = start_fromhost_addr ; + assign corew$start_is_running = 1'd1 ; assign corew$start_tohost_addr = start_tohost_addr ; assign corew$EN_set_verbosity = EN_set_verbosity ; assign corew$EN_start = EN_start ; @@ -2037,7 +2034,7 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; + assign fabric$EN_reset = CAN_FIRE_RL_rl_reset_start_initial ; assign fabric$EN_set_verbosity = 1'b0 ; // submodule mem0_controller @@ -2106,10 +2103,11 @@ module mkSoC_Top(RST_N_dm_power_on_reset, mem0_controller_axi4_deburster$to_slave_wvalid ; assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; + CAN_FIRE_RL_rl_reset_start_initial ; assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + CAN_FIRE_RL_rl_reset_complete_initial ; + assign mem0_controller$EN_set_addr_map = + CAN_FIRE_RL_rl_reset_complete_initial ; assign mem0_controller$EN_to_raw_mem_request_get = EN_to_raw_mem_request_get ; assign mem0_controller$EN_to_raw_mem_response_put = @@ -2234,9 +2232,11 @@ module mkSoC_Top(RST_N_dm_power_on_reset, assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; + assign uart0$EN_server_reset_request_put = + CAN_FIRE_RL_rl_reset_start_initial ; + assign uart0$EN_server_reset_response_get = + CAN_FIRE_RL_rl_reset_complete_initial ; + assign uart0$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete_initial ; assign uart0$EN_get_to_console_get = EN_get_to_console_get ; assign uart0$EN_put_from_console_put = EN_put_from_console_put ; @@ -2273,36 +2273,36 @@ module mkSoC_Top(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h11619 = $stime; + v__h11628 = $stime; #0; end - v__h11613 = v__h11619 / 32'd10; + v__h11622 = v__h11628 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start (tohost %0h, fromhost %0h)", - v__h11613, + v__h11622, start_tohost_addr, start_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_start_initial) begin - v__h11080 = $stime; + v__h11088 = $stime; #0; end - v__h11074 = v__h11080 / 32'd10; + v__h11082 = v__h11088 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d: %m.rl_reset_start_initial ...", v__h11074); + $display("%0d: %m.rl_reset_start_initial ...", v__h11082); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete_initial) begin - v__h11328 = $stime; + v__h11336 = $stime; #0; end - v__h11322 = v__h11328 / 32'd10; + v__h11330 = v__h11336 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d: %m.rl_reset_complete_initial", v__h11322); + $display("%0d: %m.rl_reset_complete_initial", v__h11330); end // synopsys translate_on endmodule // mkSoC_Top diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk index 1772e71..c8ff4c3 100644 --- a/builds/Resources/Include_bluesim.mk +++ b/builds/Resources/Include_bluesim.mk @@ -28,6 +28,7 @@ BSC_C_FLAGS += \ -Xl -v \ -Xc -O1 -Xc++ -O1 \ + # For Bluespec_2019.05.beta2-debian9stretch-amd64 # you may have to remove the line: -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0 diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 0bb4aac..be88f0d 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -108,6 +108,7 @@ import Trace_Data2 :: *; interface CoreReq; method Action start( + Bool running, Addr startpc, Addr toHostAddr, Addr fromHostAddr ); @@ -1206,7 +1207,9 @@ module mkCore#(CoreId coreId)(Core); // Debugger 'halt' request (e.g., GDB '^C' command) // This is initiated just like an interrupt. +`ifdef INCLUDE_GDB_CONTROL renameStage.debug_halt_req; +`endif if (show_DM_interactions) $display ("%0d: %m.rl_debug_halt_req", cur_cycle); @@ -1296,10 +1299,14 @@ module mkCore#(CoreId coreId)(Core); interface CoreReq coreReq; method Action start( + Bool running, Bit#(64) startpc, Addr toHostAddr, Addr fromHostAddr ); - fetchStage.start(startpc); +`ifdef INCLUDE_GDB_CONTROL + if (!running) renameStage.debug_halt_req; +`endif + fetchStage.start(startpc); started <= True; `ifdef INCLUDE_GDB_CONTROL rg_core_run_state <= CORE_RUNNING; diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index 6cd20d4..515c93e 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -233,10 +233,10 @@ module mkProc (Proc_IFC); // ---------------- // Start the cores running // Use toHostAddr = 0 if not monitoring tohost - method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr); + method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr); action for(Integer i = 0; i < valueof(CoreNum); i = i+1) - core[i].coreReq.start (startpc, tohostAddr, fromhostAddr); + core[i].coreReq.start (running, startpc, tohostAddr, fromhostAddr); endaction mmioPlatform.start (tohostAddr, fromhostAddr); diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index a2d4576..5611260 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -38,7 +38,7 @@ interface Proc_IFC; // ---------------- // Start the cores running // Use toHostAddr = 0 if not monitoring tohost - method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr); + method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr); // ---------------- // SoC fabric connections diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 677dbf3..3b15d5a 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -189,10 +189,9 @@ module mkCoreW #(Reset dm_power_on_reset) rule rl_dm_hart0_reset_wait (rg_hart0_reset_delay != 0); if (rg_hart0_reset_delay == 1) begin - let pc = soc_map_struct.pc_reset_value; - proc.start (pc, rg_tohost_addr, rg_fromhost_addr); - + let pc = soc_map_struct.pc_reset_value; Bool is_running = True; + proc.start (is_running, pc, rg_tohost_addr, rg_fromhost_addr); debug_module.hart0_reset_client.response.put (is_running); $display ("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr); @@ -362,12 +361,12 @@ module mkCoreW #(Reset dm_power_on_reset) // ---------------------------------------------------------------- // Start - method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base), zeroExtend (soc_map.m_plic_addr_lim)); let pc = soc_map_struct.pc_reset_value; - proc.start (pc, tohost_addr, fromhost_addr); + proc.start (is_running, pc, tohost_addr, fromhost_addr); `ifdef INCLUDE_GDB_CONTROL // Save for potential future use by rl_dm_hart0_reset diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv index 21b8928..fbcf5f6 100644 --- a/src_Core/Core/CoreW_IFC.bsv +++ b/src_Core/Core/CoreW_IFC.bsv @@ -54,7 +54,7 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources); // ---------------------------------------------------------------- // Start - method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); // ---------------------------------------------------------------- // AXI4 Fabric interfaces diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile index 13aee7e..9d4462a 100644 --- a/src_SSITH_P3/Makefile +++ b/src_SSITH_P3/Makefile @@ -33,12 +33,12 @@ BSC_COMPILATION_FLAGS += \ -D INCLUDE_GDB_CONTROL \ -D INCLUDE_TANDEM_VERIF \ -D BRVF_TRACE \ - -D JTAG_TAP \ + -D XILINX_BSCAN -D JTAG_TAP # Synth only BSC_COMPILATION_FLAGS -SYNTH_BSC_OPTIONS = -D XILINX_BSCAN -D XILINX_XCVU9P +SYNTH_BSC_OPTIONS = -D XILINX_XCVU9P -# Sim only BSC_COMPILATION_FLAGS +# Sim only BSC_COMPILATION_FLAGS SIM_BSC_OPTIONS = -D BSIM # Only used if we don't have INCLUDE_GDB_CONTROL diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 0452f06..76bc0cb 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -6,7 +6,7 @@ // // Ports: // Name I/O size props -// RDY_coreReq_start O 1 const +// RDY_coreReq_start O 1 // RDY_coreReq_perfReq O 1 reg // coreIndInv_perfResp O 73 // RDY_coreIndInv_perfResp O 1 reg @@ -104,6 +104,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -184,6 +185,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -402,6 +404,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4314,7 +4317,7 @@ module mkCore(CLK, wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, - MUX_l2Tlb$updateVMInfo_1__VAL_1; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, @@ -4464,9 +4467,10 @@ module mkCore(CLK, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, MUX_regRenamingTable$rename_0_getRename_1__SEL_3, - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_2, + MUX_renameStage_rg_m_halt_req$write_1__SEL_3, + MUX_renameStage_rg_m_halt_req$write_1__SEL_6, MUX_rf$write_3_wr_1__PSEL_5, MUX_rf$write_3_wr_1__SEL_1, MUX_rf$write_3_wr_1__SEL_2, @@ -4521,24 +4525,24 @@ module mkCore(CLK, reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4550,20 +4554,20 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84, - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85, + reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82, + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122, CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51, @@ -4572,8 +4576,8 @@ module mkCore(CLK, CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85, _theResult___fst_sfd__h346070, _theResult___fst_sfd__h354793, _theResult___fst_sfd__h363375, @@ -4609,7 +4613,7 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248, + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, @@ -4631,8 +4635,8 @@ module mkCore(CLK, CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, @@ -4698,8 +4702,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21, CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, @@ -4743,7 +4747,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, @@ -4767,22 +4771,22 @@ module mkCore(CLK, CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191, + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, @@ -4790,11 +4794,11 @@ module mkCore(CLK, CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, @@ -4872,19 +4876,19 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080; wire [463 : 0] commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942; wire [457 : 0] rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; wire [393 : 0] IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; wire [181 : 0] fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; @@ -5844,7 +5848,7 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106, x__h181701, x__h713427; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, @@ -6320,7 +6324,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911, - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388, + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388, NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667, NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008, NOT_rob_deqPort_1_deq_data__5354_BIT_25_5355_5_ETC___d15385, @@ -6390,7 +6394,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo22, + _dfoo20, _dfoo24, _dfoo26, _dfoo32, @@ -6535,7 +6539,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909, f_csr_rsps_i_notFull__5799_AND_f_csr_reqs_firs_ETC___d15902, - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093, + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191, @@ -6586,7 +6590,7 @@ module mkCore(CLK, next_deqP___1__h332215, r1__read_BIT_20___h655898, r__h614580, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956, regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037, regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444, @@ -6611,7 +6615,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935, rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15738, - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013, + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, @@ -6630,8 +6634,8 @@ module mkCore(CLK, x__h603386; // action method coreReq_start - assign RDY_coreReq_start = 1'd1 ; - assign CAN_FIRE_coreReq_start = 1'd1 ; + assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; + assign CAN_FIRE_coreReq_start = !renameStage_rg_m_halt_req[4] ; assign WILL_FIRE_coreReq_start = EN_coreReq_start ; // action method coreReq_perfReq @@ -6668,7 +6672,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6688,7 +6692,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9946,7 +9950,8 @@ module mkCore(CLK, f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] && rg_core_run_state == 2'd2 && !f_run_halt_reqs$D_OUT ; - assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ; + assign WILL_FIRE_RL_rl_debug_halt_req = + CAN_FIRE_RL_rl_debug_halt_req && !EN_coreReq_start ; // rule RL_rl_debug_halt_req_already_halted assign CAN_FIRE_RL_rl_debug_halt_req_already_halted = @@ -10371,8 +10376,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10408,7 +10413,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 && + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10443,7 +10448,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 && + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15400 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11412,9 +11417,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11422,19 +11428,21 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_csrInstOrInterruptInflight_canon assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; @@ -11479,7 +11487,8 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_mmio_pRqQ_canonicalize assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ; @@ -11952,16 +11961,17 @@ module mkCore(CLK, WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; - assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst || - WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 = - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 && - csrf_rg_dcsr[2] ; - assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_3 = + WILL_FIRE_RL_renameStage_doRenaming_Trap && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_6 = + EN_coreReq_start && !coreReq_start_running ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && coreFix_memExe_lsq$firstSt[150] ; @@ -12459,6 +12469,12 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738339 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or next_pc__h723452 or csrf_sepc_csr or csrf_mepc_csr) begin @@ -12474,12 +12490,6 @@ module mkCore(CLK, coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 = { 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ; - assign MUX_l2Tlb$updateVMInfo_1__VAL_1 = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], @@ -14811,7 +14821,7 @@ module mkCore(CLK, assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15103,21 +15113,24 @@ module mkCore(CLK, assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; // register renameStage_rg_m_halt_req - always@(WILL_FIRE_RL_rl_debug_resume or + always@(MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_3 or + WILL_FIRE_RL_rl_debug_resume or WILL_FIRE_RL_rl_debug_halt_req or - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or - MUX_renameStage_rg_m_halt_req$write_1__SEL_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; - WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30; - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || - MUX_renameStage_rg_m_halt_req$write_1__SEL_2: - renameStage_rg_m_halt_req$D_IN = 5'd31; - default: renameStage_rg_m_halt_req$D_IN = - 5'b01010 /* unspecified value */ ; - endcase - end + MUX_renameStage_rg_m_halt_req$write_1__SEL_6) + case (1'b1) + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_3: + renameStage_rg_m_halt_req$D_IN = 5'd31; + WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; + WILL_FIRE_RL_rl_debug_halt_req || + MUX_renameStage_rg_m_halt_req$write_1__SEL_6: + renameStage_rg_m_halt_req$D_IN = 5'd30; + default: renameStage_rg_m_halt_req$D_IN = + 5'b01010 /* unspecified value */ ; + endcase assign renameStage_rg_m_halt_req$EN = (WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap) && @@ -15125,6 +15138,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] || + EN_coreReq_start && !coreReq_start_running || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15157,7 +15171,7 @@ module mkCore(CLK, !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data @@ -18150,8 +18164,8 @@ module mkCore(CLK, assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; @@ -18310,8 +18324,8 @@ module mkCore(CLK, MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; assign l2Tlb$updateVMInfo_vmI = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign l2Tlb$EN_updateVMInfo = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_rl_debug_resume ; @@ -20845,8 +20859,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20878,8 +20892,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21439,8 +21453,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21450,8 +21464,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = (_theResult___fst_exp__h519940 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -22132,8 +22146,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || @@ -22158,8 +22172,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? 4'd0 : @@ -24166,10 +24180,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149 = @@ -24183,10 +24197,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 && IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093) ; + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && @@ -25474,9 +25488,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 ; - assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 = + assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25515,7 +25529,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022 = !specTagManager$canClaim || @@ -25549,21 +25563,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, x__h291618 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = @@ -26616,7 +26630,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo22 = + assign _dfoo20 = commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign _dfoo24 = @@ -28089,7 +28103,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 : + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; assign _theResult___fst_exp__h598880 = (_theResult___fst_exp__h598097 == 11'd2047) ? @@ -28220,7 +28234,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 : + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; assign _theResult___fst_sfd__h502289 = (_theResult___fst_exp__h501530 == 11'd2047) ? @@ -28231,7 +28245,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; assign _theResult___fst_sfd__h511940 = (_theResult___fst_exp__h511107 == 11'd2047) ? @@ -28242,7 +28256,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 : + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; assign _theResult___fst_sfd__h520724 = (_theResult___fst_exp__h519940 == 11'd2047) ? @@ -28283,7 +28297,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 : + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; assign _theResult___fst_sfd__h550793 = (_theResult___fst_exp__h549960 == 11'd2047) ? @@ -28294,7 +28308,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 : + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; assign _theResult___fst_sfd__h559577 = (_theResult___fst_exp__h558793 == 11'd2047) ? @@ -30231,12 +30245,14 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609378 = { 56'd0, x__h613036 } ; - assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31048,14 +31064,13 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; assign r__h614580 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31553,13 +31568,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612208 = { r1__read__h614606, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; + assign rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -31582,11 +31596,11 @@ module mkCore(CLK, assign rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 } ; + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; assign rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520 = { rob$deqPort_0_deq_data[181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 } ; + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; assign rs1__h655333 = @@ -33134,6 +33148,23 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33162,23 +33193,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19]) @@ -33555,69 +33569,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h381194 = 8'd0; endcase end - always@(guard__h346097 or - sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0, 2'b01: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - sfdin__h354192[56:34]; - 2'b10: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - out_sfd__h354718; - 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - _theResult___sfd__h354715; - endcase - end - always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - sfdin__h354192[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - _theResult___sfd__h354715; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354192) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47; - 3'd1: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48; - 3'd2: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; - 3'd3: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; - default: _theResult___fst_sfd__h354793 = 23'd0; - endcase - end always@(guard__h354806 or _theResult___snd__h362805 or out_sfd__h363300 or _theResult___sfd__h363297) begin case (guard__h354806) 2'b0, 2'b01: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___snd__h362805[56:34]; 2'b10: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = out_sfd__h363300; 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___sfd__h363297; endcase end @@ -33626,16 +33590,16 @@ module mkCore(CLK, begin case (guard__h354806) 2'b0: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___snd__h362805[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___sfd__h363297; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or _theResult___snd__h362805) @@ -33643,10 +33607,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47; 3'd1: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48; 3'd2: _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; @@ -33657,6 +33621,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h363375 = 23'd0; endcase end + always@(guard__h346097 or + sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0, 2'b01: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354192[56:34]; + 2'b10: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354718; + 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354715; + endcase + end + always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354192[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354715; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or + sfdin__h354192) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49; + 3'd1: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50; + 3'd2: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; + 3'd3: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; + 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; + default: _theResult___fst_sfd__h354793 = 23'd0; + endcase + end always@(guard__h363736 or sfdin__h371958 or out_sfd__h372484 or _theResult___sfd__h372481) begin @@ -33797,66 +33811,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354806 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h354806) - 2'b0, 2'b01, 2'b10: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - guard__h354806 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or - guard__h354806) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354806 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || - guard__h354806 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = (guard__h346097 == 2'b0) ? @@ -33873,6 +33849,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h354806 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h354806) + 2'b0, 2'b01, 2'b10: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354806 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354806) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + (guard__h354806 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || + guard__h354806 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34297,69 +34311,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h426891 = 8'd0; endcase end - always@(guard__h391796 or - sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0, 2'b01: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - sfdin__h399889[56:34]; - 2'b10: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - out_sfd__h400415; - 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - _theResult___sfd__h400412; - endcase - end - always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - sfdin__h399889[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - _theResult___sfd__h400412; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399889) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82; - 3'd1: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83; - 3'd2: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; - 3'd3: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; - default: _theResult___fst_sfd__h400490 = 23'd0; - endcase - end always@(guard__h400503 or _theResult___snd__h408502 or out_sfd__h408997 or _theResult___sfd__h408994) begin case (guard__h400503) 2'b0, 2'b01: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___snd__h408502[56:34]; 2'b10: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = out_sfd__h408997; 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___sfd__h408994; endcase end @@ -34368,16 +34332,16 @@ module mkCore(CLK, begin case (guard__h400503) 2'b0: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___snd__h408502[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___sfd__h408994; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or _theResult___snd__h408502) @@ -34385,10 +34349,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82; 3'd1: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83; 3'd2: _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; @@ -34399,6 +34363,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h409072 = 23'd0; endcase end + always@(guard__h391796 or + sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0, 2'b01: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399889[56:34]; + 2'b10: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400415; + 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400412; + endcase + end + always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399889[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400412; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or + sfdin__h399889) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84; + 3'd1: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85; + 3'd2: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; + 3'd3: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; + 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; + default: _theResult___fst_sfd__h400490 = 23'd0; + endcase + end always@(guard__h409433 or sfdin__h417655 or out_sfd__h418181 or _theResult___sfd__h418178) begin @@ -34734,61 +34748,23 @@ module mkCore(CLK, begin case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or - guard__h418269) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418269 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h418269 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h418269) - 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = guard__h418269 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = (guard__h418269 == 2'b0) ? @@ -34805,6 +34781,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end + always@(guard__h418269 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h418269) + 2'b0, 2'b01, 2'b10: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418269) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + (guard__h418269 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -35821,21 +35835,21 @@ module mkCore(CLK, _theResult___exp__h580342; endcase end - always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581038) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h581038 == 2'b11 && + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571726 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35844,12 +35858,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h581038 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || - guard__h581038 == 2'b11) && + (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || + guard__h571726 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35860,21 +35874,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571726) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h571726 == 2'b11 && + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581038 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35883,12 +35897,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h571726 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || - guard__h571726 == 2'b11) && + (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || + guard__h581038 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36259,57 +36273,15 @@ module mkCore(CLK, _theResult___exp__h589993; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - guard__h532422 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || - guard__h532422 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h590107 or _theResult___fst_exp__h598097 or _theResult___exp__h598777) begin case (guard__h590107) 2'b0: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___fst_exp__h598097; 2'b01, 2'b10, 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___exp__h598777; endcase end @@ -36317,7 +36289,7 @@ module mkCore(CLK, _theResult___fst_exp__h598097 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193) + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36331,7 +36303,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase @@ -36342,13 +36314,13 @@ module mkCore(CLK, begin case (guard__h590107) 2'b0, 2'b01: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___fst_exp__h598097; 2'b10: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = out_exp__h598780; 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___exp__h598777; endcase end @@ -36356,12 +36328,12 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = guard__h541734 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36372,12 +36344,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36387,6 +36359,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h532422 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || + guard__h532422 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -36478,58 +36492,16 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36540,12 +36512,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36555,6 +36527,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -36613,65 +36627,14 @@ module mkCore(CLK, _theResult___sfd__h541039; endcase end - always@(guard__h550803 or - _theResult___snd__h558739 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___snd__h558739[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___sfd__h559474; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558739 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558739[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - 52'd0; - endcase - end - always@(guard__h550803 or - _theResult___snd__h558739 or - out_sfd__h559477 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0, 2'b01: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___snd__h558739[56:5]; - 2'b10: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - out_sfd__h559477; - 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___sfd__h559474; - endcase - end always@(guard__h541734 or sfdin__h549954 or _theResult___sfd__h550690) begin case (guard__h541734) 2'b0: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = sfdin__h549954[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = _theResult___sfd__h550690; endcase end @@ -36679,7 +36642,7 @@ module mkCore(CLK, sfdin__h549954 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209) + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36693,7 +36656,7 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase @@ -36703,16 +36666,67 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = sfdin__h549954[56:5]; 2'b10: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = out_sfd__h550693; 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = _theResult___sfd__h550690; endcase end + always@(guard__h550803 or + _theResult___snd__h558739 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___snd__h558739[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___sfd__h559474; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h558739 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + _theResult___snd__h558739[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + 52'd0; + endcase + end + always@(guard__h550803 or + _theResult___snd__h558739 or + out_sfd__h559477 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0, 2'b01: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___snd__h558739[56:5]; + 2'b10: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + out_sfd__h559477; + 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___sfd__h559474; + endcase + end always@(guard__h502881 or _theResult___fst_exp__h511107 or _theResult___exp__h511836) begin @@ -36815,64 +36829,15 @@ module mkCore(CLK, _theResult___exp__h520620; endcase end - always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h511101[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h511837; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511101 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511101[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - 52'd0; - endcase - end - always@(guard__h502881 or - sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0, 2'b01: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h511101[56:5]; - 2'b10: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h511840; - 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h511837; - endcase - end always@(guard__h493569 or _theResult___snd__h501481 or _theResult___sfd__h502186) begin case (guard__h493569) 2'b0: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___snd__h501481[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___sfd__h502186; endcase end @@ -36880,7 +36845,7 @@ module mkCore(CLK, _theResult___snd__h501481 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217) + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36894,7 +36859,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase @@ -36905,13 +36870,13 @@ module mkCore(CLK, begin case (guard__h493569) 2'b0, 2'b01: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___snd__h501481[56:5]; 2'b10: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = out_sfd__h502189; 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___sfd__h502186; endcase end @@ -36920,10 +36885,10 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___snd__h519886[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___sfd__h520621; endcase end @@ -36931,7 +36896,7 @@ module mkCore(CLK, _theResult___snd__h519886 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219) + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36945,7 +36910,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase @@ -36956,16 +36921,65 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0, 2'b01: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___snd__h519886[56:5]; 2'b10: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = out_sfd__h520624; 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___sfd__h520621; endcase end + always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h511101[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h511837; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h511101 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + sfdin__h511101[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + 52'd0; + endcase + end + always@(guard__h502881 or + sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0, 2'b01: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + sfdin__h511101[56:5]; + 2'b10: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + out_sfd__h511840; + 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + _theResult___sfd__h511837; + endcase + end always@(guard__h571726 or _theResult___snd__h579638 or _theResult___sfd__h580343) begin @@ -38031,10 +38045,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -38042,10 +38056,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -38350,38 +38364,6 @@ module mkCore(CLK, endcase end always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) 12'd1, @@ -38428,12 +38410,44 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = 12'd2303; endcase end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + 4'd15; + endcase + end always@(commitStage_f_rob_data$D_OUT) begin case (commitStage_f_rob_data$D_OUT[97:96]) diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index bb0d3be..607e8ac 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -78,6 +78,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// start_is_running I 1 // start_tohost_addr I 64 // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 @@ -161,6 +162,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -379,6 +381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1401,7 +1404,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1609,12 +1613,12 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5047; - reg [31 : 0] v__h5190; - reg [31 : 0] v__h15930; - reg [31 : 0] v__h5041; - reg [31 : 0] v__h5184; - reg [31 : 0] v__h15924; + reg [31 : 0] v__h5055; + reg [31 : 0] v__h5198; + reg [31 : 0] v__h15940; + reg [31 : 0] v__h5049; + reg [31 : 0] v__h5192; + reg [31 : 0] v__h15934; // synopsys translate_on // remaining internal signals @@ -2523,6 +2527,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2716,22 +2721,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -3359,6 +3364,7 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_proc$start_1__SEL_1 ? rg_fromhost_addr : start_fromhost_addr ; + assign proc$start_running = MUX_proc$start_1__SEL_1 || start_is_running ; assign proc$start_startpc = 64'h0000000070000000 ; assign proc$start_tohostAddr = MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; @@ -3700,15 +3706,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h5047 = $stime; + v__h5055 = $stime; #0; end - v__h5041 = v__h5047 / 32'd10; + v__h5049 = v__h5055 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h5041, + v__h5049, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -3716,17 +3722,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h5190 = $stime; + v__h5198 = $stime; #0; end - v__h5184 = v__h5190 / 32'd10; + v__h5192 = v__h5198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h5184, + v__h5192, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); @@ -3734,15 +3740,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15930 = $stime; + v__h15940 = $stime; #0; end - v__h15924 = v__h15930 / 32'd10; + v__h15934 = v__h15940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15924, + v__h15934, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v index 7ed7f93..e079454 100644 --- a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v @@ -130,17 +130,13 @@ module mkJtagTap(CLK, // inlined wires wire [40 : 0] w_dmi_req$wget; - wire r_dmistat_busy$port1__read, + wire r_dmistat_busy$EN_port1__write, + r_dmistat_busy$port1__read, r_dmistat_busy$port2__read, r_tdo$EN_port0__write, r_tdo$port0__write_1, r_tdo$port1__read; - // register r_dmi - reg [39 : 0] r_dmi; - wire [39 : 0] r_dmi$D_IN; - wire r_dmi$EN; - // register r_dmistat_busy reg r_dmistat_busy; wire r_dmistat_busy$D_IN, r_dmistat_busy$EN; @@ -160,11 +156,6 @@ module mkJtagTap(CLK, wire [17 : 0] r_ir$D_IN; wire r_ir$EN; - // register r_state - reg [3 : 0] r_state; - wire [3 : 0] r_state$D_IN; - wire r_state$EN; - // register r_tdo reg r_tdo; wire r_tdo$D_IN, r_tdo$EN; @@ -179,6 +170,7 @@ module mkJtagTap(CLK, // ports of submodule f_dmi_req wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN; wire f_dmi_req$dCLR, + f_dmi_req$dCLR_RDY, f_dmi_req$dDEQ, f_dmi_req$dEMPTY_N, f_dmi_req$sCLR, @@ -193,18 +185,32 @@ module mkJtagTap(CLK, f_dmi_rsp$dDEQ, f_dmi_rsp$dEMPTY_N, f_dmi_rsp$sCLR, + f_dmi_rsp$sCLR_RDY, f_dmi_rsp$sENQ, f_dmi_rsp$sFULL_N; + // ports of submodule r_dmi + wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT; + wire r_dmi$EN; + + // ports of submodule r_initialize + wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT; + + // ports of submodule r_initialize2 + wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT; + + // ports of submodule r_state + wire [3 : 0] r_state$D_IN, r_state$Q_OUT; + wire r_state$EN; + // ports of submodule rst_tck wire rst_tck$OUT_RST; // ports of submodule tck_clock - wire tck_clock$CLK_IN, - tck_clock$CLK_IN_EN, - tck_clock$CLK_OUT, - tck_clock$COND_IN, - tck_clock$COND_IN_EN; + wire tck_clock$IN, tck_clock$OUT; + + // ports of submodule w_tck_crossed + wire w_tck_crossed$DOUT; // rule scheduling signals wire CAN_FIRE_RL_dmi_request, @@ -215,7 +221,9 @@ module mkJtagTap(CLK, CAN_FIRE_RL_dmi_response_ready, CAN_FIRE_RL_dmi_response_tck, CAN_FIRE_RL_dmi_start, - CAN_FIRE_RL_rl_tck, + CAN_FIRE_RL_mkConnectionVtoAf, + CAN_FIRE_RL_rl_initialize, + CAN_FIRE_RL_rl_initialize2, CAN_FIRE_RL_tick, CAN_FIRE_dmi_req_ready, CAN_FIRE_dmi_rsp_data, @@ -232,7 +240,9 @@ module mkJtagTap(CLK, WILL_FIRE_RL_dmi_response_ready, WILL_FIRE_RL_dmi_response_tck, WILL_FIRE_RL_dmi_start, - WILL_FIRE_RL_rl_tck, + WILL_FIRE_RL_mkConnectionVtoAf, + WILL_FIRE_RL_rl_initialize, + WILL_FIRE_RL_rl_initialize2, WILL_FIRE_RL_tick, WILL_FIRE_dmi_req_ready, WILL_FIRE_dmi_rsp_data, @@ -243,24 +253,24 @@ module mkJtagTap(CLK, WILL_FIRE_jtag_tms; // remaining internal signals - reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, - v__h2135; - reg [17 : 0] newir__h3435; - reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3, - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2; - wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140, - v__h2233, - v__h2601, - x__h2449, - x__h2658, - y__h2659; - wire [17 : 0] v__h3299, x__h3350, y__h3351; - wire r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72; + reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, + v__h2479; + reg [17 : 0] newir__h3774; + reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3, + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2; + wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146, + v__h2576, + v__h2941, + x__h2789, + x__h2996, + y__h2997; + wire [17 : 0] v__h3636, x__h3687, y__h3688; + wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78; // oscillator and gates for output clock CLK_jtag_tclk_out - assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ; + assign CLK_jtag_tclk_out = tck_clock$OUT ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; // action method jtag_tdi @@ -311,7 +321,7 @@ module mkJtagTap(CLK, // submodule f_dmi_busy FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST), - .CLK(tck_clock$CLK_OUT), + .CLK(tck_clock$OUT), .ENQ(f_dmi_busy$ENQ), .DEQ(f_dmi_busy$DEQ), .CLR(f_dmi_busy$CLR), @@ -321,7 +331,7 @@ module mkJtagTap(CLK, // submodule f_dmi_req SyncFIFOLevel #(.dataWidth(32'd41), .depth(32'd2), - .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT), + .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT), .dCLK(CLK), .sRST(rst_tck$OUT_RST), .sD_IN(f_dmi_req$sD_IN), @@ -335,13 +345,13 @@ module mkJtagTap(CLK, .dCOUNT(), .sCOUNT(), .sCLR_RDY(f_dmi_req$sCLR_RDY), - .dCLR_RDY()); + .dCLR_RDY(f_dmi_req$dCLR_RDY)); // submodule f_dmi_rsp SyncFIFOLevel #(.dataWidth(32'd40), .depth(32'd2), .indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK), - .dCLK(tck_clock$CLK_OUT), + .dCLK(tck_clock$OUT), .sRST(RST_N), .sD_IN(f_dmi_rsp$sD_IN), .sENQ(f_dmi_rsp$sENQ), @@ -353,29 +363,46 @@ module mkJtagTap(CLK, .dEMPTY_N(f_dmi_rsp$dEMPTY_N), .dCOUNT(), .sCOUNT(), - .sCLR_RDY(), + .sCLR_RDY(f_dmi_rsp$sCLR_RDY), .dCLR_RDY(f_dmi_rsp$dCLR_RDY)); + // submodule r_dmi + RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT), + .D_IN(r_dmi$D_IN), + .EN(r_dmi$EN), + .Q_OUT(r_dmi$Q_OUT)); + + // submodule r_initialize + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT), + .D_IN(r_initialize$D_IN), + .EN(r_initialize$EN), + .Q_OUT(r_initialize$Q_OUT)); + + // submodule r_initialize2 + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK), + .D_IN(r_initialize2$D_IN), + .EN(r_initialize2$EN), + .Q_OUT(r_initialize2$Q_OUT)); + + // submodule r_state + RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT), + .D_IN(r_state$D_IN), + .EN(r_state$EN), + .Q_OUT(r_state$Q_OUT)); + // submodule rst_tck - SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT), - .IN_RST(RST_N), - .OUT_RST(rst_tck$OUT_RST)); + SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST)); // submodule tck_clock - MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK), - .RST(RST_N), - .CLK_IN(tck_clock$CLK_IN), - .COND_IN(tck_clock$COND_IN), - .CLK_IN_EN(tck_clock$CLK_IN_EN), - .COND_IN_EN(tck_clock$COND_IN_EN), - .CLK_VAL_OUT(), - .COND_OUT(), - .CLK_GATE_OUT(), - .CLK_OUT(tck_clock$CLK_OUT)); + ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT)); - // rule RL_rl_tck - assign CAN_FIRE_RL_rl_tck = 1'd1 ; - assign WILL_FIRE_RL_rl_tck = 1'd1 ; + // submodule w_tck_crossed + SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk), + .DOUT(w_tck_crossed$DOUT)); + + // rule RL_mkConnectionVtoAf + assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; + assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ; // rule RL_tick assign CAN_FIRE_RL_tick = 1'd1 ; @@ -383,7 +410,7 @@ module mkJtagTap(CLK, // rule RL_dmi_start assign CAN_FIRE_RL_dmi_start = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 && f_dmi_req$sFULL_N && f_dmi_busy$FULL_N && w_dmi_req$wget[1:0] != 2'd0 ; @@ -406,9 +433,14 @@ module mkJtagTap(CLK, f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ; assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ; + // rule RL_rl_initialize + assign CAN_FIRE_RL_rl_initialize = + r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ; + // rule RL_dmi_reset assign CAN_FIRE_RL_dmi_reset = - r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 && (!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ; assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ; @@ -420,35 +452,37 @@ module mkJtagTap(CLK, assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ; assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ; + // rule RL_rl_initialize2 + assign CAN_FIRE_RL_rl_initialize2 = + f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ; + // inlined wires assign w_dmi_req$wget = { 1'd0, r_dr } ; - assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ; - assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ; + assign r_tdo$EN_port0__write = + r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ; + assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ; assign r_tdo$port1__read = r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ; assign r_dmistat_busy$port1__read = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 || + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 || r_dmistat_busy ; + assign r_dmistat_busy$EN_port1__write = + WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ; assign r_dmistat_busy$port2__read = - !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ; - - // register r_dmi - assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; - assign r_dmi$EN = - WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 ; + !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ; // register r_dmistat_busy assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ; assign r_dmistat_busy$EN = 1'b1 ; // register r_dr - always@(r_state or r_dr or v__h2135 or v__h2601) + always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941) begin - case (r_state) + case (r_state$Q_OUT) 4'd0: r_dr$D_IN = r_dr; - 4'd3: r_dr$D_IN = v__h2135; - 4'd4: r_dr$D_IN = v__h2601; + 4'd3: r_dr$D_IN = v__h2479; + 4'd4: r_dr$D_IN = v__h2941; default: r_dr$D_IN = r_dr; endcase end @@ -456,22 +490,15 @@ module mkJtagTap(CLK, // register r_drmask assign r_drmask$D_IN = - (r_state == 4'd3) ? - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : + (r_state$Q_OUT == 4'd3) ? + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : r_drmask ; assign r_drmask$EN = 1'd1 ; // register r_ir - assign r_ir$D_IN = newir__h3435 ; + assign r_ir$D_IN = newir__h3774 ; assign r_ir$EN = 1'd1 ; - // register r_state - assign r_state$D_IN = - jtag_tms ? - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 : - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ; - assign r_state$EN = 1'd1 ; - // register r_tdo assign r_tdo$D_IN = r_tdo$port1__read ; assign r_tdo$EN = 1'b1 ; @@ -479,69 +506,89 @@ module mkJtagTap(CLK, // submodule f_dmi_busy assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + assign f_dmi_busy$CLR = + WILL_FIRE_RL_dmi_reset && r_dr[17] || + WILL_FIRE_RL_rl_initialize ; // submodule f_dmi_req assign f_dmi_req$sD_IN = w_dmi_req$wget ; assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ; assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; - assign f_dmi_req$dCLR = 1'b0 ; + assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ; // submodule f_dmi_rsp assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ; assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ; assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_rsp$sCLR = 1'b0 ; + assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ; assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + // submodule r_dmi + assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; + assign r_dmi$EN = + WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 ; + + // submodule r_initialize + assign r_initialize$D_IN = 1'd0 ; + assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ; + + // submodule r_initialize2 + assign r_initialize2$D_IN = 1'd0 ; + assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ; + + // submodule r_state + assign r_state$D_IN = + jtag_tms ? + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 : + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ; + assign r_state$EN = 1'd1 ; + // submodule tck_clock - assign tck_clock$CLK_IN = jtag_tclk ; - assign tck_clock$COND_IN = 1'b0 ; - assign tck_clock$CLK_IN_EN = 1'd1 ; - assign tck_clock$COND_IN_EN = 1'b0 ; + assign tck_clock$IN = w_tck_crossed$DOUT ; // remaining internal signals - assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 = + assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 = (r_dmistat_busy || - r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N) ? 40'hAAAAAAAAAB : - r_dmi ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 = - r_state == 4'd8 && r_ir == 18'b100010100100100100 && + r_dmi$Q_OUT ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b100010100100100100 && (r_dr[17] || r_dr[16]) ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && !f_dmi_busy$EMPTY_N ; - assign v__h2233 = { 22'd960, r_ir } ; - assign v__h2601 = x__h2658 | y__h2659 ; - assign v__h3299 = x__h3350 | y__h3351 ; - assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ; - assign x__h2658 = { 1'd0, r_dr[39:1] } ; - assign x__h3350 = { 1'd0, r_ir[17:1] } ; - assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ; - assign y__h3351 = jtag_tdi ? 18'd131072 : 18'd0 ; - always@(r_state or r_ir or v__h3299) + assign v__h2576 = { 22'd960, r_ir } ; + assign v__h2941 = x__h2996 | y__h2997 ; + assign v__h3636 = x__h3687 | y__h3688 ; + assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ; + assign x__h2996 = { 1'd0, r_dr[39:1] } ; + assign x__h3687 = { 1'd0, r_ir[17:1] } ; + assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ; + assign y__h3688 = jtag_tdi ? 18'd131072 : 18'd0 ; + always@(r_state$Q_OUT or r_ir or v__h3636) begin - case (r_state) - 4'd0: newir__h3435 = 18'd1; - 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir; - 4'd11: newir__h3435 = v__h3299; - default: newir__h3435 = r_ir; + case (r_state$Q_OUT) + 4'd0: newir__h3774 = 18'd1; + 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir; + 4'd11: newir__h3774 = v__h3636; + default: newir__h3774 = r_ir; endcase end always@(r_ir or - v__h2233 or - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 or - x__h2449) + v__h2576 or + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 or + x__h2789) begin case (r_ir) 18'd0, @@ -552,18 +599,18 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - v__h2135 = 40'd0; - 18'd1: v__h2135 = 40'd4093; + v__h2479 = 40'd0; + 18'd1: v__h2479 = 40'd4093; 18'b000011100100100100: - v__h2135 = - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140; - 18'b100010100100100100: v__h2135 = x__h2449; - default: v__h2135 = v__h2233; + v__h2479 = + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146; + 18'b100010100100100100: v__h2479 = x__h2789; + default: v__h2479 = v__h2576; endcase end - always@(newir__h3435) + always@(newir__h3774) begin - case (newir__h3435) + case (newir__h3774) 18'd0, 18'h00012, 18'h00013, @@ -572,71 +619,67 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; 18'd1, 18'b100010100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0080000000; 18'b000011100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h8000000000; - default: CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + default: CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0100000000; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) - 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state; + case (r_state$Q_OUT) + 4'd0: + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = + r_state$Q_OUT; 4'd1, 4'd8, 4'd15: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2; - 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9; - 4'd3, 4'd4: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5; - 4'd5, 4'd7: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8; - 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7; - 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2; + 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9; + 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5; + 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8; + 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7; + 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0; 4'd10, 4'd11: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12; 4'd12, 4'd14: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15; - 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15; + 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) + case (r_state$Q_OUT) 4'd0, 4'd1, 4'd8, 4'd15: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1; - 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1; + 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3; 4'd3, 4'd4, 4'd7: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4; 4'd5, 4'd6: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6; - 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6; + 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10; 4'd10, 4'd11, 4'd14: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11; 4'd12, 4'd13: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13; endcase end // handling of inlined registers - always@(posedge tck_clock$CLK_OUT) + always@(posedge tck_clock$OUT) begin if (rst_tck$OUT_RST == `BSV_RESET_VALUE) begin - r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0; - r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - r_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN; - if (r_dmistat_busy$EN) + if (r_dmistat_busy$EN) r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN; - if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN; end if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN; if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN; @@ -649,12 +692,10 @@ module mkJtagTap(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - r_dmi = 40'hAAAAAAAAAA; r_dmistat_busy = 1'h0; r_dr = 40'hAAAAAAAAAA; r_drmask = 40'hAAAAAAAAAA; r_ir = 18'h2AAAA; - r_state = 4'hA; r_tdo = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS @@ -663,11 +704,11 @@ module mkJtagTap(CLK, // handling of system tasks // synopsys translate_off - always@(negedge tck_clock$CLK_OUT) + always@(negedge tck_clock$OUT) begin #0; if (rst_tck$OUT_RST != `BSV_RESET_VALUE) - if (r_state == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && + if (r_state$Q_OUT == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && r_ir != 18'h00013 && r_ir != 18'h00014 && r_ir != 18'h00015 && diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index b1f7022..53c9fed 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -648,14 +648,19 @@ module mkP3_Core(CLK, wire bus_dmi_rsp_fifof_q_1$EN; // register rg_corew_start_after_por - reg rg_corew_start_after_por; - wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + reg [7 : 0] rg_corew_start_after_por; + wire [7 : 0] rg_corew_start_after_por$D_IN; + wire rg_corew_start_after_por$EN; // register rg_ndm_reset_delay reg [7 : 0] rg_ndm_reset_delay; wire [7 : 0] rg_ndm_reset_delay$D_IN; wire rg_ndm_reset_delay$EN; + // register rg_running + reg rg_running; + wire rg_running$D_IN, rg_running$EN; + // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; wire bus_dmi_req_fifof$CLR, @@ -781,8 +786,10 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, + corew$ndm_reset_client_request_get, corew$ndm_reset_client_response_put, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -804,6 +811,9 @@ module mkP3_Core(CLK, // ports of submodule ndm_reset_controller wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule por_ifc + wire por_ifc$RST_N_gen_rst; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -910,15 +920,15 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1279; - reg [31 : 0] v__h1424; - reg [31 : 0] v__h1273; - reg [31 : 0] v__h1418; + reg [31 : 0] v__h1362; + reg [31 : 0] v__h1510; + reg [31 : 0] v__h1356; + reg [31 : 0] v__h1504; // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; - wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49; + wire IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99, _dfoo1, _dfoo3; @@ -1188,7 +1198,7 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(por_ifc$RST_N_gen_rst), .CLK(CLK), .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), @@ -1237,6 +1247,7 @@ module mkP3_Core(CLK, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1308,7 +1319,7 @@ module mkP3_Core(CLK, .dmi_read_data(corew$dmi_read_data), .RDY_dmi_read_data(corew$RDY_dmi_read_data), .RDY_dmi_write(corew$RDY_dmi_write), - .ndm_reset_client_request_get(), + .ndm_reset_client_request_get(corew$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), @@ -1316,7 +1327,7 @@ module mkP3_Core(CLK, // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), - .RST_N(RST_N), + .RST_N(por_ifc$RST_N_gen_rst), .dmi_req_ready(jtagtap$dmi_req_ready), .dmi_rsp_data(jtagtap$dmi_rsp_data), .dmi_rsp_response(jtagtap$dmi_rsp_response), @@ -1334,7 +1345,7 @@ module mkP3_Core(CLK, .CLK_GATE_jtag_tclk_out()); // submodule ndm_reset - ResetEither ndm_reset(.A_RST(RST_N), + ResetEither ndm_reset(.A_RST(por_ifc$RST_N_gen_rst), .B_RST(ndm_reset_controller$OUT_RST), .RST_OUT(ndm_reset$RST_OUT)); @@ -1346,6 +1357,11 @@ module mkP3_Core(CLK, .ASSERT_OUT(), .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule por_ifc + mkPowerOnReset por_ifc(.CLK(CLK), + .RST_N(RST_N), + .RST_N_gen_rst(por_ifc$RST_N_gen_rst)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1371,7 +1387,8 @@ module mkP3_Core(CLK, // rule RL_rl_step_0 assign CAN_FIRE_RL_rl_step_0 = - corew$RDY_start && !rg_corew_start_after_por ; + (rg_corew_start_after_por != 8'd1 || corew$RDY_start) && + rg_corew_start_after_por != 8'd0 ; assign WILL_FIRE_RL_rl_step_0 = CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; @@ -1422,7 +1439,7 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; + IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu @@ -1434,7 +1451,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; @@ -1526,7 +1543,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1585,7 +1602,7 @@ module mkP3_Core(CLK, WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register rg_corew_start_after_por - assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$D_IN = rg_corew_start_after_por - 8'd1 ; assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; // register rg_ndm_reset_delay @@ -1596,6 +1613,10 @@ module mkP3_Core(CLK, assign rg_ndm_reset_delay$EN = WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; + // register rg_running + assign rg_running$D_IN = corew$ndm_reset_client_request_get ; + assign rg_running$EN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; assign bus_dmi_req_fifof$ENQ = CAN_FIRE_RL_bus_dmi_req_do_enq ; @@ -1660,16 +1681,17 @@ module mkP3_Core(CLK, assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$ndm_reset_client_response_put = rg_running ; assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_is_running = !MUX_corew$start_1__SEL_1 || rg_running ; assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || - WILL_FIRE_RL_rl_step_0 ; + WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1699,7 +1721,7 @@ module mkP3_Core(CLK, assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = + assign IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || @@ -1708,11 +1730,11 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1724,7 +1746,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 8'd100; rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else @@ -1744,6 +1766,7 @@ module mkP3_Core(CLK, if (rg_ndm_reset_delay$EN) rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end + if (rg_running$EN) rg_running <= `BSV_ASSIGNMENT_DELAY rg_running$D_IN; end // synopsys translate_off @@ -1754,8 +1777,9 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_corew_start_after_por = 1'h0; + rg_corew_start_after_por = 8'hAA; rg_ndm_reset_delay = 8'hAA; + rg_running = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1767,30 +1791,34 @@ module mkP3_Core(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - begin - v__h1279 = $stime; - #0; - end - v__h1273 = v__h1279 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1273, - $signed(32'd10)); - if (RST_N != `BSV_RESET_VALUE) - if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1424 = $stime; + v__h1362 = $stime; #0; end - v__h1418 = v__h1424 / 32'd10; + v__h1356 = v__h1362 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1356, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) - $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1418); + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1510 = $stime; + #0; + end + v__h1504 = v__h1510 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1504); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v new file mode 100644 index 0000000..65d7430 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v @@ -0,0 +1,92 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// +// +// +// Ports: +// Name I/O size props +// RST_N_gen_rst O 1 reset +// CLK I 1 clock +// RST_N I 1 unused +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkPowerOnReset(CLK, + RST_N, + + RST_N_gen_rst); + input CLK; + input RST_N; + + // output resets + output RST_N_gen_rst; + + // signals for module outputs + wire RST_N_gen_rst; + + // ports of submodule ctr + wire [7 : 0] ctr$D_IN, ctr$Q_OUT; + wire ctr$EN; + + // ports of submodule isInPowerOnReset + wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT; + + // ports of submodule rst_ifc + wire rst_ifc$OUT; + + // rule scheduling signals + wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown; + + // remaining internal signals + wire NOT_isInPowerOnReset__read___d5; + + // output resets + assign RST_N_gen_rst = rst_ifc$OUT ; + + // submodule ctr + RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK), + .D_IN(ctr$D_IN), + .EN(ctr$EN), + .Q_OUT(ctr$Q_OUT)); + + // submodule isInPowerOnReset + RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK), + .D_IN(isInPowerOnReset$D_IN), + .EN(isInPowerOnReset$EN), + .Q_OUT(isInPowerOnReset$Q_OUT)); + + // submodule rst_ifc + ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT)); + + // rule RL_countDown + assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + + // submodule ctr + assign ctr$D_IN = ctr$Q_OUT - 8'd1 ; + assign ctr$EN = isInPowerOnReset$Q_OUT ; + + // submodule isInPowerOnReset + assign isInPowerOnReset$D_IN = 1'd0 ; + assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ; + + // remaining internal signals + assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ; +endmodule // mkPowerOnReset + diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index dcc8699..0888d5b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -94,6 +94,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -192,6 +193,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -454,6 +456,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1421,6 +1424,7 @@ module mkProc(CLK, core_0$EN_v_to_TV_0_get, core_0$EN_v_to_TV_1_get, core_0$RDY_coreIndInv_terminate, + core_0$RDY_coreReq_start, core_0$RDY_dCacheToParent_fromP_enq, core_0$RDY_dCacheToParent_rqToP_deq, core_0$RDY_dCacheToParent_rqToP_first, @@ -1461,6 +1465,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_respLd_enq, core_0$RDY_v_to_TV_0_get, core_0$RDY_v_to_TV_1_get, + core_0$coreReq_start_running, core_0$hart0_run_halt_server_request_put, core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, @@ -2104,60 +2109,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162844; - reg [31 : 0] v__h162380; - reg [31 : 0] v__h5520; - reg [31 : 0] v__h5693; - reg [31 : 0] v__h5953; - reg [31 : 0] v__h8095; - reg [31 : 0] v__h8310; - reg [31 : 0] v__h2670; - reg [31 : 0] v__h4343; - reg [31 : 0] v__h9480; - reg [31 : 0] v__h9973; - reg [31 : 0] v__h10136; - reg [31 : 0] v__h134337; - reg [31 : 0] v__h134504; - reg [31 : 0] v__h136607; - reg [31 : 0] v__h153951; - reg [31 : 0] v__h133718; - reg [31 : 0] v__h160645; - reg [31 : 0] v__h161153; - reg [31 : 0] v__h2664; - reg [31 : 0] v__h4337; - reg [31 : 0] v__h5514; - reg [31 : 0] v__h5687; - reg [31 : 0] v__h5947; - reg [31 : 0] v__h8089; - reg [31 : 0] v__h8304; - reg [31 : 0] v__h9474; - reg [31 : 0] v__h9967; - reg [31 : 0] v__h10130; - reg [31 : 0] v__h133712; - reg [31 : 0] v__h134331; - reg [31 : 0] v__h134498; - reg [31 : 0] v__h136601; - reg [31 : 0] v__h153945; - reg [31 : 0] v__h160639; - reg [31 : 0] v__h161147; - reg [31 : 0] v__h162374; - reg [31 : 0] v__h162838; + reg [31 : 0] v__h162856; + reg [31 : 0] v__h162388; + reg [31 : 0] v__h5528; + reg [31 : 0] v__h5701; + reg [31 : 0] v__h5961; + reg [31 : 0] v__h8103; + reg [31 : 0] v__h8318; + reg [31 : 0] v__h2678; + reg [31 : 0] v__h4351; + reg [31 : 0] v__h9488; + reg [31 : 0] v__h9981; + reg [31 : 0] v__h10144; + reg [31 : 0] v__h134345; + reg [31 : 0] v__h134512; + reg [31 : 0] v__h136615; + reg [31 : 0] v__h153959; + reg [31 : 0] v__h133726; + reg [31 : 0] v__h160653; + reg [31 : 0] v__h161161; + reg [31 : 0] v__h2672; + reg [31 : 0] v__h4345; + reg [31 : 0] v__h5522; + reg [31 : 0] v__h5695; + reg [31 : 0] v__h5955; + reg [31 : 0] v__h8097; + reg [31 : 0] v__h8312; + reg [31 : 0] v__h9482; + reg [31 : 0] v__h9975; + reg [31 : 0] v__h10138; + reg [31 : 0] v__h133720; + reg [31 : 0] v__h134339; + reg [31 : 0] v__h134506; + reg [31 : 0] v__h136609; + reg [31 : 0] v__h153953; + reg [31 : 0] v__h160647; + reg [31 : 0] v__h161155; + reg [31 : 0] v__h162382; + reg [31 : 0] v__h162850; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, @@ -2167,44 +2172,44 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, - data64__h147777, - dword__h93782, - ld_data__h131939, - old_dword__h89472, - w1__h47861, - w1__h47866, - w2__h47862, - w2__h47868, - x__h47857; + data64__h147785, + dword__h93790, + ld_data__h131947, + old_dword__h89480, + w1__h47869, + w1__h47874, + w2__h47870, + w2__h47876, + x__h47865; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147778; + reg [7 : 0] strb8__h147786; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61575; + reg [2 : 0] x__h61583; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, - x__h61582, - x__h82300; + x__h61590, + x__h82308; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - new_cline__h134640; + new_cline__h134648; wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, @@ -2225,89 +2230,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - data__h31950, - failed_testnum__h162423, - line_addr__h101846, - line_addr__h101932, - mask__h89469, - mem_req_rd_addr_araddr__h133938, - mem_req_wr_addr_awaddr__h147862, - mmioPlatform_fromHostQ_data_0__h42651, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48453, - n__read_addr__h61443, - n__read_addr__h61528, - n__read_addr__h80062, - n__read_addr__h80141, - n__read_snd_addr__h123373, - newData__h32031, - newData__h34961, - new_dword__h89473, - op_result__h48469, - op_result__h48999, - op_result__h49004, - op_result__h49009, - op_result__h49014, - op_result__h49020, - op_result__h49027, - op_result__h49033, - result__h47912, - result__h48036, - result__h48064, - result__h48092, - result__h48120, - result__h48148, - result__h48176, - result__h48204, - result__h48232, - result__h48277, - result__h48305, - result__h48333, - result__h48361, - result__h48402, - result__h48430, - result__h48556, - result__h48583, - result__h48610, - result__h48637, - result__h48664, - result__h48691, - result__h48718, - result__h48745, - result__h48789, - result__h48816, - result__h48843, - result__h48870, - result__h48910, - result__h48937, - result__h49054, - result__h49120, - result__h49186, - result__h49252, - result__h49318, - result__h49384, - result__h49450, - result__h49512, - result__h49557, - result__h49623, - result__h49689, - result__h49747, - result__h49792, - w1___1__h47971, - w2___1__h47972, - x1_avValue_data__h40323, - x1_avValue_data__h44790, - x__h32142, - x__h35052, - x__h37412, - x__h40841, - x__h40852, - x__h42861, - x__h42872, - x__h49969, - x__h90635, - y__h90636, - y__h90637; + data__h31958, + failed_testnum__h162431, + line_addr__h101854, + line_addr__h101940, + mask__h89477, + mem_req_rd_addr_araddr__h133946, + mem_req_wr_addr_awaddr__h147870, + mmioPlatform_fromHostQ_data_0__h42659, + mmioPlatform_mtime__h37272, + mmioPlatform_reqData__h48461, + n__read_addr__h61451, + n__read_addr__h61536, + n__read_addr__h80070, + n__read_addr__h80149, + n__read_snd_addr__h123381, + newData__h32039, + newData__h34969, + new_dword__h89481, + op_result__h48477, + op_result__h49007, + op_result__h49012, + op_result__h49017, + op_result__h49022, + op_result__h49028, + op_result__h49035, + op_result__h49041, + result__h47920, + result__h48044, + result__h48072, + result__h48100, + result__h48128, + result__h48156, + result__h48184, + result__h48212, + result__h48240, + result__h48285, + result__h48313, + result__h48341, + result__h48369, + result__h48410, + result__h48438, + result__h48564, + result__h48591, + result__h48618, + result__h48645, + result__h48672, + result__h48699, + result__h48726, + result__h48753, + result__h48797, + result__h48824, + result__h48851, + result__h48878, + result__h48918, + result__h48945, + result__h49062, + result__h49128, + result__h49194, + result__h49260, + result__h49326, + result__h49392, + result__h49458, + result__h49520, + result__h49565, + result__h49631, + result__h49697, + result__h49755, + result__h49800, + w1___1__h47979, + w2___1__h47980, + x1_avValue_data__h40331, + x1_avValue_data__h44798, + x__h32150, + x__h35060, + x__h37420, + x__h40849, + x__h40860, + x__h42869, + x__h42880, + x__h49977, + x__h90643, + y__h90644, + y__h90645; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; @@ -2319,16 +2324,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w17861_BITS_31_TO_0__q15, - w27862_BITS_31_TO_0__q16, - x_data__h30533; + v__h31751, + v__h31788, + w17869_BITS_31_TO_0__q15, + w27870_BITS_31_TO_0__q16, + x_data__h30541; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; - wire [5 : 0] x__h133973, x__h147887; + wire [5 : 0] x__h133981, x__h147895; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; - wire [3 : 0] b__h133645, b__h2564; - wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; + wire [3 : 0] b__h133653, b__h2572; + wire [2 : 0] n__read_id__h61455, n__read_id__h61540, x__h7933; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, @@ -2390,27 +2395,28 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqBE_BIT_0___h30166, + mmioPlatform_reqBE_BIT_4___h30126, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61448, - n__read_child__h61533, - n__read_child__h80065, - n__read_child__h80144, - n__read_snd_id__h123374, + n__read_child__h61456, + n__read_child__h61541, + n__read_child__h80073, + n__read_child__h80152, + n__read_snd_id__h123382, propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, - x__h61261, - x__h74813, - x__h79884; + x__h61269, + x__h74821, + x__h79892; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; - assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; + assign CAN_FIRE_start = + mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; assign WILL_FIRE_start = EN_start ; // value method master0_m_awvalid @@ -2845,6 +2851,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -2901,7 +2908,7 @@ module mkProc(CLK, .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), .EN_v_to_TV_0_get(core_0$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(core_0$EN_v_to_TV_1_get), - .RDY_coreReq_start(), + .RDY_coreReq_start(core_0$RDY_coreReq_start), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), .RDY_coreIndInv_perfResp(), @@ -3676,14 +3683,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2564 == 4'd0 ; + b__h2572 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2564 != 4'd0 && + b__h2572 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3796,7 +3803,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42861 == 64'd0 || + x__h42869 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -4116,13 +4123,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133645 == 4'd0 ; + b__h133653 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133645 != 4'd0 && + b__h133653 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4226,7 +4233,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30541 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -4266,7 +4273,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31958 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -4291,10 +4298,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101846, + { line_addr__h101854, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101932, + { line_addr__h101940, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4305,11 +4312,11 @@ module mkProc(CLK, { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4408,7 +4415,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47857 } ; + x__h47865 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4417,7 +4424,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49977, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4432,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42869 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42861 != 64'd0 ; + x__h42869 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40841 == 64'd0 ; + x__h40849 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - x__h61261 ; + x__h61269 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - x__h79884 ; + x__h79892 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; + { 1'd1, n__read_snd_addr__h123381, n__read_snd_id__h123382 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4526,11 +4533,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2564 - 4'd1 ; + b__h2572 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2564 ; + b__h2572 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4579,11 +4586,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133645 - 4'd1 ; + b__h133653 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133645 ; + b__h133653 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4646,7 +4653,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133946, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4664,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147870, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147777, strb8__h147778, 1'd1 } ; + { data64__h147785, strb8__h147786, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4682,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134648 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4730,8 +4737,8 @@ module mkProc(CLK, // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101846 : - line_addr__h101932 ; + line_addr__h101854 : + line_addr__h101940 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4892,7 +4899,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34969 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4908,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32039 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5118,7 +5125,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7925, + x__h7933, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -5218,6 +5225,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -5321,7 +5329,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131939, llc$dma_respLd_first[3] } ; + { ld_data__h131947, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5475,7 +5483,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134640, + { new_cline__h134648, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5559,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93782, 3'd1 } ; + { 4'd0, dword__h93790, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5854,47 +5862,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37420), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h32150)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37272), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h35060)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40852)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42659), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h40860)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h42872)); + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h42880)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40323 } } ; + x1_avValue_data__h40331 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5910,7 +5918,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; + newData__h32039 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5975,7 +5983,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - x__h74813 } ; + x__h74821 } ; assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5987,29 +5995,29 @@ module mkProc(CLK, assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? @@ -6154,11 +6162,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42861 == 64'd0 : - x__h40841 == 64'd0, + x__h42869 == 64'd0 : + x__h40849 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44790 } ; + x1_avValue_data__h44798 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6392,58 +6400,58 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = - { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + { CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = - { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + { CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - x__h82300 } ; + x__h82308 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = - { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + { CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = - { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - x__h61575, - x__h61582 } ; - assign b__h133645 = + { CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + x__h61583, + x__h61590 } ; + assign b__h133653 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2564 = + assign b__h2572 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31958 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h162423 = + { v__h31751, 32'd0 } ; + assign failed_testnum__h162431 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101846 = + assign line_addr__h101854 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101932 = + assign line_addr__h101940 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = - line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; + line_addr__h101940 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = - line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89469 = + line_addr__h101854 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89477 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6476,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133938 = - { llc$to_mem_toM_first[68:11], x__h133973 } ; - assign mem_req_wr_addr_awaddr__h147862 = - { llc$to_mem_toM_first[639:582], x__h147887 } ; + assign mem_req_rd_addr_araddr__h133946 = + { llc$to_mem_toM_first[68:11], x__h133981 } ; + assign mem_req_wr_addr_awaddr__h147870 = + { llc$to_mem_toM_first[639:582], x__h147895 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42651 = + assign mmioPlatform_fromHostQ_data_0__h42659 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,18 +6494,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37272 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + mmioPlatform_mtimecmp_0 <= newData__h34969 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30166 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30126 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48461 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6529,105 +6537,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61443 = + assign n__read_addr__h61451 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61528 = + assign n__read_addr__h61536 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80062 = + assign n__read_addr__h80070 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : 64'd0 ; - assign n__read_addr__h80141 = + assign n__read_addr__h80149 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : 64'd0 ; - assign n__read_child__h61448 = + assign n__read_child__h61456 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61533 = + assign n__read_child__h61541 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80065 = + assign n__read_child__h80073 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; - assign n__read_child__h80144 = + assign n__read_child__h80152 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; - assign n__read_id__h61447 = + assign n__read_id__h61455 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61532 = + assign n__read_id__h61540 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123373 = + assign n__read_snd_addr__h123381 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123374 = + assign n__read_snd_id__h123382 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32039 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : + x__h32150 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + assign newData__h34969 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : + x__h35060 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h134640 = + assign new_cline__h134648 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89473 = x__h90635 | y__h90636 ; - assign op_result__h48469 = + assign new_dword__h89481 = x__h90643 | y__h90644 ; + assign op_result__h48477 = IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; - assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; - assign op_result__h49004 = w1__h47866 & w2__h47868 ; - assign op_result__h49009 = w1__h47866 | w2__h47868 ; - assign op_result__h49014 = - (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; - assign op_result__h49020 = - (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; - assign op_result__h49027 = + assign op_result__h49007 = w1__h47874 ^ w2__h47876 ; + assign op_result__h49012 = w1__h47874 & w2__h47876 ; + assign op_result__h49017 = w1__h47874 | w2__h47876 ; + assign op_result__h49022 = + (w1__h47874 < w2__h47876) ? w1__h47874 : w2__h47876 ; + assign op_result__h49028 = + (w1__h47874 <= w2__h47876) ? w2__h47876 : w1__h47874 ; + assign op_result__h49035 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w1__h47866 : - w2__h47868 ; - assign op_result__h49033 = + w1__h47874 : + w2__h47876 ; + assign op_result__h49041 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w2__h47868 : - w1__h47866 ; + w2__h47876 : + w1__h47874 ; assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6638,126 +6646,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47912 = + assign result__h47920 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; - assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48556 = + assign result__h48044 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48072 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48100 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48128 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48156 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48184 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48212 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48240 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48285 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48313 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48341 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48369 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48410 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48438 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48564 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48583 = + assign result__h48591 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48610 = + assign result__h48618 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48637 = + assign result__h48645 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48664 = + assign result__h48672 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48691 = + assign result__h48699 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48718 = + assign result__h48726 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48745 = + assign result__h48753 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48789 = + assign result__h48797 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48816 = + assign result__h48824 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48843 = + assign result__h48851 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48870 = + assign result__h48878 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48910 = + assign result__h48918 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48937 = + assign result__h48945 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49054 = + assign result__h49062 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49120 = + assign result__h49128 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49186 = + assign result__h49194 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49252 = + assign result__h49260 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49318 = + assign result__h49326 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49384 = + assign result__h49392 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49450 = + assign result__h49458 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49512 = + assign result__h49520 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; - assign result__h49557 = + assign result__h49565 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49623 = + assign result__h49631 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49689 = + assign result__h49697 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49747 = + assign result__h49755 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; - assign result__h49792 = + assign result__h49800 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; - assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; - assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; - assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; - assign x1_avValue_data__h40323 = + assign v__h31751 = mmioPlatform_waitUpperMSIPCRs ? v__h31788 : 32'd0 ; + assign v__h31788 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17869_BITS_31_TO_0__q15 = w1__h47869[31:0] ; + assign w1___1__h47979 = { 32'd0, w1__h47869[31:0] } ; + assign w27870_BITS_31_TO_0__q16 = w2__h47870[31:0] ; + assign w2___1__h47980 = { 32'd0, w2__h47870[31:0] } ; + assign x1_avValue_data__h40331 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44790 = + assign x1_avValue_data__h44798 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40841 = + assign x__h133981 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147895 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37420 = mmioPlatform_mtimecmp_0 ; + assign x__h40849 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40852 : + x__h40860 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; - assign x__h42861 = + assign x__h42869 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42872 : + x__h42880 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6774,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61261 = + assign x__h49977 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61269 = SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; - assign x__h74813 = + assign x__h74821 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; - assign x__h7925 = + assign x__h7933 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79884 = + assign x__h79892 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; - assign x__h90635 = old_dword__h89472 & y__h90637 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90636 = + assign x__h90643 = old_dword__h89480 & y__h90645 ; + assign x_data__h30541 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90644 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89469 ; - assign y__h90637 = + mask__h89477 ; + assign y__h90645 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,141 +7009,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h147785 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147785 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147785 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147785 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147785 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147785 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147785 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147785 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131947 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131947 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131947 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131947 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131947 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131947 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131947 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131947 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147786 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147786 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147786 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147786 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147786 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147786 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147786 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147786 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48036 or - result__h48064 or - result__h48092 or - result__h48120 or - result__h48148 or - result__h48176 or result__h48204 or result__h48232) + result__h48044 or + result__h48072 or + result__h48100 or + result__h48128 or + result__h48156 or + result__h48184 or result__h48212 or result__h48240) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48036; + result__h48044; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48064; + result__h48072; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48092; + result__h48100; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48120; + result__h48128; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48148; + result__h48156; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48176; + result__h48184; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48204; + result__h48212; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48232; + result__h48240; endcase end always@(mmioPlatform_curReq or - result__h48277 or - result__h48305 or result__h48333 or result__h48361) + result__h48285 or + result__h48313 or result__h48341 or result__h48369) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48277; + result__h48285; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48305; + result__h48313; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48333; + result__h48341; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48361; + result__h48369; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48402 or result__h48430) + always@(mmioPlatform_curReq or result__h48410 or result__h48438) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48402; + result__h48410; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48430; + result__h48438; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase @@ -7148,103 +7156,103 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - w2__h47862 = + w2__h47870 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w2___1__h47972 or + w2___1__h47980 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; - 2'b10: w2__h47868 = w2___1__h47972; + 2'b10: w2__h47876 = w2___1__h47980; 2'b11: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_curReq or - result__h48556 or - result__h48583 or - result__h48610 or - result__h48637 or - result__h48664 or - result__h48691 or result__h48718 or result__h48745) + result__h48564 or + result__h48591 or + result__h48618 or + result__h48645 or + result__h48672 or + result__h48699 or result__h48726 or result__h48753) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48556; + result__h48564; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48583; + result__h48591; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48610; + result__h48618; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48637; + result__h48645; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48664; + result__h48672; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48691; + result__h48699; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48718; + result__h48726; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48745; + result__h48753; endcase end always@(mmioPlatform_curReq or - result__h48789 or - result__h48816 or result__h48843 or result__h48870) + result__h48797 or + result__h48824 or result__h48851 or result__h48878) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48789; + result__h48797; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48816; + result__h48824; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48843; + result__h48851; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48870; + result__h48878; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48910 or result__h48937) + always@(mmioPlatform_curReq or result__h48918 or result__h48945) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48910; + result__h48918; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48937; + result__h48945; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase @@ -7257,42 +7265,42 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - w1__h47861 = + w1__h47869 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w1___1__h47971 or + w1___1__h47979 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; - 2'b10: w1__h47866 = w1___1__h47971; + 2'b10: w1__h47874 = w1___1__h47979; 2'b11: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w17861_BITS_31_TO_0__q15 or + w17869_BITS_31_TO_0__q15 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) @@ -7304,8 +7312,8 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - { {32{w17861_BITS_31_TO_0__q15[31]}}, - w17861_BITS_31_TO_0__q15 }; + { {32{w17869_BITS_31_TO_0__q15[31]}}, + w17869_BITS_31_TO_0__q15 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; @@ -7314,7 +7322,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w27862_BITS_31_TO_0__q16 or + w27870_BITS_31_TO_0__q16 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) @@ -7326,116 +7334,116 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - { {32{w27862_BITS_31_TO_0__q16[31]}}, - w27862_BITS_31_TO_0__q16 }; + { {32{w27870_BITS_31_TO_0__q16[31]}}, + w27870_BITS_31_TO_0__q16 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49033 or - w2__h47868 or - op_result__h48469 or - op_result__h48999 or - op_result__h49004 or - op_result__h49009 or - op_result__h49027 or op_result__h49014 or op_result__h49020) + op_result__h49041 or + w2__h47876 or + op_result__h48477 or + op_result__h49007 or + op_result__h49012 or + op_result__h49017 or + op_result__h49035 or op_result__h49022 or op_result__h49028) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - w2__h47868; + w2__h47876; 4'd1: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48469; + op_result__h48477; 4'd2: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48999; + op_result__h49007; 4'd3: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49004; + op_result__h49012; 4'd4: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49009; + op_result__h49017; 4'd5: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49027; + op_result__h49035; 4'd7: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49014; + op_result__h49022; 4'd8: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49020; + op_result__h49028; default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49033; + op_result__h49041; endcase end always@(mmioPlatform_curReq or - result__h49512 or - result__h49557 or result__h49623 or result__h49689) + result__h49520 or + result__h49565 or result__h49631 or result__h49697) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49512; + result__h49520; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49557; + result__h49565; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49623; + result__h49631; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49689; + result__h49697; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47912 or - result__h49054 or - result__h49120 or - result__h49186 or - result__h49252 or - result__h49318 or result__h49384 or result__h49450) + result__h47920 or + result__h49062 or + result__h49128 or + result__h49194 or + result__h49260 or + result__h49326 or result__h49392 or result__h49458) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h47912; + result__h47920; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49054; + result__h49062; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49120; + result__h49128; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49186; + result__h49194; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49252; + result__h49260; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49318; + result__h49326; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49384; + result__h49392; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49450; + result__h49458; endcase end - always@(mmioPlatform_curReq or result__h49747 or result__h49792) + always@(mmioPlatform_curReq or result__h49755 or result__h49800) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49747; + result__h49755; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49792; + result__h49800; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase @@ -7448,15 +7456,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; 2'b01: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; 2'b10: - x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47865 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end @@ -7540,278 +7548,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; endcase end - always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) + always@(x__h61269 or n__read_id__h61455 or n__read_id__h61540) begin - case (x__h61261) - 1'd0: x__h61575 = n__read_id__h61447; - 1'd1: x__h61575 = n__read_id__h61532; + case (x__h61269) + 1'd0: x__h61583 = n__read_id__h61455; + 1'd1: x__h61583 = n__read_id__h61540; endcase end - always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) + always@(x__h61269 or n__read_child__h61456 or n__read_child__h61541) begin - case (x__h61261) - 1'd0: x__h61582 = n__read_child__h61448; - 1'd1: x__h61582 = n__read_child__h61533; + case (x__h61269) + 1'd0: x__h61590 = n__read_child__h61456; + 1'd1: x__h61590 = n__read_child__h61541; endcase end - always@(x__h61261 or + always@(x__h61269 or propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; 1'd1: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; endcase end - always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) + always@(x__h61269 or n__read_addr__h61451 or n__read_addr__h61536) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61443; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61451; 1'd1: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61528; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61536; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) + always@(x__h79892 or n__read_child__h80073 or n__read_child__h80152) begin - case (x__h79884) - 1'd0: x__h82300 = n__read_child__h80065; - 1'd1: x__h82300 = n__read_child__h80144; + case (x__h79892) + 1'd0: x__h82308 = n__read_child__h80073; + 1'd1: x__h82308 = n__read_child__h80152; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79884 or + always@(x__h79892 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : 2'd0; 1'd1: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : 2'd0; endcase end - always@(x__h79884 or + always@(x__h79892 or NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; 1'd1: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; endcase end - always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) + always@(x__h79892 or n__read_addr__h80070 or n__read_addr__h80149) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80062; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80070; 1'd1: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80141; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80149; endcase end @@ -8227,14 +8235,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162844 = $stime; + v__h162856 = $stime; #0; end - v__h162838 = v__h162844 / 32'd10; + v__h162850 = v__h162856 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162838, + v__h162850, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8244,14 +8252,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162380 = $stime; + v__h162388 = $stime; #0; end - v__h162374 = v__h162380 / 32'd10; + v__h162382 = v__h162388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162374, + v__h162382, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8261,7 +8269,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162423); + $display("FAIL %0d", failed_testnum__h162431); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8269,14 +8277,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5520 = $stime; + v__h5528 = $stime; #0; end - v__h5514 = v__h5520 / 32'd10; + v__h5522 = v__h5528 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5514); + $display("%0d: %m.rl_handle_read_rsps ", v__h5522); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8336,16 +8344,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5693 = $stime; + v__h5701 = $stime; #0; end - v__h5687 = v__h5693 / 32'd10; + v__h5695 = v__h5701 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5687); + v__h5695); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8449,14 +8457,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5953 = $stime; + v__h5961 = $stime; #0; end - v__h5947 = v__h5953 / 32'd10; + v__h5955 = v__h5961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5947); + $display("%d: %m.rl_handle_write_req: St request:", v__h5955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8626,15 +8634,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h8095 = $stime; + v__h8103 = $stime; #0; end - v__h8089 = v__h8095 / 32'd10; + v__h8097 = v__h8103 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h8089); + $display("%0d: ERROR: CreditCounter: overflow", v__h8097); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8684,7 +8692,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7925); + $write("'h%h", x__h7933); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8815,16 +8823,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8310 = $stime; + v__h8318 = $stime; #0; end - v__h8304 = v__h8310 / 32'd10; + v__h8312 = v__h8318 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8304); + v__h8312); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9030,14 +9038,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2670 = $stime; + v__h2678 = $stime; #0; end - v__h2664 = v__h2670 / 32'd10; + v__h2672 = v__h2678 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2664); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2672); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9327,16 +9335,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4343 = $stime; + v__h4351 = $stime; #0; end - v__h4337 = v__h4343 / 32'd10; + v__h4345 = v__h4351 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4337); + v__h4345); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9542,14 +9550,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9480 = $stime; + v__h9488 = $stime; #0; end - v__h9474 = v__h9480 / 32'd10; + v__h9482 = v__h9488 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9474); + $display("%0d: %m.rl_discard_write_rsp", v__h9482); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9586,15 +9594,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9973 = $stime; + v__h9981 = $stime; #0; end - v__h9967 = v__h9973 / 32'd10; + v__h9975 = v__h9981 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9967); + v__h9975); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9634,14 +9642,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h10136 = $stime; + v__h10144 = $stime; #0; end - v__h10130 = v__h10136 / 32'd10; + v__h10138 = v__h10144 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h10130); + v__h10138); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9828,15 +9836,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h134337 = $stime; + v__h134345 = $stime; #0; end - v__h134331 = v__h134337 / 32'd10; + v__h134339 = v__h134345 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134331, + v__h134339, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9896,15 +9904,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134504 = $stime; + v__h134512 = $stime; #0; end - v__h134498 = v__h134504 / 32'd10; + v__h134506 = v__h134512 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134498); + v__h134506); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10085,16 +10093,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136607 = $stime; + v__h136615 = $stime; #0; end - v__h136601 = v__h136607 / 32'd10; + v__h136609 = v__h136615 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136601); + v__h136609); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11292,14 +11300,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153951 = $stime; + v__h153959 = $stime; #0; end - v__h153945 = v__h153951 / 32'd10; + v__h153953 = v__h153959 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153945); + $display("%0d: ERROR: CreditCounter: overflow", v__h153953); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11323,7 +11331,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_wr_addr_awaddr__h147862); + $write("'h%h", mem_req_wr_addr_awaddr__h147870); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11411,7 +11419,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", data64__h147777); + $write("'h%h", data64__h147785); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11419,7 +11427,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", strb8__h147778); + $write("'h%h", strb8__h147786); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11445,16 +11453,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133718 = $stime; + v__h133726 = $stime; #0; end - v__h133712 = v__h133718 / 32'd10; + v__h133720 = v__h133726 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133712, + v__h133720, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11542,7 +11550,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_rd_addr_araddr__h133938); + $write("'h%h", mem_req_rd_addr_araddr__h133946); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11623,15 +11631,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h160645 = $stime; + v__h160653 = $stime; #0; end - v__h160639 = v__h160645 / 32'd10; + v__h160647 = v__h160653 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160639, + v__h160647, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -11669,15 +11677,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161153 = $stime; + v__h161161 = $stime; #0; end - v__h161147 = v__h161153 / 32'd10; + v__h161155 = v__h161161 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161147); + v__h161155); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v b/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v new file mode 100644 index 0000000..4bedc0b --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/ASSIGN1.v @@ -0,0 +1,5 @@ +module ASSIGN1(IN, OUT); + output OUT; + input IN; + assign OUT = IN; +endmodule diff --git a/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v b/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v new file mode 100644 index 0000000..1dc1123 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/MakeReset0.v @@ -0,0 +1,87 @@ + +// Copyright (c) 2000-2012 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + + +module MakeReset0 ( + CLK, + RST, + ASSERT_IN, + ASSERT_OUT, + + OUT_RST + ); + + parameter init = 1 ; + + input CLK ; + input RST ; + input ASSERT_IN ; + output ASSERT_OUT ; + + output OUT_RST ; + + reg rst ; + + assign ASSERT_OUT = rst == `BSV_RESET_VALUE ; + + assign OUT_RST = rst ; + + always@(posedge CLK or `BSV_RESET_EDGE RST) begin + if (RST == `BSV_RESET_VALUE) + rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE; + else + begin + if (ASSERT_IN) + rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE; + else // if (rst == 1'b0) + rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE; + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + + +`ifdef BSV_NO_INITIAL_BLOCKS +`else // not BSV_NO_INITIAL_BLOCKS + // synopsys translate_off + initial begin + #0 ; + rst = ~ `BSV_RESET_VALUE ; + end + // synopsys translate_on +`endif // BSV_NO_INITIAL_BLOCKS + +endmodule // MakeReset0 diff --git a/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v b/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v new file mode 100644 index 0000000..9b50bfb --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/RegUNInit.v @@ -0,0 +1,49 @@ + +// Copyright (c) 2000-2019 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +// Basic register with initial value but without reset (not for ASIC synthesis). +module RegUNInit(CLK, Q_OUT, D_IN, EN); + + parameter width = 1; + parameter init = { width {1'b0} } ; + + input CLK; + input EN; + input [width - 1 : 0] D_IN; + output [width - 1 : 0] Q_OUT; + + reg [width - 1 : 0] Q_OUT; + initial Q_OUT = init; + + always@(posedge CLK) + begin + if (EN) + Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; + end +endmodule diff --git a/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v b/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v new file mode 100644 index 0000000..61a23bf --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/SyncWire.v @@ -0,0 +1,41 @@ + +// Copyright (c) 2000-2009 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else +`define BSV_ASSIGNMENT_DELAY +`endif + + +module SyncWire( DIN, DOUT ); + + parameter width = 1; + + input [width - 1 : 0] DIN; + output [width - 1 : 0] DOUT; + + assign DOUT = DIN ; + + +endmodule diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index 97d20b6..ab95b20 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -6,7 +6,7 @@ // // Ports: // Name I/O size props -// RDY_coreReq_start O 1 const +// RDY_coreReq_start O 1 // RDY_coreReq_perfReq O 1 reg // coreIndInv_perfResp O 73 // RDY_coreIndInv_perfResp O 1 reg @@ -104,6 +104,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -184,6 +185,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -402,6 +404,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4510,9 +4513,10 @@ module mkCore(CLK, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, MUX_regRenamingTable$rename_0_getRename_1__SEL_3, - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_2, + MUX_renameStage_rg_m_halt_req$write_1__SEL_3, + MUX_renameStage_rg_m_halt_req$write_1__SEL_6, MUX_rf$write_3_wr_1__PSEL_1, MUX_rf$write_3_wr_1__SEL_1, MUX_rf$write_3_wr_1__SEL_2, @@ -4602,12 +4606,12 @@ module mkCore(CLK, CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q88, CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89, CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q90, - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120, - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121, + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118, + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119, CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50, CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q51, - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118, - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119, + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120, + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121, CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48, CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q49, CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122, @@ -4671,14 +4675,14 @@ module mkCore(CLK, CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q184, CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q185, CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q186, - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189, - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190, + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187, + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188, CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q160, CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q161, - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187, - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188, - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191, - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192, + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191, + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192, + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189, + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190, CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q143, CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619, @@ -4801,8 +4805,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q276, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244, + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243, CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241, CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, @@ -4818,14 +4822,14 @@ module mkCore(CLK, CASE_guard22690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, CASE_guard37351_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, CASE_guard37351_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, CASE_guard46663_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, CASE_guard46663_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard50518_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, CASE_guard50518_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, CASE_guard50619_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, CASE_guard55732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard55732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard59227_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59, @@ -4836,13 +4840,13 @@ module mkCore(CLK, CASE_guard68157_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard76655_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard76993_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, CASE_guard76993_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, CASE_guard85967_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, CASE_guard85967_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, CASE_guard95036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard96217_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, CASE_guard96217_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, @@ -4918,19 +4922,19 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3042; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2240, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16400; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16401; wire [463 : 0] commitStage_f_rob_data_first__5082_BIT_167_518_ETC___d15254; wire [457 : 0] rob_deqPort_0_deq_data__4661_BITS_161_TO_98_46_ETC___d15638; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037; wire [393 : 0] IF_commitStage_f_rob_data_first__5082_BITS_97__ETC___d15253; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3026, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16391; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392; wire [321 : 0] basicExec___d12137, basicExec___d12839; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3017, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16382, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11191, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11204, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11197; @@ -5903,7 +5907,7 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2176, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16427, x__h184591, x__h722372; wire [4 : 0] IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14628, @@ -6387,7 +6391,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13996, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14138, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14156, - NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_RDY_ETC___d15704, + NOT_rob_deqPort_0_canDeq__5662_5663_OR_regRena_ETC___d15704, NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_deq_ETC___d15988, NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320, NOT_rob_deqPort_1_deq_data__5670_BIT_25_5671_5_ETC___d15701, @@ -6618,7 +6622,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14136, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14154, f_csr_rsps_i_notFull__6120_AND_f_csr_reqs_firs_ETC___d16223, - fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338, + fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14467, @@ -6669,7 +6673,7 @@ module mkCore(CLK, next_deqP___1__h336636, r1__read_BIT_20___h663156, r__h620917, - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544, + regRenamingTable_RDY_commit_0_commit__5265_AND_ETC___d15325, regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201, regRenamingTable_RDY_rename_1_getRename__4264__ETC___d14282, regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690, @@ -6698,7 +6702,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180, rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16059, - rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325, + rob_RDY_enqPort_1_enq__4330_AND_NOT_fetchStage_ETC___d14338, tsr_val__h736523, tvm_val__h736525, v__h303709, @@ -6714,8 +6718,8 @@ module mkCore(CLK, x__h608480; // action method coreReq_start - assign RDY_coreReq_start = 1'd1 ; - assign CAN_FIRE_coreReq_start = 1'd1 ; + assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; + assign CAN_FIRE_coreReq_start = !renameStage_rg_m_halt_req[4] ; assign WILL_FIRE_coreReq_start = EN_coreReq_start ; // action method coreReq_perfReq @@ -6752,7 +6756,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16400 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16401 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6772,7 +6776,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q274, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16427 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9965,8 +9969,9 @@ module mkCore(CLK, assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ; // rule RL_setDoFlushBrPred - assign CAN_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_flushBrPred ; - assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_flushBrPred ; + assign CAN_FIRE_RL_setDoFlushBrPred = + flush_brpred && fetchStage$emptyForFlush ; + assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = @@ -9982,8 +9987,8 @@ module mkCore(CLK, assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ; // rule RL_flushBrPred - assign CAN_FIRE_RL_flushBrPred = flush_brpred && fetchStage$emptyForFlush ; - assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_flushBrPred ; + assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; + assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; // rule RL_rl_debug_gpr_read assign CAN_FIRE_RL_rl_debug_gpr_read = @@ -10028,7 +10033,8 @@ module mkCore(CLK, f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] && rg_core_run_state == 2'd2 && !f_run_halt_reqs$D_OUT ; - assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ; + assign WILL_FIRE_RL_rl_debug_halt_req = + CAN_FIRE_RL_rl_debug_halt_req && !EN_coreReq_start ; // rule RL_rl_debug_halt_req_already_halted assign CAN_FIRE_RL_rl_debug_halt_req_already_halted = @@ -10443,8 +10449,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10498,7 +10504,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325 && + regRenamingTable_RDY_commit_0_commit__5265_AND_ETC___d15325 && NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15342 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10533,7 +10539,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_RDY_ETC___d15704 && + NOT_rob_deqPort_0_canDeq__5662_5663_OR_regRena_ETC___d15704 && NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15716 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11527,9 +11533,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13290 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11537,19 +11544,21 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13600 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_csrInstOrInterruptInflight_canon assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; @@ -11594,7 +11603,8 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_mmio_pRqQ_canonicalize assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ; @@ -12067,16 +12077,17 @@ module mkCore(CLK, WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; - assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst || - WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 = - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 && - csrf_rg_dcsr[2] ; - assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_3 = + WILL_FIRE_RL_renameStage_doRenaming_Trap && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_6 = + EN_coreReq_start && !coreReq_start_running ; assign MUX_rf$write_3_wr_1__PSEL_1 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || WILL_FIRE_RL_coreFix_memExe_doRespLdMem ; @@ -15277,21 +15288,24 @@ module mkCore(CLK, assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; // register renameStage_rg_m_halt_req - always@(WILL_FIRE_RL_rl_debug_resume or + always@(MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_3 or + WILL_FIRE_RL_rl_debug_resume or WILL_FIRE_RL_rl_debug_halt_req or - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or - MUX_renameStage_rg_m_halt_req$write_1__SEL_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; - WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30; - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || - MUX_renameStage_rg_m_halt_req$write_1__SEL_2: - renameStage_rg_m_halt_req$D_IN = 5'd31; - default: renameStage_rg_m_halt_req$D_IN = - 5'b01010 /* unspecified value */ ; - endcase - end + MUX_renameStage_rg_m_halt_req$write_1__SEL_6) + case (1'b1) + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_3: + renameStage_rg_m_halt_req$D_IN = 5'd31; + WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; + WILL_FIRE_RL_rl_debug_halt_req || + MUX_renameStage_rg_m_halt_req$write_1__SEL_6: + renameStage_rg_m_halt_req$D_IN = 5'd30; + default: renameStage_rg_m_halt_req$D_IN = + 5'b01010 /* unspecified value */ ; + endcase assign renameStage_rg_m_halt_req$EN = (WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap) && @@ -15299,6 +15313,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && csrf_rg_dcsr[2] || + EN_coreReq_start && !coreReq_start_running || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -16630,18 +16645,18 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = x__h290202 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; + assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] : (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] : 3'd0) ; - assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n = - coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ; + coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n ; always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or @@ -18468,7 +18483,7 @@ module mkCore(CLK, assign fetchStage$EN_train_predictors = coreFix_trainBPQ_1$EMPTY_N || WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ; - assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_flushBrPred ; + assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ; assign fetchStage$EN_perf_setStatus = 1'b0 ; assign fetchStage$EN_perf_req = 1'b0 ; assign fetchStage$EN_perf_resp = 1'b0 ; @@ -21604,8 +21619,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10049 = (_theResult___fst_exp__h603026 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21615,8 +21630,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10585 = (_theResult___fst_exp__h563722 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -24330,10 +24345,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14214 = IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14411 = @@ -24347,10 +24362,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14301 && IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14093 && (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14328 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338) ; + rob_RDY_enqPort_1_enq__4330_AND_NOT_fetchStage_ETC___d14338) ; assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14628 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && @@ -24702,7 +24717,7 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd11) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; assign NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14958 = NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14951 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && @@ -24724,7 +24739,7 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd14) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; assign NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15331 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -25693,9 +25708,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13985 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14154 ; - assign NOT_rob_deqPort_0_canDeq__5662_5663_OR_rob_RDY_ETC___d15704 = + assign NOT_rob_deqPort_0_canDeq__5662_5663_OR_regRena_ETC___d15704 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25734,7 +25749,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14267 = !specTagManager$canClaim || @@ -25768,21 +25783,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, x__h295972 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16427 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16382 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16391 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16382, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16400 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16391, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16401 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10246 = @@ -28158,7 +28173,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 : + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 ; assign _theResult___fst_exp__h564505 = (_theResult___fst_exp__h563722 == 11'd2047) ? @@ -28284,7 +28299,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 : + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 ; assign _theResult___fst_exp__h595025 = (_theResult___fst_exp__h594193 == 11'd2047) ? @@ -28314,7 +28329,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 : + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 ; assign _theResult___fst_exp__h603809 = (_theResult___fst_exp__h603026 == 11'd2047) ? @@ -29752,7 +29767,7 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd11 || !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 ; assign commitStage_f_rob_data_first__5082_BIT_167_518_ETC___d15254 = { commitStage_f_rob_data$D_OUT[167:166], commitStage_f_rob_data$D_OUT[166] ? @@ -30568,12 +30583,14 @@ module mkCore(CLK, fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; assign fcsr_csr__read__h615715 = { 56'd0, x__h619373 } ; - assign fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14334) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31385,14 +31402,13 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign r__h620917 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__5265_AND_ETC___d15325 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320 ; assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31921,13 +31937,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h618545 = { r1__read__h620943, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320 ; + assign rob_RDY_enqPort_1_enq__4330_AND_NOT_fetchStage_ETC___d14338 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14334) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4661_BITS_161_TO_98_46_ETC___d15638 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -33498,23 +33513,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33543,6 +33541,23 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19]) @@ -35403,70 +35418,18 @@ module mkCore(CLK, default: _theResult___fst_exp__h477007 = 8'd0; endcase end - always@(guard__h450619 or - _theResult___snd__h458618 or - out_sfd__h459113 or _theResult___sfd__h459110) - begin - case (guard__h450619) - 2'b0, 2'b01: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = - _theResult___snd__h458618[56:34]; - 2'b10: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = - out_sfd__h459113; - 2'b11: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = - _theResult___sfd__h459110; - endcase - end - always@(guard__h450619 or - _theResult___snd__h458618 or _theResult___sfd__h459110) - begin - case (guard__h450619) - 2'b0: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 = - _theResult___snd__h458618[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 = - _theResult___sfd__h459110; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 or - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 or - _theResult___snd__h458618) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h459188 = - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118; - 3'd1: - _theResult___fst_sfd__h459188 = - CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119; - 3'd2: - _theResult___fst_sfd__h459188 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860; - 3'd3: - _theResult___fst_sfd__h459188 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862; - 3'd4: _theResult___fst_sfd__h459188 = _theResult___snd__h458618[56:34]; - default: _theResult___fst_sfd__h459188 = 23'd0; - endcase - end always@(guard__h441912 or sfdin__h450005 or out_sfd__h450531 or _theResult___sfd__h450528) begin case (guard__h441912) 2'b0, 2'b01: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 = sfdin__h450005[56:34]; 2'b10: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 = out_sfd__h450531; 2'b11: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 = _theResult___sfd__h450528; endcase end @@ -35474,16 +35437,16 @@ module mkCore(CLK, begin case (guard__h441912) 2'b0: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119 = sfdin__h450005[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119 = _theResult___sfd__h450528; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 or - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 or + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118 or + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843 or sfdin__h450005) @@ -35491,10 +35454,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h450606 = - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q118; 3'd1: _theResult___fst_sfd__h450606 = - CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q119; 3'd2: _theResult___fst_sfd__h450606 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841; @@ -35505,6 +35468,58 @@ module mkCore(CLK, default: _theResult___fst_sfd__h450606 = 23'd0; endcase end + always@(guard__h450619 or + _theResult___snd__h458618 or + out_sfd__h459113 or _theResult___sfd__h459110) + begin + case (guard__h450619) + 2'b0, 2'b01: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 = + _theResult___snd__h458618[56:34]; + 2'b10: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 = + out_sfd__h459113; + 2'b11: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 = + _theResult___sfd__h459110; + endcase + end + always@(guard__h450619 or + _theResult___snd__h458618 or _theResult___sfd__h459110) + begin + case (guard__h450619) + 2'b0: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121 = + _theResult___snd__h458618[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121 = + _theResult___sfd__h459110; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120 or + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 or + _theResult___snd__h458618) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h459188 = + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q120; + 3'd1: + _theResult___fst_sfd__h459188 = + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q121; + 3'd2: + _theResult___fst_sfd__h459188 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860; + 3'd3: + _theResult___fst_sfd__h459188 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862; + 3'd4: _theResult___fst_sfd__h459188 = _theResult___snd__h458618[56:34]; + default: _theResult___fst_sfd__h459188 = 23'd0; + endcase + end always@(guard__h459549 or sfdin__h467771 or out_sfd__h468297 or _theResult___sfd__h468294) begin @@ -35612,61 +35627,23 @@ module mkCore(CLK, begin case (guard__h441912) 2'b0, 2'b01, 2'b10: - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h441912 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h441912) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - (guard__h441912 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h441912 != 2'b01 && guard__h441912 != 2'b10 && - guard__h441912 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h441912 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h441912) - 2'b0, 2'b01, 2'b10: - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = guard__h441912 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or guard__h441912) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = - CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = (guard__h441912 == 2'b0) ? @@ -35688,23 +35665,23 @@ module mkCore(CLK, begin case (guard__h450619) 2'b0, 2'b01, 2'b10: - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = guard__h450619 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or guard__h450619) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = - CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128; + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = (guard__h450619 == 2'b0) ? @@ -35721,6 +35698,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end + always@(guard__h441912 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h441912) + 2'b0, 2'b01, 2'b10: + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h441912 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h441912) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + (guard__h441912 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h441912 != 2'b01 && guard__h441912 != 2'b10 && + guard__h441912 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end always@(guard__h450619 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -36341,21 +36356,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595036 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576655 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595036) + case (guard__h576655) 2'b0, 2'b01, 2'b10: - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h595036 != 2'b11 || + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h576655 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595036) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576655) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36364,12 +36379,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h595036 == 2'b0) ? + (guard__h576655 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595036 != 2'b01 && guard__h595036 != 2'b10 && - guard__h595036 != 2'b11 || + guard__h576655 != 2'b01 && guard__h576655 != 2'b10 && + guard__h576655 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36380,21 +36395,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h576655 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576655) + case (guard__h595036) 2'b0, 2'b01, 2'b10: - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h576655 != 2'b11 || + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h595036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576655) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36403,12 +36418,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h576655 == 2'b0) ? + (guard__h595036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h576655 != 2'b01 && guard__h576655 != 2'b10 && - guard__h576655 != 2'b11 || + guard__h595036 != 2'b01 && guard__h595036 != 2'b10 && + guard__h595036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36521,66 +36536,15 @@ module mkCore(CLK, _theResult___exp__h555618; endcase end - always@(guard__h585967 or - _theResult___fst_exp__h594193 or _theResult___exp__h594922) - begin - case (guard__h585967) - 2'b0: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187 = - _theResult___fst_exp__h594193; - 2'b01, 2'b10, 2'b11: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187 = - _theResult___exp__h594922; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h594193 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 or - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - _theResult___fst_exp__h594193; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q187; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - 11'd0; - endcase - end - always@(guard__h585967 or - _theResult___fst_exp__h594193 or - out_exp__h594925 or _theResult___exp__h594922) - begin - case (guard__h585967) - 2'b0, 2'b01: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 = - _theResult___fst_exp__h594193; - 2'b10: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 = - out_exp__h594925; - 2'b11: - CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q188 = - _theResult___exp__h594922; - endcase - end always@(guard__h555732 or _theResult___fst_exp__h563722 or _theResult___exp__h564402) begin case (guard__h555732) 2'b0: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187 = _theResult___fst_exp__h563722; 2'b01, 2'b10, 2'b11: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187 = _theResult___exp__h564402; endcase end @@ -36588,7 +36552,7 @@ module mkCore(CLK, _theResult___fst_exp__h563722 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682 or - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189) + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36602,7 +36566,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q189; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = 11'd0; endcase @@ -36613,13 +36577,13 @@ module mkCore(CLK, begin case (guard__h555732) 2'b0, 2'b01: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = _theResult___fst_exp__h563722; 2'b10: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = out_exp__h564405; 2'b11: - CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q190 = + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = _theResult___exp__h564402; endcase end @@ -36628,10 +36592,10 @@ module mkCore(CLK, begin case (guard__h595036) 2'b0: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189 = _theResult___fst_exp__h603026; 2'b01, 2'b10, 2'b11: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189 = _theResult___exp__h603706; endcase end @@ -36639,7 +36603,7 @@ module mkCore(CLK, _theResult___fst_exp__h603026 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912 or - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191) + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36653,7 +36617,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = 11'd0; endcase @@ -36664,16 +36628,67 @@ module mkCore(CLK, begin case (guard__h595036) 2'b0, 2'b01: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 = _theResult___fst_exp__h603026; 2'b10: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 = out_exp__h603709; 2'b11: - CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q190 = _theResult___exp__h603706; endcase end + always@(guard__h585967 or + _theResult___fst_exp__h594193 or _theResult___exp__h594922) + begin + case (guard__h585967) + 2'b0: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191 = + _theResult___fst_exp__h594193; + 2'b01, 2'b10, 2'b11: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191 = + _theResult___exp__h594922; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h594193 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 or + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + _theResult___fst_exp__h594193; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q191; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = + 11'd0; + endcase + end + always@(guard__h585967 or + _theResult___fst_exp__h594193 or + out_exp__h594925 or _theResult___exp__h594922) + begin + case (guard__h585967) + 2'b0, 2'b01: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 = + _theResult___fst_exp__h594193; + 2'b10: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 = + out_exp__h594925; + 2'b11: + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q192 = + _theResult___exp__h594922; + endcase + end always@(guard__h537351 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h537351) @@ -38471,26 +38486,26 @@ module mkCore(CLK, begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = - !csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = + csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = - !csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = - !csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = + csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = + csrf_rg_dcsr[12]; endcase end always@(csrf_prv_reg or csrf_rg_dcsr) begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = - csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = + !csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = - csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = - csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = + !csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = + !csrf_rg_dcsr[12]; endcase end always@(rob$deqPort_0_deq_data) @@ -38944,15 +38959,6 @@ module mkCore(CLK, 3'd0; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -39166,6 +39172,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9999 or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9289 or diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index bb0d3be..607e8ac 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -78,6 +78,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// start_is_running I 1 // start_tohost_addr I 64 // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 @@ -161,6 +162,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -379,6 +381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1401,7 +1404,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1609,12 +1613,12 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5047; - reg [31 : 0] v__h5190; - reg [31 : 0] v__h15930; - reg [31 : 0] v__h5041; - reg [31 : 0] v__h5184; - reg [31 : 0] v__h15924; + reg [31 : 0] v__h5055; + reg [31 : 0] v__h5198; + reg [31 : 0] v__h15940; + reg [31 : 0] v__h5049; + reg [31 : 0] v__h5192; + reg [31 : 0] v__h15934; // synopsys translate_on // remaining internal signals @@ -2523,6 +2527,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2716,22 +2721,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -3359,6 +3364,7 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_proc$start_1__SEL_1 ? rg_fromhost_addr : start_fromhost_addr ; + assign proc$start_running = MUX_proc$start_1__SEL_1 || start_is_running ; assign proc$start_startpc = 64'h0000000070000000 ; assign proc$start_tohostAddr = MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; @@ -3700,15 +3706,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h5047 = $stime; + v__h5055 = $stime; #0; end - v__h5041 = v__h5047 / 32'd10; + v__h5049 = v__h5055 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h5041, + v__h5049, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -3716,17 +3722,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h5190 = $stime; + v__h5198 = $stime; #0; end - v__h5184 = v__h5190 / 32'd10; + v__h5192 = v__h5198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h5184, + v__h5192, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); @@ -3734,15 +3740,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15930 = $stime; + v__h15940 = $stime; #0; end - v__h15924 = v__h15930 / 32'd10; + v__h15934 = v__h15940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15924, + v__h15934, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v index add4077..64142bb 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v @@ -130,17 +130,13 @@ module mkJtagTap(CLK, // inlined wires wire [40 : 0] w_dmi_req$wget; - wire r_dmistat_busy$port1__read, + wire r_dmistat_busy$EN_port1__write, + r_dmistat_busy$port1__read, r_dmistat_busy$port2__read, r_tdo$EN_port0__write, r_tdo$port0__write_1, r_tdo$port1__read; - // register r_dmi - reg [39 : 0] r_dmi; - wire [39 : 0] r_dmi$D_IN; - wire r_dmi$EN; - // register r_dmistat_busy reg r_dmistat_busy; wire r_dmistat_busy$D_IN, r_dmistat_busy$EN; @@ -160,11 +156,6 @@ module mkJtagTap(CLK, wire [4 : 0] r_ir$D_IN; wire r_ir$EN; - // register r_state - reg [3 : 0] r_state; - wire [3 : 0] r_state$D_IN; - wire r_state$EN; - // register r_tdo reg r_tdo; wire r_tdo$D_IN, r_tdo$EN; @@ -179,6 +170,7 @@ module mkJtagTap(CLK, // ports of submodule f_dmi_req wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN; wire f_dmi_req$dCLR, + f_dmi_req$dCLR_RDY, f_dmi_req$dDEQ, f_dmi_req$dEMPTY_N, f_dmi_req$sCLR, @@ -193,18 +185,32 @@ module mkJtagTap(CLK, f_dmi_rsp$dDEQ, f_dmi_rsp$dEMPTY_N, f_dmi_rsp$sCLR, + f_dmi_rsp$sCLR_RDY, f_dmi_rsp$sENQ, f_dmi_rsp$sFULL_N; + // ports of submodule r_dmi + wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT; + wire r_dmi$EN; + + // ports of submodule r_initialize + wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT; + + // ports of submodule r_initialize2 + wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT; + + // ports of submodule r_state + wire [3 : 0] r_state$D_IN, r_state$Q_OUT; + wire r_state$EN; + // ports of submodule rst_tck wire rst_tck$OUT_RST; // ports of submodule tck_clock - wire tck_clock$CLK_IN, - tck_clock$CLK_IN_EN, - tck_clock$CLK_OUT, - tck_clock$COND_IN, - tck_clock$COND_IN_EN; + wire tck_clock$IN, tck_clock$OUT; + + // ports of submodule w_tck_crossed + wire w_tck_crossed$DOUT; // rule scheduling signals wire CAN_FIRE_RL_dmi_request, @@ -215,7 +221,9 @@ module mkJtagTap(CLK, CAN_FIRE_RL_dmi_response_ready, CAN_FIRE_RL_dmi_response_tck, CAN_FIRE_RL_dmi_start, - CAN_FIRE_RL_rl_tck, + CAN_FIRE_RL_mkConnectionVtoAf, + CAN_FIRE_RL_rl_initialize, + CAN_FIRE_RL_rl_initialize2, CAN_FIRE_RL_tick, CAN_FIRE_dmi_req_ready, CAN_FIRE_dmi_rsp_data, @@ -232,7 +240,9 @@ module mkJtagTap(CLK, WILL_FIRE_RL_dmi_response_ready, WILL_FIRE_RL_dmi_response_tck, WILL_FIRE_RL_dmi_start, - WILL_FIRE_RL_rl_tck, + WILL_FIRE_RL_mkConnectionVtoAf, + WILL_FIRE_RL_rl_initialize, + WILL_FIRE_RL_rl_initialize2, WILL_FIRE_RL_tick, WILL_FIRE_dmi_req_ready, WILL_FIRE_dmi_rsp_data, @@ -243,24 +253,24 @@ module mkJtagTap(CLK, WILL_FIRE_jtag_tms; // remaining internal signals - reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1, - v__h2135; - reg [4 : 0] newir__h3435; - reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3, - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2; - wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140, - v__h2233, - v__h2601, - x__h2449, - x__h2658, - y__h2659; - wire [4 : 0] v__h3299, x__h3350, y__h3351; - wire r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57, - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68, - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72; + reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1, + v__h2479; + reg [4 : 0] newir__h3774; + reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3, + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2; + wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146, + v__h2576, + v__h2941, + x__h2789, + x__h2996, + y__h2997; + wire [4 : 0] v__h3636, x__h3687, y__h3688; + wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78; // oscillator and gates for output clock CLK_jtag_tclk_out - assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ; + assign CLK_jtag_tclk_out = tck_clock$OUT ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; // action method jtag_tdi @@ -311,7 +321,7 @@ module mkJtagTap(CLK, // submodule f_dmi_busy FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST), - .CLK(tck_clock$CLK_OUT), + .CLK(tck_clock$OUT), .ENQ(f_dmi_busy$ENQ), .DEQ(f_dmi_busy$DEQ), .CLR(f_dmi_busy$CLR), @@ -321,7 +331,7 @@ module mkJtagTap(CLK, // submodule f_dmi_req SyncFIFOLevel #(.dataWidth(32'd41), .depth(32'd2), - .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT), + .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT), .dCLK(CLK), .sRST(rst_tck$OUT_RST), .sD_IN(f_dmi_req$sD_IN), @@ -335,13 +345,13 @@ module mkJtagTap(CLK, .dCOUNT(), .sCOUNT(), .sCLR_RDY(f_dmi_req$sCLR_RDY), - .dCLR_RDY()); + .dCLR_RDY(f_dmi_req$dCLR_RDY)); // submodule f_dmi_rsp SyncFIFOLevel #(.dataWidth(32'd40), .depth(32'd2), .indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK), - .dCLK(tck_clock$CLK_OUT), + .dCLK(tck_clock$OUT), .sRST(RST_N), .sD_IN(f_dmi_rsp$sD_IN), .sENQ(f_dmi_rsp$sENQ), @@ -353,29 +363,46 @@ module mkJtagTap(CLK, .dEMPTY_N(f_dmi_rsp$dEMPTY_N), .dCOUNT(), .sCOUNT(), - .sCLR_RDY(), + .sCLR_RDY(f_dmi_rsp$sCLR_RDY), .dCLR_RDY(f_dmi_rsp$dCLR_RDY)); + // submodule r_dmi + RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT), + .D_IN(r_dmi$D_IN), + .EN(r_dmi$EN), + .Q_OUT(r_dmi$Q_OUT)); + + // submodule r_initialize + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT), + .D_IN(r_initialize$D_IN), + .EN(r_initialize$EN), + .Q_OUT(r_initialize$Q_OUT)); + + // submodule r_initialize2 + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK), + .D_IN(r_initialize2$D_IN), + .EN(r_initialize2$EN), + .Q_OUT(r_initialize2$Q_OUT)); + + // submodule r_state + RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT), + .D_IN(r_state$D_IN), + .EN(r_state$EN), + .Q_OUT(r_state$Q_OUT)); + // submodule rst_tck - SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT), - .IN_RST(RST_N), - .OUT_RST(rst_tck$OUT_RST)); + SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST)); // submodule tck_clock - MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK), - .RST(RST_N), - .CLK_IN(tck_clock$CLK_IN), - .COND_IN(tck_clock$COND_IN), - .CLK_IN_EN(tck_clock$CLK_IN_EN), - .COND_IN_EN(tck_clock$COND_IN_EN), - .CLK_VAL_OUT(), - .COND_OUT(), - .CLK_GATE_OUT(), - .CLK_OUT(tck_clock$CLK_OUT)); + ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT)); - // rule RL_rl_tck - assign CAN_FIRE_RL_rl_tck = 1'd1 ; - assign WILL_FIRE_RL_rl_tck = 1'd1 ; + // submodule w_tck_crossed + SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk), + .DOUT(w_tck_crossed$DOUT)); + + // rule RL_mkConnectionVtoAf + assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; + assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ; // rule RL_tick assign CAN_FIRE_RL_tick = 1'd1 ; @@ -383,7 +410,7 @@ module mkJtagTap(CLK, // rule RL_dmi_start assign CAN_FIRE_RL_dmi_start = - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78 && f_dmi_req$sFULL_N && f_dmi_busy$FULL_N && w_dmi_req$wget[1:0] != 2'd0 ; @@ -406,9 +433,14 @@ module mkJtagTap(CLK, f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ; assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ; + // rule RL_rl_initialize + assign CAN_FIRE_RL_rl_initialize = + r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ; + // rule RL_dmi_reset assign CAN_FIRE_RL_dmi_reset = - r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63 && (!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ; assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ; @@ -420,35 +452,37 @@ module mkJtagTap(CLK, assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ; assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ; + // rule RL_rl_initialize2 + assign CAN_FIRE_RL_rl_initialize2 = + f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ; + // inlined wires assign w_dmi_req$wget = { 1'd0, r_dr } ; - assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ; - assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ; + assign r_tdo$EN_port0__write = + r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ; + assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ; assign r_tdo$port1__read = r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ; assign r_dmistat_busy$port1__read = - r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68 || + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74 || r_dmistat_busy ; + assign r_dmistat_busy$EN_port1__write = + WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ; assign r_dmistat_busy$port2__read = - !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ; - - // register r_dmi - assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; - assign r_dmi$EN = - WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 ; + !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ; // register r_dmistat_busy assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ; assign r_dmistat_busy$EN = 1'b1 ; // register r_dr - always@(r_state or r_dr or v__h2135 or v__h2601) + always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941) begin - case (r_state) + case (r_state$Q_OUT) 4'd0: r_dr$D_IN = r_dr; - 4'd3: r_dr$D_IN = v__h2135; - 4'd4: r_dr$D_IN = v__h2601; + 4'd3: r_dr$D_IN = v__h2479; + 4'd4: r_dr$D_IN = v__h2941; default: r_dr$D_IN = r_dr; endcase end @@ -456,22 +490,15 @@ module mkJtagTap(CLK, // register r_drmask assign r_drmask$D_IN = - (r_state == 4'd3) ? - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 : + (r_state$Q_OUT == 4'd3) ? + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 : r_drmask ; assign r_drmask$EN = 1'd1 ; // register r_ir - assign r_ir$D_IN = newir__h3435 ; + assign r_ir$D_IN = newir__h3774 ; assign r_ir$EN = 1'd1 ; - // register r_state - assign r_state$D_IN = - jtag_tms ? - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 : - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ; - assign r_state$EN = 1'd1 ; - // register r_tdo assign r_tdo$D_IN = r_tdo$port1__read ; assign r_tdo$EN = 1'b1 ; @@ -479,146 +506,165 @@ module mkJtagTap(CLK, // submodule f_dmi_busy assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + assign f_dmi_busy$CLR = + WILL_FIRE_RL_dmi_reset && r_dr[17] || + WILL_FIRE_RL_rl_initialize ; // submodule f_dmi_req assign f_dmi_req$sD_IN = w_dmi_req$wget ; assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ; assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; - assign f_dmi_req$dCLR = 1'b0 ; + assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ; // submodule f_dmi_rsp assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ; assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ; assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_rsp$sCLR = 1'b0 ; + assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ; assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + // submodule r_dmi + assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; + assign r_dmi$EN = + WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 ; + + // submodule r_initialize + assign r_initialize$D_IN = 1'd0 ; + assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ; + + // submodule r_initialize2 + assign r_initialize2$D_IN = 1'd0 ; + assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ; + + // submodule r_state + assign r_state$D_IN = + jtag_tms ? + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 : + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ; + assign r_state$EN = 1'd1 ; + // submodule tck_clock - assign tck_clock$CLK_IN = jtag_tclk ; - assign tck_clock$COND_IN = 1'b0 ; - assign tck_clock$CLK_IN_EN = 1'd1 ; - assign tck_clock$COND_IN_EN = 1'b0 ; + assign tck_clock$IN = w_tck_crossed$DOUT ; // remaining internal signals - assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 = + assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 = (r_dmistat_busy || - r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N) ? 40'hAAAAAAAAAB : - r_dmi ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0x10_2_AND_r_dr_8_B_ETC___d57 = - r_state == 4'd8 && r_ir == 5'h10 && (r_dr[17] || r_dr[16]) ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d68 = - r_state == 4'd8 && r_ir == 5'h11 && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x10_9_AND__ETC___d63 = + r_state$Q_OUT == 4'd8 && r_ir == 5'h10 && + (r_dr[17] || r_dr[16]) ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d74 = + r_state$Q_OUT == 4'd8 && r_ir == 5'h11 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0x11_4_AND_NOT_r_dm_ETC___d72 = - r_state == 4'd8 && r_ir == 5'h11 && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0x11_1_AND__ETC___d78 = + r_state$Q_OUT == 4'd8 && r_ir == 5'h11 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && !f_dmi_busy$EMPTY_N ; - assign v__h2233 = { 35'd7864320, r_ir } ; - assign v__h2601 = x__h2658 | y__h2659 ; - assign v__h3299 = x__h3350 | y__h3351 ; - assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ; - assign x__h2658 = { 1'd0, r_dr[39:1] } ; - assign x__h3350 = { 1'd0, r_ir[4:1] } ; - assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ; - assign y__h3351 = jtag_tdi ? 5'd16 : 5'd0 ; - always@(r_state or r_ir or v__h3299) + assign v__h2576 = { 35'd7864320, r_ir } ; + assign v__h2941 = x__h2996 | y__h2997 ; + assign v__h3636 = x__h3687 | y__h3688 ; + assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ; + assign x__h2996 = { 1'd0, r_dr[39:1] } ; + assign x__h3687 = { 1'd0, r_ir[4:1] } ; + assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ; + assign y__h3688 = jtag_tdi ? 5'd16 : 5'd0 ; + always@(r_state$Q_OUT or r_ir or v__h3636) begin - case (r_state) - 4'd0: newir__h3435 = 5'd1; - 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir; - 4'd11: newir__h3435 = v__h3299; - default: newir__h3435 = r_ir; + case (r_state$Q_OUT) + 4'd0: newir__h3774 = 5'd1; + 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir; + 4'd11: newir__h3774 = v__h3636; + default: newir__h3774 = r_ir; endcase end always@(r_ir or - v__h2233 or - x__h2449 or - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140) + v__h2576 or + x__h2789 or + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146) begin case (r_ir) - 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: v__h2135 = 40'd0; - 5'd1: v__h2135 = 40'd4093; - 5'h10: v__h2135 = x__h2449; + 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: v__h2479 = 40'd0; + 5'd1: v__h2479 = 40'd4093; + 5'h10: v__h2479 = x__h2789; 5'h11: - v__h2135 = - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140; - default: v__h2135 = v__h2233; + v__h2479 = + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146; + default: v__h2479 = v__h2576; endcase end - always@(newir__h3435) + always@(newir__h3774) begin - case (newir__h3435) + case (newir__h3774) 5'd0, 5'h12, 5'h13, 5'h14, 5'h15, 5'h16, 5'h17, 5'd31: - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'd1; + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'd1; 5'd1, 5'h10: - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'h0080000000; 5'h11: - CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'h8000000000; - default: CASE_newir435_0_1_1_2147483648_0x10_2147483648_ETC__q1 = + default: CASE_newir774_0_1_1_2147483648_0x10_2147483648_ETC__q1 = 40'h0100000000; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) - 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state; + case (r_state$Q_OUT) + 4'd0: + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = + r_state$Q_OUT; 4'd1, 4'd8, 4'd15: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2; - 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9; - 4'd3, 4'd4: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5; - 4'd5, 4'd7: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8; - 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7; - 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2; + 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9; + 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5; + 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8; + 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7; + 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0; 4'd10, 4'd11: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12; 4'd12, 4'd14: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15; - 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15; + 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) + case (r_state$Q_OUT) 4'd0, 4'd1, 4'd8, 4'd15: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1; - 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1; + 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3; 4'd3, 4'd4, 4'd7: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4; 4'd5, 4'd6: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6; - 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6; + 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10; 4'd10, 4'd11, 4'd14: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11; 4'd12, 4'd13: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13; endcase end // handling of inlined registers - always@(posedge tck_clock$CLK_OUT) + always@(posedge tck_clock$OUT) begin if (rst_tck$OUT_RST == `BSV_RESET_VALUE) begin - r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0; - r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - r_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN; - if (r_dmistat_busy$EN) + if (r_dmistat_busy$EN) r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN; - if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN; end if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN; if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN; @@ -631,12 +677,10 @@ module mkJtagTap(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - r_dmi = 40'hAAAAAAAAAA; r_dmistat_busy = 1'h0; r_dr = 40'hAAAAAAAAAA; r_drmask = 40'hAAAAAAAAAA; r_ir = 5'h0A; - r_state = 4'hA; r_tdo = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS @@ -645,11 +689,12 @@ module mkJtagTap(CLK, // handling of system tasks // synopsys translate_off - always@(negedge tck_clock$CLK_OUT) + always@(negedge tck_clock$OUT) begin #0; if (rst_tck$OUT_RST != `BSV_RESET_VALUE) - if (r_state == 4'd3 && r_ir != 5'd0 && r_ir != 5'h12 && r_ir != 5'h13 && + if (r_state$Q_OUT == 4'd3 && r_ir != 5'd0 && r_ir != 5'h12 && + r_ir != 5'h13 && r_ir != 5'h14 && r_ir != 5'h15 && r_ir != 5'h16 && diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v index b1f7022..4f1d8af 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v @@ -648,14 +648,19 @@ module mkP3_Core(CLK, wire bus_dmi_rsp_fifof_q_1$EN; // register rg_corew_start_after_por - reg rg_corew_start_after_por; - wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + reg [7 : 0] rg_corew_start_after_por; + wire [7 : 0] rg_corew_start_after_por$D_IN; + wire rg_corew_start_after_por$EN; // register rg_ndm_reset_delay reg [7 : 0] rg_ndm_reset_delay; wire [7 : 0] rg_ndm_reset_delay$D_IN; wire rg_ndm_reset_delay$EN; + // register rg_running + reg rg_running; + wire rg_running$D_IN, rg_running$EN; + // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; wire bus_dmi_req_fifof$CLR, @@ -781,8 +786,10 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, + corew$ndm_reset_client_request_get, corew$ndm_reset_client_response_put, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -804,6 +811,9 @@ module mkP3_Core(CLK, // ports of submodule ndm_reset_controller wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule por_ifc + wire por_ifc$RST_N_gen_rst; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -896,7 +906,7 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2, - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1, + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2; wire [7 : 0] MUX_rg_ndm_reset_delay$write_1__VAL_1; @@ -910,15 +920,15 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1279; - reg [31 : 0] v__h1424; - reg [31 : 0] v__h1273; - reg [31 : 0] v__h1418; + reg [31 : 0] v__h1362; + reg [31 : 0] v__h1510; + reg [31 : 0] v__h1356; + reg [31 : 0] v__h1504; // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; - wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49; + wire IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99, _dfoo1, _dfoo3; @@ -1188,7 +1198,7 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(por_ifc$RST_N_gen_rst), .CLK(CLK), .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), @@ -1237,6 +1247,7 @@ module mkP3_Core(CLK, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1308,7 +1319,7 @@ module mkP3_Core(CLK, .dmi_read_data(corew$dmi_read_data), .RDY_dmi_read_data(corew$RDY_dmi_read_data), .RDY_dmi_write(corew$RDY_dmi_write), - .ndm_reset_client_request_get(), + .ndm_reset_client_request_get(corew$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), @@ -1316,7 +1327,7 @@ module mkP3_Core(CLK, // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), - .RST_N(RST_N), + .RST_N(por_ifc$RST_N_gen_rst), .dmi_req_ready(jtagtap$dmi_req_ready), .dmi_rsp_data(jtagtap$dmi_rsp_data), .dmi_rsp_response(jtagtap$dmi_rsp_response), @@ -1334,7 +1345,7 @@ module mkP3_Core(CLK, .CLK_GATE_jtag_tclk_out()); // submodule ndm_reset - ResetEither ndm_reset(.A_RST(RST_N), + ResetEither ndm_reset(.A_RST(por_ifc$RST_N_gen_rst), .B_RST(ndm_reset_controller$OUT_RST), .RST_OUT(ndm_reset$RST_OUT)); @@ -1346,6 +1357,11 @@ module mkP3_Core(CLK, .ASSERT_OUT(), .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule por_ifc + mkPowerOnReset por_ifc(.CLK(CLK), + .RST_N(RST_N), + .RST_N_gen_rst(por_ifc$RST_N_gen_rst)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1371,7 +1387,8 @@ module mkP3_Core(CLK, // rule RL_rl_step_0 assign CAN_FIRE_RL_rl_step_0 = - corew$RDY_start && !rg_corew_start_after_por ; + (rg_corew_start_after_por != 8'd1 || corew$RDY_start) && + rg_corew_start_after_por != 8'd0 ; assign WILL_FIRE_RL_rl_step_0 = CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; @@ -1422,7 +1439,7 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; + IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu @@ -1434,7 +1451,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; @@ -1478,15 +1495,15 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 ; + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ; @@ -1495,16 +1512,16 @@ module mkP3_Core(CLK, assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 = bus_dmi_rsp_fifof_cntr_r + 2'd1 ; assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 = - (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : - bus_dmi_rsp_fifof_q_1 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 ? MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 : MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 = + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = + (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : + bus_dmi_rsp_fifof_q_1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 = (bus_dmi_rsp_fifof_cntr_r == 2'd2) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : 34'd0 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 = { 32'hAAAAAAAA, @@ -1526,7 +1543,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1553,25 +1570,25 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_0$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register bus_dmi_rsp_fifof_q_1 always@(MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 or - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 or + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 or MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 or - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 or WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr) begin case (1'b1) // synopsys parallel_case MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1; + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1; MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2; + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2; WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr: bus_dmi_rsp_fifof_q_1$D_IN = 34'd0; default: bus_dmi_rsp_fifof_q_1$D_IN = @@ -1579,13 +1596,13 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_1$EN = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register rg_corew_start_after_por - assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$D_IN = rg_corew_start_after_por - 8'd1 ; assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; // register rg_ndm_reset_delay @@ -1596,6 +1613,10 @@ module mkP3_Core(CLK, assign rg_ndm_reset_delay$EN = WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; + // register rg_running + assign rg_running$D_IN = corew$ndm_reset_client_request_get ; + assign rg_running$EN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; assign bus_dmi_req_fifof$ENQ = CAN_FIRE_RL_bus_dmi_req_do_enq ; @@ -1660,16 +1681,17 @@ module mkP3_Core(CLK, assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$ndm_reset_client_response_put = rg_running ; assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_is_running = !MUX_corew$start_1__SEL_1 || rg_running ; assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || - WILL_FIRE_RL_rl_step_0 ; + WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1699,7 +1721,7 @@ module mkP3_Core(CLK, assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = + assign IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || @@ -1708,11 +1730,11 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1724,7 +1746,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 8'd100; rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else @@ -1744,6 +1766,7 @@ module mkP3_Core(CLK, if (rg_ndm_reset_delay$EN) rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end + if (rg_running$EN) rg_running <= `BSV_ASSIGNMENT_DELAY rg_running$D_IN; end // synopsys translate_off @@ -1754,8 +1777,9 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_corew_start_after_por = 1'h0; + rg_corew_start_after_por = 8'hAA; rg_ndm_reset_delay = 8'hAA; + rg_running = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1767,30 +1791,34 @@ module mkP3_Core(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - begin - v__h1279 = $stime; - #0; - end - v__h1273 = v__h1279 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1273, - $signed(32'd10)); - if (RST_N != `BSV_RESET_VALUE) - if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1424 = $stime; + v__h1362 = $stime; #0; end - v__h1418 = v__h1424 / 32'd10; + v__h1356 = v__h1362 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1356, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) - $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1418); + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1510 = $stime; + #0; + end + v__h1504 = v__h1510 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1504); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v new file mode 100644 index 0000000..65d7430 --- /dev/null +++ b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v @@ -0,0 +1,92 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// +// +// +// Ports: +// Name I/O size props +// RST_N_gen_rst O 1 reset +// CLK I 1 clock +// RST_N I 1 unused +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkPowerOnReset(CLK, + RST_N, + + RST_N_gen_rst); + input CLK; + input RST_N; + + // output resets + output RST_N_gen_rst; + + // signals for module outputs + wire RST_N_gen_rst; + + // ports of submodule ctr + wire [7 : 0] ctr$D_IN, ctr$Q_OUT; + wire ctr$EN; + + // ports of submodule isInPowerOnReset + wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT; + + // ports of submodule rst_ifc + wire rst_ifc$OUT; + + // rule scheduling signals + wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown; + + // remaining internal signals + wire NOT_isInPowerOnReset__read___d5; + + // output resets + assign RST_N_gen_rst = rst_ifc$OUT ; + + // submodule ctr + RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK), + .D_IN(ctr$D_IN), + .EN(ctr$EN), + .Q_OUT(ctr$Q_OUT)); + + // submodule isInPowerOnReset + RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK), + .D_IN(isInPowerOnReset$D_IN), + .EN(isInPowerOnReset$EN), + .Q_OUT(isInPowerOnReset$Q_OUT)); + + // submodule rst_ifc + ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT)); + + // rule RL_countDown + assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + + // submodule ctr + assign ctr$D_IN = ctr$Q_OUT - 8'd1 ; + assign ctr$EN = isInPowerOnReset$Q_OUT ; + + // submodule isInPowerOnReset + assign isInPowerOnReset$D_IN = 1'd0 ; + assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ; + + // remaining internal signals + assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ; +endmodule // mkPowerOnReset + diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index 6ec567d..6af5681 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -94,6 +94,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -192,6 +193,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -454,6 +456,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1421,6 +1424,7 @@ module mkProc(CLK, core_0$EN_v_to_TV_0_get, core_0$EN_v_to_TV_1_get, core_0$RDY_coreIndInv_terminate, + core_0$RDY_coreReq_start, core_0$RDY_dCacheToParent_fromP_enq, core_0$RDY_dCacheToParent_rqToP_deq, core_0$RDY_dCacheToParent_rqToP_first, @@ -1461,6 +1465,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_respLd_enq, core_0$RDY_v_to_TV_0_get, core_0$RDY_v_to_TV_1_get, + core_0$coreReq_start_running, core_0$hart0_run_halt_server_request_put, core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, @@ -2104,60 +2109,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163582; - reg [31 : 0] v__h163118; - reg [31 : 0] v__h5520; - reg [31 : 0] v__h5693; - reg [31 : 0] v__h5953; - reg [31 : 0] v__h8095; - reg [31 : 0] v__h8310; - reg [31 : 0] v__h2670; - reg [31 : 0] v__h4343; - reg [31 : 0] v__h9480; - reg [31 : 0] v__h9973; - reg [31 : 0] v__h10136; - reg [31 : 0] v__h135075; - reg [31 : 0] v__h135242; - reg [31 : 0] v__h137345; - reg [31 : 0] v__h154689; - reg [31 : 0] v__h134456; - reg [31 : 0] v__h161383; - reg [31 : 0] v__h161891; - reg [31 : 0] v__h2664; - reg [31 : 0] v__h4337; - reg [31 : 0] v__h5514; - reg [31 : 0] v__h5687; - reg [31 : 0] v__h5947; - reg [31 : 0] v__h8089; - reg [31 : 0] v__h8304; - reg [31 : 0] v__h9474; - reg [31 : 0] v__h9967; - reg [31 : 0] v__h10130; - reg [31 : 0] v__h134450; - reg [31 : 0] v__h135069; - reg [31 : 0] v__h135236; - reg [31 : 0] v__h137339; - reg [31 : 0] v__h154683; - reg [31 : 0] v__h161377; - reg [31 : 0] v__h161885; - reg [31 : 0] v__h163112; - reg [31 : 0] v__h163576; + reg [31 : 0] v__h163594; + reg [31 : 0] v__h163126; + reg [31 : 0] v__h5528; + reg [31 : 0] v__h5701; + reg [31 : 0] v__h5961; + reg [31 : 0] v__h8103; + reg [31 : 0] v__h8318; + reg [31 : 0] v__h2678; + reg [31 : 0] v__h4351; + reg [31 : 0] v__h9488; + reg [31 : 0] v__h9981; + reg [31 : 0] v__h10144; + reg [31 : 0] v__h135083; + reg [31 : 0] v__h135250; + reg [31 : 0] v__h137353; + reg [31 : 0] v__h154697; + reg [31 : 0] v__h134464; + reg [31 : 0] v__h161391; + reg [31 : 0] v__h161899; + reg [31 : 0] v__h2672; + reg [31 : 0] v__h4345; + reg [31 : 0] v__h5522; + reg [31 : 0] v__h5695; + reg [31 : 0] v__h5955; + reg [31 : 0] v__h8097; + reg [31 : 0] v__h8312; + reg [31 : 0] v__h9482; + reg [31 : 0] v__h9975; + reg [31 : 0] v__h10138; + reg [31 : 0] v__h134458; + reg [31 : 0] v__h135077; + reg [31 : 0] v__h135244; + reg [31 : 0] v__h137347; + reg [31 : 0] v__h154691; + reg [31 : 0] v__h161385; + reg [31 : 0] v__h161893; + reg [31 : 0] v__h163120; + reg [31 : 0] v__h163588; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34, + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, @@ -2167,44 +2172,44 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, - data64__h148515, - dword__h94382, - ld_data__h132631, - old_dword__h90072, - w1__h48093, - w1__h48098, - w2__h48094, - w2__h48100, - x__h48089; + data64__h148523, + dword__h94390, + ld_data__h132639, + old_dword__h90080, + w1__h48101, + w1__h48106, + w2__h48102, + w2__h48108, + x__h48097; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h148516; + reg [7 : 0] strb8__h148524; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61807; + reg [2 : 0] x__h61815; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; + CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, + CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20, SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, - x__h61814, - x__h82716; + x__h61822, + x__h82724; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - new_cline__h135378; + new_cline__h135386; wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, @@ -2225,89 +2230,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - data__h31950, - failed_testnum__h163161, - line_addr__h102446, - line_addr__h102532, - mask__h90069, - mem_req_rd_addr_araddr__h134676, - mem_req_wr_addr_awaddr__h148600, - mmioPlatform_fromHostQ_data_0__h42745, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48685, - n__read_addr__h61675, - n__read_addr__h61760, - n__read_addr__h80478, - n__read_addr__h80557, - n__read_snd_addr__h123973, - newData__h32031, - newData__h34961, - new_dword__h90073, - op_result__h48701, - op_result__h49231, - op_result__h49236, - op_result__h49241, - op_result__h49246, - op_result__h49252, - op_result__h49259, - op_result__h49265, - result__h48144, - result__h48268, - result__h48296, - result__h48324, - result__h48352, - result__h48380, - result__h48408, - result__h48436, - result__h48464, - result__h48509, - result__h48537, - result__h48565, - result__h48593, - result__h48634, - result__h48662, - result__h48788, - result__h48815, - result__h48842, - result__h48869, - result__h48896, - result__h48923, - result__h48950, - result__h48977, - result__h49021, - result__h49048, - result__h49075, - result__h49102, - result__h49142, - result__h49169, - result__h49286, - result__h49352, - result__h49418, - result__h49484, - result__h49550, - result__h49616, - result__h49682, - result__h49744, - result__h49789, - result__h49855, - result__h49921, - result__h49979, - result__h50024, - w1___1__h48203, - w2___1__h48204, - x1_avValue_data__h40417, - x1_avValue_data__h45022, - x__h32142, - x__h35052, - x__h37412, - x__h40935, - x__h40946, - x__h43001, - x__h43012, - x__h50201, - x__h91235, - y__h91236, - y__h91237; + data__h31958, + failed_testnum__h163169, + line_addr__h102454, + line_addr__h102540, + mask__h90077, + mem_req_rd_addr_araddr__h134684, + mem_req_wr_addr_awaddr__h148608, + mmioPlatform_fromHostQ_data_0__h42753, + mmioPlatform_mtime__h37272, + mmioPlatform_reqData__h48693, + n__read_addr__h61683, + n__read_addr__h61768, + n__read_addr__h80486, + n__read_addr__h80565, + n__read_snd_addr__h123981, + newData__h32039, + newData__h34969, + new_dword__h90081, + op_result__h48709, + op_result__h49239, + op_result__h49244, + op_result__h49249, + op_result__h49254, + op_result__h49260, + op_result__h49267, + op_result__h49273, + result__h48152, + result__h48276, + result__h48304, + result__h48332, + result__h48360, + result__h48388, + result__h48416, + result__h48444, + result__h48472, + result__h48517, + result__h48545, + result__h48573, + result__h48601, + result__h48642, + result__h48670, + result__h48796, + result__h48823, + result__h48850, + result__h48877, + result__h48904, + result__h48931, + result__h48958, + result__h48985, + result__h49029, + result__h49056, + result__h49083, + result__h49110, + result__h49150, + result__h49177, + result__h49294, + result__h49360, + result__h49426, + result__h49492, + result__h49558, + result__h49624, + result__h49690, + result__h49752, + result__h49797, + result__h49863, + result__h49929, + result__h49987, + result__h50032, + w1___1__h48211, + w2___1__h48212, + x1_avValue_data__h40425, + x1_avValue_data__h45030, + x__h32150, + x__h35060, + x__h37420, + x__h40943, + x__h40954, + x__h43009, + x__h43020, + x__h50209, + x__h91243, + y__h91244, + y__h91245; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; @@ -2319,16 +2324,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w18093_BITS_31_TO_0__q15, - w28094_BITS_31_TO_0__q16, - x_data__h30533; + v__h31751, + v__h31788, + w18101_BITS_31_TO_0__q15, + w28102_BITS_31_TO_0__q16, + x_data__h30541; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; - wire [5 : 0] x__h134711, x__h148625; + wire [5 : 0] x__h134719, x__h148633; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; - wire [3 : 0] b__h134383, b__h2564; - wire [2 : 0] n__read_id__h61679, n__read_id__h61764, x__h7925; + wire [3 : 0] b__h134391, b__h2572; + wire [2 : 0] n__read_id__h61687, n__read_id__h61772, x__h7933; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, @@ -2390,27 +2395,28 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqBE_BIT_0___h30166, + mmioPlatform_reqBE_BIT_4___h30126, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61680, - n__read_child__h61765, - n__read_child__h80481, - n__read_child__h80560, - n__read_snd_id__h123974, + n__read_child__h61688, + n__read_child__h61773, + n__read_child__h80489, + n__read_child__h80568, + n__read_snd_id__h123982, propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, - x__h61493, - x__h75229, - x__h80300; + x__h61501, + x__h75237, + x__h80308; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; - assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; + assign CAN_FIRE_start = + mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; assign WILL_FIRE_start = EN_start ; // value method master0_m_awvalid @@ -2845,6 +2851,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -2901,7 +2908,7 @@ module mkProc(CLK, .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), .EN_v_to_TV_0_get(core_0$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(core_0$EN_v_to_TV_1_get), - .RDY_coreReq_start(), + .RDY_coreReq_start(core_0$RDY_coreReq_start), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), .RDY_coreIndInv_perfResp(), @@ -3676,14 +3683,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2564 == 4'd0 ; + b__h2572 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2564 != 4'd0 && + b__h2572 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3796,7 +3803,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h43001 == 64'd0 || + x__h43009 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -4116,13 +4123,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134383 == 4'd0 ; + b__h134391 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134383 != 4'd0 && + b__h134391 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4226,7 +4233,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30541 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -4266,7 +4273,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31958 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -4291,10 +4298,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102446, + { line_addr__h102454, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102532, + { line_addr__h102540, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4305,11 +4312,11 @@ module mkProc(CLK, { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4408,7 +4415,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48089 } ; + x__h48097 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4417,7 +4424,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50201, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50209, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4432,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43001 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43009 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h43001 != 64'd0 ; + x__h43009 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40935 == 64'd0 ; + x__h40943 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61493 ; + x__h61501 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23, SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80300 ; + x__h80308 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123973, n__read_snd_id__h123974 } ; + { 1'd1, n__read_snd_addr__h123981, n__read_snd_id__h123982 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4526,11 +4533,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2564 - 4'd1 ; + b__h2572 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2564 ; + b__h2572 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4579,11 +4586,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134383 - 4'd1 ; + b__h134391 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134383 ; + b__h134391 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4646,7 +4653,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134676, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134684, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4664,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148600, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148608, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148515, strb8__h148516, 1'd1 } ; + { data64__h148523, strb8__h148524, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4682,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135378 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135386 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4730,8 +4737,8 @@ module mkProc(CLK, // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102446 : - line_addr__h102532 ; + line_addr__h102454 : + line_addr__h102540 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4892,7 +4899,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34969 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4908,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32039 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5118,7 +5125,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7925, + x__h7933, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -5218,6 +5225,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -5321,7 +5329,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132631, llc$dma_respLd_first[3] } ; + { ld_data__h132639, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5475,7 +5483,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135378, + { new_cline__h135386, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5559,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94382, 3'd1 } ; + { 4'd0, dword__h94390, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5854,47 +5862,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37420), + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h32150)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37272), + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h35060)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42745), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40946)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42753), + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h40954)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h43012)); + .amoExec_in_data(mmioPlatform_reqData__h48693), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h43020)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40417 } } ; + x1_avValue_data__h40425 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5910,7 +5918,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; + newData__h32039 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5975,7 +5983,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - x__h75229 } ; + x__h75237 } ; assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5987,29 +5995,29 @@ module mkProc(CLK, assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90073 : + new_dword__h90081 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? @@ -6154,11 +6162,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h43001 == 64'd0 : - x__h40935 == 64'd0, + x__h43009 == 64'd0 : + x__h40943 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h45022 } ; + x1_avValue_data__h45030 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6392,58 +6400,58 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = - { CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, + { CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = - { CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + { CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - x__h82716 } ; + x__h82724 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = - { CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + { CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = - { CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, - x__h61807, - x__h61814 } ; - assign b__h134383 = + { CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20, + x__h61815, + x__h61822 } ; + assign b__h134391 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2564 = + assign b__h2572 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31958 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h163161 = + { v__h31751, 32'd0 } ; + assign failed_testnum__h163169 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102446 = + assign line_addr__h102454 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102532 = + assign line_addr__h102540 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = - line_addr__h102532 == llc_mem_server_rg_cacheline_cache_addr ; + line_addr__h102540 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = - line_addr__h102446 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90069 = + line_addr__h102454 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90077 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6476,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134676 = - { llc$to_mem_toM_first[68:11], x__h134711 } ; - assign mem_req_wr_addr_awaddr__h148600 = - { llc$to_mem_toM_first[639:582], x__h148625 } ; + assign mem_req_rd_addr_araddr__h134684 = + { llc$to_mem_toM_first[68:11], x__h134719 } ; + assign mem_req_wr_addr_awaddr__h148608 = + { llc$to_mem_toM_first[639:582], x__h148633 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42745 = + assign mmioPlatform_fromHostQ_data_0__h42753 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,18 +6494,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37272 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + mmioPlatform_mtimecmp_0 <= newData__h34969 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48685 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30166 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30126 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48693 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6529,105 +6537,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61675 = + assign n__read_addr__h61683 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61760 = + assign n__read_addr__h61768 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80478 = + assign n__read_addr__h80486 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : 64'd0 ; - assign n__read_addr__h80557 = + assign n__read_addr__h80565 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : 64'd0 ; - assign n__read_child__h61680 = + assign n__read_child__h61688 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61765 = + assign n__read_child__h61773 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80481 = + assign n__read_child__h80489 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; - assign n__read_child__h80560 = + assign n__read_child__h80568 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; - assign n__read_id__h61679 = + assign n__read_id__h61687 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61764 = + assign n__read_id__h61772 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123973 = + assign n__read_snd_addr__h123981 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123974 = + assign n__read_snd_id__h123982 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32039 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : + x__h32150 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + assign newData__h34969 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : + x__h35060 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h135378 = + assign new_cline__h135386 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90073 = x__h91235 | y__h91236 ; - assign op_result__h48701 = + assign new_dword__h90081 = x__h91243 | y__h91244 ; + assign op_result__h48709 = IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; - assign op_result__h49231 = w1__h48098 ^ w2__h48100 ; - assign op_result__h49236 = w1__h48098 & w2__h48100 ; - assign op_result__h49241 = w1__h48098 | w2__h48100 ; - assign op_result__h49246 = - (w1__h48098 < w2__h48100) ? w1__h48098 : w2__h48100 ; - assign op_result__h49252 = - (w1__h48098 <= w2__h48100) ? w2__h48100 : w1__h48098 ; - assign op_result__h49259 = + assign op_result__h49239 = w1__h48106 ^ w2__h48108 ; + assign op_result__h49244 = w1__h48106 & w2__h48108 ; + assign op_result__h49249 = w1__h48106 | w2__h48108 ; + assign op_result__h49254 = + (w1__h48106 < w2__h48108) ? w1__h48106 : w2__h48108 ; + assign op_result__h49260 = + (w1__h48106 <= w2__h48108) ? w2__h48108 : w1__h48106 ; + assign op_result__h49267 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w1__h48098 : - w2__h48100 ; - assign op_result__h49265 = + w1__h48106 : + w2__h48108 ; + assign op_result__h49273 = ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w2__h48100 : - w1__h48098 ; + w2__h48108 : + w1__h48106 ; assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6638,126 +6646,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48144 = + assign result__h48152 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; - assign result__h48268 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48296 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48324 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48352 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48380 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48408 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48436 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48464 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48509 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48537 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48565 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48593 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48634 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48662 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48788 = + assign result__h48276 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48304 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48332 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48360 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48388 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48416 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48444 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48472 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48517 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48545 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48573 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48601 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48642 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48670 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48796 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48815 = + assign result__h48823 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48842 = + assign result__h48850 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48869 = + assign result__h48877 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48896 = + assign result__h48904 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48923 = + assign result__h48931 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48950 = + assign result__h48958 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48977 = + assign result__h48985 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h49021 = + assign result__h49029 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h49048 = + assign result__h49056 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h49075 = + assign result__h49083 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49102 = + assign result__h49110 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49142 = + assign result__h49150 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49169 = + assign result__h49177 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49286 = + assign result__h49294 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49352 = + assign result__h49360 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49418 = + assign result__h49426 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49484 = + assign result__h49492 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49550 = + assign result__h49558 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49616 = + assign result__h49624 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49682 = + assign result__h49690 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49744 = + assign result__h49752 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; - assign result__h49789 = + assign result__h49797 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49855 = + assign result__h49863 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49921 = + assign result__h49929 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49979 = + assign result__h49987 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; - assign result__h50024 = + assign result__h50032 = { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18093_BITS_31_TO_0__q15 = w1__h48093[31:0] ; - assign w1___1__h48203 = { 32'd0, w1__h48093[31:0] } ; - assign w28094_BITS_31_TO_0__q16 = w2__h48094[31:0] ; - assign w2___1__h48204 = { 32'd0, w2__h48094[31:0] } ; - assign x1_avValue_data__h40417 = + assign v__h31751 = mmioPlatform_waitUpperMSIPCRs ? v__h31788 : 32'd0 ; + assign v__h31788 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18101_BITS_31_TO_0__q15 = w1__h48101[31:0] ; + assign w1___1__h48211 = { 32'd0, w1__h48101[31:0] } ; + assign w28102_BITS_31_TO_0__q16 = w2__h48102[31:0] ; + assign w2___1__h48212 = { 32'd0, w2__h48102[31:0] } ; + assign x1_avValue_data__h40425 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h45022 = + assign x1_avValue_data__h45030 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134711 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148625 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40935 = + assign x__h134719 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148633 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37420 = mmioPlatform_mtimecmp_0 ; + assign x__h40943 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40946 : + x__h40954 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; - assign x__h43001 = + assign x__h43009 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h43012 : + x__h43020 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6774,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50201 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61493 = + assign x__h50209 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61501 = SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; - assign x__h75229 = + assign x__h75237 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; - assign x__h7925 = + assign x__h7933 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80300 = + assign x__h80308 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; - assign x__h91235 = old_dword__h90072 & y__h91237 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91236 = + assign x__h91243 = old_dword__h90080 & y__h91245 ; + assign x_data__h30541 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91244 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90069 ; - assign y__h91237 = + mask__h90077 ; + assign y__h91245 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,141 +7009,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94390 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148515 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148515 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148515 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148515 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148515 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148515 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148515 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148515 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h148523 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148523 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148523 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148523 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148523 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148523 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148523 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148523 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132631 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132631 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132631 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132631 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132631 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132631 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132631 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132631 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132639 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132639 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132639 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132639 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132639 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132639 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132639 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132639 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148516 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148516 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148516 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148516 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148516 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148516 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148516 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148516 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148524 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148524 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148524 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148524 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148524 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148524 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148524 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148524 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90080 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48268 or - result__h48296 or - result__h48324 or - result__h48352 or - result__h48380 or - result__h48408 or result__h48436 or result__h48464) + result__h48276 or + result__h48304 or + result__h48332 or + result__h48360 or + result__h48388 or + result__h48416 or result__h48444 or result__h48472) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48268; + result__h48276; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48296; + result__h48304; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48324; + result__h48332; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48352; + result__h48360; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48380; + result__h48388; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48408; + result__h48416; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48436; + result__h48444; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48464; + result__h48472; endcase end always@(mmioPlatform_curReq or - result__h48509 or - result__h48537 or result__h48565 or result__h48593) + result__h48517 or + result__h48545 or result__h48573 or result__h48601) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48509; + result__h48517; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48537; + result__h48545; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48565; + result__h48573; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48593; + result__h48601; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48634 or result__h48662) + always@(mmioPlatform_curReq or result__h48642 or result__h48670) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48634; + result__h48642; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48662; + result__h48670; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase @@ -7148,103 +7156,103 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h48094 = + w2__h48102 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48094 = + w2__h48102 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - w2__h48094 = + w2__h48102 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h48094 = + w2__h48102 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w2___1__h48204 or + w2___1__h48212 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48100 = + w2__h48108 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48100 = + w2__h48108 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; - 2'b10: w2__h48100 = w2___1__h48204; + 2'b10: w2__h48108 = w2___1__h48212; 2'b11: - w2__h48100 = + w2__h48108 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_curReq or - result__h48788 or - result__h48815 or - result__h48842 or - result__h48869 or - result__h48896 or - result__h48923 or result__h48950 or result__h48977) + result__h48796 or + result__h48823 or + result__h48850 or + result__h48877 or + result__h48904 or + result__h48931 or result__h48958 or result__h48985) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48788; + result__h48796; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48815; + result__h48823; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48842; + result__h48850; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48869; + result__h48877; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48896; + result__h48904; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48923; + result__h48931; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48950; + result__h48958; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48977; + result__h48985; endcase end always@(mmioPlatform_curReq or - result__h49021 or - result__h49048 or result__h49075 or result__h49102) + result__h49029 or + result__h49056 or result__h49083 or result__h49110) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49021; + result__h49029; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49048; + result__h49056; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49075; + result__h49083; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49102; + result__h49110; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h49142 or result__h49169) + always@(mmioPlatform_curReq or result__h49150 or result__h49177) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49142; + result__h49150; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49169; + result__h49177; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase @@ -7257,42 +7265,42 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h48093 = + w1__h48101 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48093 = + w1__h48101 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - w1__h48093 = + w1__h48101 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h48093 = + w1__h48101 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w1___1__h48203 or + w1___1__h48211 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48098 = + w1__h48106 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48098 = + w1__h48106 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; - 2'b10: w1__h48098 = w1___1__h48203; + 2'b10: w1__h48106 = w1___1__h48211; 2'b11: - w1__h48098 = + w1__h48106 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w18093_BITS_31_TO_0__q15 or + w18101_BITS_31_TO_0__q15 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) @@ -7304,8 +7312,8 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - { {32{w18093_BITS_31_TO_0__q15[31]}}, - w18093_BITS_31_TO_0__q15 }; + { {32{w18101_BITS_31_TO_0__q15[31]}}, + w18101_BITS_31_TO_0__q15 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; @@ -7314,7 +7322,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w28094_BITS_31_TO_0__q16 or + w28102_BITS_31_TO_0__q16 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) @@ -7326,116 +7334,116 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - { {32{w28094_BITS_31_TO_0__q16[31]}}, - w28094_BITS_31_TO_0__q16 }; + { {32{w28102_BITS_31_TO_0__q16[31]}}, + w28102_BITS_31_TO_0__q16 }; 2'b11: IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49265 or - w2__h48100 or - op_result__h48701 or - op_result__h49231 or - op_result__h49236 or - op_result__h49241 or - op_result__h49259 or op_result__h49246 or op_result__h49252) + op_result__h49273 or + w2__h48108 or + op_result__h48709 or + op_result__h49239 or + op_result__h49244 or + op_result__h49249 or + op_result__h49267 or op_result__h49254 or op_result__h49260) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - w2__h48100; + w2__h48108; 4'd1: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h48701; + op_result__h48709; 4'd2: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49231; + op_result__h49239; 4'd3: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49236; + op_result__h49244; 4'd4: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49241; + op_result__h49249; 4'd5: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49259; + op_result__h49267; 4'd7: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49246; + op_result__h49254; 4'd8: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49252; + op_result__h49260; default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49265; + op_result__h49273; endcase end always@(mmioPlatform_curReq or - result__h49744 or - result__h49789 or result__h49855 or result__h49921) + result__h49752 or + result__h49797 or result__h49863 or result__h49929) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49744; + result__h49752; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49789; + result__h49797; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49855; + result__h49863; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49921; + result__h49929; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48144 or - result__h49286 or - result__h49352 or - result__h49418 or - result__h49484 or - result__h49550 or result__h49616 or result__h49682) + result__h48152 or + result__h49294 or + result__h49360 or + result__h49426 or + result__h49492 or + result__h49558 or result__h49624 or result__h49690) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h48144; + result__h48152; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49286; + result__h49294; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49352; + result__h49360; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49418; + result__h49426; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49484; + result__h49492; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49550; + result__h49558; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49616; + result__h49624; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49682; + result__h49690; endcase end - always@(mmioPlatform_curReq or result__h49979 or result__h50024) + always@(mmioPlatform_curReq or result__h49987 or result__h50032) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49979; + result__h49987; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h50024; + result__h50032; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase @@ -7448,15 +7456,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h48089 = + x__h48097 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; 2'b01: - x__h48089 = + x__h48097 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; 2'b10: - x__h48089 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h48097 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h48089 = + x__h48097 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end @@ -7540,278 +7548,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; endcase end - always@(x__h61493 or n__read_id__h61679 or n__read_id__h61764) + always@(x__h61501 or n__read_id__h61687 or n__read_id__h61772) begin - case (x__h61493) - 1'd0: x__h61807 = n__read_id__h61679; - 1'd1: x__h61807 = n__read_id__h61764; + case (x__h61501) + 1'd0: x__h61815 = n__read_id__h61687; + 1'd1: x__h61815 = n__read_id__h61772; endcase end - always@(x__h61493 or n__read_child__h61680 or n__read_child__h61765) + always@(x__h61501 or n__read_child__h61688 or n__read_child__h61773) begin - case (x__h61493) - 1'd0: x__h61814 = n__read_child__h61680; - 1'd1: x__h61814 = n__read_child__h61765; + case (x__h61501) + 1'd0: x__h61822 = n__read_child__h61688; + 1'd1: x__h61822 = n__read_child__h61773; endcase end - always@(x__h61493 or + always@(x__h61501 or propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = + CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20 = propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; 1'd1: - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = + CASE_x1501_0_propDstData_0_dummy2_1_read__100__ETC__q20 = propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; endcase end - always@(x__h61493 or + always@(x__h61501 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; 1'd1: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; endcase end - always@(x__h61493 or + always@(x__h61501 or IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; 1'd1: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + CASE_x1501_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; endcase end - always@(x__h61493 or n__read_addr__h61675 or n__read_addr__h61760) + always@(x__h61501 or n__read_addr__h61683 or n__read_addr__h61768) begin - case (x__h61493) + case (x__h61501) 1'd0: - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = - n__read_addr__h61675; + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23 = + n__read_addr__h61683; 1'd1: - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = - n__read_addr__h61760; + CASE_x1501_0_n__read_addr1683_1_n__read_addr17_ETC__q23 = + n__read_addr__h61768; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80300 or n__read_child__h80481 or n__read_child__h80560) + always@(x__h80308 or n__read_child__h80489 or n__read_child__h80568) begin - case (x__h80300) - 1'd0: x__h82716 = n__read_child__h80481; - 1'd1: x__h82716 = n__read_child__h80560; + case (x__h80308) + 1'd0: x__h82724 = n__read_child__h80489; + 1'd1: x__h82724 = n__read_child__h80568; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80300 or + always@(x__h80308 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0308_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80300 or + always@(x__h80308 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : 2'd0; 1'd1: - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0308_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : 2'd0; endcase end - always@(x__h80300 or + always@(x__h80308 or NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; 1'd1: - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x0308_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; endcase end - always@(x__h80300 or n__read_addr__h80478 or n__read_addr__h80557) + always@(x__h80308 or n__read_addr__h80486 or n__read_addr__h80565) begin - case (x__h80300) + case (x__h80308) 1'd0: - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = - n__read_addr__h80478; + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34 = + n__read_addr__h80486; 1'd1: - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = - n__read_addr__h80557; + CASE_x0308_0_n__read_addr0486_1_n__read_addr05_ETC__q34 = + n__read_addr__h80565; endcase end @@ -8227,14 +8235,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163582 = $stime; + v__h163594 = $stime; #0; end - v__h163576 = v__h163582 / 32'd10; + v__h163588 = v__h163594 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163576, + v__h163588, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8245,7 +8253,7 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61493 && + x__h61501 && (!propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8256,7 +8264,7 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80300 && + x__h80308 && (!propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8266,14 +8274,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163118 = $stime; + v__h163126 = $stime; #0; end - v__h163112 = v__h163118 / 32'd10; + v__h163120 = v__h163126 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163112, + v__h163120, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8283,7 +8291,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163161); + $display("FAIL %0d", failed_testnum__h163169); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8291,14 +8299,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5520 = $stime; + v__h5528 = $stime; #0; end - v__h5514 = v__h5520 / 32'd10; + v__h5522 = v__h5528 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5514); + $display("%0d: %m.rl_handle_read_rsps ", v__h5522); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8358,16 +8366,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5693 = $stime; + v__h5701 = $stime; #0; end - v__h5687 = v__h5693 / 32'd10; + v__h5695 = v__h5701 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5687); + v__h5695); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8471,14 +8479,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5953 = $stime; + v__h5961 = $stime; #0; end - v__h5947 = v__h5953 / 32'd10; + v__h5955 = v__h5961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5947); + $display("%d: %m.rl_handle_write_req: St request:", v__h5955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8648,15 +8656,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h8095 = $stime; + v__h8103 = $stime; #0; end - v__h8089 = v__h8095 / 32'd10; + v__h8097 = v__h8103 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h8089); + $display("%0d: ERROR: CreditCounter: overflow", v__h8097); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8706,7 +8714,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7925); + $write("'h%h", x__h7933); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8837,16 +8845,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8310 = $stime; + v__h8318 = $stime; #0; end - v__h8304 = v__h8310 / 32'd10; + v__h8312 = v__h8318 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8304); + v__h8312); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9052,14 +9060,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2670 = $stime; + v__h2678 = $stime; #0; end - v__h2664 = v__h2670 / 32'd10; + v__h2672 = v__h2678 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2664); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2672); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9349,16 +9357,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4343 = $stime; + v__h4351 = $stime; #0; end - v__h4337 = v__h4343 / 32'd10; + v__h4345 = v__h4351 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4337); + v__h4345); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9564,14 +9572,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9480 = $stime; + v__h9488 = $stime; #0; end - v__h9474 = v__h9480 / 32'd10; + v__h9482 = v__h9488 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9474); + $display("%0d: %m.rl_discard_write_rsp", v__h9482); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9608,15 +9616,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9973 = $stime; + v__h9981 = $stime; #0; end - v__h9967 = v__h9973 / 32'd10; + v__h9975 = v__h9981 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9967); + v__h9975); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9656,14 +9664,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h10136 = $stime; + v__h10144 = $stime; #0; end - v__h10130 = v__h10136 / 32'd10; + v__h10138 = v__h10144 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h10130); + v__h10138); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9861,13 +9869,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43001 != 64'd0) + x__h43009 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40935 != 64'd0) + x__h40943 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9887,15 +9895,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h135075 = $stime; + v__h135083 = $stime; #0; end - v__h135069 = v__h135075 / 32'd10; + v__h135077 = v__h135083 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135069, + v__h135077, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9955,15 +9963,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135242 = $stime; + v__h135250 = $stime; #0; end - v__h135236 = v__h135242 / 32'd10; + v__h135244 = v__h135250 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135236); + v__h135244); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10144,16 +10152,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137345 = $stime; + v__h137353 = $stime; #0; end - v__h137339 = v__h137345 / 32'd10; + v__h137347 = v__h137353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137339); + v__h137347); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11351,14 +11359,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154689 = $stime; + v__h154697 = $stime; #0; end - v__h154683 = v__h154689 / 32'd10; + v__h154691 = v__h154697 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154683); + $display("%0d: ERROR: CreditCounter: overflow", v__h154691); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11382,7 +11390,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_wr_addr_awaddr__h148600); + $write("'h%h", mem_req_wr_addr_awaddr__h148608); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11470,7 +11478,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", data64__h148515); + $write("'h%h", data64__h148523); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11478,7 +11486,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", strb8__h148516); + $write("'h%h", strb8__h148524); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11504,16 +11512,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134456 = $stime; + v__h134464 = $stime; #0; end - v__h134450 = v__h134456 / 32'd10; + v__h134458 = v__h134464 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134450, + v__h134458, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11601,7 +11609,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_rd_addr_araddr__h134676); + $write("'h%h", mem_req_rd_addr_araddr__h134684); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) @@ -11682,15 +11690,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h161383 = $stime; + v__h161391 = $stime; #0; end - v__h161377 = v__h161383 / 32'd10; + v__h161385 = v__h161391 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161377, + v__h161385, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -11728,15 +11736,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161891 = $stime; + v__h161899 = $stime; #0; end - v__h161885 = v__h161891 / 32'd10; + v__h161893 = v__h161899 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161885); + v__h161893); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/src_BSV/ClockHacks.bsv b/src_SSITH_P3/src_BSV/ClockHacks.bsv new file mode 100644 index 0000000..dde2445 --- /dev/null +++ b/src_SSITH_P3/src_BSV/ClockHacks.bsv @@ -0,0 +1,117 @@ + +package ClockHacks; + +import Clocks ::*; +import Connectable ::*; + +(* always_ready, always_enabled *) +interface OutputBit; + method Bit#(1) out; +endinterface + +import "BVI" ASSIGN1 = +module packClock#(Clock clk)(OutputBit); + + default_clock no_clock; + default_reset no_reset; + + input_clock clk(IN) = clk; + + method OUT out; + + schedule (out) CF (out); + +endmodule + +import "BVI" ASSIGN1 = +module packReset#(Reset rst)(OutputBit); + + default_clock no_clock; + default_reset no_reset; + + input_reset rst(IN) = rst; + + method OUT out reset_by(rst); + + schedule (out) CF (out); + +endmodule + +(* always_ready, always_enabled *) +interface UnpackedClock; + interface Clock clk; + method Action in(Bit#(1) x); +endinterface + +import "BVI" ASSIGN1 = +module unpackClock(UnpackedClock); + + default_clock no_clock; + default_reset no_reset; + + output_clock clk(OUT); + + method in(IN) enable((*inhigh*)en) clocked_by(clk); + + schedule (in) CF (in); + +endmodule + +(* always_ready, always_enabled *) +interface UnpackedReset; + interface Reset rst; + method Action in(Bit#(1) x); +endinterface + +import "BVI" ASSIGN1 = +module unpackReset#(Clock clk)(UnpackedReset); + + default_clock no_clock; + default_reset no_reset; + + input_clock clk() = clk; + output_reset rst(OUT); + + method in(IN) enable((*inhigh*)en) clocked_by(clk) reset_by(rst); + + schedule (in) CF (in); + +endmodule + +//////////////////// + +interface BlockIfc; + interface Clock clk; + interface Reset rst; +endinterface + +module mkBlock(BlockIfc); + let default_clock <- exposeCurrentClock; + let default_reset <- exposeCurrentReset; + + interface clk = default_clock; + interface rst = default_reset; +endmodule + +module mkTop(Empty); + + let clk_unpack <- unpackClock; + let clk = clk_unpack.clk; + + let rst_unpack <- unpackReset(clk); + let rst = rst_unpack.rst; + + let a <- mkBlock(clocked_by clk, reset_by rst); + let b <- mkBlock(clocked_by clk, reset_by rst); + + let clk_pack <- packClock(b.clk, clocked_by clk); + let rst_pack <- packReset(b.rst, clocked_by clk); + + mkConnection(clk_unpack.in, clk_pack.out); + mkConnection(rst_unpack.in, rst_pack.out); + +endmodule + +//////////////////// + +endpackage : ClockHacks diff --git a/src_SSITH_P3/src_BSV/JtagTap.bsv b/src_SSITH_P3/src_BSV/JtagTap.bsv index fe68d51..1efe670 100644 --- a/src_SSITH_P3/src_BSV/JtagTap.bsv +++ b/src_SSITH_P3/src_BSV/JtagTap.bsv @@ -3,11 +3,14 @@ package JtagTap; import BUtils ::*; import Clocks ::*; +import Connectable ::*; import DefaultValue ::*; import FIFOF ::*; import FIFOLevel ::*; import Reserved ::*; +import PowerOnReset ::*; +import ClockHacks ::*; import Giraffe_IFC ::*; typedef 6 ABITS; @@ -16,6 +19,10 @@ typedef 6 ABITS; typedef 6 IR_LENGTH; `elsif XILINX_XCVU9P typedef 18 IR_LENGTH; +`elsif XILINX_XC7K325T +typedef 6 IR_LENGTH; +`else +typedef 5 IR_LENGTH; `endif `else typedef 5 IR_LENGTH; @@ -34,6 +41,12 @@ Bit#(IR_LENGTH) ir_dtmcs = 'b100010100100100100; // USER3 // 'b000010100100100100; USER1 Bit#(IR_LENGTH) ir_dmi = 'b000011100100100100; +`elsif XILINX_XC7K325T +Bit#(IR_LENGTH) ir_dtmcs = 'h22; +Bit#(IR_LENGTH) ir_dmi = 'h03; +`else +Bit#(IR_LENGTH) ir_dtmcs = 'h10; +Bit#(IR_LENGTH) ir_dmi = 'h11; `endif `else Bit#(IR_LENGTH) ir_dtmcs = 'h10; @@ -176,15 +189,12 @@ module mkJtagTap(JtagTap_IFC); Wire#(Bit#(1)) w_tck <- mkDWire(?); - let tck_clock <- mkUngatedClock(?); - let tck = tck_clock.new_clk; + let tck_clock <- unpackClock; + let tck = tck_clock.clk; + let w_tck_crossed <- mkNullCrossing(tck, w_tck); + mkConnection(w_tck_crossed, tck_clock.in); - (* no_implicit_conditions, fire_when_enabled *) - rule rl_tck; - tck_clock.setClockValue(w_tck); - endrule - - let rst_tck <- mkAsyncResetFromCR(4, tck); + let rst_tck <- mkAsyncResetFromCR(0, tck); // value independent of tck Wire#(Bit#(1)) w_tms <- mkDWire(?, clocked_by tck, reset_by rst_tck); Wire#(Bit#(1)) w_tdi <- mkDWire(?, clocked_by tck, reset_by rst_tck); @@ -201,13 +211,16 @@ module mkJtagTap(JtagTap_IFC); Array#(Reg#(Bit#(1))) r_tdo <- mkCRegU(2, clocked_by tck, reset_by rst_tck); - Reg#(JtagState) r_state <- mkReg(TEST_LOGIC_RESET, clocked_by tck, reset_by rst_tck); + Reg#(JtagState) r_state <- mkRegUNInit(TEST_LOGIC_RESET, clocked_by tck, reset_by rst_tck); + Reg#(Bool) r_initialize <- mkRegUNInit(True, clocked_by tck, reset_by rst_tck); + Reg#(Bool) r_initialize2 <- mkRegUNInit(True); + PulseWire w_initialize <- mkPulseWire( clocked_by tck, reset_by rst_tck); Reg#(Bit#(IR_LENGTH)) r_ir <- mkRegU(clocked_by tck, reset_by rst_tck); Reg#(Bit#(DR_LENGTH)) r_dr <- mkRegU(clocked_by tck, reset_by rst_tck); Reg#(Bit#(DR_LENGTH)) r_drmask <- mkRegU(clocked_by tck, reset_by rst_tck); - Reg#(DMI) r_dmi <- mkReg(defaultValue, clocked_by tck, reset_by rst_tck); + Reg#(DMI) r_dmi <- mkRegUNInit(defaultValue, clocked_by tck, reset_by rst_tck); Wire#(Tuple3#(Bit#(7),Bit#(32),Bit#(2))) w_dmi_req <- mkWire(clocked_by tck, reset_by rst_tck); SyncFIFOLevelIfc#(Tuple3#(Bit#(7),Bit#(32),Bit#(2)), 2) f_dmi_req <- mkSyncFIFOLevel(tck, rst_tck, clk); @@ -216,6 +229,19 @@ module mkJtagTap(JtagTap_IFC); Array#(Reg#(Bool)) r_dmistat_busy <- mkCReg(2, False, clocked_by tck, reset_by rst_tck); SyncFIFOLevelIfc#(DMI, 2) f_dmi_rsp <- mkSyncFIFOLevel(clk, rst, tck); + rule rl_initialize2(r_initialize2); + r_initialize2 <= False; + + f_dmi_req.dClear; + f_dmi_rsp.sClear; + endrule + + (* no_implicit_conditions, fire_when_enabled *) + rule rl_initialize(w_initialize); + f_dmi_busy.clear; + r_dmistat_busy[1] <= False; + endrule + (* no_implicit_conditions, fire_when_enabled *) rule tick; let newir = r_ir; @@ -224,6 +250,10 @@ module mkJtagTap(JtagTap_IFC); if (r_state == TEST_LOGIC_RESET) begin newir = ir_idcode; + if (r_initialize) begin + r_initialize <= False; + w_initialize.send(); + end end else if (r_state == CAPTURE_DR) begin if (newir == ir_bypass0 || diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 3f05153..da97bd6 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -36,7 +36,8 @@ import Cur_Cycle :: *; // ================================================================ // Project imports -import SoC_Map :: *; +import SoC_Map :: *; +import PowerOnReset :: *; // The basic core import CoreW_IFC :: *; @@ -121,8 +122,11 @@ module mkP3_Core (P3_Core_IFC); // its reset down from here. // (power-on reset) and the Debug Module's 'hart_reset' control. + let default_reset <- exposeCurrentReset(); - let power_on_reset <- exposeCurrentReset; + let por_ifc <- mkPowerOnReset(); + let power_on_reset = por_ifc.gen_rst; // This line and the next + //let power_on_reset <- default_reset; //are alternatives. let dm_power_on_reset = power_on_reset; // The rest of the system (corew minus the Debug Module) are reset: @@ -131,13 +135,24 @@ module mkP3_Core (P3_Core_IFC); `ifdef INCLUDE_GDB_CONTROL let clk <- exposeCurrentClock; - Bool initial_reset_val = False; + // Setting initial_reset_val to True ensures that if the mkReset is itself in + // reset (controlled by mkP3_Core's default reset), its output reset will be + // asserted. Thus ndm_reset will be asserted if any of + // power_on_reset, default_reset, ndm_reset from debug module + // is asserted. + + // Currently initial_reset_val=False -- thus ndm_reset will be asserted only + // if any of + // power_on_reset, ndm_reset from debug module + // is asserted. + Bool initial_reset_val = False; // was True; Integer ndm_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for NDM let ndm_reset_controller <- mkReset(ndm_reset_duration, initial_reset_val, clk); let ndm_reset <- mkResetEither (power_on_reset, ndm_reset_controller.new_rst); `else - let ndm_reset = power_on_reset; + let rstn <- exposeCurrentReset; + let ndm_reset <- mkResetEither (power_on_reset, rstn); `endif // ================================================================ @@ -165,11 +180,13 @@ module mkP3_Core (P3_Core_IFC); // NDM reset (reset for non-DebugModule) Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0); + Reg #(Bool) rg_running <- mkRegU; // Get an NDM-reset request from the Debug Module, assert ndm-reset, // and then wait for a suitable delay. rule rl_ndm_reset (rg_ndm_reset_delay == 0); let x <- corew.ndm_reset_client.request.get; + rg_running <= x; ndm_reset_controller.assertReset; rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 100); // NOTE: heuristic @@ -180,9 +197,9 @@ module mkP3_Core (P3_Core_IFC); // Wait for suitable delay, then send ack response to Debug Module for NDM-reset request rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0); if (rg_ndm_reset_delay == 1) begin - Bool is_running = True; + Bool is_running = rg_running; // Restart the corew - corew.start (0, 0); + corew.start (rg_running, 0, 0); corew.ndm_reset_client.response.put (is_running); $display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", cur_cycle); @@ -191,11 +208,13 @@ module mkP3_Core (P3_Core_IFC); endrule // ================================================================ - // Start the corew after a PoR - Reg #(Bool) rg_corew_start_after_por <- mkReg(False); - rule rl_step_0 (!rg_corew_start_after_por); - corew.start (0, 0); - rg_corew_start_after_por <= True; + // Start the corew a suitable time after a PoR + UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew + Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait); + rule rl_step_0 (rg_corew_start_after_por != 0); + let n = rg_corew_start_after_por - 1; + rg_corew_start_after_por <= n; + if (n==0) corew.start (True, 0, 0); // initial start leaves proc running endrule // ================================================================ @@ -217,7 +236,7 @@ module mkP3_Core (P3_Core_IFC); BusSender#(Tuple2#(Bit#(32),Bit#(2))) bus_dmi_rsp <- mkBusSender(unpack(0)); `ifdef JTAG_TAP - let jtagtap <- mkJtagTap; + let jtagtap <- mkJtagTap(reset_by power_on_reset); mkConnection(jtagtap.dmi.req_ready, pack(bus_dmi_req.in.ready)); mkConnection(jtagtap.dmi.req_valid, compose(bus_dmi_req.in.valid, unpack)); diff --git a/src_SSITH_P3/src_BSV/PowerOnReset.bsv b/src_SSITH_P3/src_BSV/PowerOnReset.bsv new file mode 100644 index 0000000..30bafe2 --- /dev/null +++ b/src_SSITH_P3/src_BSV/PowerOnReset.bsv @@ -0,0 +1,51 @@ +package PowerOnReset; + +import Clocks::*; + +UInt#(8) resetCycles = 10; + +import "BVI" RegUNInit = +module mkRegUNInit#(parameter a init) (Reg#(a)) + provisos (Bits#(a,sa)); + + parameter width = valueOf(sa); + parameter init = pack(init); + + default_clock clk(CLK, (*unused*)CLK_GATE); + no_reset; + + method Q_OUT _read(); + method _write(D_IN) enable(EN); + + schedule _read CF _read; + schedule _write SBR _write; + schedule _read SB _write; +endmodule + + + +import "BVI" ASSIGN1 = +module mkBoolToReset#(Bool xin) (ResetGenIfc); + default_clock (); + no_reset; + + port IN = xin; + output_reset gen_rst(OUT); +endmodule + +(*synthesize*) +module mkPowerOnReset (ResetGenIfc); + Reg#(UInt#(8)) ctr <- mkRegUNInit(resetCycles); + Reg#(Bool) isInPowerOnReset <- mkRegUNInit(True); + + rule countDown(isInPowerOnReset); + let n = ctr - 1; + ctr <= n; + if (n==0) isInPowerOnReset <= False; + endrule + + let rst_ifc <- mkBoolToReset(!isInPowerOnReset); + return rst_ifc; +endmodule + +endpackage diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index 63770e1..6760f41 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -165,14 +165,6 @@ master0_awready - - - WID - - - master0_wid - - WDATA @@ -495,14 +487,6 @@ master1_awready - - - WID - - - master1_wid - - WDATA @@ -801,7 +785,7 @@ viewChecksum - 63c940c2 + c8a99f02 @@ -826,7 +810,7 @@ viewChecksum - 63c940c2 + 02500583 @@ -1080,23 +1064,6 @@ - - master0_wid - - out - - 3 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - master0_wdata @@ -1737,23 +1704,6 @@ - - master1_wid - - out - - 3 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - master1_wdata @@ -2405,6 +2355,21 @@ USED_IN_implementation USED_IN_synthesis + + hdl/ASSIGN1.v + verilogSource + IMPORTED_FILE + + + hdl/RegUNInit.v + verilogSource + IMPORTED_FILE + + + hdl/mkPowerOnReset.v + verilogSource + IMPORTED_FILE + hdl/BRAM2.v verilogSource @@ -2470,6 +2435,16 @@ verilogSource IMPORTED_FILE + + hdl/SyncReset0.v + verilogSource + IMPORTED_FILE + + + hdl/SyncWire.v + verilogSource + IMPORTED_FILE + hdl/mkAluDispToRegFifo.v verilogSource @@ -2785,6 +2760,11 @@ verilogSource IMPORTED_FILE + + hdl/mkTrace_Data2_to_Trace_Data.v + verilogSource + IMPORTED_FILE + hdl/mkTV_Xactor.v verilogSource @@ -2932,6 +2912,7 @@ hdl/FIFOL1.v verilogSource + CHECKSUM_bfe3b3df @@ -2966,6 +2947,21 @@ xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/ASSIGN1.v + verilogSource + IMPORTED_FILE + + + hdl/RegUNInit.v + verilogSource + IMPORTED_FILE + + + hdl/mkPowerOnReset.v + verilogSource + IMPORTED_FILE + hdl/BRAM2.v verilogSource @@ -3031,6 +3027,16 @@ verilogSource IMPORTED_FILE + + hdl/SyncReset0.v + verilogSource + IMPORTED_FILE + + + hdl/SyncWire.v + verilogSource + IMPORTED_FILE + hdl/mkAluDispToRegFifo.v verilogSource @@ -3346,6 +3352,11 @@ verilogSource IMPORTED_FILE + + hdl/mkTrace_Data2_to_Trace_Data.v + verilogSource + IMPORTED_FILE + hdl/mkTV_Xactor.v verilogSource @@ -3551,23 +3562,28 @@ mkP3_Core_v1_0 package_project - 1 + 2 user.org:user:mkP3_Core:1.0 - 2019-04-07T20:09:49Z + 2020-02-20T15:03:34Z /home/charlie/ssith_processor /home/charlie/ssith_processor /home/charlie/ssith_processor + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip + /home/stoy/gfe/bluespec-processors/P3/Toooba/src_SSITH_P3/xilinx_ip - 2017.4 - + 2019.1 + - - + + diff --git a/src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v b/src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v new file mode 100644 index 0000000..4bedc0b --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/ASSIGN1.v @@ -0,0 +1,5 @@ +module ASSIGN1(IN, OUT); + output OUT; + input IN; + assign OUT = IN; +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v b/src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v new file mode 100644 index 0000000..1dc1123 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/MakeReset0.v @@ -0,0 +1,87 @@ + +// Copyright (c) 2000-2012 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + + +module MakeReset0 ( + CLK, + RST, + ASSERT_IN, + ASSERT_OUT, + + OUT_RST + ); + + parameter init = 1 ; + + input CLK ; + input RST ; + input ASSERT_IN ; + output ASSERT_OUT ; + + output OUT_RST ; + + reg rst ; + + assign ASSERT_OUT = rst == `BSV_RESET_VALUE ; + + assign OUT_RST = rst ; + + always@(posedge CLK or `BSV_RESET_EDGE RST) begin + if (RST == `BSV_RESET_VALUE) + rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE; + else + begin + if (ASSERT_IN) + rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE; + else // if (rst == 1'b0) + rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE; + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + + +`ifdef BSV_NO_INITIAL_BLOCKS +`else // not BSV_NO_INITIAL_BLOCKS + // synopsys translate_off + initial begin + #0 ; + rst = ~ `BSV_RESET_VALUE ; + end + // synopsys translate_on +`endif // BSV_NO_INITIAL_BLOCKS + +endmodule // MakeReset0 diff --git a/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v b/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v new file mode 100644 index 0000000..9b50bfb --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/RegUNInit.v @@ -0,0 +1,49 @@ + +// Copyright (c) 2000-2019 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +// Basic register with initial value but without reset (not for ASIC synthesis). +module RegUNInit(CLK, Q_OUT, D_IN, EN); + + parameter width = 1; + parameter init = { width {1'b0} } ; + + input CLK; + input EN; + input [width - 1 : 0] D_IN; + output [width - 1 : 0] Q_OUT; + + reg [width - 1 : 0] Q_OUT; + initial Q_OUT = init; + + always@(posedge CLK) + begin + if (EN) + Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; + end +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v b/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v new file mode 100644 index 0000000..e97c94f --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/SyncReset0.v @@ -0,0 +1,50 @@ + +// Copyright (c) 2000-2012 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + + +module SyncReset0 ( + IN_RST, + OUT_RST + ); + + input IN_RST ; + output OUT_RST ; + + assign OUT_RST = IN_RST ; + +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/SyncWire.v b/src_SSITH_P3/xilinx_ip/hdl/SyncWire.v new file mode 100644 index 0000000..61a23bf --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/SyncWire.v @@ -0,0 +1,41 @@ + +// Copyright (c) 2000-2009 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else +`define BSV_ASSIGNMENT_DELAY +`endif + + +module SyncWire( DIN, DOUT ); + + parameter width = 1; + + input [width - 1 : 0] DIN; + output [width - 1 : 0] DOUT; + + assign DOUT = DIN ; + + +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 0452f06..76bc0cb 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -6,7 +6,7 @@ // // Ports: // Name I/O size props -// RDY_coreReq_start O 1 const +// RDY_coreReq_start O 1 // RDY_coreReq_perfReq O 1 reg // coreIndInv_perfResp O 73 // RDY_coreIndInv_perfResp O 1 reg @@ -104,6 +104,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// coreReq_start_running I 1 // coreReq_start_startpc I 64 // coreReq_start_toHostAddr I 64 reg // coreReq_start_fromHostAddr I 64 reg @@ -184,6 +185,7 @@ module mkCore(CLK, RST_N, + coreReq_start_running, coreReq_start_startpc, coreReq_start_toHostAddr, coreReq_start_fromHostAddr, @@ -402,6 +404,7 @@ module mkCore(CLK, input RST_N; // action method coreReq_start + input coreReq_start_running; input [63 : 0] coreReq_start_startpc; input [63 : 0] coreReq_start_toHostAddr; input [63 : 0] coreReq_start_fromHostAddr; @@ -4314,7 +4317,7 @@ module mkCore(CLK, wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, - MUX_l2Tlb$updateVMInfo_1__VAL_1; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, @@ -4464,9 +4467,10 @@ module mkCore(CLK, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, MUX_regRenamingTable$rename_0_getRename_1__SEL_3, - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_1, MUX_renameStage_rg_m_halt_req$write_1__SEL_2, + MUX_renameStage_rg_m_halt_req$write_1__SEL_3, + MUX_renameStage_rg_m_halt_req$write_1__SEL_6, MUX_rf$write_3_wr_1__PSEL_5, MUX_rf$write_3_wr_1__SEL_1, MUX_rf$write_3_wr_1__SEL_2, @@ -4521,24 +4525,24 @@ module mkCore(CLK, reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215, - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219, - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205, CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209, - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207, - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221, CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223, CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225, CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217, - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4550,20 +4554,20 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84, - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85, + reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82, + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86, CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88, CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119, CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47, - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117, CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49, - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121, CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122, CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51, @@ -4572,8 +4576,8 @@ module mkCore(CLK, CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53, CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82, - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85, _theResult___fst_sfd__h346070, _theResult___fst_sfd__h354793, _theResult___fst_sfd__h363375, @@ -4609,7 +4613,7 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248, + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, @@ -4631,8 +4635,8 @@ module mkCore(CLK, CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189, CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193, - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143, CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, @@ -4698,8 +4702,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21, CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, @@ -4743,7 +4747,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, @@ -4767,22 +4771,22 @@ module mkCore(CLK, CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191, + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, @@ -4790,11 +4794,11 @@ module mkCore(CLK, CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, @@ -4872,19 +4876,19 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080; wire [463 : 0] commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942; wire [457 : 0] rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; wire [393 : 0] IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; wire [181 : 0] fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; @@ -5844,7 +5848,7 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106, x__h181701, x__h713427; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, @@ -6320,7 +6324,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911, - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388, + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388, NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667, NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008, NOT_rob_deqPort_1_deq_data__5354_BIT_25_5355_5_ETC___d15385, @@ -6390,7 +6394,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo22, + _dfoo20, _dfoo24, _dfoo26, _dfoo32, @@ -6535,7 +6539,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909, f_csr_rsps_i_notFull__5799_AND_f_csr_reqs_firs_ETC___d15902, - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093, + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191, @@ -6586,7 +6590,7 @@ module mkCore(CLK, next_deqP___1__h332215, r1__read_BIT_20___h655898, r__h614580, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956, regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037, regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444, @@ -6611,7 +6615,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935, rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15738, - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013, + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, @@ -6630,8 +6634,8 @@ module mkCore(CLK, x__h603386; // action method coreReq_start - assign RDY_coreReq_start = 1'd1 ; - assign CAN_FIRE_coreReq_start = 1'd1 ; + assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; + assign CAN_FIRE_coreReq_start = !renameStage_rg_m_halt_req[4] ; assign WILL_FIRE_coreReq_start = EN_coreReq_start ; // action method coreReq_perfReq @@ -6668,7 +6672,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6688,7 +6692,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9946,7 +9950,8 @@ module mkCore(CLK, f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] && rg_core_run_state == 2'd2 && !f_run_halt_reqs$D_OUT ; - assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ; + assign WILL_FIRE_RL_rl_debug_halt_req = + CAN_FIRE_RL_rl_debug_halt_req && !EN_coreReq_start ; // rule RL_rl_debug_halt_req_already_halted assign CAN_FIRE_RL_rl_debug_halt_req_already_halted = @@ -10371,8 +10376,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10408,7 +10413,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 && + regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10443,7 +10448,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 && + NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 && NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15400 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11412,9 +11417,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11422,19 +11428,21 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_csrInstOrInterruptInflight_canon assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ; @@ -11479,7 +11487,8 @@ module mkCore(CLK, CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_rl_debug_halt_req ; + !WILL_FIRE_RL_rl_debug_halt_req && + !EN_coreReq_start ; // rule RL_mmio_pRqQ_canonicalize assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ; @@ -11952,16 +11961,17 @@ module mkCore(CLK, WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; - assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst || - WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 = - MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 && - csrf_rg_dcsr[2] ; - assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_3 = + WILL_FIRE_RL_renameStage_doRenaming_Trap && csrf_rg_dcsr[2] ; + assign MUX_renameStage_rg_m_halt_req$write_1__SEL_6 = + EN_coreReq_start && !coreReq_start_running ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && coreFix_memExe_lsq$firstSt[150] ; @@ -12459,6 +12469,12 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738339 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or next_pc__h723452 or csrf_sepc_csr or csrf_mepc_csr) begin @@ -12474,12 +12490,6 @@ module mkCore(CLK, coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 = { 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ; - assign MUX_l2Tlb$updateVMInfo_1__VAL_1 = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], @@ -14811,7 +14821,7 @@ module mkCore(CLK, assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15103,21 +15113,24 @@ module mkCore(CLK, assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ; // register renameStage_rg_m_halt_req - always@(WILL_FIRE_RL_rl_debug_resume or + always@(MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 or + MUX_renameStage_rg_m_halt_req$write_1__SEL_3 or + WILL_FIRE_RL_rl_debug_resume or WILL_FIRE_RL_rl_debug_halt_req or - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or - MUX_renameStage_rg_m_halt_req$write_1__SEL_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; - WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30; - MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || - MUX_renameStage_rg_m_halt_req$write_1__SEL_2: - renameStage_rg_m_halt_req$D_IN = 5'd31; - default: renameStage_rg_m_halt_req$D_IN = - 5'b01010 /* unspecified value */ ; - endcase - end + MUX_renameStage_rg_m_halt_req$write_1__SEL_6) + case (1'b1) + MUX_renameStage_rg_m_halt_req$write_1__SEL_1 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_2 || + MUX_renameStage_rg_m_halt_req$write_1__SEL_3: + renameStage_rg_m_halt_req$D_IN = 5'd31; + WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10; + WILL_FIRE_RL_rl_debug_halt_req || + MUX_renameStage_rg_m_halt_req$write_1__SEL_6: + renameStage_rg_m_halt_req$D_IN = 5'd30; + default: renameStage_rg_m_halt_req$D_IN = + 5'b01010 /* unspecified value */ ; + endcase assign renameStage_rg_m_halt_req$EN = (WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap) && @@ -15125,6 +15138,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] || + EN_coreReq_start && !coreReq_start_running || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15157,7 +15171,7 @@ module mkCore(CLK, !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data @@ -18150,8 +18164,8 @@ module mkCore(CLK, assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; @@ -18310,8 +18324,8 @@ module mkCore(CLK, MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; assign l2Tlb$updateVMInfo_vmI = MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? - MUX_l2Tlb$updateVMInfo_1__VAL_1 : - MUX_l2Tlb$updateVMInfo_1__VAL_1 ; + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign l2Tlb$EN_updateVMInfo = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_rl_debug_resume ; @@ -20845,8 +20859,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20878,8 +20892,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21439,8 +21453,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21450,8 +21464,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = (_theResult___fst_exp__h519940 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -22132,8 +22146,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || @@ -22158,8 +22172,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? 4'd0 : @@ -24166,10 +24180,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149 = @@ -24183,10 +24197,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 && IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093) ; + rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && @@ -25474,9 +25488,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 ; - assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_RDY_ETC___d15388 = + assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25515,7 +25529,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022 = !specTagManager$canClaim || @@ -25549,21 +25563,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, x__h291618 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16105 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16079 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = @@ -26616,7 +26630,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo22 = + assign _dfoo20 = commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign _dfoo24 = @@ -28089,7 +28103,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 : + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; assign _theResult___fst_exp__h598880 = (_theResult___fst_exp__h598097 == 11'd2047) ? @@ -28220,7 +28234,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 : + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; assign _theResult___fst_sfd__h502289 = (_theResult___fst_exp__h501530 == 11'd2047) ? @@ -28231,7 +28245,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; assign _theResult___fst_sfd__h511940 = (_theResult___fst_exp__h511107 == 11'd2047) ? @@ -28242,7 +28256,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 : + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; assign _theResult___fst_sfd__h520724 = (_theResult___fst_exp__h519940 == 11'd2047) ? @@ -28283,7 +28297,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 : + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; assign _theResult___fst_sfd__h550793 = (_theResult___fst_exp__h549960 == 11'd2047) ? @@ -28294,7 +28308,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 : + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; assign _theResult___fst_sfd__h559577 = (_theResult___fst_exp__h558793 == 11'd2047) ? @@ -30231,12 +30245,14 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609378 = { 56'd0, x__h613036 } ; - assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31048,14 +31064,13 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; assign r__h614580 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31553,13 +31568,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612208 = { r1__read__h614606, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; + assign rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -31582,11 +31596,11 @@ module mkCore(CLK, assign rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 } ; + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; assign rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520 = { rob$deqPort_0_deq_data[181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 } ; + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; assign rs1__h655333 = @@ -33134,6 +33148,23 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33162,23 +33193,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19]) @@ -33555,69 +33569,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h381194 = 8'd0; endcase end - always@(guard__h346097 or - sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0, 2'b01: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - sfdin__h354192[56:34]; - 2'b10: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - out_sfd__h354718; - 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 = - _theResult___sfd__h354715; - endcase - end - always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) - begin - case (guard__h346097) - 2'b0: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - sfdin__h354192[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 = - _theResult___sfd__h354715; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47 or - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354192) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q47; - 3'd1: - _theResult___fst_sfd__h354793 = - CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q48; - 3'd2: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; - 3'd3: - _theResult___fst_sfd__h354793 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; - default: _theResult___fst_sfd__h354793 = 23'd0; - endcase - end always@(guard__h354806 or _theResult___snd__h362805 or out_sfd__h363300 or _theResult___sfd__h363297) begin case (guard__h354806) 2'b0, 2'b01: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___snd__h362805[56:34]; 2'b10: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = out_sfd__h363300; 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = _theResult___sfd__h363297; endcase end @@ -33626,16 +33590,16 @@ module mkCore(CLK, begin case (guard__h354806) 2'b0: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___snd__h362805[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = _theResult___sfd__h363297; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49 or - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or _theResult___snd__h362805) @@ -33643,10 +33607,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q49; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47; 3'd1: _theResult___fst_sfd__h363375 = - CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q50; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48; 3'd2: _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; @@ -33657,6 +33621,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h363375 = 23'd0; endcase end + always@(guard__h346097 or + sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0, 2'b01: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354192[56:34]; + 2'b10: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354718; + 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354715; + endcase + end + always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) + begin + case (guard__h346097) + 2'b0: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354192[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354715; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or + sfdin__h354192) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49; + 3'd1: + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50; + 3'd2: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; + 3'd3: + _theResult___fst_sfd__h354793 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; + 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; + default: _theResult___fst_sfd__h354793 = 23'd0; + endcase + end always@(guard__h363736 or sfdin__h371958 or out_sfd__h372484 or _theResult___sfd__h372481) begin @@ -33797,66 +33811,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354806 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h354806) - 2'b0, 2'b01, 2'b10: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - guard__h354806 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or - guard__h354806) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354806 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || - guard__h354806 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = (guard__h346097 == 2'b0) ? @@ -33873,6 +33849,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h354806 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h354806) + 2'b0, 2'b01, 2'b10: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354806 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354806) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + (guard__h354806 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || + guard__h354806 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34297,69 +34311,19 @@ module mkCore(CLK, default: _theResult___fst_exp__h426891 = 8'd0; endcase end - always@(guard__h391796 or - sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0, 2'b01: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - sfdin__h399889[56:34]; - 2'b10: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - out_sfd__h400415; - 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 = - _theResult___sfd__h400412; - endcase - end - always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) - begin - case (guard__h391796) - 2'b0: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - sfdin__h399889[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 = - _theResult___sfd__h400412; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82 or - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399889) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q82; - 3'd1: - _theResult___fst_sfd__h400490 = - CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q83; - 3'd2: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; - 3'd3: - _theResult___fst_sfd__h400490 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; - default: _theResult___fst_sfd__h400490 = 23'd0; - endcase - end always@(guard__h400503 or _theResult___snd__h408502 or out_sfd__h408997 or _theResult___sfd__h408994) begin case (guard__h400503) 2'b0, 2'b01: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___snd__h408502[56:34]; 2'b10: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = out_sfd__h408997; 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = _theResult___sfd__h408994; endcase end @@ -34368,16 +34332,16 @@ module mkCore(CLK, begin case (guard__h400503) 2'b0: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___snd__h408502[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = _theResult___sfd__h408994; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84 or - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or _theResult___snd__h408502) @@ -34385,10 +34349,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q84; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82; 3'd1: _theResult___fst_sfd__h409072 = - CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q85; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83; 3'd2: _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; @@ -34399,6 +34363,56 @@ module mkCore(CLK, default: _theResult___fst_sfd__h409072 = 23'd0; endcase end + always@(guard__h391796 or + sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0, 2'b01: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399889[56:34]; + 2'b10: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400415; + 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400412; + endcase + end + always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) + begin + case (guard__h391796) + 2'b0: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399889[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400412; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or + sfdin__h399889) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84; + 3'd1: + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85; + 3'd2: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; + 3'd3: + _theResult___fst_sfd__h400490 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; + 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; + default: _theResult___fst_sfd__h400490 = 23'd0; + endcase + end always@(guard__h409433 or sfdin__h417655 or out_sfd__h418181 or _theResult___sfd__h418178) begin @@ -34734,61 +34748,23 @@ module mkCore(CLK, begin case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or - guard__h418269) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418269 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && - guard__h418269 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h418269 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h418269) - 2'b0, 2'b01, 2'b10: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = guard__h418269 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = (guard__h418269 == 2'b0) ? @@ -34805,6 +34781,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end + always@(guard__h418269 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h418269) + 2'b0, 2'b01, 2'b10: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418269) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + (guard__h418269 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && + guard__h418269 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -35821,21 +35835,21 @@ module mkCore(CLK, _theResult___exp__h580342; endcase end - always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581038) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h581038 == 2'b11 && + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571726 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35844,12 +35858,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h581038 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || - guard__h581038 == 2'b11) && + (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || + guard__h571726 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35860,21 +35874,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571726) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h571726 == 2'b11 && + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581038 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35883,12 +35897,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h571726 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || - guard__h571726 == 2'b11) && + (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || + guard__h581038 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36259,57 +36273,15 @@ module mkCore(CLK, _theResult___exp__h589993; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q191 = - guard__h532422 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || - guard__h532422 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h590107 or _theResult___fst_exp__h598097 or _theResult___exp__h598777) begin case (guard__h590107) 2'b0: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___fst_exp__h598097; 2'b01, 2'b10, 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = _theResult___exp__h598777; endcase end @@ -36317,7 +36289,7 @@ module mkCore(CLK, _theResult___fst_exp__h598097 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193) + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36331,7 +36303,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q193; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase @@ -36342,13 +36314,13 @@ module mkCore(CLK, begin case (guard__h590107) 2'b0, 2'b01: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___fst_exp__h598097; 2'b10: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = out_exp__h598780; 2'b11: - CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q194 = + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = _theResult___exp__h598777; endcase end @@ -36356,12 +36328,12 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = guard__h541734 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36372,12 +36344,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36387,6 +36359,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h532422 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || + guard__h532422 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -36478,58 +36492,16 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h532422) - 2'b0, 2'b01, 2'b10: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h532422 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && - guard__h532422 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36540,12 +36512,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || @@ -36555,6 +36527,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h532422) + 2'b0, 2'b01, 2'b10: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = + (guard__h532422 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && + guard__h532422 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -36613,65 +36627,14 @@ module mkCore(CLK, _theResult___sfd__h541039; endcase end - always@(guard__h550803 or - _theResult___snd__h558739 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___snd__h558739[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207 = - _theResult___sfd__h559474; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558739 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558739[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - 52'd0; - endcase - end - always@(guard__h550803 or - _theResult___snd__h558739 or - out_sfd__h559477 or _theResult___sfd__h559474) - begin - case (guard__h550803) - 2'b0, 2'b01: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___snd__h558739[56:5]; - 2'b10: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - out_sfd__h559477; - 2'b11: - CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q208 = - _theResult___sfd__h559474; - endcase - end always@(guard__h541734 or sfdin__h549954 or _theResult___sfd__h550690) begin case (guard__h541734) 2'b0: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = sfdin__h549954[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = _theResult___sfd__h550690; endcase end @@ -36679,7 +36642,7 @@ module mkCore(CLK, sfdin__h549954 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209) + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36693,7 +36656,7 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q209; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase @@ -36703,16 +36666,67 @@ module mkCore(CLK, begin case (guard__h541734) 2'b0, 2'b01: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = sfdin__h549954[56:5]; 2'b10: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = out_sfd__h550693; 2'b11: - CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q210 = + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = _theResult___sfd__h550690; endcase end + always@(guard__h550803 or + _theResult___snd__h558739 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___snd__h558739[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___sfd__h559474; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h558739 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + _theResult___snd__h558739[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = + 52'd0; + endcase + end + always@(guard__h550803 or + _theResult___snd__h558739 or + out_sfd__h559477 or _theResult___sfd__h559474) + begin + case (guard__h550803) + 2'b0, 2'b01: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___snd__h558739[56:5]; + 2'b10: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + out_sfd__h559477; + 2'b11: + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___sfd__h559474; + endcase + end always@(guard__h502881 or _theResult___fst_exp__h511107 or _theResult___exp__h511836) begin @@ -36815,64 +36829,15 @@ module mkCore(CLK, _theResult___exp__h520620; endcase end - always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h511101[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h511837; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511101 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511101[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q215; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - 52'd0; - endcase - end - always@(guard__h502881 or - sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) - begin - case (guard__h502881) - 2'b0, 2'b01: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h511101[56:5]; - 2'b10: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h511840; - 2'b11: - CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h511837; - endcase - end always@(guard__h493569 or _theResult___snd__h501481 or _theResult___sfd__h502186) begin case (guard__h493569) 2'b0: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___snd__h501481[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = _theResult___sfd__h502186; endcase end @@ -36880,7 +36845,7 @@ module mkCore(CLK, _theResult___snd__h501481 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217) + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36894,7 +36859,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q217; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase @@ -36905,13 +36870,13 @@ module mkCore(CLK, begin case (guard__h493569) 2'b0, 2'b01: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___snd__h501481[56:5]; 2'b10: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = out_sfd__h502189; 2'b11: - CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q218 = + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = _theResult___sfd__h502186; endcase end @@ -36920,10 +36885,10 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___snd__h519886[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 = _theResult___sfd__h520621; endcase end @@ -36931,7 +36896,7 @@ module mkCore(CLK, _theResult___snd__h519886 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219) + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36945,7 +36910,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase @@ -36956,16 +36921,65 @@ module mkCore(CLK, begin case (guard__h511950) 2'b0, 2'b01: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___snd__h519886[56:5]; 2'b10: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = out_sfd__h520624; 2'b11: - CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 = _theResult___sfd__h520621; endcase end + always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h511101[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h511837; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h511101 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + sfdin__h511101[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = + 52'd0; + endcase + end + always@(guard__h502881 or + sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) + begin + case (guard__h502881) + 2'b0, 2'b01: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + sfdin__h511101[56:5]; + 2'b10: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + out_sfd__h511840; + 2'b11: + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 = + _theResult___sfd__h511837; + endcase + end always@(guard__h571726 or _theResult___snd__h579638 or _theResult___sfd__h580343) begin @@ -38031,10 +38045,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = + coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -38042,10 +38056,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = - coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -38350,38 +38364,6 @@ module mkCore(CLK, endcase end always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q246 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) 12'd1, @@ -38428,12 +38410,44 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q248 = + default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = 12'd2303; endcase end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + 4'd15; + endcase + end always@(commitStage_f_rob_data$D_OUT) begin case (commitStage_f_rob_data$D_OUT[97:96]) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index bb0d3be..607e8ac 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -78,6 +78,7 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// start_is_running I 1 // start_tohost_addr I 64 // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 @@ -161,6 +162,7 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_set_verbosity, RDY_set_verbosity, + start_is_running, start_tohost_addr, start_fromhost_addr, EN_start, @@ -379,6 +381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, output RDY_set_verbosity; // action method start + input start_is_running; input [63 : 0] start_tohost_addr; input [63 : 0] start_fromhost_addr; input EN_start; @@ -1401,7 +1404,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master1_wready, proc$master1_wvalid, proc$non_maskable_interrupt_req_set_not_clear, - proc$s_external_interrupt_req_set_not_clear; + proc$s_external_interrupt_req_set_not_clear, + proc$start_running; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, @@ -1609,12 +1613,12 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5047; - reg [31 : 0] v__h5190; - reg [31 : 0] v__h15930; - reg [31 : 0] v__h5041; - reg [31 : 0] v__h5184; - reg [31 : 0] v__h15924; + reg [31 : 0] v__h5055; + reg [31 : 0] v__h5198; + reg [31 : 0] v__h15940; + reg [31 : 0] v__h5049; + reg [31 : 0] v__h5192; + reg [31 : 0] v__h15934; // synopsys translate_on // remaining internal signals @@ -2523,6 +2527,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), .start_fromhostAddr(proc$start_fromhostAddr), + .start_running(proc$start_running), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), @@ -2716,22 +2721,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -3359,6 +3364,7 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_proc$start_1__SEL_1 ? rg_fromhost_addr : start_fromhost_addr ; + assign proc$start_running = MUX_proc$start_1__SEL_1 || start_is_running ; assign proc$start_startpc = 64'h0000000070000000 ; assign proc$start_tohostAddr = MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; @@ -3700,15 +3706,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h5047 = $stime; + v__h5055 = $stime; #0; end - v__h5041 = v__h5047 / 32'd10; + v__h5049 = v__h5055 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h5041, + v__h5049, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -3716,17 +3722,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h5190 = $stime; + v__h5198 = $stime; #0; end - v__h5184 = v__h5190 / 32'd10; + v__h5192 = v__h5198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h5184, + v__h5192, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); @@ -3734,15 +3740,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15930 = $stime; + v__h15940 = $stime; #0; end - v__h15924 = v__h15930 / 32'd10; + v__h15934 = v__h15940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15924, + v__h15934, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v index 7ed7f93..e079454 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v @@ -130,17 +130,13 @@ module mkJtagTap(CLK, // inlined wires wire [40 : 0] w_dmi_req$wget; - wire r_dmistat_busy$port1__read, + wire r_dmistat_busy$EN_port1__write, + r_dmistat_busy$port1__read, r_dmistat_busy$port2__read, r_tdo$EN_port0__write, r_tdo$port0__write_1, r_tdo$port1__read; - // register r_dmi - reg [39 : 0] r_dmi; - wire [39 : 0] r_dmi$D_IN; - wire r_dmi$EN; - // register r_dmistat_busy reg r_dmistat_busy; wire r_dmistat_busy$D_IN, r_dmistat_busy$EN; @@ -160,11 +156,6 @@ module mkJtagTap(CLK, wire [17 : 0] r_ir$D_IN; wire r_ir$EN; - // register r_state - reg [3 : 0] r_state; - wire [3 : 0] r_state$D_IN; - wire r_state$EN; - // register r_tdo reg r_tdo; wire r_tdo$D_IN, r_tdo$EN; @@ -179,6 +170,7 @@ module mkJtagTap(CLK, // ports of submodule f_dmi_req wire [40 : 0] f_dmi_req$dD_OUT, f_dmi_req$sD_IN; wire f_dmi_req$dCLR, + f_dmi_req$dCLR_RDY, f_dmi_req$dDEQ, f_dmi_req$dEMPTY_N, f_dmi_req$sCLR, @@ -193,18 +185,32 @@ module mkJtagTap(CLK, f_dmi_rsp$dDEQ, f_dmi_rsp$dEMPTY_N, f_dmi_rsp$sCLR, + f_dmi_rsp$sCLR_RDY, f_dmi_rsp$sENQ, f_dmi_rsp$sFULL_N; + // ports of submodule r_dmi + wire [39 : 0] r_dmi$D_IN, r_dmi$Q_OUT; + wire r_dmi$EN; + + // ports of submodule r_initialize + wire r_initialize$D_IN, r_initialize$EN, r_initialize$Q_OUT; + + // ports of submodule r_initialize2 + wire r_initialize2$D_IN, r_initialize2$EN, r_initialize2$Q_OUT; + + // ports of submodule r_state + wire [3 : 0] r_state$D_IN, r_state$Q_OUT; + wire r_state$EN; + // ports of submodule rst_tck wire rst_tck$OUT_RST; // ports of submodule tck_clock - wire tck_clock$CLK_IN, - tck_clock$CLK_IN_EN, - tck_clock$CLK_OUT, - tck_clock$COND_IN, - tck_clock$COND_IN_EN; + wire tck_clock$IN, tck_clock$OUT; + + // ports of submodule w_tck_crossed + wire w_tck_crossed$DOUT; // rule scheduling signals wire CAN_FIRE_RL_dmi_request, @@ -215,7 +221,9 @@ module mkJtagTap(CLK, CAN_FIRE_RL_dmi_response_ready, CAN_FIRE_RL_dmi_response_tck, CAN_FIRE_RL_dmi_start, - CAN_FIRE_RL_rl_tck, + CAN_FIRE_RL_mkConnectionVtoAf, + CAN_FIRE_RL_rl_initialize, + CAN_FIRE_RL_rl_initialize2, CAN_FIRE_RL_tick, CAN_FIRE_dmi_req_ready, CAN_FIRE_dmi_rsp_data, @@ -232,7 +240,9 @@ module mkJtagTap(CLK, WILL_FIRE_RL_dmi_response_ready, WILL_FIRE_RL_dmi_response_tck, WILL_FIRE_RL_dmi_start, - WILL_FIRE_RL_rl_tck, + WILL_FIRE_RL_mkConnectionVtoAf, + WILL_FIRE_RL_rl_initialize, + WILL_FIRE_RL_rl_initialize2, WILL_FIRE_RL_tick, WILL_FIRE_dmi_req_ready, WILL_FIRE_dmi_rsp_data, @@ -243,24 +253,24 @@ module mkJtagTap(CLK, WILL_FIRE_jtag_tms; // remaining internal signals - reg [39 : 0] CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, - v__h2135; - reg [17 : 0] newir__h3435; - reg [3 : 0] CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3, - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2; - wire [39 : 0] IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140, - v__h2233, - v__h2601, - x__h2449, - x__h2658, - y__h2659; - wire [17 : 0] v__h3299, x__h3350, y__h3351; - wire r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68, - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72; + reg [39 : 0] CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1, + v__h2479; + reg [17 : 0] newir__h3774; + reg [3 : 0] CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3, + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2; + wire [39 : 0] IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146, + v__h2576, + v__h2941, + x__h2789, + x__h2996, + y__h2997; + wire [17 : 0] v__h3636, x__h3687, y__h3688; + wire r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74, + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78; // oscillator and gates for output clock CLK_jtag_tclk_out - assign CLK_jtag_tclk_out = tck_clock$CLK_OUT ; + assign CLK_jtag_tclk_out = tck_clock$OUT ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; // action method jtag_tdi @@ -311,7 +321,7 @@ module mkJtagTap(CLK, // submodule f_dmi_busy FIFO20 #(.guarded(32'd1)) f_dmi_busy(.RST(rst_tck$OUT_RST), - .CLK(tck_clock$CLK_OUT), + .CLK(tck_clock$OUT), .ENQ(f_dmi_busy$ENQ), .DEQ(f_dmi_busy$DEQ), .CLR(f_dmi_busy$CLR), @@ -321,7 +331,7 @@ module mkJtagTap(CLK, // submodule f_dmi_req SyncFIFOLevel #(.dataWidth(32'd41), .depth(32'd2), - .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$CLK_OUT), + .indxWidth(32'd1)) f_dmi_req(.sCLK(tck_clock$OUT), .dCLK(CLK), .sRST(rst_tck$OUT_RST), .sD_IN(f_dmi_req$sD_IN), @@ -335,13 +345,13 @@ module mkJtagTap(CLK, .dCOUNT(), .sCOUNT(), .sCLR_RDY(f_dmi_req$sCLR_RDY), - .dCLR_RDY()); + .dCLR_RDY(f_dmi_req$dCLR_RDY)); // submodule f_dmi_rsp SyncFIFOLevel #(.dataWidth(32'd40), .depth(32'd2), .indxWidth(32'd1)) f_dmi_rsp(.sCLK(CLK), - .dCLK(tck_clock$CLK_OUT), + .dCLK(tck_clock$OUT), .sRST(RST_N), .sD_IN(f_dmi_rsp$sD_IN), .sENQ(f_dmi_rsp$sENQ), @@ -353,29 +363,46 @@ module mkJtagTap(CLK, .dEMPTY_N(f_dmi_rsp$dEMPTY_N), .dCOUNT(), .sCOUNT(), - .sCLR_RDY(), + .sCLR_RDY(f_dmi_rsp$sCLR_RDY), .dCLR_RDY(f_dmi_rsp$dCLR_RDY)); + // submodule r_dmi + RegUNInit #(.width(32'd40), .init(40'd0)) r_dmi(.CLK(tck_clock$OUT), + .D_IN(r_dmi$D_IN), + .EN(r_dmi$EN), + .Q_OUT(r_dmi$Q_OUT)); + + // submodule r_initialize + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize(.CLK(tck_clock$OUT), + .D_IN(r_initialize$D_IN), + .EN(r_initialize$EN), + .Q_OUT(r_initialize$Q_OUT)); + + // submodule r_initialize2 + RegUNInit #(.width(32'd1), .init(1'd1)) r_initialize2(.CLK(CLK), + .D_IN(r_initialize2$D_IN), + .EN(r_initialize2$EN), + .Q_OUT(r_initialize2$Q_OUT)); + + // submodule r_state + RegUNInit #(.width(32'd4), .init(4'd0)) r_state(.CLK(tck_clock$OUT), + .D_IN(r_state$D_IN), + .EN(r_state$EN), + .Q_OUT(r_state$Q_OUT)); + // submodule rst_tck - SyncResetA #(.RSTDELAY(32'd3)) rst_tck(.CLK(tck_clock$CLK_OUT), - .IN_RST(RST_N), - .OUT_RST(rst_tck$OUT_RST)); + SyncReset0 rst_tck(.IN_RST(RST_N), .OUT_RST(rst_tck$OUT_RST)); // submodule tck_clock - MakeClock #(.initVal(1'h0), .initGate(1'd1)) tck_clock(.CLK(CLK), - .RST(RST_N), - .CLK_IN(tck_clock$CLK_IN), - .COND_IN(tck_clock$COND_IN), - .CLK_IN_EN(tck_clock$CLK_IN_EN), - .COND_IN_EN(tck_clock$COND_IN_EN), - .CLK_VAL_OUT(), - .COND_OUT(), - .CLK_GATE_OUT(), - .CLK_OUT(tck_clock$CLK_OUT)); + ASSIGN1 tck_clock(.IN(tck_clock$IN), .OUT(tck_clock$OUT)); - // rule RL_rl_tck - assign CAN_FIRE_RL_rl_tck = 1'd1 ; - assign WILL_FIRE_RL_rl_tck = 1'd1 ; + // submodule w_tck_crossed + SyncWire #(.width(32'd1)) w_tck_crossed(.DIN(jtag_tclk), + .DOUT(w_tck_crossed$DOUT)); + + // rule RL_mkConnectionVtoAf + assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; + assign WILL_FIRE_RL_mkConnectionVtoAf = 1'd1 ; // rule RL_tick assign CAN_FIRE_RL_tick = 1'd1 ; @@ -383,7 +410,7 @@ module mkJtagTap(CLK, // rule RL_dmi_start assign CAN_FIRE_RL_dmi_start = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 && f_dmi_req$sFULL_N && f_dmi_busy$FULL_N && w_dmi_req$wget[1:0] != 2'd0 ; @@ -406,9 +433,14 @@ module mkJtagTap(CLK, f_dmi_rsp$dEMPTY_N && f_dmi_busy$EMPTY_N ; assign WILL_FIRE_RL_dmi_response_tck = CAN_FIRE_RL_dmi_response_tck ; + // rule RL_rl_initialize + assign CAN_FIRE_RL_rl_initialize = + r_state$Q_OUT == 4'd0 && r_initialize$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize = CAN_FIRE_RL_rl_initialize ; + // rule RL_dmi_reset assign CAN_FIRE_RL_dmi_reset = - r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 && + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 && (!r_dr[17] || f_dmi_req$sCLR_RDY && f_dmi_rsp$dCLR_RDY) ; assign WILL_FIRE_RL_dmi_reset = CAN_FIRE_RL_dmi_reset ; @@ -420,35 +452,37 @@ module mkJtagTap(CLK, assign CAN_FIRE_RL_dmi_response = f_dmi_rsp$sFULL_N && dmi_rsp_valid ; assign WILL_FIRE_RL_dmi_response = CAN_FIRE_RL_dmi_response ; + // rule RL_rl_initialize2 + assign CAN_FIRE_RL_rl_initialize2 = + f_dmi_rsp$sCLR_RDY && f_dmi_req$dCLR_RDY && r_initialize2$Q_OUT ; + assign WILL_FIRE_RL_rl_initialize2 = CAN_FIRE_RL_rl_initialize2 ; + // inlined wires assign w_dmi_req$wget = { 1'd0, r_dr } ; - assign r_tdo$EN_port0__write = r_state == 4'd4 || r_state == 4'd11 ; - assign r_tdo$port0__write_1 = (r_state == 4'd4) ? r_dr[0] : r_ir[0] ; + assign r_tdo$EN_port0__write = + r_state$Q_OUT == 4'd4 || r_state$Q_OUT == 4'd11 ; + assign r_tdo$port0__write_1 = (r_state$Q_OUT == 4'd4) ? r_dr[0] : r_ir[0] ; assign r_tdo$port1__read = r_tdo$EN_port0__write ? r_tdo$port0__write_1 : r_tdo ; assign r_dmistat_busy$port1__read = - r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 || + r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 || r_dmistat_busy ; + assign r_dmistat_busy$EN_port1__write = + WILL_FIRE_RL_dmi_reset || WILL_FIRE_RL_rl_initialize ; assign r_dmistat_busy$port2__read = - !CAN_FIRE_RL_dmi_reset && r_dmistat_busy$port1__read ; - - // register r_dmi - assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; - assign r_dmi$EN = - WILL_FIRE_RL_dmi_response_tck && r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 ; + !r_dmistat_busy$EN_port1__write && r_dmistat_busy$port1__read ; // register r_dmistat_busy assign r_dmistat_busy$D_IN = r_dmistat_busy$port2__read ; assign r_dmistat_busy$EN = 1'b1 ; // register r_dr - always@(r_state or r_dr or v__h2135 or v__h2601) + always@(r_state$Q_OUT or r_dr or v__h2479 or v__h2941) begin - case (r_state) + case (r_state$Q_OUT) 4'd0: r_dr$D_IN = r_dr; - 4'd3: r_dr$D_IN = v__h2135; - 4'd4: r_dr$D_IN = v__h2601; + 4'd3: r_dr$D_IN = v__h2479; + 4'd4: r_dr$D_IN = v__h2941; default: r_dr$D_IN = r_dr; endcase end @@ -456,22 +490,15 @@ module mkJtagTap(CLK, // register r_drmask assign r_drmask$D_IN = - (r_state == 4'd3) ? - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : + (r_state$Q_OUT == 4'd3) ? + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 : r_drmask ; assign r_drmask$EN = 1'd1 ; // register r_ir - assign r_ir$D_IN = newir__h3435 ; + assign r_ir$D_IN = newir__h3774 ; assign r_ir$EN = 1'd1 ; - // register r_state - assign r_state$D_IN = - jtag_tms ? - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 : - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 ; - assign r_state$EN = 1'd1 ; - // register r_tdo assign r_tdo$D_IN = r_tdo$port1__read ; assign r_tdo$EN = 1'b1 ; @@ -479,69 +506,89 @@ module mkJtagTap(CLK, // submodule f_dmi_busy assign f_dmi_busy$ENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_busy$DEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_busy$CLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + assign f_dmi_busy$CLR = + WILL_FIRE_RL_dmi_reset && r_dr[17] || + WILL_FIRE_RL_rl_initialize ; // submodule f_dmi_req assign f_dmi_req$sD_IN = w_dmi_req$wget ; assign f_dmi_req$sENQ = CAN_FIRE_RL_dmi_start ; assign f_dmi_req$dDEQ = CAN_FIRE_RL_dmi_request_deq ; assign f_dmi_req$sCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; - assign f_dmi_req$dCLR = 1'b0 ; + assign f_dmi_req$dCLR = CAN_FIRE_RL_rl_initialize2 ; // submodule f_dmi_rsp assign f_dmi_rsp$sD_IN = { 6'h2A, dmi_rsp_data, dmi_rsp_response } ; assign f_dmi_rsp$sENQ = CAN_FIRE_RL_dmi_response ; assign f_dmi_rsp$dDEQ = CAN_FIRE_RL_dmi_response_tck ; - assign f_dmi_rsp$sCLR = 1'b0 ; + assign f_dmi_rsp$sCLR = CAN_FIRE_RL_rl_initialize2 ; assign f_dmi_rsp$dCLR = WILL_FIRE_RL_dmi_reset && r_dr[17] ; + // submodule r_dmi + assign r_dmi$D_IN = f_dmi_rsp$dD_OUT ; + assign r_dmi$EN = + WILL_FIRE_RL_dmi_response_tck && r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 ; + + // submodule r_initialize + assign r_initialize$D_IN = 1'd0 ; + assign r_initialize$EN = CAN_FIRE_RL_rl_initialize ; + + // submodule r_initialize2 + assign r_initialize2$D_IN = 1'd0 ; + assign r_initialize2$EN = CAN_FIRE_RL_rl_initialize2 ; + + // submodule r_state + assign r_state$D_IN = + jtag_tms ? + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 : + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 ; + assign r_state$EN = 1'd1 ; + // submodule tck_clock - assign tck_clock$CLK_IN = jtag_tclk ; - assign tck_clock$COND_IN = 1'b0 ; - assign tck_clock$CLK_IN_EN = 1'd1 ; - assign tck_clock$COND_IN_EN = 1'b0 ; + assign tck_clock$IN = w_tck_crossed$DOUT ; // remaining internal signals - assign IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 = + assign IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 = (r_dmistat_busy || - r_dmi[1:0] != 2'd2 && r_dmi[1:0] != 2'd3 && + r_dmi$Q_OUT[1:0] != 2'd2 && r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N) ? 40'hAAAAAAAAAB : - r_dmi ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b10001010010010010_ETC___d57 = - r_state == 4'd8 && r_ir == 18'b100010100100100100 && + r_dmi$Q_OUT ; + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b100010100_ETC___d63 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b100010100100100100 && (r_dr[17] || r_dr[16]) ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d68 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d74 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && f_dmi_busy$EMPTY_N ; - assign r_state_EQ_8_2_AND_r_ir_EQ_0b11100100100100_4__ETC___d72 = - r_state == 4'd8 && r_ir == 18'b000011100100100100 && - r_dmi[1:0] != 2'd2 && - r_dmi[1:0] != 2'd3 && + assign r_state__read_EQ_8_8_AND_r_ir_3_EQ_0b111001001_ETC___d78 = + r_state$Q_OUT == 4'd8 && r_ir == 18'b000011100100100100 && + r_dmi$Q_OUT[1:0] != 2'd2 && + r_dmi$Q_OUT[1:0] != 2'd3 && !f_dmi_busy$EMPTY_N ; - assign v__h2233 = { 22'd960, r_ir } ; - assign v__h2601 = x__h2658 | y__h2659 ; - assign v__h3299 = x__h3350 | y__h3351 ; - assign x__h2449 = { 28'd0, r_dmi[1:0], 10'd97 } ; - assign x__h2658 = { 1'd0, r_dr[39:1] } ; - assign x__h3350 = { 1'd0, r_ir[17:1] } ; - assign y__h2659 = jtag_tdi ? r_drmask : 40'd0 ; - assign y__h3351 = jtag_tdi ? 18'd131072 : 18'd0 ; - always@(r_state or r_ir or v__h3299) + assign v__h2576 = { 22'd960, r_ir } ; + assign v__h2941 = x__h2996 | y__h2997 ; + assign v__h3636 = x__h3687 | y__h3688 ; + assign x__h2789 = { 28'd0, r_dmi$Q_OUT[1:0], 10'd97 } ; + assign x__h2996 = { 1'd0, r_dr[39:1] } ; + assign x__h3687 = { 1'd0, r_ir[17:1] } ; + assign y__h2997 = jtag_tdi ? r_drmask : 40'd0 ; + assign y__h3688 = jtag_tdi ? 18'd131072 : 18'd0 ; + always@(r_state$Q_OUT or r_ir or v__h3636) begin - case (r_state) - 4'd0: newir__h3435 = 18'd1; - 4'd3, 4'd4, 4'd8: newir__h3435 = r_ir; - 4'd11: newir__h3435 = v__h3299; - default: newir__h3435 = r_ir; + case (r_state$Q_OUT) + 4'd0: newir__h3774 = 18'd1; + 4'd3, 4'd4, 4'd8: newir__h3774 = r_ir; + 4'd11: newir__h3774 = v__h3636; + default: newir__h3774 = r_ir; endcase end always@(r_ir or - v__h2233 or - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140 or - x__h2449) + v__h2576 or + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146 or + x__h2789) begin case (r_ir) 18'd0, @@ -552,18 +599,18 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - v__h2135 = 40'd0; - 18'd1: v__h2135 = 40'd4093; + v__h2479 = 40'd0; + 18'd1: v__h2479 = 40'd4093; 18'b000011100100100100: - v__h2135 = - IF_r_dmistat_busy_port0__read__37_OR_NOT_r_dmi_ETC___d140; - 18'b100010100100100100: v__h2135 = x__h2449; - default: v__h2135 = v__h2233; + v__h2479 = + IF_r_dmistat_busy_port0__read__43_OR_NOT_r_dmi_ETC___d146; + 18'b100010100100100100: v__h2479 = x__h2789; + default: v__h2479 = v__h2576; endcase end - always@(newir__h3435) + always@(newir__h3774) begin - case (newir__h3435) + case (newir__h3774) 18'd0, 18'h00012, 18'h00013, @@ -572,71 +619,67 @@ module mkJtagTap(CLK, 18'h00016, 18'h00017, 18'd262143: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'd1; 18'd1, 18'b100010100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0080000000; 18'b000011100100100100: - CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h8000000000; - default: CASE_newir435_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = + default: CASE_newir774_0_1_1_2147483648_0x12_1_0x13_1_0_ETC__q1 = 40'h0100000000; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) - 4'd0: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = r_state; + case (r_state$Q_OUT) + 4'd0: + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = + r_state$Q_OUT; 4'd1, 4'd8, 4'd15: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd2; - 4'd2: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd9; - 4'd3, 4'd4: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd5; - 4'd5, 4'd7: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd8; - 4'd6: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd7; - 4'd9: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd0; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd2; + 4'd2: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd9; + 4'd3, 4'd4: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd5; + 4'd5, 4'd7: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd8; + 4'd6: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd7; + 4'd9: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd0; 4'd10, 4'd11: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd12; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd12; 4'd12, 4'd14: - CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd15; - 4'd13: CASE_r_state_0_r_state_1_2_2_9_3_5_4_5_5_8_6_7_ETC__q2 = 4'd14; + CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd15; + 4'd13: CASE_r_stateQ_OUT_0_r_stateQ_OUT_1_2_2_9_3_5_ETC__q2 = 4'd14; endcase end - always@(r_state) + always@(r_state$Q_OUT) begin - case (r_state) + case (r_state$Q_OUT) 4'd0, 4'd1, 4'd8, 4'd15: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd1; - 4'd2: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd3; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd1; + 4'd2: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd3; 4'd3, 4'd4, 4'd7: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd4; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd4; 4'd5, 4'd6: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd6; - 4'd9: CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd10; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd6; + 4'd9: CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd10; 4'd10, 4'd11, 4'd14: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd11; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd11; 4'd12, 4'd13: - CASE_r_state_0_1_1_1_2_3_3_4_4_4_5_6_6_6_7_4_8_ETC__q3 = 4'd13; + CASE_r_stateQ_OUT_0_1_1_1_2_3_3_4_4_4_5_6_6_6_ETC__q3 = 4'd13; endcase end // handling of inlined registers - always@(posedge tck_clock$CLK_OUT) + always@(posedge tck_clock$OUT) begin if (rst_tck$OUT_RST == `BSV_RESET_VALUE) begin - r_dmi <= `BSV_ASSIGNMENT_DELAY 40'd0; - r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - r_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin - if (r_dmi$EN) r_dmi <= `BSV_ASSIGNMENT_DELAY r_dmi$D_IN; - if (r_dmistat_busy$EN) + if (r_dmistat_busy$EN) r_dmistat_busy <= `BSV_ASSIGNMENT_DELAY r_dmistat_busy$D_IN; - if (r_state$EN) r_state <= `BSV_ASSIGNMENT_DELAY r_state$D_IN; end if (r_dr$EN) r_dr <= `BSV_ASSIGNMENT_DELAY r_dr$D_IN; if (r_drmask$EN) r_drmask <= `BSV_ASSIGNMENT_DELAY r_drmask$D_IN; @@ -649,12 +692,10 @@ module mkJtagTap(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - r_dmi = 40'hAAAAAAAAAA; r_dmistat_busy = 1'h0; r_dr = 40'hAAAAAAAAAA; r_drmask = 40'hAAAAAAAAAA; r_ir = 18'h2AAAA; - r_state = 4'hA; r_tdo = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS @@ -663,11 +704,11 @@ module mkJtagTap(CLK, // handling of system tasks // synopsys translate_off - always@(negedge tck_clock$CLK_OUT) + always@(negedge tck_clock$OUT) begin #0; if (rst_tck$OUT_RST != `BSV_RESET_VALUE) - if (r_state == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && + if (r_state$Q_OUT == 4'd3 && r_ir != 18'd0 && r_ir != 18'h00012 && r_ir != 18'h00013 && r_ir != 18'h00014 && r_ir != 18'h00015 && diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index b1f7022..53c9fed 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -648,14 +648,19 @@ module mkP3_Core(CLK, wire bus_dmi_rsp_fifof_q_1$EN; // register rg_corew_start_after_por - reg rg_corew_start_after_por; - wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + reg [7 : 0] rg_corew_start_after_por; + wire [7 : 0] rg_corew_start_after_por$D_IN; + wire rg_corew_start_after_por$EN; // register rg_ndm_reset_delay reg [7 : 0] rg_ndm_reset_delay; wire [7 : 0] rg_ndm_reset_delay$D_IN; wire rg_ndm_reset_delay$EN; + // register rg_running + reg rg_running; + wire rg_running$D_IN, rg_running$EN; + // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; wire bus_dmi_req_fifof$CLR, @@ -781,8 +786,10 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, + corew$ndm_reset_client_request_get, corew$ndm_reset_client_response_put, - corew$nmi_req_set_not_clear; + corew$nmi_req_set_not_clear, + corew$start_is_running; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -804,6 +811,9 @@ module mkP3_Core(CLK, // ports of submodule ndm_reset_controller wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; + // ports of submodule por_ifc + wire por_ifc$RST_N_gen_rst; + // ports of submodule tv_xactor wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; @@ -910,15 +920,15 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1279; - reg [31 : 0] v__h1424; - reg [31 : 0] v__h1273; - reg [31 : 0] v__h1418; + reg [31 : 0] v__h1362; + reg [31 : 0] v__h1510; + reg [31 : 0] v__h1356; + reg [31 : 0] v__h1504; // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; - wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49; + wire IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99, _dfoo1, _dfoo3; @@ -1188,7 +1198,7 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(por_ifc$RST_N_gen_rst), .CLK(CLK), .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), @@ -1237,6 +1247,7 @@ module mkP3_Core(CLK, .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .start_fromhost_addr(corew$start_fromhost_addr), + .start_is_running(corew$start_is_running), .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), @@ -1308,7 +1319,7 @@ module mkP3_Core(CLK, .dmi_read_data(corew$dmi_read_data), .RDY_dmi_read_data(corew$RDY_dmi_read_data), .RDY_dmi_write(corew$RDY_dmi_write), - .ndm_reset_client_request_get(), + .ndm_reset_client_request_get(corew$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put), .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), @@ -1316,7 +1327,7 @@ module mkP3_Core(CLK, // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), - .RST_N(RST_N), + .RST_N(por_ifc$RST_N_gen_rst), .dmi_req_ready(jtagtap$dmi_req_ready), .dmi_rsp_data(jtagtap$dmi_rsp_data), .dmi_rsp_response(jtagtap$dmi_rsp_response), @@ -1334,7 +1345,7 @@ module mkP3_Core(CLK, .CLK_GATE_jtag_tclk_out()); // submodule ndm_reset - ResetEither ndm_reset(.A_RST(RST_N), + ResetEither ndm_reset(.A_RST(por_ifc$RST_N_gen_rst), .B_RST(ndm_reset_controller$OUT_RST), .RST_OUT(ndm_reset$RST_OUT)); @@ -1346,6 +1357,11 @@ module mkP3_Core(CLK, .ASSERT_OUT(), .OUT_RST(ndm_reset_controller$OUT_RST)); + // submodule por_ifc + mkPowerOnReset por_ifc(.CLK(CLK), + .RST_N(RST_N), + .RST_N_gen_rst(por_ifc$RST_N_gen_rst)); + // submodule tv_xactor mkTV_Xactor tv_xactor(.CLK(CLK), .RST_N(RST_N), @@ -1371,7 +1387,8 @@ module mkP3_Core(CLK, // rule RL_rl_step_0 assign CAN_FIRE_RL_rl_step_0 = - corew$RDY_start && !rg_corew_start_after_por ; + (rg_corew_start_after_por != 8'd1 || corew$RDY_start) && + rg_corew_start_after_por != 8'd0 ; assign WILL_FIRE_RL_rl_step_0 = CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; @@ -1422,7 +1439,7 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; + IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu @@ -1434,7 +1451,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; @@ -1526,7 +1543,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1585,7 +1602,7 @@ module mkP3_Core(CLK, WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register rg_corew_start_after_por - assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$D_IN = rg_corew_start_after_por - 8'd1 ; assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; // register rg_ndm_reset_delay @@ -1596,6 +1613,10 @@ module mkP3_Core(CLK, assign rg_ndm_reset_delay$EN = WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; + // register rg_running + assign rg_running$D_IN = corew$ndm_reset_client_request_get ; + assign rg_running$EN = CAN_FIRE_RL_rl_ndm_reset ; + // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; assign bus_dmi_req_fifof$ENQ = CAN_FIRE_RL_bus_dmi_req_do_enq ; @@ -1660,16 +1681,17 @@ module mkP3_Core(CLK, assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$ndm_reset_client_response_put = rg_running ; assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_is_running = !MUX_corew$start_1__SEL_1 || rg_running ; assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || - WILL_FIRE_RL_rl_step_0 ; + WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1699,7 +1721,7 @@ module mkP3_Core(CLK, assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = + assign IF_bus_dmi_req_fifof_first__8_BITS_1_TO_0_9_EQ_ETC___d99 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || @@ -1708,11 +1730,11 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = + bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_1_MINUS_1___d49 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1724,7 +1746,7 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 8'd100; rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else @@ -1744,6 +1766,7 @@ module mkP3_Core(CLK, if (rg_ndm_reset_delay$EN) rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end + if (rg_running$EN) rg_running <= `BSV_ASSIGNMENT_DELAY rg_running$D_IN; end // synopsys translate_off @@ -1754,8 +1777,9 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_corew_start_after_por = 1'h0; + rg_corew_start_after_por = 8'hAA; rg_ndm_reset_delay = 8'hAA; + rg_running = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1767,30 +1791,34 @@ module mkP3_Core(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - begin - v__h1279 = $stime; - #0; - end - v__h1273 = v__h1279 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset) - $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1273, - $signed(32'd10)); - if (RST_N != `BSV_RESET_VALUE) - if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1424 = $stime; + v__h1362 = $stime; #0; end - v__h1418 = v__h1424 / 32'd10; + v__h1356 = v__h1362 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1356, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) - $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1418); + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1510 = $stime; + #0; + end + v__h1504 = v__h1510 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1504); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v new file mode 100644 index 0000000..65d7430 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v @@ -0,0 +1,92 @@ +// +// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// +// +// +// +// Ports: +// Name I/O size props +// RST_N_gen_rst O 1 reset +// CLK I 1 clock +// RST_N I 1 unused +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkPowerOnReset(CLK, + RST_N, + + RST_N_gen_rst); + input CLK; + input RST_N; + + // output resets + output RST_N_gen_rst; + + // signals for module outputs + wire RST_N_gen_rst; + + // ports of submodule ctr + wire [7 : 0] ctr$D_IN, ctr$Q_OUT; + wire ctr$EN; + + // ports of submodule isInPowerOnReset + wire isInPowerOnReset$D_IN, isInPowerOnReset$EN, isInPowerOnReset$Q_OUT; + + // ports of submodule rst_ifc + wire rst_ifc$OUT; + + // rule scheduling signals + wire CAN_FIRE_RL_countDown, WILL_FIRE_RL_countDown; + + // remaining internal signals + wire NOT_isInPowerOnReset__read___d5; + + // output resets + assign RST_N_gen_rst = rst_ifc$OUT ; + + // submodule ctr + RegUNInit #(.width(32'd8), .init(8'd10)) ctr(.CLK(CLK), + .D_IN(ctr$D_IN), + .EN(ctr$EN), + .Q_OUT(ctr$Q_OUT)); + + // submodule isInPowerOnReset + RegUNInit #(.width(32'd1), .init(1'd1)) isInPowerOnReset(.CLK(CLK), + .D_IN(isInPowerOnReset$D_IN), + .EN(isInPowerOnReset$EN), + .Q_OUT(isInPowerOnReset$Q_OUT)); + + // submodule rst_ifc + ASSIGN1 rst_ifc(.IN(NOT_isInPowerOnReset__read___d5), .OUT(rst_ifc$OUT)); + + // rule RL_countDown + assign CAN_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + assign WILL_FIRE_RL_countDown = isInPowerOnReset$Q_OUT ; + + // submodule ctr + assign ctr$D_IN = ctr$Q_OUT - 8'd1 ; + assign ctr$EN = isInPowerOnReset$Q_OUT ; + + // submodule isInPowerOnReset + assign isInPowerOnReset$D_IN = 1'd0 ; + assign isInPowerOnReset$EN = isInPowerOnReset$Q_OUT && ctr$Q_OUT == 8'd1 ; + + // remaining internal signals + assign NOT_isInPowerOnReset__read___d5 = !isInPowerOnReset$Q_OUT ; +endmodule // mkPowerOnReset + diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index dcc8699..0888d5b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -94,6 +94,7 @@ // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset +// start_running I 1 // start_startpc I 64 // start_tohostAddr I 64 reg // start_fromhostAddr I 64 reg @@ -192,6 +193,7 @@ module mkProc(CLK, RST_N, + start_running, start_startpc, start_tohostAddr, start_fromhostAddr, @@ -454,6 +456,7 @@ module mkProc(CLK, input RST_N; // action method start + input start_running; input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; input [63 : 0] start_fromhostAddr; @@ -1421,6 +1424,7 @@ module mkProc(CLK, core_0$EN_v_to_TV_0_get, core_0$EN_v_to_TV_1_get, core_0$RDY_coreIndInv_terminate, + core_0$RDY_coreReq_start, core_0$RDY_dCacheToParent_fromP_enq, core_0$RDY_dCacheToParent_rqToP_deq, core_0$RDY_dCacheToParent_rqToP_first, @@ -1461,6 +1465,7 @@ module mkProc(CLK, core_0$RDY_tlbToMem_respLd_enq, core_0$RDY_v_to_TV_0_get, core_0$RDY_v_to_TV_1_get, + core_0$coreReq_start_running, core_0$hart0_run_halt_server_request_put, core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, @@ -2104,60 +2109,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162844; - reg [31 : 0] v__h162380; - reg [31 : 0] v__h5520; - reg [31 : 0] v__h5693; - reg [31 : 0] v__h5953; - reg [31 : 0] v__h8095; - reg [31 : 0] v__h8310; - reg [31 : 0] v__h2670; - reg [31 : 0] v__h4343; - reg [31 : 0] v__h9480; - reg [31 : 0] v__h9973; - reg [31 : 0] v__h10136; - reg [31 : 0] v__h134337; - reg [31 : 0] v__h134504; - reg [31 : 0] v__h136607; - reg [31 : 0] v__h153951; - reg [31 : 0] v__h133718; - reg [31 : 0] v__h160645; - reg [31 : 0] v__h161153; - reg [31 : 0] v__h2664; - reg [31 : 0] v__h4337; - reg [31 : 0] v__h5514; - reg [31 : 0] v__h5687; - reg [31 : 0] v__h5947; - reg [31 : 0] v__h8089; - reg [31 : 0] v__h8304; - reg [31 : 0] v__h9474; - reg [31 : 0] v__h9967; - reg [31 : 0] v__h10130; - reg [31 : 0] v__h133712; - reg [31 : 0] v__h134331; - reg [31 : 0] v__h134498; - reg [31 : 0] v__h136601; - reg [31 : 0] v__h153945; - reg [31 : 0] v__h160639; - reg [31 : 0] v__h161147; - reg [31 : 0] v__h162374; - reg [31 : 0] v__h162838; + reg [31 : 0] v__h162856; + reg [31 : 0] v__h162388; + reg [31 : 0] v__h5528; + reg [31 : 0] v__h5701; + reg [31 : 0] v__h5961; + reg [31 : 0] v__h8103; + reg [31 : 0] v__h8318; + reg [31 : 0] v__h2678; + reg [31 : 0] v__h4351; + reg [31 : 0] v__h9488; + reg [31 : 0] v__h9981; + reg [31 : 0] v__h10144; + reg [31 : 0] v__h134345; + reg [31 : 0] v__h134512; + reg [31 : 0] v__h136615; + reg [31 : 0] v__h153959; + reg [31 : 0] v__h133726; + reg [31 : 0] v__h160653; + reg [31 : 0] v__h161161; + reg [31 : 0] v__h2672; + reg [31 : 0] v__h4345; + reg [31 : 0] v__h5522; + reg [31 : 0] v__h5695; + reg [31 : 0] v__h5955; + reg [31 : 0] v__h8097; + reg [31 : 0] v__h8312; + reg [31 : 0] v__h9482; + reg [31 : 0] v__h9975; + reg [31 : 0] v__h10138; + reg [31 : 0] v__h133720; + reg [31 : 0] v__h134339; + reg [31 : 0] v__h134506; + reg [31 : 0] v__h136609; + reg [31 : 0] v__h153953; + reg [31 : 0] v__h160647; + reg [31 : 0] v__h161155; + reg [31 : 0] v__h162382; + reg [31 : 0] v__h162850; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, @@ -2167,44 +2172,44 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, - data64__h147777, - dword__h93782, - ld_data__h131939, - old_dword__h89472, - w1__h47861, - w1__h47866, - w2__h47862, - w2__h47868, - x__h47857; + data64__h147785, + dword__h93790, + ld_data__h131947, + old_dword__h89480, + w1__h47869, + w1__h47874, + w2__h47870, + w2__h47876, + x__h47865; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147778; + reg [7 : 0] strb8__h147786; reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61575; + reg [2 : 0] x__h61583; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, - x__h61582, - x__h82300; + x__h61590, + x__h82308; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - new_cline__h134640; + new_cline__h134648; wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, @@ -2225,89 +2230,89 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - data__h31950, - failed_testnum__h162423, - line_addr__h101846, - line_addr__h101932, - mask__h89469, - mem_req_rd_addr_araddr__h133938, - mem_req_wr_addr_awaddr__h147862, - mmioPlatform_fromHostQ_data_0__h42651, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48453, - n__read_addr__h61443, - n__read_addr__h61528, - n__read_addr__h80062, - n__read_addr__h80141, - n__read_snd_addr__h123373, - newData__h32031, - newData__h34961, - new_dword__h89473, - op_result__h48469, - op_result__h48999, - op_result__h49004, - op_result__h49009, - op_result__h49014, - op_result__h49020, - op_result__h49027, - op_result__h49033, - result__h47912, - result__h48036, - result__h48064, - result__h48092, - result__h48120, - result__h48148, - result__h48176, - result__h48204, - result__h48232, - result__h48277, - result__h48305, - result__h48333, - result__h48361, - result__h48402, - result__h48430, - result__h48556, - result__h48583, - result__h48610, - result__h48637, - result__h48664, - result__h48691, - result__h48718, - result__h48745, - result__h48789, - result__h48816, - result__h48843, - result__h48870, - result__h48910, - result__h48937, - result__h49054, - result__h49120, - result__h49186, - result__h49252, - result__h49318, - result__h49384, - result__h49450, - result__h49512, - result__h49557, - result__h49623, - result__h49689, - result__h49747, - result__h49792, - w1___1__h47971, - w2___1__h47972, - x1_avValue_data__h40323, - x1_avValue_data__h44790, - x__h32142, - x__h35052, - x__h37412, - x__h40841, - x__h40852, - x__h42861, - x__h42872, - x__h49969, - x__h90635, - y__h90636, - y__h90637; + data__h31958, + failed_testnum__h162431, + line_addr__h101854, + line_addr__h101940, + mask__h89477, + mem_req_rd_addr_araddr__h133946, + mem_req_wr_addr_awaddr__h147870, + mmioPlatform_fromHostQ_data_0__h42659, + mmioPlatform_mtime__h37272, + mmioPlatform_reqData__h48461, + n__read_addr__h61451, + n__read_addr__h61536, + n__read_addr__h80070, + n__read_addr__h80149, + n__read_snd_addr__h123381, + newData__h32039, + newData__h34969, + new_dword__h89481, + op_result__h48477, + op_result__h49007, + op_result__h49012, + op_result__h49017, + op_result__h49022, + op_result__h49028, + op_result__h49035, + op_result__h49041, + result__h47920, + result__h48044, + result__h48072, + result__h48100, + result__h48128, + result__h48156, + result__h48184, + result__h48212, + result__h48240, + result__h48285, + result__h48313, + result__h48341, + result__h48369, + result__h48410, + result__h48438, + result__h48564, + result__h48591, + result__h48618, + result__h48645, + result__h48672, + result__h48699, + result__h48726, + result__h48753, + result__h48797, + result__h48824, + result__h48851, + result__h48878, + result__h48918, + result__h48945, + result__h49062, + result__h49128, + result__h49194, + result__h49260, + result__h49326, + result__h49392, + result__h49458, + result__h49520, + result__h49565, + result__h49631, + result__h49697, + result__h49755, + result__h49800, + w1___1__h47979, + w2___1__h47980, + x1_avValue_data__h40331, + x1_avValue_data__h44798, + x__h32150, + x__h35060, + x__h37420, + x__h40849, + x__h40860, + x__h42869, + x__h42880, + x__h49977, + x__h90643, + y__h90644, + y__h90645; wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; @@ -2319,16 +2324,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w17861_BITS_31_TO_0__q15, - w27862_BITS_31_TO_0__q16, - x_data__h30533; + v__h31751, + v__h31788, + w17869_BITS_31_TO_0__q15, + w27870_BITS_31_TO_0__q16, + x_data__h30541; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; - wire [5 : 0] x__h133973, x__h147887; + wire [5 : 0] x__h133981, x__h147895; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; - wire [3 : 0] b__h133645, b__h2564; - wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; + wire [3 : 0] b__h133653, b__h2572; + wire [2 : 0] n__read_id__h61455, n__read_id__h61540, x__h7933; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, @@ -2390,27 +2395,28 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqBE_BIT_0___h30166, + mmioPlatform_reqBE_BIT_4___h30126, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61448, - n__read_child__h61533, - n__read_child__h80065, - n__read_child__h80144, - n__read_snd_id__h123374, + n__read_child__h61456, + n__read_child__h61541, + n__read_child__h80073, + n__read_child__h80152, + n__read_snd_id__h123382, propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, - x__h61261, - x__h74813, - x__h79884; + x__h61269, + x__h74821, + x__h79892; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; - assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; + assign CAN_FIRE_start = + mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; assign WILL_FIRE_start = EN_start ; // value method master0_m_awvalid @@ -2845,6 +2851,7 @@ module mkProc(CLK, .coreReq_perfReq_loc(core_0$coreReq_perfReq_loc), .coreReq_perfReq_t(core_0$coreReq_perfReq_t), .coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr), + .coreReq_start_running(core_0$coreReq_start_running), .coreReq_start_startpc(core_0$coreReq_start_startpc), .coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr), .dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x), @@ -2901,7 +2908,7 @@ module mkProc(CLK, .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), .EN_v_to_TV_0_get(core_0$EN_v_to_TV_0_get), .EN_v_to_TV_1_get(core_0$EN_v_to_TV_1_get), - .RDY_coreReq_start(), + .RDY_coreReq_start(core_0$RDY_coreReq_start), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), .RDY_coreIndInv_perfResp(), @@ -3676,14 +3683,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2564 == 4'd0 ; + b__h2572 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2564 != 4'd0 && + b__h2572 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3796,7 +3803,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42861 == 64'd0 || + x__h42869 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -4116,13 +4123,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133645 == 4'd0 ; + b__h133653 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133645 != 4'd0 && + b__h133653 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4226,7 +4233,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30541 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && @@ -4266,7 +4273,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31958 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -4291,10 +4298,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101846, + { line_addr__h101854, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101932, + { line_addr__h101940, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4305,11 +4312,11 @@ module mkProc(CLK, { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4408,7 +4415,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47857 } ; + x__h47865 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, @@ -4417,7 +4424,7 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49977, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4432,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42869 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42861 != 64'd0 ; + x__h42869 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40841 == 64'd0 ; + x__h40849 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - x__h61261 ; + x__h61269 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23, SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - x__h79884 ; + x__h79892 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; + { 1'd1, n__read_snd_addr__h123381, n__read_snd_id__h123382 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4526,11 +4533,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2564 - 4'd1 ; + b__h2572 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2564 ; + b__h2572 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4579,11 +4586,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133645 - 4'd1 ; + b__h133653 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133645 ; + b__h133653 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4646,7 +4653,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133946, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4664,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147870, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147777, strb8__h147778, 1'd1 } ; + { data64__h147785, strb8__h147786, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4682,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134648 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4730,8 +4737,8 @@ module mkProc(CLK, // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101846 : - line_addr__h101932 ; + line_addr__h101854 : + line_addr__h101940 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4892,7 +4899,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34969 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4908,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32039 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5118,7 +5125,7 @@ module mkProc(CLK, { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78], 8'd0, - x__h7925, + x__h7933, 18'd65536 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -5218,6 +5225,7 @@ module mkProc(CLK, assign core_0$coreReq_perfReq_loc = 4'h0 ; assign core_0$coreReq_perfReq_t = 5'h0 ; assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ; + assign core_0$coreReq_start_running = start_running ; assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = @@ -5321,7 +5329,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131939, llc$dma_respLd_first[3] } ; + { ld_data__h131947, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5475,7 +5483,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134640, + { new_cline__h134648, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5559,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93782, 3'd1 } ; + { 4'd0, dword__h93790, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5854,47 +5862,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37420), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h32150)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37272), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h35060)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40852)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42659), + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h40860)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30126 && + mmioPlatform_reqBE_BIT_0___h30166, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h42872)); + .amoExec_in_data(mmioPlatform_reqData__h48461), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30126 && + !mmioPlatform_reqBE_BIT_0___h30166), + .amoExec(x__h42880)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40323 } } ; + x1_avValue_data__h40331 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || @@ -5910,7 +5918,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; + newData__h32039 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5975,7 +5983,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - x__h74813 } ; + x__h74821 } ; assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5987,29 +5995,29 @@ module mkProc(CLK, assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89473 : + new_dword__h89481 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? @@ -6154,11 +6162,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42861 == 64'd0 : - x__h40841 == 64'd0, + x__h42869 == 64'd0 : + x__h40849 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44790 } ; + x1_avValue_data__h44798 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6392,58 +6400,58 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = - { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + { CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = - { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + { CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - x__h82300 } ; + x__h82308 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = - { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + { CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = - { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - x__h61575, - x__h61582 } ; - assign b__h133645 = + { CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20, + x__h61583, + x__h61590 } ; + assign b__h133653 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2564 = + assign b__h2572 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31958 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h162423 = + { v__h31751, 32'd0 } ; + assign failed_testnum__h162431 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101846 = + assign line_addr__h101854 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101932 = + assign line_addr__h101940 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = - line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; + line_addr__h101940 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = - line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89469 = + line_addr__h101854 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89477 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6476,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133938 = - { llc$to_mem_toM_first[68:11], x__h133973 } ; - assign mem_req_wr_addr_awaddr__h147862 = - { llc$to_mem_toM_first[639:582], x__h147887 } ; + assign mem_req_rd_addr_araddr__h133946 = + { llc$to_mem_toM_first[68:11], x__h133981 } ; + assign mem_req_wr_addr_awaddr__h147870 = + { llc$to_mem_toM_first[639:582], x__h147895 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42651 = + assign mmioPlatform_fromHostQ_data_0__h42659 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,18 +6494,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37272 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + mmioPlatform_mtimecmp_0 <= newData__h34969 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30166 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30126 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48461 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -6529,105 +6537,105 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61443 = + assign n__read_addr__h61451 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61528 = + assign n__read_addr__h61536 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80062 = + assign n__read_addr__h80070 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : 64'd0 ; - assign n__read_addr__h80141 = + assign n__read_addr__h80149 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : 64'd0 ; - assign n__read_child__h61448 = + assign n__read_child__h61456 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61533 = + assign n__read_child__h61541 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80065 = + assign n__read_child__h80073 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; - assign n__read_child__h80144 = + assign n__read_child__h80152 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; - assign n__read_id__h61447 = + assign n__read_id__h61455 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61532 = + assign n__read_id__h61540 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123373 = + assign n__read_snd_addr__h123381 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123374 = + assign n__read_snd_id__h123382 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32039 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : + x__h32150 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + assign newData__h34969 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : + x__h35060 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h134640 = + assign new_cline__h134648 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89473 = x__h90635 | y__h90636 ; - assign op_result__h48469 = + assign new_dword__h89481 = x__h90643 | y__h90644 ; + assign op_result__h48477 = IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; - assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; - assign op_result__h49004 = w1__h47866 & w2__h47868 ; - assign op_result__h49009 = w1__h47866 | w2__h47868 ; - assign op_result__h49014 = - (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; - assign op_result__h49020 = - (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; - assign op_result__h49027 = + assign op_result__h49007 = w1__h47874 ^ w2__h47876 ; + assign op_result__h49012 = w1__h47874 & w2__h47876 ; + assign op_result__h49017 = w1__h47874 | w2__h47876 ; + assign op_result__h49022 = + (w1__h47874 < w2__h47876) ? w1__h47874 : w2__h47876 ; + assign op_result__h49028 = + (w1__h47874 <= w2__h47876) ? w2__h47876 : w1__h47874 ; + assign op_result__h49035 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w1__h47866 : - w2__h47868 ; - assign op_result__h49033 = + w1__h47874 : + w2__h47876 ; + assign op_result__h49041 = ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w2__h47868 : - w1__h47866 ; + w2__h47876 : + w1__h47874 ; assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6638,126 +6646,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47912 = + assign result__h47920 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; - assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48556 = + assign result__h48044 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48072 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48100 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48128 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48156 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48184 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48212 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48240 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48285 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48313 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48341 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48369 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48410 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48438 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48564 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48583 = + assign result__h48591 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48610 = + assign result__h48618 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48637 = + assign result__h48645 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48664 = + assign result__h48672 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48691 = + assign result__h48699 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48718 = + assign result__h48726 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48745 = + assign result__h48753 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48789 = + assign result__h48797 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48816 = + assign result__h48824 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48843 = + assign result__h48851 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48870 = + assign result__h48878 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48910 = + assign result__h48918 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48937 = + assign result__h48945 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49054 = + assign result__h49062 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49120 = + assign result__h49128 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49186 = + assign result__h49194 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49252 = + assign result__h49260 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49318 = + assign result__h49326 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49384 = + assign result__h49392 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49450 = + assign result__h49458 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49512 = + assign result__h49520 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; - assign result__h49557 = + assign result__h49565 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49623 = + assign result__h49631 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49689 = + assign result__h49697 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49747 = + assign result__h49755 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; - assign result__h49792 = + assign result__h49800 = { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; - assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; - assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; - assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; - assign x1_avValue_data__h40323 = + assign v__h31751 = mmioPlatform_waitUpperMSIPCRs ? v__h31788 : 32'd0 ; + assign v__h31788 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17869_BITS_31_TO_0__q15 = w1__h47869[31:0] ; + assign w1___1__h47979 = { 32'd0, w1__h47869[31:0] } ; + assign w27870_BITS_31_TO_0__q16 = w2__h47870[31:0] ; + assign w2___1__h47980 = { 32'd0, w2__h47870[31:0] } ; + assign x1_avValue_data__h40331 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44790 = + assign x1_avValue_data__h44798 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40841 = + assign x__h133981 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147895 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37420 = mmioPlatform_mtimecmp_0 ; + assign x__h40849 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40852 : + x__h40860 : IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; - assign x__h42861 = + assign x__h42869 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42872 : + x__h42880 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6774,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61261 = + assign x__h49977 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61269 = SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; - assign x__h74813 = + assign x__h74821 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; - assign x__h7925 = + assign x__h7933 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79884 = + assign x__h79892 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; - assign x__h90635 = old_dword__h89472 & y__h90637 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90636 = + assign x__h90643 = old_dword__h89480 & y__h90645 ; + assign x_data__h30541 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90644 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89469 ; - assign y__h90637 = + mask__h89477 ; + assign y__h90645 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,141 +7009,141 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93790 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h147785 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147785 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147785 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147785 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147785 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147785 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147785 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147785 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131947 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131947 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131947 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131947 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131947 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131947 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131947 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131947 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147786 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147786 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147786 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147786 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147786 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147786 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147786 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147786 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89480 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48036 or - result__h48064 or - result__h48092 or - result__h48120 or - result__h48148 or - result__h48176 or result__h48204 or result__h48232) + result__h48044 or + result__h48072 or + result__h48100 or + result__h48128 or + result__h48156 or + result__h48184 or result__h48212 or result__h48240) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48036; + result__h48044; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48064; + result__h48072; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48092; + result__h48100; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48120; + result__h48128; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48148; + result__h48156; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48176; + result__h48184; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48204; + result__h48212; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48232; + result__h48240; endcase end always@(mmioPlatform_curReq or - result__h48277 or - result__h48305 or result__h48333 or result__h48361) + result__h48285 or + result__h48313 or result__h48341 or result__h48369) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48277; + result__h48285; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48305; + result__h48313; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48333; + result__h48341; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48361; + result__h48369; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48402 or result__h48430) + always@(mmioPlatform_curReq or result__h48410 or result__h48438) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48402; + result__h48410; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48430; + result__h48438; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase @@ -7148,103 +7156,103 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - w2__h47862 = + w2__h47870 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47862 = + w2__h47870 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w2___1__h47972 or + w2___1__h47980 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; - 2'b10: w2__h47868 = w2___1__h47972; + 2'b10: w2__h47876 = w2___1__h47980; 2'b11: - w2__h47868 = + w2__h47876 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_curReq or - result__h48556 or - result__h48583 or - result__h48610 or - result__h48637 or - result__h48664 or - result__h48691 or result__h48718 or result__h48745) + result__h48564 or + result__h48591 or + result__h48618 or + result__h48645 or + result__h48672 or + result__h48699 or result__h48726 or result__h48753) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48556; + result__h48564; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48583; + result__h48591; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48610; + result__h48618; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48637; + result__h48645; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48664; + result__h48672; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48691; + result__h48699; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48718; + result__h48726; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48745; + result__h48753; endcase end always@(mmioPlatform_curReq or - result__h48789 or - result__h48816 or result__h48843 or result__h48870) + result__h48797 or + result__h48824 or result__h48851 or result__h48878) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48789; + result__h48797; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48816; + result__h48824; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48843; + result__h48851; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48870; + result__h48878; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48910 or result__h48937) + always@(mmioPlatform_curReq or result__h48918 or result__h48945) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48910; + result__h48918; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48937; + result__h48945; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase @@ -7257,42 +7265,42 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - w1__h47861 = + w1__h47869 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47861 = + w1__h47869 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w1___1__h47971 or + w1___1__h47979 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; - 2'b10: w1__h47866 = w1___1__h47971; + 2'b10: w1__h47874 = w1___1__h47979; 2'b11: - w1__h47866 = + w1__h47874 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w17861_BITS_31_TO_0__q15 or + w17869_BITS_31_TO_0__q15 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) @@ -7304,8 +7312,8 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - { {32{w17861_BITS_31_TO_0__q15[31]}}, - w17861_BITS_31_TO_0__q15 }; + { {32{w17869_BITS_31_TO_0__q15[31]}}, + w17869_BITS_31_TO_0__q15 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; @@ -7314,7 +7322,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w27862_BITS_31_TO_0__q16 or + w27870_BITS_31_TO_0__q16 or IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) @@ -7326,116 +7334,116 @@ module mkProc(CLK, IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - { {32{w27862_BITS_31_TO_0__q16[31]}}, - w27862_BITS_31_TO_0__q16 }; + { {32{w27870_BITS_31_TO_0__q16[31]}}, + w27870_BITS_31_TO_0__q16 }; 2'b11: IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49033 or - w2__h47868 or - op_result__h48469 or - op_result__h48999 or - op_result__h49004 or - op_result__h49009 or - op_result__h49027 or op_result__h49014 or op_result__h49020) + op_result__h49041 or + w2__h47876 or + op_result__h48477 or + op_result__h49007 or + op_result__h49012 or + op_result__h49017 or + op_result__h49035 or op_result__h49022 or op_result__h49028) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - w2__h47868; + w2__h47876; 4'd1: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48469; + op_result__h48477; 4'd2: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48999; + op_result__h49007; 4'd3: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49004; + op_result__h49012; 4'd4: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49009; + op_result__h49017; 4'd5: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49027; + op_result__h49035; 4'd7: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49014; + op_result__h49022; 4'd8: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49020; + op_result__h49028; default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49033; + op_result__h49041; endcase end always@(mmioPlatform_curReq or - result__h49512 or - result__h49557 or result__h49623 or result__h49689) + result__h49520 or + result__h49565 or result__h49631 or result__h49697) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49512; + result__h49520; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49557; + result__h49565; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49623; + result__h49631; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49689; + result__h49697; default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47912 or - result__h49054 or - result__h49120 or - result__h49186 or - result__h49252 or - result__h49318 or result__h49384 or result__h49450) + result__h47920 or + result__h49062 or + result__h49128 or + result__h49194 or + result__h49260 or + result__h49326 or result__h49392 or result__h49458) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h47912; + result__h47920; 3'h1: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49054; + result__h49062; 3'h2: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49120; + result__h49128; 3'h3: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49186; + result__h49194; 3'h4: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49252; + result__h49260; 3'h5: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49318; + result__h49326; 3'h6: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49384; + result__h49392; 3'h7: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49450; + result__h49458; endcase end - always@(mmioPlatform_curReq or result__h49747 or result__h49792) + always@(mmioPlatform_curReq or result__h49755 or result__h49800) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49747; + result__h49755; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49792; + result__h49800; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase @@ -7448,15 +7456,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; 2'b01: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; 2'b10: - x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47865 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47857 = + x__h47865 = IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end @@ -7540,278 +7548,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; endcase end - always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) + always@(x__h61269 or n__read_id__h61455 or n__read_id__h61540) begin - case (x__h61261) - 1'd0: x__h61575 = n__read_id__h61447; - 1'd1: x__h61575 = n__read_id__h61532; + case (x__h61269) + 1'd0: x__h61583 = n__read_id__h61455; + 1'd1: x__h61583 = n__read_id__h61540; endcase end - always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) + always@(x__h61269 or n__read_child__h61456 or n__read_child__h61541) begin - case (x__h61261) - 1'd0: x__h61582 = n__read_child__h61448; - 1'd1: x__h61582 = n__read_child__h61533; + case (x__h61269) + 1'd0: x__h61590 = n__read_child__h61456; + 1'd1: x__h61590 = n__read_child__h61541; endcase end - always@(x__h61261 or + always@(x__h61269 or propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; 1'd1: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + CASE_x1269_0_propDstData_0_dummy2_1_read__092__ETC__q20 = propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; endcase end - always@(x__h61261 or + always@(x__h61269 or IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + CASE_x1269_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; endcase end - always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) + always@(x__h61269 or n__read_addr__h61451 or n__read_addr__h61536) begin - case (x__h61261) + case (x__h61269) 1'd0: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61443; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61451; 1'd1: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61528; + CASE_x1269_0_n__read_addr1451_1_n__read_addr15_ETC__q23 = + n__read_addr__h61536; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) + always@(x__h79892 or n__read_child__h80073 or n__read_child__h80152) begin - case (x__h79884) - 1'd0: x__h82300 = n__read_child__h80065; - 1'd1: x__h82300 = n__read_child__h80144; + case (x__h79892) + 1'd0: x__h82308 = n__read_child__h80073; + 1'd1: x__h82308 = n__read_child__h80152; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79884 or + always@(x__h79892 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9892_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79884 or + always@(x__h79892 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : 2'd0; 1'd1: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9892_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : 2'd0; endcase end - always@(x__h79884 or + always@(x__h79892 or NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; 1'd1: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + CASE_x9892_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; endcase end - always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) + always@(x__h79892 or n__read_addr__h80070 or n__read_addr__h80149) begin - case (x__h79884) + case (x__h79892) 1'd0: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80062; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80070; 1'd1: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80141; + CASE_x9892_0_n__read_addr0070_1_n__read_addr01_ETC__q34 = + n__read_addr__h80149; endcase end @@ -8227,14 +8235,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162844 = $stime; + v__h162856 = $stime; #0; end - v__h162838 = v__h162844 / 32'd10; + v__h162850 = v__h162856 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162838, + v__h162850, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8244,14 +8252,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162380 = $stime; + v__h162388 = $stime; #0; end - v__h162374 = v__h162380 / 32'd10; + v__h162382 = v__h162388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162374, + v__h162382, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8261,7 +8269,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162423); + $display("FAIL %0d", failed_testnum__h162431); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8269,14 +8277,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5520 = $stime; + v__h5528 = $stime; #0; end - v__h5514 = v__h5520 / 32'd10; + v__h5522 = v__h5528 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h5514); + $display("%0d: %m.rl_handle_read_rsps ", v__h5522); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8336,16 +8344,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5693 = $stime; + v__h5701 = $stime; #0; end - v__h5687 = v__h5693 / 32'd10; + v__h5695 = v__h5701 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h5687); + v__h5695); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8449,14 +8457,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5953 = $stime; + v__h5961 = $stime; #0; end - v__h5947 = v__h5953 / 32'd10; + v__h5955 = v__h5961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h5947); + $display("%d: %m.rl_handle_write_req: St request:", v__h5955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8626,15 +8634,15 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h8095 = $stime; + v__h8103 = $stime; #0; end - v__h8089 = v__h8095 / 32'd10; + v__h8097 = v__h8103 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h8089); + $display("%0d: ERROR: CreditCounter: overflow", v__h8097); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8684,7 +8692,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", x__h7925); + $write("'h%h", x__h7933); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8815,16 +8823,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h8310 = $stime; + v__h8318 = $stime; #0; end - v__h8304 = v__h8310 / 32'd10; + v__h8312 = v__h8318 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h8304); + v__h8312); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9030,14 +9038,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2670 = $stime; + v__h2678 = $stime; #0; end - v__h2664 = v__h2670 / 32'd10; + v__h2672 = v__h2678 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h2664); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2672); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9327,16 +9335,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4343 = $stime; + v__h4351 = $stime; #0; end - v__h4337 = v__h4343 / 32'd10; + v__h4345 = v__h4351 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h4337); + v__h4345); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9542,14 +9550,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h9480 = $stime; + v__h9488 = $stime; #0; end - v__h9474 = v__h9480 / 32'd10; + v__h9482 = v__h9488 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h9474); + $display("%0d: %m.rl_discard_write_rsp", v__h9482); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9586,15 +9594,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h9973 = $stime; + v__h9981 = $stime; #0; end - v__h9967 = v__h9973 / 32'd10; + v__h9975 = v__h9981 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h9967); + v__h9975); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9634,14 +9642,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h10136 = $stime; + v__h10144 = $stime; #0; end - v__h10130 = v__h10136 / 32'd10; + v__h10138 = v__h10144 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h10130); + v__h10138); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9828,15 +9836,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h134337 = $stime; + v__h134345 = $stime; #0; end - v__h134331 = v__h134337 / 32'd10; + v__h134339 = v__h134345 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134331, + v__h134339, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9896,15 +9904,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134504 = $stime; + v__h134512 = $stime; #0; end - v__h134498 = v__h134504 / 32'd10; + v__h134506 = v__h134512 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134498); + v__h134506); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10085,16 +10093,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136607 = $stime; + v__h136615 = $stime; #0; end - v__h136601 = v__h136607 / 32'd10; + v__h136609 = v__h136615 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136601); + v__h136609); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11292,14 +11300,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153951 = $stime; + v__h153959 = $stime; #0; end - v__h153945 = v__h153951 / 32'd10; + v__h153953 = v__h153959 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153945); + $display("%0d: ERROR: CreditCounter: overflow", v__h153953); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11323,7 +11331,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_wr_addr_awaddr__h147862); + $write("'h%h", mem_req_wr_addr_awaddr__h147870); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11411,7 +11419,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", data64__h147777); + $write("'h%h", data64__h147785); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11419,7 +11427,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", strb8__h147778); + $write("'h%h", strb8__h147786); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11445,16 +11453,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133718 = $stime; + v__h133726 = $stime; #0; end - v__h133712 = v__h133718 / 32'd10; + v__h133720 = v__h133726 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133712, + v__h133720, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11542,7 +11550,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_rd_addr_araddr__h133938); + $write("'h%h", mem_req_rd_addr_araddr__h133946); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) @@ -11623,15 +11631,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h160645 = $stime; + v__h160653 = $stime; #0; end - v__h160639 = v__h160645 / 32'd10; + v__h160647 = v__h160653 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160639, + v__h160647, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -11669,15 +11677,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161153 = $stime; + v__h161161 = $stime; #0; end - v__h161147 = v__h161153 / 32'd10; + v__h161155 = v__h161161 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161147); + v__h161155); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index 0015cc0..31227b4 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -324,7 +324,8 @@ module mkSoC_Top #(Reset dm_power_on_reset) method Action start (Fabric_Addr tohost_addr, Fabric_Addr fromhost_addr); Bool watch_tohost = (tohost_addr != 0); mem0_controller.set_watch_tohost (watch_tohost, tohost_addr); - corew.start (tohost_addr, fromhost_addr); + Bool is_running = True; + corew.start (is_running, tohost_addr, fromhost_addr); $display ("%0d: %m.method start (tohost %0h, fromhost %0h)", cur_cycle, tohost_addr, fromhost_addr); endmethod From 4e0bd06a10a9c83a0e63cde4150dd04968011241 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Thu, 2 Apr 2020 04:20:13 +0100 Subject: [PATCH 3/8] RenameStage.bsv: Fix single-step when only one instruction available If we never look at the second instruction in the FIFO from the fetch unit when successfully renaming the first, we do not end up setting debug_step and thus we will not halt on the next instruction but some time later. Instead, check for single-stepping at the end of renaming the first instruction. --- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index c15b93b..75623f1 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -843,13 +843,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); Addr fallthrough_pc = ((orig_inst[1:0] == 2'b11) ? pc + 4 : pc + 2); -`ifdef INCLUDE_GDB_CONTROL - if ((i != 0) && (csrf.dcsr_step_bit == 1'b1)) begin - stop = True; - debug_step = True; - end -`endif - // check for wrong path, if wrong path, don't process it, leave to the other rule in next cycle if(!epochManager.checkEpoch[i].check(main_epoch)) begin stop = True; @@ -1104,6 +1097,13 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); if(spec_tag matches tagged Valid .t) begin spec_bits = spec_bits | (1 << t); end + +`ifdef INCLUDE_GDB_CONTROL + if ((i == 0) && (csrf.dcsr_step_bit == 1'b1)) begin + stop = True; + debug_step = True; + end +`endif end end end From 85b4a738a92631a0bf9573f5a6748886e0b4cb2e Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 8 Apr 2020 04:21:13 +0100 Subject: [PATCH 4/8] FetchStage.bsv: Fix a mkRegU that should be a mkReg We should not use a mkRegU for rg_pending_n_items, as otherwise there is a chance the epochs for rg_pending_f32d happen to match depending on the uninitialised values. Instead ensure we always reset with no pending items. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index f848372..bd8a66b 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -390,7 +390,7 @@ module mkFetchStage(FetchStage); Ehr #(2, Maybe #(Tuple3 #(Addr, Bit #(16), Bool))) ehr_pending_straddle <- mkEhr(tagged Invalid); // Reg to hold extra instructions from Fetch3 to send to decode the next cycle Reg #(Vector #(SupSizeX2S1, Inst_Item)) rg_pending_decode <- mkReg(replicate(defaultValue)); - Reg #(SupCntX2S1) rg_pending_n_items <- mkRegU; + Reg #(SupCntX2S1) rg_pending_n_items <- mkReg(0); Reg #(Fetch3ToDecode) rg_pending_f32d <- mkRegU; // Pipeline Stage FIFOs From 10c983d101a0602c706ea00a9424879ee76beb9c Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 8 Apr 2020 04:22:49 +0100 Subject: [PATCH 5/8] FetchStage.bsv: Drop unused pc from Fetch3ToDecode Each instruction carries its own PC by this point, so it just duplicates the PC of the first item in the vector. Moreover, when including a pending straddle at the head, the PC value was not set to the previous half's, ie PC-2. We keep pred_next_pc as that's used to determine where the bundle is predicted to go next, and the duplication avoids having to dynamically index the vector based on the number of instructions fed to decode. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 3 --- 1 file changed, 3 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index bd8a66b..a10af69 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -125,7 +125,6 @@ typedef struct { } Fetch2ToFetch3 deriving(Bits, Eq, FShow); typedef struct { - Addr pc; Addr pred_next_pc; Bool mispred_first_half; Maybe#(Exception) cause; @@ -692,7 +691,6 @@ module mkFetchStage(FetchStage); if (pending_n_items == 0) begin out = Fetch3ToDecode { - pc: fetch3In.pc, pred_next_pc: pred_next_pc, mispred_first_half: mispred_first_half, cause: fetch3In.cause, @@ -742,7 +740,6 @@ module mkFetchStage(FetchStage); next_pending_n_items = truncate(n_items - fromInteger(valueOf(SupSize))); rg_pending_decode <= drop(v_items); rg_pending_f32d <= Fetch3ToDecode { - pc: v_items[valueOf(SupSize)].pc, pred_next_pc: out.pred_next_pc, mispred_first_half: False, cause: tagged Invalid, From 8455ee3f0644e0228ef8c1131fcf93c0cce84491 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 8 Apr 2020 04:47:55 +0100 Subject: [PATCH 6/8] FetchStage.bsv: Fix fav_parse_insts when pending_straddle has "even" PC Despite the name, we can end up having a pending_straddle at an "even" PC (and thus an "odd" pc_start). In this case, we would erroneously treat it as if pc_start were "even", effectively shifting all the instruction parcels along by one and duplicating the first one, since the first element of the parcels vector will be a copy of the straddle's parcel itself. Instead, we should just ignore pending_straddle when determining where to start in the parcels vector, as the two are completely independent, and no longer hard-code that the straddle is merged with element 0. This can happen if we predict that the first half of an uncompressed instruction is a taken branch. We will have the instruction bytes available, but not the prediction information, so still have to do a normal Fetch3 redirect in the same manner as an unaligned uncompressed instruction. We could perhaps special-case with a fast-path (or query the predictor directly in Fetch3), but it should hit in the TLB and L1 cache, and is probably not common enough to warrant the complexity. The FreeRTOS-based netboot loader trips up on this as it overwrites itself with the payload, and thus all the branch prediction still has many taken branch entries, most of which will not be correct. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index a10af69..9cd18ee 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -272,8 +272,8 @@ function ActionValue #(Tuple4 #(SupCntX2, orig_inst: 0, inst: 0}); Maybe #(Tuple3 #(Addr, Bit #(16), Bool)) next_straddle = tagged Invalid; - // Start parse at parcel 0/1 depending on pc lsbs and pending straddle - SupCntX2 j = ((pc_start [1:0] == 2'b00 || isValid(pending_straddle)) ? 0 : 1); + // Start parse at parcel 0/1 depending on pc lsbs. + SupCntX2 j = (pc_start [1:0] == 2'b00 ? 0 : 1); Addr pc = pc_start; Integer n_items = 0; for (Integer i = 0; i < valueOf (SupSizeX2); i = i + 1) begin @@ -289,9 +289,9 @@ function ActionValue #(Tuple4 #(SupCntX2, end pc = s_pc; inst_kind = Inst_32b; - orig_inst = { v_x16[0], s_lsbs }; + orig_inst = { v_x16[j], s_lsbs }; inst = orig_inst; - j = 1; + j = j + 1; next_pc = s_pc + 4; n_items = 1; end From a76af876a13347456304df4ab8142c7b33f7286a Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 15 Apr 2020 16:45:28 +0100 Subject: [PATCH 7/8] MMIOPlatform.bsv: Discard write response for uncached AMOs Otherwise, the next MMIO access will see the 0 from the write response instead of its response, and every subsequent access will see the previous's response, further accumulating if more uncached AMOs are performed. --- src_Core/CPU/MMIOPlatform.bsv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv index 8273326..ded8dbe 100644 --- a/src_Core/CPU/MMIOPlatform.bsv +++ b/src_Core/CPU/MMIOPlatform.bsv @@ -282,6 +282,10 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, // CRs, we record the AMO resp at processing time Reg#(Data) amoResp <- mkRegU; + // For AMOs to the fabric, we end up with read and write responses, and need + // to discard the latter. This tracks which of the two we're waiting for. + Reg#(Bool) amoWaitWriteResp <- mkRegU; + // we increment mtime periodically Reg#(Bit#(TLog#(CyclesPerTimeInc))) cycle <- mkReg(0); @@ -928,6 +932,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, let req = MMIOCRq {addr:addr, func:tagged Ld, byteEn:?, data:?}; mmio_fabric_adapter_core_side.request.put (req); state <= WaitResp; + amoWaitWriteResp <= False; if (verbosity > 0) begin $display ("MMIOPlatform.rl_mmio_to_fabric_amo_req: addr 0x%0h", addr); @@ -941,7 +946,11 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, &&& isAmo); MMIODataPRs dprs <- mmio_fabric_adapter_core_side.response.get; - if (! dprs.valid) begin + if (amoWaitWriteResp) begin + // Discard the write response; we're now ready for another request + state <= SelectReq; + end + else if (! dprs.valid) begin // Access fault let prs = tagged DataAccess dprs; cores[reqCore].pRs.enq (prs); @@ -958,7 +967,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, let prs = tagged DataAccess (MMIODataPRs { valid: True, data: ld_val }); cores[reqCore].pRs.enq (prs); - state <= SelectReq; + // Stay in WaitResp but wait to discard the write response + amoWaitWriteResp <= True; if (verbosity > 1) begin $display ("MMIO_Platform.rl_mmio_from_fabric_amo_rsp: addr 0x%0h, size %0d, amofunc %0d", From 1d12a97741572c4c68f06e5877b12efff5d6cf18 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 3 Jun 2020 18:14:58 +0100 Subject: [PATCH 8/8] CPU_Decode_C.bsv: Sync from Flute This incorporates the fix made to Piccolo and Flute to not trap on C.FLWSP/C.FLDSP when rd == 0; unlike the compressed stack pointer relative integer loads/stores, these are legal, since f0 is a real FPR rather than a constant zero. --- src_Core/CPU/CPU_Decode_C.bsv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src_Core/CPU/CPU_Decode_C.bsv b/src_Core/CPU/CPU_Decode_C.bsv index e8d8276..bc3e999 100644 --- a/src_Core/CPU/CPU_Decode_C.bsv +++ b/src_Core/CPU/CPU_Decode_C.bsv @@ -240,7 +240,6 @@ function Tuple2 #(Bool, Instr) fv_decode_C_FLWSP (MISA misa, Bit #(2) xl, Inst Bool is_legal = ((misa.c == 1'b1) && (op == opcode_C2) - && (rd != 0) && (funct3 == funct3_C_FLWSP) && (misa.f == 1'b1)); @@ -262,7 +261,6 @@ function Tuple2 #(Bool, Instr) fv_decode_C_FLDSP (MISA misa, Bit #(2) xl, Inst Bool is_legal = ((misa.c == 1'b1) && (op == opcode_C2) - && (rd != 0) && (funct3 == funct3_C_FLDSP) && (misa.d == 1'b1) && ( (xl == misa_mxl_64)