From 87a88a749b834149a583323f1c3fc3d014ab10a7 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Tue, 21 Feb 2023 10:45:56 +0000 Subject: [PATCH] Set up config for next-2-lines on miss L1I prefetcher --- builds/Resources/Include_RISCY_Config.mk | 4 ++-- src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk index 068ff52..9960a4f 100644 --- a/builds/Resources/Include_RISCY_Config.mk +++ b/builds/Resources/Include_RISCY_Config.mk @@ -45,9 +45,9 @@ SIM_LLC_ARBITER_LAT ?= # default check cache deadlock and rename error CHECK_DEADLOCK ?= true RENAME_DEBUG ?= false -INSTR_PREFETCHER_LOCATION ?= NONE +INSTR_PREFETCHER_LOCATION ?= L1 INSTR_PREFETCHER_TYPE ?= NEXT_LINE_ON_MISS -DATA_PREFETCHER_LOCATION ?= L1 +DATA_PREFETCHER_LOCATION ?= NONE DATA_PREFETCHER_TYPE ?= BLOCK # clk frequency depends on core size diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index 2f20e8f..62df04b 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -54,7 +54,7 @@ endmodule module mkNextLineOnMissPrefetcher(Prefetcher) provisos ( - NumAlias#(nextLinesOnMiss, 3), + NumAlias#(nextLinesOnMiss, 2), Alias#(rqCntT, Bit#(TLog#(TAdd#(nextLinesOnMiss, 1)))) ); Reg#(Addr) lastMissAddr <- mkReg(0);