From 88ca03f4ed1cfeb2b3d1593e0e1b02ce63f41160 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Wed, 25 Mar 2020 11:51:33 +0000 Subject: [PATCH] Pipe through an exception to the Reorder buffer from each execute pipe. Also move to SetAddrUnsafe, as is traditional for setting the address of PCC where we do proper checks on branches so we really only have the possibility of executing off the end of the length, and therefore cannot become unrepresentable. --- .../procs/RV64G_OOO/AluExePipeline.bsv | 2 ++ .../procs/RV64G_OOO/FpuMulDivExePipeline.bsv | 4 +-- .../procs/RV64G_OOO/MemExePipeline.bsv | 3 +- .../RISCY_OOO/procs/lib/ReorderBuffer.bsv | 28 ++++++++++++------- 4 files changed, 24 insertions(+), 13 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index a5b9e4a..438d0da 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -154,6 +154,7 @@ interface AluExeInput; Data dst_data, Maybe#(Data) csrData, ControlFlow cf, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -346,6 +347,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); x.data, x.csrData, x.controlFlow, + tagged Invalid, cast(inIfc.scaprf_rd(SCR_PCC)) `ifdef RVFI , x.traceBundle diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv index 413e6cc..0622d4c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv @@ -96,7 +96,7 @@ interface FpuMulDivExeInput; // Special Capability Register file. method CapReg scaprf_rd(SCR csr); // ROB - method Action rob_setExecuted(InstTag t, Data dst_data, Bit#(5) fflags, CapPipe pcc); + method Action rob_setExecuted(InstTag t, Data dst_data, Bit#(5) fflags, Maybe#(Exception) cast, CapPipe pcc); // global broadcast methods // write reg file & set both conservative and aggressive sb & wake up inst @@ -233,7 +233,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); inIfc.writeRegFile(valid_dst.indx, data); end // update the instruction in the reorder buffer. - inIfc.rob_setExecuted(tag, data, fflags, cast(inIfc.scaprf_rd(SCR_PCC))); + inIfc.rob_setExecuted(tag, data, fflags, tagged Invalid, cast(inIfc.scaprf_rd(SCR_PCC))); // since FPU op has no spec tag, this doFinish rule is ordered before // other rules that calls incorrectSpec, and BSV compiler creates // cycles in scheduling. We manually creates a conflict between this diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index a8488e1..c06e51c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -161,7 +161,7 @@ interface MemExeInput; Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done, - CapPipe pcc + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb `endif @@ -562,6 +562,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); Bool non_mmio_st_done = !isValid(cause) && !isMMIO && x.mem_func == St; inIfc.rob_setExecuted_doFinishMem(x.tag, x.vaddr, store_data, store_data_BE, access_at_commit, non_mmio_st_done, + tagged Invalid, cast(inIfc.scaprf_rd(SCR_PCC)) `ifdef RVFI , ExtraTraceBundle{ diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index fe8ca9d..5ed90d6 100644 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -114,6 +114,7 @@ interface Row_setExecuted_doFinishAlu; Data dst_data, Maybe#(Data) csrData, ControlFlow cf, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -122,7 +123,7 @@ interface Row_setExecuted_doFinishAlu; endinterface interface Row_setExecuted_doFinishFpuMulDiv; - method Action set(Data dst_data, Bit#(5) fflags, CapPipe pcc); + method Action set(Data dst_data, Bit#(5) fflags, Maybe#(Exception) cause, CapPipe pcc); endinterface interface ReorderBufferRowEhr#(numeric type aluExeNum, numeric type fpuMulDivExeNum); @@ -147,6 +148,7 @@ interface ReorderBufferRowEhr#(numeric type aluExeNum, numeric type fpuMulDivExe method Action setExecuted_doFinishMem(Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -274,6 +276,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p Data dst_data, Maybe#(Data) csrData, ControlFlow cf, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -291,7 +294,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p else begin ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= PPC (setAddr(almightyCap, cf.nextPc).value); end - pc[pc_finishAlu_port(i)] <= setAddr(pcc, getAddr(pc[pc_finishAlu_port(i)])).value; + pc[pc_finishAlu_port(i)] <= setAddrUnsafe(pcc, getAddr(pc[pc_finishAlu_port(i)])); trap[trap_finishAlu_port(i)] <= trap[trap_finishAlu_port(i)]; tval[trap_finishAlu_port(i)] <= tval[trap_finishAlu_port(i)]; `ifdef RVFI @@ -306,13 +309,13 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p Vector#(fpuMulDivExeNum, Row_setExecuted_doFinishFpuMulDiv) fpuMulDivExe; for(Integer i = 0; i < valueof(fpuMulDivExeNum); i = i+1) begin fpuMulDivExe[i] = (interface Row_setExecuted_doFinishFpuMulDiv; - method Action set(Data dst_data, Bit#(5) new_fflags, CapPipe pcc); + method Action set(Data dst_data, Bit#(5) new_fflags, Maybe#(Exception) cause, CapPipe pcc); // inst is done rob_inst_state[state_finishFpuMulDiv_port(i)] <= Executed; rg_dst_data <= dst_data; // update fflags fflags[fflags_finishFpuMulDiv_port(i)] <= new_fflags; - //pc[pc_finishFpuMulDiv_port(i)] <= setAddr(pcc, getAddr(pc[pc_finishFpuMulDiv_port(i)])).value; //XXX add pcc checks on FPU instructions + //pc[pc_finishFpuMulDiv_port(i)] <= setAddrUnsafe(pcc, getAddr(pc[pc_finishFpuMulDiv_port(i)])).value; //XXX add pcc checks on FPU instructions endmethod endinterface); end @@ -328,6 +331,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p method Action setExecuted_doFinishMem(Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -355,7 +359,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p memAccessAtCommit[accessCom_finishMem_port] <= access_at_commit; // udpate non mmio st nonMMIOStDone[nonMMIOSt_finishMem_port] <= non_mmio_st_done; - pc[pc_finishMem_port] <= setAddr(pcc, getAddr(pc[pc_finishMem_port])).value; + pc[pc_finishMem_port] <= setAddrUnsafe(pcc, getAddr(pc[pc_finishMem_port])); endmethod `ifdef INCLUDE_TANDEM_VERIF @@ -541,6 +545,7 @@ interface ROB_setExecuted_doFinishAlu; Data dst_data, Maybe#(Data) csrData, ControlFlow cf, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -549,7 +554,7 @@ interface ROB_setExecuted_doFinishAlu; endinterface interface ROB_setExecuted_doFinishFpuMulDiv; - method Action set(InstTag x, Data dst_data, Bit#(5) fflags, CapPipe pcc); + method Action set(InstTag x, Data dst_data, Bit#(5) fflags, Maybe#(Exception) cause, CapPipe pcc); endinterface interface ROB_getOrigPC; @@ -586,6 +591,7 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -1079,6 +1085,7 @@ module mkSupReorderBuffer#( Data dst_data, Maybe#(Data) csrData, ControlFlow cf, + Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , ExtraTraceBundle tb @@ -1090,6 +1097,7 @@ module mkSupReorderBuffer#( dst_data, csrData, cf, + cause, pcc `ifdef RVFI , tb @@ -1103,11 +1111,11 @@ module mkSupReorderBuffer#( for(Integer i = 0; i < valueof(fpuMulDivExeNum); i = i+1) begin fpuMulDivSetExeIfc[i] = (interface ROB_setExecuted_doFinishFpuMulDiv; method Action set( - InstTag x, Data dst_data, Bit#(5) fflags, CapPipe pcc + InstTag x, Data dst_data, Bit#(5) fflags, Maybe#(Exception) cause, CapPipe pcc ) if( all(id, readVReg(setExeFpuMulDiv_SB_enq)) // ordering: < enq ); - row[x.way][x.ptr].setExecuted_doFinishFpuMulDiv[i].set(dst_data, fflags, pcc); + row[x.way][x.ptr].setExecuted_doFinishFpuMulDiv[i].set(dst_data, fflags, cause, pcc); endmethod endinterface); end @@ -1184,7 +1192,7 @@ module mkSupReorderBuffer#( method Action setExecuted_doFinishMem( InstTag x, Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, - Bool non_mmio_st_done, CapPipe pcc + Bool non_mmio_st_done, Maybe#(Exception) cause, CapPipe pcc `ifdef RVFI , tb `endif @@ -1194,7 +1202,7 @@ module mkSupReorderBuffer#( row[x.way][x.ptr].setExecuted_doFinishMem(vaddr, store_data, store_data_BE, access_at_commit, non_mmio_st_done, - pcc + cause, pcc `ifdef RVFI , tb `endif