From 8990ae56ed704d6ef101290e44699c272802569e Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Fri, 5 Apr 2024 10:44:50 +0100 Subject: [PATCH] Revert "Potential workaround for issue with vcu118 memory bus error." This reverts commit f86ea0203d9e1f96e787efdabe661aac61568c24. --- src_SSITH_P3/src_BSV/P3_Core.bsv | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 5517aae..dc029bf 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -340,13 +340,9 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ `endif - // Work around issue that is not understood with multiple outstanding - // requests in VCU118 GFE system. - let master0_inOrder <- mkAXI4SingleIDMaster(master_0_delay.master); - // ================================================================ // INTERFACE - let master0_sig <- toAXI4_Master_Sig (master0_inOrder); + let master0_sig <- toAXI4_Master_Sig (master_0_delay.master); let master1_sig <- toAXI4_Master_Sig (master_1_delay.master); // ---------------------------------------------------------------- // Core CPU interfaces