From 89f0c3a45fcbb65f47f611e6dbb7f8487190037f Mon Sep 17 00:00:00 2001
From: jon <>
Date: Fri, 5 Mar 2021 12:11:49 +0000
Subject: [PATCH] Reduce verbosity.

---
 src_Core/CPU/MMIOPlatform.bsv                         | 2 +-
 src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv
index e3c4194..667fb9c 100644
--- a/src_Core/CPU/MMIOPlatform.bsv
+++ b/src_Core/CPU/MMIOPlatform.bsv
@@ -162,7 +162,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
 
    provisos (Bits #(Data, 64)); // this module assumes Data is 64-bit wide
 
-   Integer verbosity = 2;
+   Integer verbosity = 0;
 
    // mtimecmp
    Vector#(CoreNum, Reg#(Data)) mtimecmp <- replicateM(mkReg(0));
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index 39ceb05..752bb49 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -239,7 +239,7 @@ interface MemExePipeline;
 endinterface
 
 module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
-    Bool verbose = True;
+    Bool verbose = False;
 
     // we change cache request in case of single core, becaues our MSI protocol
     // is not good with single core