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Revert "initial commit, test compiled and run sucessfully"

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This reverts commit d025278195.
This commit is contained in:
Yuecheng-CAM
2025-06-01 18:17:24 +01:00
parent d025278195
commit 8af3b2e85a
22 changed files with 3 additions and 123434 deletions
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10
src_Core/RISCY_OOO/coherence/src/CCTypes.bsv
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@@ -218,16 +218,6 @@ interface L1ProcResp#(type idT);
method ActionValue#(Tuple2#(LineByteEn, Line)) respSt(idT id);
method Action evict(LineAddr a); // called when cache line is evicted
endinterface
// General replacement interface
interface ReplacePolicy#(numeric type wayNum, type repInfoT);
method repInfoT initRepInfo;
method Maybe#(Bit#(TLog#(wayNum))) getReplaceWay(
Vector#(wayNum, Bool) unlocked,
Vector#(wayNum, Bool) invalid,
repInfoT repInfo
);
method repInfoT updateRepInfo(repInfoT old, Bit#(TLog#(wayNum)) way);
endinterface
// RISCV-specific store-cond return values
typedef 0 ScSuccVal;

180
src_Core/RISCY_OOO/coherence/src/L1LL.bsv
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@@ -1,180 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Types::*;
import CacheUtils::*;
import CCTypes::*;
import L1Wrapper::*;
import LLWrapper::*;
import CrossBar::*;
import Vector::*;
import GetPut::*;
import ClientServer::*;
import L1Bank::*;
import LLBank::*;
import L1LLSizes::*;
import Connectable::*;
export L1LL(..);
export mkL1LL;
// LLChildNum == L1Num
// XXX no LLC banking: LgLLBankNum = 0
typedef TExp#(LgLLBankNum) LLNum;
typedef Bit#(LgLLBankNum) LLIdx;
typedef Bit#(TLog#(L1Num)) L1Idx;
typedef CRqMsg#(L1Way, void) CRqFromL1;
typedef CRqMsg#(LLCRqId, LLChild) CRqToLL;
typedef CRsMsg#(void) CRsFromL1;
typedef CRsMsg#(LLChild) CRsToLL;
typedef PRqRsMsg#(LLCRqId, LLChild) PRqRsFromLL;
typedef PRqRsMsg#(L1Way, void) PRqRsToL1;
typedef 1 XBarSrcDelay;
typedef 2 XBarDstDelay;
// cross bar for L1 cRq to LL
typedef CrossBar#(L1Num, XBarSrcDelay, CRqFromL1, LLNum, XBarDstDelay, CRqToLL) L1CRqToLLXBar;
(* synthesize *)
module mkL1CRqToLLXBar(L1CRqToLLXBar);
function XBarDstInfo#(LLIdx, CRqToLL) getL1CRqDstInfo(L1Idx whichL1, CRqFromL1 rq);
return XBarDstInfo {
idx: 0,
data: CRqMsg {
addr: rq.addr,
fromState: rq.fromState,
toState: rq.toState,
canUpToE: rq.canUpToE,
id: rq.id,
child: whichL1
}
};
endfunction
let m <- mkCrossBar(getL1CRqDstInfo);
return m;
endmodule
// cross bar for L1 cRs to LL
typedef CrossBar#(L1Num, XBarSrcDelay, CRsFromL1, LLNum, XBarDstDelay, CRsToLL) L1CRsToLLXBar;
(* synthesize *)
module mkL1CRsToLLXBar(L1CRsToLLXBar);
function XBarDstInfo#(LLIdx, CRsToLL) getL1CRsDstInfo(L1Idx whichL1, CRsFromL1 rs);
return XBarDstInfo {
idx: 0,
data: CRsMsg {
addr: rs.addr,
toState: rs.toState,
data: rs.data,
child: whichL1
}
};
endfunction
let m <- mkCrossBar(getL1CRsDstInfo);
return m;
endmodule
// cross bar for LL pRqRs to L1
typedef CrossBar#(LLNum, XBarSrcDelay, PRqRsFromLL, L1Num, XBarDstDelay, PRqRsToL1) LLPRqRsToL1XBar;
(* synthesize *)
module mkLLPRqRsToL1XBar(LLPRqRsToL1XBar);
function XBarDstInfo#(L1Idx, PRqRsToL1) getLLPRqRsDstInfo(LLIdx whichLL, PRqRsFromLL msg);
return (case(msg) matches
tagged PRq .rq: return XBarDstInfo {
idx: rq.child,
data: PRq (PRqMsg {
addr: rq.addr,
toState: rq.toState,
child: ?
})
};
tagged PRs .rs: return XBarDstInfo {
idx: rs.child,
data: PRs (PRsMsg {
addr: rs.addr,
toState: rs.toState,
child: ?,
data: rs.data,
id: rs.id
})
};
endcase);
endfunction
let m <- mkCrossBar(getLLPRqRsDstInfo);
return m;
endmodule
// L1 + LL
// LLC port mapping:
// 0 ~ L1DNum -1 -- D$ 0~L1DNum-1
// L1Dnum ~ L1Num -- I$ 0~L1INum-1
interface L1LL;
interface Vector#(L1DNum, L1ProcReq#(ProcRqId)) dReq;
interface Vector#(L1INum, InstServer#(L1ISupSz)) inst;
interface DmaServer#(DmaRqId) dma;
interface MemFifoClient#(LdMemRqId#(LLCRqMshrIdx), void) to_mem;
endinterface
module mkL1LL#(Vector#(L1DNum, L1ProcResp#(ProcRqId)) procResp)(L1LL) provisos(
Add#(0, 0, LgLLBankNum),
Add#(1, 0, LLNum)
);
Vector#(L1DNum, L1CacheWrapper) dc = ?;
for(Integer i = 0; i < valueof(L1DNum); i = i+1) begin
dc[i] <- mkL1CacheWrapper(procResp[i]);
end
Vector#(LLNum, LLBankWrapper) llc <- replicateM(mkLLBankWrapper);
let cRqXBar <- mkL1CRqToLLXBar;
let cRsXBar <- mkL1CRsToLLXBar;
let pXBar <- mkLLPRqRsToL1XBar;
for(Integer i = 0; i < valueOf(L1DNum); i = i+1) begin
mkConnection(cRqXBar.srcIfc[i], dc[i].to_parent.rqToP);
mkConnection(cRsXBar.srcIfc[i], dc[i].to_parent.rsToP);
mkConnection(pXBar.dstIfc[i], dc[i].to_parent.fromP);
end
for(Integer i = 0; i < valueOf(LLNum); i = i+1) begin
mkConnection(cRqXBar.dstIfc[i], llc[i].to_child.rqFromC);
mkConnection(cRsXBar.dstIfc[i], llc[i].to_child.rsFromC);
mkConnection(pXBar.srcIfc[i], llc[i].to_child.toC);
end
function L1ProcReq#(ProcRqId) getDReqIfc(L1CacheWrapper ifc);
return ifc.procReq;
endfunction
interface dReq = map(getDReqIfc, dc);
interface dma = llc[0].dma;
interface to_mem = llc[0].to_mem;
endmodule

86
src_Core/RISCY_OOO/coherence/src/L1LLSizes.bsv
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@@ -1,86 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Types::*;
import Vector::*;
import CCTypes::*;
// cache size = bank num * way num * set num * 64B
// L1 connect to LL
// 32KB L1
typedef 1 L1DNum;
typedef 0 L1INum;
typedef TAdd#(L1DNum, L1INum) L1Num;
typedef 4 L1WayNum;
typedef Bit#(TLog#(L1WayNum)) L1Way;
typedef 0 LgL1BankNum;
typedef 7 LgL1SetNum;
typedef TExp#(LgL1BankNum) L1BankNum;
typedef Bit#(LgL1BankNum) L1BankId;
typedef LgL1SetNum L1IndexSz;
typedef Bit#(L1IndexSz) L1Index;
typedef GetTagSz#(LgL1BankNum, LgL1SetNum) L1TagSz;
typedef Bit#(L1TagSz) L1Tag;
typedef 0 LgIBankNum;
typedef 7 LgISetNum;
typedef Bit#(LgIBankNum) IBankId;
typedef LgISetNum IIndexSz;
typedef Bit#(IIndexSz) IIndex;
typedef GetTagSz#(LgIBankNum, LgISetNum) ITagSz;
typedef Bit#(ITagSz) ITag;
typedef 4 L1CRqNum;
typedef 2 L1PRqNum;
typedef Bit#(TLog#(L1CRqNum)) L1CRqMshrIdx;
typedef Bit#(TLog#(L1PRqNum)) L1PRqMshrIdx;
typedef Bit#(32) ProcRqId;
typedef 4 L1ISupSz;
typedef Vector#(L1ISupSz, Maybe#(Instruction)) L1InstResult;
// Last-Level: 512KB per bank
typedef 16 LLWayNum;
typedef 0 LgLLBankNum;
typedef 9 LgLLSetNum;
typedef Bit#(LgLLBankNum) LLBankId;
typedef LgLLSetNum LLIndexSz;
typedef Bit#(LLIndexSz) LLIndex;
typedef GetTagSz#(LgLLBankNum, LgLLSetNum) LLTagSz;
typedef Bit#(LLTagSz) LLTag;
typedef Bit#(TLog#(LLWayNum)) LLWay;
typedef 16 LLCRqNum;
typedef Bit#(TLog#(LLCRqNum)) LLCRqMshrIdx;
typedef L1Num LLChildNum;
typedef Bit#(TLog#(LLChildNum)) LLChild;
typedef L1Way LLCRqId;
typedef Bit#(32) DmaRqId;

78
src_Core/RISCY_OOO/coherence/src/L1Wrapper.bsv
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@@ -1,78 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import CacheUtils::*;
import Types::*;
import CCTypes::*;
import L1Pipe::*;
import L1CRqMshr::*;
import L1PRqMshr::*;
import L1LLSizes::*;
import L1Bank::*;
import RWBramCore::*;
import LruReplace::*;
import L1CoCache::*;
(* synthesize *)
module mkL1CRqMshrWrapper(
L1CRqMshr#(L1CRqNum, L1Index,L1Way, L1Tag, ProcRq#(ProcRqId))
);
function Addr getAddrFromReq(ProcRq#(ProcRqId) r);
return r.addr;
endfunction
function L1Index getIndexFromAddr(Addr addr);
return truncate(addr >> (valueOf(LgLineSzBytes) + valueOf(LgDBankNum)));
endfunction
function Bool isReqToExclusive(ProcRq#(ProcRqId) r);
return r.toState >= E;
endfunction
let m <- mkL1CRqMshr(getAddrFromReq,getIndexFromAddr);
return m;
endmodule
(* synthesize *)
module mkL1PRqMshrWrapper(
L1PRqMshr#(L1PRqNum)
);
let m <- mkL1PRqMshr;
return m;
endmodule
typedef TrueLruRepInfo#(L1WayNum) L1RepInfo;
(* synthesize *)
module mkL1Pipeline(
L1Pipe#(LgL1BankNum, L1WayNum, L1Index, L1Tag, L1CRqMshrIdx, L1PRqMshrIdx)
);
RWBramCore#(L1Index, L1RepInfo) repRam <- mkRWBramCore;
ReplacePolicy#(L1WayNum, L1RepInfo) repPolicy <- mkTrueLruReplace;
let m <- mkL1Pipe;
return m;
endmodule
typedef L1Bank#(LgL1BankNum, L1WayNum, L1IndexSz, L1TagSz, L1CRqNum, L1PRqNum, ProcRqId) L1CacheWrapper;
module mkL1CacheWrapper#(L1ProcResp#(ProcRqId) procResp)(L1CacheWrapper);
let m <- mkL1Cache(mkL1CRqMshrWrapper, mkL1PRqMshrWrapper, mkL1Pipeline, procResp);
return m;
endmodule

8
src_Core/RISCY_OOO/coherence/src/LLBank.bsv
View File

@@ -191,7 +191,7 @@ module mkLLBank#(
Add#(TLog#(TDiv#(childNum,2)), c__, TLog#(childNum))
);
Bool verbose = True;
Bool verbose = False;
LLCRqMshr#(cRqNum, wayT, tagT, Vector#(childNum, DirPend), cRqT) cRqMshr <- mkLLMshr;
@@ -1012,7 +1012,6 @@ endfunction
line: ram.line // use line in ram
}, True); // hit, so update rep info
if (!cRqIsPrefetch[n]) begin
/*
if (cRq.child[0] == 1) begin
instrPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, HIT);
@@ -1021,7 +1020,6 @@ endfunction
dataPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, HIT);
end
*/
end
endaction
endfunction
@@ -1219,7 +1217,6 @@ endfunction
line: ram.line
}, False);
if (!cRqIsPrefetch[n]) begin
/*
if (cRq.child[0] == 1) begin
instrPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
@@ -1228,7 +1225,6 @@ endfunction
dataPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
end
*/
end
endaction
endfunction
@@ -1299,7 +1295,6 @@ endfunction
});
end
if (!cRqIsPrefetch[n]) begin
/*
if (cRq.child[0] == 1) begin
instrPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
@@ -1308,7 +1303,6 @@ endfunction
dataPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
end
*/
end
endaction
endfunction

61
src_Core/RISCY_OOO/coherence/src/LLWrapper.bsv
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@@ -1,61 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Vector::*;
import CacheUtils::*;
import Types::*;
import CCTypes::*;
import LLPipe::*;
import LLCRqMshr::*;
import LLBank::*;
import L1LLSizes::*;
(* synthesize *)
module mkLastLvCRqMshr(
LLCRqMshr#(LLCRqNum, LLWay, LLTag, Vector#(LLChildNum, DirPend), cRqT)
) provisos(
Alias#(cRqT, LLRq#(LLCRqId, DmaRqId, LLChild))
);
function Addr getAddr(cRqT r) = r.addr;
let m <- mkLLCRqMshr(getAddr, getNeedReqChild, getDirPendInitVal);
return m;
endmodule
(* synthesize *)
module mkLLPipeline(
LLPipe#(LgLLBankNum, LLChildNum, LLWayNum, LLIndex, LLTag, LLCRqMshrIdx)
);
let m <- mkLLPipe;
return m;
endmodule
typedef LLBank#(LgLLBankNum, LLChildNum, LLWayNum, LLIndexSz, LLTagSz, LLCRqNum, LLCRqId, DmaRqId) LLBankWrapper;
(* synthesize *)
module mkLLBankWrapper(LLBankWrapper);
// resp load req with E when it fills cache line from mem
function Bool respE(Bool fromMem) = fromMem;
let m <- mkLLBank(mkLastLvCRqMshr, mkLLPipeline, respE);
return m;
endmodule

92
src_Core/RISCY_OOO/coherence/src/LruReplace.bsv
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@@ -1,92 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Vector::*;
import CCTypes::*;
import RWBramCore::*;
// True LRU
// vec[0] -- MRU, vec[wayNum-1] -- LRU
typedef Vector#(wayNum, Bit#(TLog#(wayNum))) TrueLruRepInfo#(numeric type wayNum);
module mkTrueLruReplace(ReplacePolicy#(wayNum, TrueLruRepInfo#(wayNum))) provisos(
Add#(1, a__, wayNum),
Alias#(wayT, Bit#(TLog#(wayNum))),
Alias#(repT, TrueLruRepInfo#(wayNum))
);
// rand rep as fall back if LRU way is locked
Reg#(wayT) randWay <- mkReg(0);
rule tick;
randWay <= randWay == fromInteger(valueOf(wayNum) - 1) ? 0 : randWay + 1;
endrule
method repT initRepInfo;
return genWith(fromInteger);
endmethod
method Maybe#(wayT) getReplaceWay(
Vector#(wayNum, Bool) unlocked,
Vector#(wayNum, Bool) invalid,
repT repInfo
);
// first search for invalid & unlocked way
function Bool isInvUnlock(Integer i);
return unlocked[i] && invalid[i];
endfunction
Vector#(wayNum, Integer) idxVec = genVector;
Maybe#(wayT) repWay = searchIndex(isInvUnlock, idxVec);
if(!isValid(repWay)) begin
// check whether LRU way is unlocked
wayT lruWay = repInfo[valueof(wayNum) - 1];
if(unlocked[lruWay]) begin
repWay = Valid (lruWay);
end
else begin
// check if a random way is unlocked
if(unlocked[randWay]) begin
repWay = Valid (randWay);
end
else begin
// just find a unlocked way
repWay = searchIndex(id, unlocked);
end
end
end
return repWay;
endmethod
method repT updateRepInfo(repT repInfo, wayT hitWay);
repT newInfo = repInfo;
// find which vector index contains hitWay, and shift rep info
if(findElem(hitWay, repInfo) matches tagged Valid .idx) begin
newInfo[0] = hitWay;
for(Integer i = 0; i < valueof(wayNum) - 1; i = i+1) begin
if(fromInteger(i) < idx) begin
newInfo[i + 1] = repInfo[i];
end
end
end
return newInfo;
endmethod
endmodule

4
src_Core/RISCY_OOO/coherence/tests/L1LL/.gitignore vendored
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@@ -1,4 +0,0 @@
build*
sim*
*.log
log

90
src_Core/RISCY_OOO/coherence/tests/L1LL/Makefile
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@@ -1,90 +0,0 @@
# Copyright (c) 2017 Massachusetts Institute of Technology
#
# Permission is hereby granted, free of charge, to any person
# obtaining a copy of this software and associated documentation
# files (the "Software"), to deal in the Software without
# restriction, including without limitation the rights to use, copy,
# modify, merge, publish, distribute, sublicense, and/or sell copies
# of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
BLUESTUFFDIR ?= $(CURDIR)/../../../../../libs/BlueStuff
include $(BLUESTUFFDIR)/bluestuff.inc.mk
EXTPATH = -p +:../../../../../src_bsc_lib_RTL:../L1LL:../include:../../../../ISA:../../../../CPU:../../../../Core:../../../../BSV_Additional_Libs:../../../../../libs/BlueStuff/BlueBasics:../../../../../libs/BlueStuff/BlueAXI4/AXI4:../../../../../libs/BlueStuff/BlueAXI4:../../../../../libs/:TagController/TagController:../../../../../src_Testbench/SoC:../../../../../libs/cheri-cap-lib:../../../procs/lib:../../../procs/RV64G_OOO:../../src
CFILES = ../include/atomic_mem.c
TARGETS = CHERIL1LL
STORE_PREFETCH ?= false
MACROS = -D CCSIZES_FILE=\"L1LLSizes.bsv\" \
-D NO_REQ_STALL -D NO_DMA_REQ_STALL \
-D BSIM \
-D NUM_CORES=1 \
-D sizeSup=1 \
-D NUM_EPOCHS=1 \
-D NUM_SPEC_TAGS=1 \
-D ROB_SIZE=1 \
-D SB_SIZE=1 \
-D LDQ_SIZE=1 \
-D STQ_SIZE=1 \
-D LOG_LLC_WAYS=4 \
-D RV64 \
-D LOG_L1_WAYS=2 \
-D LOG_L1_LINES=9 \
-D LOG_LLC_LINES=8 \
-D verbose
ifeq ($(STORE_PREFETCH),true)
MACROS += -D STORE_PREFETCH -D DEBUG_STORE_PREFETCH
endif
LINK_JOBS ?= 8
$(TARGETS): %:
mkdir -p build$@Dir
bsc -u -sim \
-bdir build$@Dir \
-info-dir build$@Dir \
-simdir build$@Dir \
-vdir build$@Dir \
+RTS -K500M -RTS \
-steps-warn-interval 1000000 \
-show-schedule \
-aggressive-conditions \
-check-assert \
$(MACROS) \
$(EXTPATH) Tb$@.bsv
grep -n "Blocking rules" build$@Dir/mkTb$@.sched | sed '/(none)/d'
bsc -sim -e mkTb$@ \
-bdir build$@Dir \
-info-dir build$@Dir \
-simdir build$@Dir \
+RTS -K500M -RTS \
-Xc -std=c99 \
-Xc++ -D_GLIBCXX_USE_CXX11_ABI=1 \
-parallel-sim-link $(LINK_JOBS) \
-o sim$@ build$@Dir/*.ba $(CFILES)
all: $(TARGETS)
clean:
rm -rf build*Dir sim* log *.log ../include/*.o
.PHONY: clean all $(TARGETS)
.DEFAULT_GOAL := all

22
src_Core/RISCY_OOO/coherence/tests/L1LL/ProcConfiglocal.bsv
View File

@@ -1,22 +0,0 @@
// just to make things compile
`define rv64 True
`define m True
`define a True
`define f True
`define d True
`define sizeSup 1
`define NUM_CORES 1
`define NUM_EPOCHS 1
`define NUM_SPEC_TAGS 1
`define ROB_SIZE 1
`define LDQ_SIZE 1
`define STQ_SIZE 1
`define SB_SIZE 1
`define DRAM_MAX_REQS 1
`define DRAM_MAX_READS 1
`define DRAM_MAX_WRITES 1
`define DRAM_LATENCY 1
`define LOG_BOOT_ROM_BYTES 12
// used for checking deadlock
`define LOG_DEADLOCK_CYCLES 26

384
src_Core/RISCY_OOO/coherence/tests/L1LL/TbCHERIL1LL.bsv
View File

@@ -1,384 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Types::*;
import MemoryTypes::*;
import Amo::*;
import CacheUtils::*;
import CCTypes::*;
import FShow::*;
import Randomizable::*;
import Vector::*;
import FIFO::*;
import RegFile::*;
import Connectable::*;
import GetPut::*;
import ClientServer::*;
//import AtomicMem::*;
import DelayMemTypes::*;
import IdealDelayMem::*;
import Printf::*;
import ConfigReg::*;
import L1LLSizes::*;
import L1LL::*;
// FIXME assume no banking
// number of reqs (tests) per core
typedef 1 TestNum;
typedef Bit#(TLog#(TestNum)) TestId;
typedef Bit#(TLog#(TAdd#(TestNum, 1))) TestCnt;
typedef TDiv#(TestNum, 1) TestPrintNum;
// number of DMA reqs
typedef 1 DmaTestNum; //TMul#(TestNum, L1Num) DmaTestNum; // To reduce sc failure
typedef Bit#(TLog#(DmaTestNum)) DmaTestId;
typedef Bit#(TLog#(TAdd#(DmaTestNum, 1))) DmaTestCnt;
typedef TDiv#(DmaTestNum, 1) DmaTestPrintNum;
// memory delay
typedef 30 MemDelay;
// time out
typedef 10000 MaxTimeOut;
typedef Bit#(TLog#(MaxTimeOut)) TimeOutCnt;
// test index, tag, data offset choices
typedef TMul#(4, LLWayNum) TagNum;
typedef 2 IndexNum;
typedef LLTag LLCTag;
typedef LLIndex LLCIndex;
function Addr getAddr(LLCTag tag, LLCIndex index, LineDataOffset sel);
DataBytesOffset off = 0;
return {tag, index, sel, off};
endfunction
/*
function Addr getInstAddr(LLCTag tag, LLCIndex index, LineInstOffset sel);
Bit#(TLog#(TDiv#(InstSz, 8))) off = 0;
return {tag, index, sel, off};
endfunction
*/
// memory size for testing
typedef TAdd#(TSub#(AddrSz, SizeOf#(LLCTag)), TLog#(TagNum)) LgTestMemSzBytes;
// req/resp to/from memory system
typedef enum {
Ld, St, Lr, Sc, Amo
`ifdef STORE_PREFETCH
, StPrefetch
`endif
} MemTestOp deriving(Bits, Eq, FShow, Bounded);
function MemOp getMemOp(MemTestOp op);
case(op)
Ld: return Ld;
St: return St;
Lr: return Lr;
Sc: return Sc;
Amo: return Amo;
`ifdef STORE_PREFETCH
StPrefetch: return StPrefetch;
`endif
default: return ?;
endcase
endfunction
function Msi getToState(MemTestOp op);
case(op)
Ld: return S;
Lr: return E;
St, Sc, Amo: return M;
`ifdef STORE_PREFETCH
StPrefetch: return E;
`endif
default: return ?;
endcase
endfunction
typedef struct {
TestId id;
MemTestOp op;
Addr addr;
MemDataByteEn byteEn; // for Sc
MemTaggedData data; // for Sc/Amo
LineByteEn lineBE; // for St
Line line; // for St
AmoInst amoInst; // for Amo
} MemTestReq deriving(Bits, Eq, FShow);
typedef enum {
Ld, St, LrScAmo
`ifdef STORE_PREFETCH
, StPrefetch
`endif
} MemRespType deriving(Bits, Eq, FShow);
typedef struct {
MemRespType t;
TestId id;
MemTaggedData data;
} MemTestResp deriving(Bits, Eq, FShow);
function MemRespType getMemRespType(MemTestOp op);
case(op)
Ld: return Ld;
St: return St;
Lr, Sc, Amo: return LrScAmo;
`ifdef STORE_PREFETCH
StPrefetch: return StPrefetch;
`endif
default: return ?;
endcase
endfunction
// random req stall
typedef Bit#(2) ReqStall;
function Bool getReqStall(ReqStall x);
`ifdef NO_REQ_STALL
return False;
`else
return x == 0;
`endif
endfunction
function Bool getDmaReqStall(ReqStall x);
`ifdef NO_DMA_REQ_STALL
return False;
`else
return x == 0;
`endif
endfunction
// update cache line
// test FSM
typedef enum {InitTable, InitAddr, Idle, Process, Done} TestFSM deriving(Bits, Eq, FShow);
(* synthesize *)
module mkTbCHERIL1LL(Empty);
// Reference
//AtomicMem#(LgTestMemSzBytes) refMem <- mkAtomicMem;
Reg#(Vector#(L1DNum, Vector#(L1BankNum, Maybe#(LineAddr)))) refLink <- mkReg(replicate(replicate(Invalid)));
// record req
// D$
Vector#(L1DNum, RegFile#(TestId, Maybe#(MemTestReq))) dcReqTable <- replicateM(mkRegFileFull);
Vector#(L1DNum, Randomize#(ReqStall)) randDCReqStall <- replicateM(mkGenericRandomizer);
Vector#(L1DNum, Randomize#(MemTestOp)) randDCOp <- replicateM(mkConstrainedRandomizer(minBound, maxBound));
Vector#(L1DNum, Randomize#(LLCTag)) randDCTag <- replicateM(mkConstrainedRandomizer(0, fromInteger(valueOf(TagNum) - 1)));
Vector#(L1DNum, Randomize#(LLCIndex)) randDCIndex <- replicateM(mkConstrainedRandomizer(0, fromInteger(valueOf(IndexNum) - 1)));
Vector#(L1DNum, Randomize#(LineDataOffset)) randDCDataSel <- replicateM(mkGenericRandomizer);
Vector#(L1DNum, Randomize#(Bit#(MemDataSzBytes))) randDCDataBE <- replicateM(mkConstrainedRandomizer(1, maxBound)); // it could be all 0 though..
Vector#(L1DNum, Randomize#(MemTaggedData)) randDCData <- replicateM(mkGenericRandomizer);
Vector#(L1DNum, Randomize#(Bit#(LineSzBytes))) randDCLineBE <- replicateM(mkConstrainedRandomizer(1, maxBound)); // it could be all 0 though..
Vector#(L1DNum, Randomize#(Line)) randDCLine <- replicateM(mkGenericRandomizer);
Vector#(L1DNum, Randomize#(AmoFunc)) randDCAmoFunc <- replicateM(mkConstrainedRandomizer(Swap, Maxu));
Vector#(L1DNum, Randomize#(Bool)) randDCDoubleWord <- replicateM(mkGenericRandomizer);
Vector#(L1DNum, Reg#(TestCnt)) sendDCCnt <- replicateM(mkReg(0));
Vector#(L1DNum, RWire#(MemTestReq)) sendDCReq <- replicateM(mkRWire);
// randomize req
// D$
Vector#(L1DNum, Reg#(File)) dcReqLog <- replicateM(mkReg(InvalidFile));
Vector#(L1DNum, Reg#(File)) dcRespLog <- replicateM(mkReg(InvalidFile));
Reg#(TestFSM) testFSM <- mkConfigReg(InitTable);
Reg#(Bool) coreTableInitDone <- mkReg(False);
Reg#(TestId) iterId <- mkReg(0);
Vector#(L1DNum, RegFile#(TestId, Bool)) dcRespDoneTable <- replicateM(mkRegFileFull);
Vector#(L1DNum, RWire#(MemTestResp)) recvDCResp <- replicateM(mkRWire);
Reg#(LLCTag) iterTag <- mkReg(0);
Reg#(LLCIndex) iterIndex <- mkReg(0);
function L1ProcResp#(ProcRqId) getL1ProcResp(Integer i);
return (interface L1ProcResp;
method Action respLd(ProcRqId id, MemTaggedData d);
recvDCResp[i].wset(MemTestResp {t: Ld, id: truncate(id), data: d});
endmethod
method Action respLrScAmo(ProcRqId id, MemTaggedData d);
recvDCResp[i].wset(MemTestResp {t: LrScAmo, id: truncate(id), data: d});
endmethod
method ActionValue#(Tuple2#(LineByteEn, Line)) respSt(ProcRqId id);
recvDCResp[i].wset(MemTestResp {t: St, id: truncate(id), data: ?});
let req = validValue(dcReqTable[i].sub(truncate(id)));
return tuple2(req.lineBE, req.line);
endmethod
`ifdef DEBUG_STORE_PREFETCH
method Action respStPrefetch(ProcRqId id);
recvDCResp[i].wset(MemTestResp {t: StPrefetch, id: truncate(id), data: ?});
endmethod
`endif
method Action evict(LineAddr a);
noAction;
endmethod
endinterface);
endfunction
IdealDelayMem#(MemDelay, LgTestMemSzBytes, LdMemRqId#(LLCRqMshrIdx), void) delayMem <- mkIdealDelayMem;
let memSys <- mkL1LL(map(getL1ProcResp, genVector));
mkConnection(memSys.to_mem, delayMem.to_proc);
DelayMemTest dutMem = delayMem.to_test;
rule doInitCoreTable(testFSM == InitTable && !coreTableInitDone);
for(Integer i = 0; i < valueOf(L1DNum); i = i+1) begin
dcReqTable[i].upd(iterId, Invalid);
dcRespDoneTable[i].upd(iterId, False);
end
// change state
if(iterId == fromInteger(valueof(TestNum) - 1)) begin
iterId <= 0;
coreTableInitDone <= True;
end
else begin
iterId <= iterId + 1;
end
endrule
rule doInitTableDone(testFSM == InitTable && coreTableInitDone);
testFSM <= InitAddr;
$fdisplay(stderr, "INFO: init table done");
endrule
rule doInitAddr(testFSM == InitAddr);
Addr addr = getAddr(iterTag, iterIndex, 0);
Line initV = unpack(0); //replicate(replicate(addr));
dutMem.initLine(addr, initV);
//refMem.writeLine(addr, initV);
if(iterIndex == fromInteger(valueOf(IndexNum) - 1)) begin
iterIndex <= 0;
if(iterTag == fromInteger(valueOf(TagNum) - 1)) begin
iterTag <= 0;
// init randomizers and files for each core
for(Integer i = 0; i < valueOf(L1DNum); i = i+1) begin
randDCReqStall[i].cntrl.init;
randDCOp[i].cntrl.init;
randDCTag[i].cntrl.init;
randDCIndex[i].cntrl.init;
randDCDataSel[i].cntrl.init;
randDCDataBE[i].cntrl.init;
randDCData[i].cntrl.init;
randDCLineBE[i].cntrl.init;
randDCLine[i].cntrl.init;
randDCAmoFunc[i].cntrl.init;
randDCDoubleWord[i].cntrl.init;
String name = sprintf("req_dc_%d.log", i);
File f <- $fopen(name, "w");
dcReqLog[i] <= f;
name = sprintf("resp_dc_%d.log", i);
f <- $fopen(name, "w");
dcRespLog[i] <= f;
end
// init randomizers and files for DMA
// notify memory that init done
dutMem.initDone;
// change state
testFSM <= Idle;
$fdisplay(stderr, "INFO: init addr done");
end
else begin
iterTag <= iterTag + 1;
end
end
else begin
iterIndex <= iterIndex + 1;
end
endrule
Reg#(Bit#(64)) waitCount <- mkReg(0);
rule simplyWait(testFSM == Idle);
// wait for LLC to init all BRAMs
waitCount <= waitCount + 1;
if(waitCount == fromInteger(valueOf(TExp#(LLIndexSz)))) begin
$display("%t %m Start Issuing Requests only now!!!!", $time);
$fdisplay(stderr, "INFO: start issue req");
testFSM <= Process;
end
endrule
Vector#(L1DNum, L1ProcReq#(ProcRqId)) ifcDC = memSys.dReq;
Vector#(L1DNum, Reg#(TestCnt)) sendPrintDCCnt <- replicateM(mkReg(fromInteger(valueOf(TestPrintNum))));
for(Integer i = 0; i < valueOf(L1DNum); i = i+1) begin
rule doDCReq(testFSM == Process && sendDCCnt[i] < fromInteger(valueOf(TestNum)));
// randomize req
let index <- randDCIndex[i].next;
let tag <- randDCTag[i].next;
let sel <- randDCDataSel[i].next;
let addr = getAddr(tag, index, sel);
let op <- randDCOp[i].next;
let data <- randDCData[i].next;
let rBE <- randDCDataBE[i].next;
MemDataByteEn be = unpack(rBE);
let line <- randDCLine[i].next;
let rlbe <- randDCLineBE[i].next;
LineByteEn lineBE = unpack(rlbe);
let doubleWord <- randDCDoubleWord[i].next;
let amoFunc <- randDCAmoFunc[i].next;
let req = MemTestReq {
id: truncate(sendDCCnt[i]),
op: St, //op,
addr: 64'h10000, //addr,
byteEn: be,
data: data,
lineBE: replicate(replicate(True)),// lineBE,
line: line, //line,
amoInst: AmoInst {
func: amoFunc,
//doubleWord: doubleWord,
aq: False,
rl: False
}
};
// randomize stall
let rStall <- randDCReqStall[i].next;
if(!getReqStall(rStall)) begin
// no stall, send req & record
ifcDC[i].req(ProcRq {
id: zeroExtend(req.id),
addr: req.addr,
toState: getToState(req.op),
op: getMemOp(req.op),
byteEn: req.byteEn,
data: req.data,
amoInst: req.amoInst
});
testFSM <= Done;
sendDCReq[i].wset(req);
// output req cnt
if((sendDCCnt[i] + 1) == sendPrintDCCnt[i]) begin
$fdisplay(stderr, "INFO: %t D$ %d send req %d/%d",
$time, i, sendDCCnt[i] + 1, valueOf(TestNum)
);
sendPrintDCCnt[i] <= sendPrintDCCnt[i] + fromInteger(valueOf(TestPrintNum));
end
end
endrule
end
endmodule

122095
src_Core/RISCY_OOO/coherence/tests/L1LL/cache.vcd
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File diff suppressed because it is too large Load Diff

43
src_Core/RISCY_OOO/coherence/tests/L1LL/load_log
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@@ -1,43 +0,0 @@
[C AtomicMem] INFO: try to allocate 2097152B
[C AtomicMem] INFO: allocate 2097152B mem
20 File L1PRqMshR L1PRqMshrSafe top.memSys_dc_0_m_banks_0_pRqMshr: init empty entry done
40 L1CRqMshrSafe top.memSys_dc_0_m_banks_0_cRqMshr: init empty entry done
160 LLCRqMshrSafe top.memSys_llc_0.m_cRqMshr: init empty entry done
6430 top Start Issuing Requests only now!!!!
6440 L1 top cRqTransfer_new: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } }
6450 L1 top.memSys_dc_0_m_banks_0_pipeline tagMatch: tagged CRq L1PipeRqIn { addr: 'h00000000001c0030, mshrIdx: 'h0 } ; 'h00000000000e0<V 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 > ; <V I I I I > ; <V tagged Invalid tagged Invalid tagged Invalid tagged Invalid > ;
6460 L1 top pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, repInfo: <V 'h0 'h1 'h2 'h3 > }
6460 L1 top pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } }
6460 L1 top pipelineResp: cRq: no owner, miss no replace
6480 L1 top sendRqToP: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, id: 'h0, child: }
6510 XBar top.memSys_cRqXBar: deq src 0
6510 XBAR top.memSys_cRqXBar: enq dst 0 ; CRqMsg { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, id: 'h0, child: 'h0 }
6550 LL top.memSys_llc_0 cRqTransfer_new_child: 'h0 ; CRqMsg { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, id: 'h0, child: 'h0 } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V >, id: tagged Child 'h0 }
6560 LL top.memSys_llc_0.m_pipeline tagMatch: tagged CRq LLPipeCRqIn { addr: 'h00000000001c0030, mshrIdx: 'h0 } ; 'h0000000000038 ; <V 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 > ; <V I I I I I I I I I I I I I I I I > ; <V tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid >
6570 LL top.memSys_llc_0 pipelineResp: PipeOut { cmd: tagged LLCRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: <V I >, owner: tagged Invalid , other: }, line: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, repInfo: }
6570 LL top.memSys_llc_0 pipelineResp: cRq: 'h0 ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True >, id: tagged Child 'h0 }
6570 LL top.memSys_llc_0 pipelineResp: cRq: no owner, miss no replace: <V tagged Invalid >
6580 LL top.memSys_llc_0 sendToM: ToMemInfo { mshrIdx: 'h0, t: Ld } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True >, id: tagged Child 'h0 } ; LLCRqSlot { way: 'h0, repTag: 'h0aaaaaaaaaaaa, waitP: True, dirPend: <V tagged Invalid > } ; tagged Invalid ; False
6580 LL top.memSys_llc_0 sendToM: load only: tagged Ld LdMemRq { addr: 'h00000000001c0030, child: , id: LdMemRqId { refill: True, mshrIdx: 'h0 } }
6920 LL top.memSys_llc_0 mRsTransfer: MemRsMsg { data: <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 >, child: , id: LdMemRqId { refill: True, mshrIdx: 'h0 } } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True >, id: tagged Child 'h0 } ; LLCRqSlot { way: 'h0, repTag: 'h0aaaaaaaaaaaa, waitP: True, dirPend: <V tagged Invalid > } ;
6930 LL top.memSys_llc_0.m_pipeline tagMatch: tagged MRs LLPipeMRsCmd { addr: 'h00000000001c0030, way: 'h0 } ; 'h0000000000038 ; <V 'h0000000000038 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 > ; <V I I I I I I I I I I I I I I I I > ; <V tagged Valid CRqOwner { mshrIdx: 'h0, replacing: False } tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid >
6940 LL top.memSys_llc_0 pipelineResp: mRs: CRqOwner { mshrIdx: 'h0, replacing: False } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True >, id: tagged Child 'h0 } ; LLCRqSlot { way: 'h0, repTag: 'h0aaaaaaaaaaaa, waitP: True, dirPend: <V tagged Invalid > }
6940 LL top.memSys_llc_0 pipelineResp: cRq from child Hit func: 'h0 ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True >, id: tagged Child 'h0 }
6950 LL top.memSys_llc_0 sendRsToC: 'h0 ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True >, id: tagged Child 'h0 } ; tagged Valid <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 > ; E
6980 XBar top.memSys_pXBar: deq src 0
6980 XBAR top.memSys_pXBar: enq dst 0 ; tagged PRs PRsMsg { addr: 'h00000000001c0030, toState: E, child: , data: tagged Valid <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 >, id: 'h0 }
7020 L1 top pRsTransfer: PRsMsg { addr: 'h00000000001c0030, toState: E, child: , data: tagged Valid <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 >, id: 'h0 }
7030 L1 top.memSys_dc_0_m_banks_0_pipeline tagMatch: tagged PRs L1PipePRsCmd { addr: 'h00000000001c0030, way: 'h0 } ; 'h00000000000e0<V 'h00000000000e0 'h0000000000000 'h0000000000000 'h0000000000000 > ; <V I I I I > ; <V tagged Valid 'h0 tagged Invalid tagged Invalid tagged Invalid > ;
7040 L1 top pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h00000000000e0, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 > }, repInfo: <V 'h0 'h1 'h2 'h3 > }
7040 L1 top pipelineResp: pRs:
7040 L1 top pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } }
7040 L1 top pipelineResp: Hit func: update ram: <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 > ; tagged Invalid
start DMA request
7070 LL top.memSys_llc_0 cRqTransfer_new_dma: 'h1 ; DmaRq { addr: 'h0000000000000000, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False >, data: <V 'h59ad4f8c1a6389b5 'h7262438d537b614b 'h5089ba923e931c67 'h7aee26f5412250a9 'h0479e6ca06bedde8 'h2f0376f316d654e0 'h17e0fbfa5932e0e4 'h2fdb7c5f0c93dbbd >, id: 'h00000000 } ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False >, id: tagged Dma 'h00000000 }
7080 LL top.memSys_llc_0.m_pipeline tagMatch: tagged CRq LLPipeCRqIn { addr: 'h0000000000000000, mshrIdx: 'h1 } ; 'h0000000000000 ; <V 'h0000000000038 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 > ; <V E I I I I I I I I I I I I I I I > ; <V tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid tagged Invalid >
7090 LL top.memSys_llc_0 pipelineResp: PipeOut { cmd: tagged LLCRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: <V I >, owner: tagged Invalid , other: }, line: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, repInfo: }
7090 LL top.memSys_llc_0 pipelineResp: cRq: 'h1 ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False >, id: tagged Dma 'h00000000 }
7090 LL top.memSys_llc_0 pipelineResp: cRq from dma: no owner, miss req mem
7100 LL top.memSys_llc_0 sendToM: ToMemInfo { mshrIdx: 'h1, t: DmaWr } ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False >, id: tagged Dma 'h00000000 } ; LLCRqSlot { way: 'h1, repTag: 'h0aaaaaaaaaaaa, waitP: False, dirPend: <V tagged Invalid > } ; tagged Valid <V 'h59ad4f8c1a6389b5 'h7262438d537b614b 'h5089ba923e931c67 'h7aee26f5412250a9 'h0479e6ca06bedde8 'h2f0376f316d654e0 'h17e0fbfa5932e0e4 'h2fdb7c5f0c93dbbd > ; False
7100 LL top.memSys_llc_0 sendToM: dma write: tagged Wb WbMemRs { addr: 'h0000000000000000, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False >, data: <V 'h59ad4f8c1a6389b5 'h7262438d537b614b 'h5089ba923e931c67 'h7aee26f5412250a9 'h0479e6ca06bedde8 'h2f0376f316d654e0 'h17e0fbfa5932e0e4 'h2fdb7c5f0c93dbbd > }
7120 LL top.memSys_llc_0 sendRsToDma: St: 'h1 ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False >, id: tagged Dma 'h00000000 }

46
src_Core/RISCY_OOO/coherence/tests/L1LL/run.sh
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@@ -1,46 +0,0 @@
# Copyright (c) 2017 Massachusetts Institute of Technology
#
# Permission is hereby granted, free of charge, to any person
# obtaining a copy of this software and associated documentation
# files (the "Software"), to deal in the Software without
# restriction, including without limitation the rights to use, copy,
# modify, merge, publish, distribute, sublicense, and/or sell copies
# of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#make
#if [ $? -ne 0 ]; then
# exit $?
#fi
./simL1LL > log
grep "L1 .* tagMatch" log > L1TagMatch.log
grep "L1 .* cRqTransfer" log > L1CRqTransfer.log
grep "L1 .* pRqTransfer" log > L1PRqTransfer.log
grep "L1 .* pRsTransfer" log > L1PRsTransfer.log
grep "L1 .* sendRqToP" log > L1SendRqToP.log
grep "L1 .* pipelineResp" log > L1PipelineResp.log
grep "LL .* tagMatch" log > LLTagMatch.log
grep "LL .* cRqTransfer" log > LLCRqTransfer.log
grep "LL .* cRsTransfer" log > LLCRsTransfer.log
grep "LL .* mRsTransfer" log > LLMRsTransfer.log
grep "LL .* sendToM" log > LLSendToM.log
grep "LL .* sendRsToDma" log > LLSendRsToDma.log
grep "LL .* sendRsToC" log > LLSendRsToC.log
grep "LL .* sendRqToC" log > LLSendRqToC.log
grep "LL .* pipelineResp" log > LLPipelineResp.log
grep "XBAR:" log > XBar.log
tail log

1
src_Core/RISCY_OOO/coherence/tests/include/.gitignore vendored
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@@ -1 +0,0 @@
*.o

72
src_Core/RISCY_OOO/coherence/tests/include/AtomicMem.bsv
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@@ -1,72 +0,0 @@
import CCTypes::*;
import Types::*;
import Vector::*;
import CacheUtils::*;
// imported C function to handle monolithic memory
import "BDPI" function ActionValue#(Bit#(64)) c_createMem(Bit#(32) lgSzBytes);
import "BDPI" function ActionValue#(Bit#(64)) c_readMem(Bit#(64) memPtr, Bit#(64) addr);
import "BDPI" function Action c_writeMem(Bit#(64) memPtr, Bit#(64) addr, Bit#(64) d);
interface AtomicMem#(numeric type lgMemSzBytes);
method ActionValue#(Data) readData(Addr a);
method Action writeData(Addr a, Data d);
method ActionValue#(Line) readLine(Addr a);
method Action writeLine(Addr a, Line d);
endinterface
module mkAtomicMem(AtomicMem#(lgMemSzBytes));
Reg#(Addr) memPtr <- mkReg(0);
Reg#(Bool) initDone <- mkReg(False);
function Action checkAddrOverflow(Addr a);
return action
if(a >= fromInteger(valueOf(TExp#(lgMemSzBytes)))) begin
$fwrite(stderr, "[AtomicMem] ERROR: time %t, addr %x overflow\n", $time, a);
$finish;
end
endaction;
endfunction
rule doInit(!initDone);
let ptr <- c_createMem(fromInteger(valueOf(lgMemSzBytes)));
memPtr <= ptr;
initDone <= True;
endrule
method ActionValue#(Data) readData(Addr a) if(initDone);
checkAddrOverflow(a);
let d <- c_readMem(memPtr, a);
$display("%t AtomicMem readData Addr %x, Data %x", $time, a, d);
return d;
endmethod
method Action writeData(Addr a, Data d) if(initDone);
checkAddrOverflow(a);
$display("%t AtomicMem writeData Addr %x, Data %x", $time, a, d);
c_writeMem(memPtr, a, d);
endmethod
method ActionValue#(Line) readLine(Addr addr) if(initDone);
checkAddrOverflow(addr);
Line line = ?;
LineAddr la = truncateLSB(addr);
DataBytesOffset off = 0;
for(Integer i = 0; i < valueOf(LineSzData); i = i+1) begin
LineDataOffset sel = fromInteger(i);
line.data[i] <- c_readMem(memPtr, {la, sel, off});
end
return line;
endmethod
method Action writeLine(Addr addr, Line line) if(initDone);
checkAddrOverflow(addr);
LineAddr la = truncateLSB(addr);
DataBytesOffset off = 0;
for(Integer i = 0; i < valueOf(LineSzData); i = i+1) begin
LineDataOffset sel = fromInteger(i);
c_writeMem(memPtr, {la, sel, off}, line[i]);
end
endmethod
endmodule

9
src_Core/RISCY_OOO/coherence/tests/include/DelayMemTypes.bsv
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@@ -1,9 +0,0 @@
import CCTypes::*;
import Types::*;
// interface to testbench
interface DelayMemTest;
method Action initLine(Addr a, Line d); // for init
method Action initDone;
method Line getLine(Addr a); // for checking
endinterface

120
src_Core/RISCY_OOO/coherence/tests/include/IdealDelayMem.bsv
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@@ -1,120 +0,0 @@
import FIFO::*;
import GetPut::*;
import ClientServer::*;
import Connectable::*;
import Vector::*;
import RegFile::*;
import Types::*;
import CCTypes::*;
import DelayMemTypes::*;
import Fifos::*;
import CacheUtils::*;
typedef struct {
Addr addr;
Bool wr;
Line data;
} IdealDelayMemReq deriving(Bits, Eq);
// delay: number of pipeline stages to delay the response
// logMemNumBytes: log size of memory (in term of bytes)
interface IdealDelayMem#(
numeric type delay,
numeric type logMemNumBytes,
type rqIdT,
type childT
);
interface DelayMemTest to_test;
interface MemFifoServer#(rqIdT, childT) to_proc;
endinterface
module mkIdealDelayMem(IdealDelayMem#(delay, lgMemSzBytes, rqIdT, childT)) provisos(
NumAlias#(memAddrWidth, TSub#(lgMemSzBytes, LgLineSzBytes)),
Alias#(memAddr, Bit#(memAddrWidth)),
Alias#(toMemT, ToMemMsg#(rqIdT, childT)),
Alias#(memRsT, MemRsMsg#(rqIdT, childT)),
Add#(memAddrWidth, a__, AddrSz),
Bits#(rqIdT, _rqIdSz),
Bits#(childT, _childSz)
);
function memAddr getMemAddr(Addr a);
return truncate(a >> valueOf(LgLineSzBytes));
endfunction
function Action checkAddrOverflow(Addr a);
return action
if(a >= fromInteger(valueOf(TExp#(lgMemSzBytes)))) begin
$fwrite(stderr, "[IdealDelayMem] ERROR: time %t, addr %x overflow\n", $time, a);
$finish;
end
endaction;
endfunction
Reg#(Bool) inited <- mkReg(False);
RegFile#(memAddr, Line) mem <- mkRegFileFull;
Vector#(delay, FIFO#(memRsT)) rdRespQ <- replicateM(mkFIFO);
Fifo#(2, toMemT) inQ <- mkCFFifo;
Fifo#(2, memRsT) outQ <- mkCFFifo;
for(Integer i = 0; i < valueOf(delay) - 1; i = i+1) begin
mkConnection(toGet(rdRespQ[i]), toPut(rdRespQ[i+1]));
end
mkConnection(toGet(rdRespQ[valueOf(delay) - 1]), toPut(outQ));
rule doLd(inited &&& inQ.first matches tagged Ld .ld);
$display("%t IdealDelayMem doLd Addr %x", $time, ld.addr);
inQ.deq;
checkAddrOverflow(ld.addr);
let mAddr = getMemAddr(ld.addr);
rdRespQ[0].enq(MemRsMsg {
data: mem.sub(mAddr),
child: ld.child,
id: ld.id
});
endrule
rule doWb(inited &&& inQ.first matches tagged Wb .wb);
inQ.deq;
checkAddrOverflow(wb.addr);
let mAddr = getMemAddr(wb.addr);
// calculate write line
Line curLine = mem.sub(mAddr);
Line wrLine = wb.data;
/*
function Bit#(8) getNewByte(Integer i);
return wb.byteEn[i/valueOf(CLineNumMemTaggedData)][i%valueOf(CLineNumMemTaggedData)] ? wrLine[i] : curLine[i];
endfunction
*/
Vector#(LineSzBytes, Integer) idxVec = genVector;
Line newLine = getUpdatedLine(curLine, wb.byteEn,wrLine);
//unpack(pack(map(getNewByte, idxVec)));
// update mem
mem.upd(mAddr, newLine);
$display("%t IdealDelayMem doWb Addr %x Data %x", $time, wb.addr,wb.data, fshow(newLine));
endrule
interface DelayMemTest to_test;
method Action initLine(Addr a, Line d) if(!inited);
checkAddrOverflow(a);
let mAddr = getMemAddr(a);
mem.upd(mAddr, d);
endmethod
method Action initDone if(!inited);
inited <= True;
endmethod
method Line getLine(Addr a);
return mem.sub(getMemAddr(a));
endmethod
endinterface
interface MemFifoServer to_proc;
interface fromC = toFifoEnq(inQ);
interface rsToC = toFifoDeq(outQ);
endinterface
endmodule

31
src_Core/RISCY_OOO/coherence/tests/include/atomic_mem.c
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@@ -1,31 +0,0 @@
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
uint64_t c_createMem(uint32_t lg_sz_bytes) {
uint64_t size = 0x01ULL << lg_sz_bytes;
printf("[C AtomicMem] INFO: try to allocate %lldB\n", (long long)size);
uint64_t *mem = (uint64_t*)malloc(size); // should be dword-aligned
if(mem == NULL) {
fprintf(stderr, "[C AtomicMem] ERROR: fail to malloc %lldB\n", (long long)size);
return 0;
}
// set uninitialized words to 0xAAAAAAAA (default of BSV regfile)
for(uint64_t i = 0; i < (size >> 3); i++) {
mem[i] = 0xAAAAAAAAAAAAAAAAULL;
}
printf("[C AtomicMem] INFO: allocate %lldB mem\n", (long long)size);
return (uint64_t)mem;
}
uint64_t c_readMem(uint64_t ptr, uint64_t addr) {
uint64_t *mem = (uint64_t*)ptr;
return mem[addr >> 3];
}
void c_writeMem(uint64_t ptr, uint64_t addr, uint64_t data) {
uint64_t *mem = (uint64_t*)ptr;
mem[addr >> 3] = data;
}

2
src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv
View File

@@ -65,7 +65,7 @@ function CLineDataSel getCLineDataSel(Addr a) =
typedef struct {
Vector#(CLineNumMemTaggedData, MemTag) tag;
Vector#(CLineNumMemTaggedData, MemData) data;
} CLine deriving (Bits, Eq, FShow, Bounded);
} CLine deriving (Bits, Eq, FShow);
function Vector#(CLineNumMemTaggedData, MemTaggedData) clineToMemTaggedDataVector(CLine line);
function f(x,y) = MemTaggedData{tag: x, data: y};
return zipWith(f, line.tag, line.data);

1
src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
View File

@@ -67,7 +67,6 @@ export L1Num;
export LgL1WayNum;
export L1WayNum;
export L1Way;
export LgDBankNum;
export DProcReqId;
export L1DCRqStuck(..);

2
src_Core/RISCY_OOO/procs/lib/Types.bsv
View File

@@ -56,7 +56,7 @@ typedef Vector#(DataBytes, Bool) ByteEn;
typedef struct {
tag_t tag;
data_t data;
} TaggedData#(type tag_t, type data_t) deriving (Bits, FShow, Eq, Bounded);
} TaggedData#(type tag_t, type data_t) deriving (Bits, FShow, Eq);
function tag_t getTag(TaggedData#(tag_t, data_t) td) = td.tag;
function data_t getData(TaggedData#(tag_t, data_t) td) = td.data;
typedef Vector#(2, Data) MemData;