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Revert "initial commit, test compiled and run sucessfully"

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This reverts commit d025278195.
This commit is contained in:
Yuecheng-CAM
2025-06-01 18:17:24 +01:00
parent d025278195
commit 8af3b2e85a
22 changed files with 3 additions and 123434 deletions
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10
src_Core/RISCY_OOO/coherence/src/CCTypes.bsv
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@@ -218,16 +218,6 @@ interface L1ProcResp#(type idT);
method ActionValue#(Tuple2#(LineByteEn, Line)) respSt(idT id);
method Action evict(LineAddr a); // called when cache line is evicted
endinterface
// General replacement interface
interface ReplacePolicy#(numeric type wayNum, type repInfoT);
method repInfoT initRepInfo;
method Maybe#(Bit#(TLog#(wayNum))) getReplaceWay(
Vector#(wayNum, Bool) unlocked,
Vector#(wayNum, Bool) invalid,
repInfoT repInfo
);
method repInfoT updateRepInfo(repInfoT old, Bit#(TLog#(wayNum)) way);
endinterface
// RISCV-specific store-cond return values
typedef 0 ScSuccVal;

180
src_Core/RISCY_OOO/coherence/src/L1LL.bsv
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@@ -1,180 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Types::*;
import CacheUtils::*;
import CCTypes::*;
import L1Wrapper::*;
import LLWrapper::*;
import CrossBar::*;
import Vector::*;
import GetPut::*;
import ClientServer::*;
import L1Bank::*;
import LLBank::*;
import L1LLSizes::*;
import Connectable::*;
export L1LL(..);
export mkL1LL;
// LLChildNum == L1Num
// XXX no LLC banking: LgLLBankNum = 0
typedef TExp#(LgLLBankNum) LLNum;
typedef Bit#(LgLLBankNum) LLIdx;
typedef Bit#(TLog#(L1Num)) L1Idx;
typedef CRqMsg#(L1Way, void) CRqFromL1;
typedef CRqMsg#(LLCRqId, LLChild) CRqToLL;
typedef CRsMsg#(void) CRsFromL1;
typedef CRsMsg#(LLChild) CRsToLL;
typedef PRqRsMsg#(LLCRqId, LLChild) PRqRsFromLL;
typedef PRqRsMsg#(L1Way, void) PRqRsToL1;
typedef 1 XBarSrcDelay;
typedef 2 XBarDstDelay;
// cross bar for L1 cRq to LL
typedef CrossBar#(L1Num, XBarSrcDelay, CRqFromL1, LLNum, XBarDstDelay, CRqToLL) L1CRqToLLXBar;
(* synthesize *)
module mkL1CRqToLLXBar(L1CRqToLLXBar);
function XBarDstInfo#(LLIdx, CRqToLL) getL1CRqDstInfo(L1Idx whichL1, CRqFromL1 rq);
return XBarDstInfo {
idx: 0,
data: CRqMsg {
addr: rq.addr,
fromState: rq.fromState,
toState: rq.toState,
canUpToE: rq.canUpToE,
id: rq.id,
child: whichL1
}
};
endfunction
let m <- mkCrossBar(getL1CRqDstInfo);
return m;
endmodule
// cross bar for L1 cRs to LL
typedef CrossBar#(L1Num, XBarSrcDelay, CRsFromL1, LLNum, XBarDstDelay, CRsToLL) L1CRsToLLXBar;
(* synthesize *)
module mkL1CRsToLLXBar(L1CRsToLLXBar);
function XBarDstInfo#(LLIdx, CRsToLL) getL1CRsDstInfo(L1Idx whichL1, CRsFromL1 rs);
return XBarDstInfo {
idx: 0,
data: CRsMsg {
addr: rs.addr,
toState: rs.toState,
data: rs.data,
child: whichL1
}
};
endfunction
let m <- mkCrossBar(getL1CRsDstInfo);
return m;
endmodule
// cross bar for LL pRqRs to L1
typedef CrossBar#(LLNum, XBarSrcDelay, PRqRsFromLL, L1Num, XBarDstDelay, PRqRsToL1) LLPRqRsToL1XBar;
(* synthesize *)
module mkLLPRqRsToL1XBar(LLPRqRsToL1XBar);
function XBarDstInfo#(L1Idx, PRqRsToL1) getLLPRqRsDstInfo(LLIdx whichLL, PRqRsFromLL msg);
return (case(msg) matches
tagged PRq .rq: return XBarDstInfo {
idx: rq.child,
data: PRq (PRqMsg {
addr: rq.addr,
toState: rq.toState,
child: ?
})
};
tagged PRs .rs: return XBarDstInfo {
idx: rs.child,
data: PRs (PRsMsg {
addr: rs.addr,
toState: rs.toState,
child: ?,
data: rs.data,
id: rs.id
})
};
endcase);
endfunction
let m <- mkCrossBar(getLLPRqRsDstInfo);
return m;
endmodule
// L1 + LL
// LLC port mapping:
// 0 ~ L1DNum -1 -- D$ 0~L1DNum-1
// L1Dnum ~ L1Num -- I$ 0~L1INum-1
interface L1LL;
interface Vector#(L1DNum, L1ProcReq#(ProcRqId)) dReq;
interface Vector#(L1INum, InstServer#(L1ISupSz)) inst;
interface DmaServer#(DmaRqId) dma;
interface MemFifoClient#(LdMemRqId#(LLCRqMshrIdx), void) to_mem;
endinterface
module mkL1LL#(Vector#(L1DNum, L1ProcResp#(ProcRqId)) procResp)(L1LL) provisos(
Add#(0, 0, LgLLBankNum),
Add#(1, 0, LLNum)
);
Vector#(L1DNum, L1CacheWrapper) dc = ?;
for(Integer i = 0; i < valueof(L1DNum); i = i+1) begin
dc[i] <- mkL1CacheWrapper(procResp[i]);
end
Vector#(LLNum, LLBankWrapper) llc <- replicateM(mkLLBankWrapper);
let cRqXBar <- mkL1CRqToLLXBar;
let cRsXBar <- mkL1CRsToLLXBar;
let pXBar <- mkLLPRqRsToL1XBar;
for(Integer i = 0; i < valueOf(L1DNum); i = i+1) begin
mkConnection(cRqXBar.srcIfc[i], dc[i].to_parent.rqToP);
mkConnection(cRsXBar.srcIfc[i], dc[i].to_parent.rsToP);
mkConnection(pXBar.dstIfc[i], dc[i].to_parent.fromP);
end
for(Integer i = 0; i < valueOf(LLNum); i = i+1) begin
mkConnection(cRqXBar.dstIfc[i], llc[i].to_child.rqFromC);
mkConnection(cRsXBar.dstIfc[i], llc[i].to_child.rsFromC);
mkConnection(pXBar.srcIfc[i], llc[i].to_child.toC);
end
function L1ProcReq#(ProcRqId) getDReqIfc(L1CacheWrapper ifc);
return ifc.procReq;
endfunction
interface dReq = map(getDReqIfc, dc);
interface dma = llc[0].dma;
interface to_mem = llc[0].to_mem;
endmodule

86
src_Core/RISCY_OOO/coherence/src/L1LLSizes.bsv
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@@ -1,86 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Types::*;
import Vector::*;
import CCTypes::*;
// cache size = bank num * way num * set num * 64B
// L1 connect to LL
// 32KB L1
typedef 1 L1DNum;
typedef 0 L1INum;
typedef TAdd#(L1DNum, L1INum) L1Num;
typedef 4 L1WayNum;
typedef Bit#(TLog#(L1WayNum)) L1Way;
typedef 0 LgL1BankNum;
typedef 7 LgL1SetNum;
typedef TExp#(LgL1BankNum) L1BankNum;
typedef Bit#(LgL1BankNum) L1BankId;
typedef LgL1SetNum L1IndexSz;
typedef Bit#(L1IndexSz) L1Index;
typedef GetTagSz#(LgL1BankNum, LgL1SetNum) L1TagSz;
typedef Bit#(L1TagSz) L1Tag;
typedef 0 LgIBankNum;
typedef 7 LgISetNum;
typedef Bit#(LgIBankNum) IBankId;
typedef LgISetNum IIndexSz;
typedef Bit#(IIndexSz) IIndex;
typedef GetTagSz#(LgIBankNum, LgISetNum) ITagSz;
typedef Bit#(ITagSz) ITag;
typedef 4 L1CRqNum;
typedef 2 L1PRqNum;
typedef Bit#(TLog#(L1CRqNum)) L1CRqMshrIdx;
typedef Bit#(TLog#(L1PRqNum)) L1PRqMshrIdx;
typedef Bit#(32) ProcRqId;
typedef 4 L1ISupSz;
typedef Vector#(L1ISupSz, Maybe#(Instruction)) L1InstResult;
// Last-Level: 512KB per bank
typedef 16 LLWayNum;
typedef 0 LgLLBankNum;
typedef 9 LgLLSetNum;
typedef Bit#(LgLLBankNum) LLBankId;
typedef LgLLSetNum LLIndexSz;
typedef Bit#(LLIndexSz) LLIndex;
typedef GetTagSz#(LgLLBankNum, LgLLSetNum) LLTagSz;
typedef Bit#(LLTagSz) LLTag;
typedef Bit#(TLog#(LLWayNum)) LLWay;
typedef 16 LLCRqNum;
typedef Bit#(TLog#(LLCRqNum)) LLCRqMshrIdx;
typedef L1Num LLChildNum;
typedef Bit#(TLog#(LLChildNum)) LLChild;
typedef L1Way LLCRqId;
typedef Bit#(32) DmaRqId;

78
src_Core/RISCY_OOO/coherence/src/L1Wrapper.bsv
View File

@@ -1,78 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import CacheUtils::*;
import Types::*;
import CCTypes::*;
import L1Pipe::*;
import L1CRqMshr::*;
import L1PRqMshr::*;
import L1LLSizes::*;
import L1Bank::*;
import RWBramCore::*;
import LruReplace::*;
import L1CoCache::*;
(* synthesize *)
module mkL1CRqMshrWrapper(
L1CRqMshr#(L1CRqNum, L1Index,L1Way, L1Tag, ProcRq#(ProcRqId))
);
function Addr getAddrFromReq(ProcRq#(ProcRqId) r);
return r.addr;
endfunction
function L1Index getIndexFromAddr(Addr addr);
return truncate(addr >> (valueOf(LgLineSzBytes) + valueOf(LgDBankNum)));
endfunction
function Bool isReqToExclusive(ProcRq#(ProcRqId) r);
return r.toState >= E;
endfunction
let m <- mkL1CRqMshr(getAddrFromReq,getIndexFromAddr);
return m;
endmodule
(* synthesize *)
module mkL1PRqMshrWrapper(
L1PRqMshr#(L1PRqNum)
);
let m <- mkL1PRqMshr;
return m;
endmodule
typedef TrueLruRepInfo#(L1WayNum) L1RepInfo;
(* synthesize *)
module mkL1Pipeline(
L1Pipe#(LgL1BankNum, L1WayNum, L1Index, L1Tag, L1CRqMshrIdx, L1PRqMshrIdx)
);
RWBramCore#(L1Index, L1RepInfo) repRam <- mkRWBramCore;
ReplacePolicy#(L1WayNum, L1RepInfo) repPolicy <- mkTrueLruReplace;
let m <- mkL1Pipe;
return m;
endmodule
typedef L1Bank#(LgL1BankNum, L1WayNum, L1IndexSz, L1TagSz, L1CRqNum, L1PRqNum, ProcRqId) L1CacheWrapper;
module mkL1CacheWrapper#(L1ProcResp#(ProcRqId) procResp)(L1CacheWrapper);
let m <- mkL1Cache(mkL1CRqMshrWrapper, mkL1PRqMshrWrapper, mkL1Pipeline, procResp);
return m;
endmodule

8
src_Core/RISCY_OOO/coherence/src/LLBank.bsv
View File

@@ -191,7 +191,7 @@ module mkLLBank#(
Add#(TLog#(TDiv#(childNum,2)), c__, TLog#(childNum))
);
Bool verbose = True;
Bool verbose = False;
LLCRqMshr#(cRqNum, wayT, tagT, Vector#(childNum, DirPend), cRqT) cRqMshr <- mkLLMshr;
@@ -1012,7 +1012,6 @@ endfunction
line: ram.line // use line in ram
}, True); // hit, so update rep info
if (!cRqIsPrefetch[n]) begin
/*
if (cRq.child[0] == 1) begin
instrPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, HIT);
@@ -1021,7 +1020,6 @@ endfunction
dataPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, HIT);
end
*/
end
endaction
endfunction
@@ -1219,7 +1217,6 @@ endfunction
line: ram.line
}, False);
if (!cRqIsPrefetch[n]) begin
/*
if (cRq.child[0] == 1) begin
instrPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
@@ -1228,7 +1225,6 @@ endfunction
dataPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
end
*/
end
endaction
endfunction
@@ -1299,7 +1295,6 @@ endfunction
});
end
if (!cRqIsPrefetch[n]) begin
/*
if (cRq.child[0] == 1) begin
instrPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
@@ -1308,7 +1303,6 @@ endfunction
dataPrefetchers.reportAccess(
truncateLSB(cRq.child), cRq.addr, MISS);
end
*/
end
endaction
endfunction

61
src_Core/RISCY_OOO/coherence/src/LLWrapper.bsv
View File

@@ -1,61 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Vector::*;
import CacheUtils::*;
import Types::*;
import CCTypes::*;
import LLPipe::*;
import LLCRqMshr::*;
import LLBank::*;
import L1LLSizes::*;
(* synthesize *)
module mkLastLvCRqMshr(
LLCRqMshr#(LLCRqNum, LLWay, LLTag, Vector#(LLChildNum, DirPend), cRqT)
) provisos(
Alias#(cRqT, LLRq#(LLCRqId, DmaRqId, LLChild))
);
function Addr getAddr(cRqT r) = r.addr;
let m <- mkLLCRqMshr(getAddr, getNeedReqChild, getDirPendInitVal);
return m;
endmodule
(* synthesize *)
module mkLLPipeline(
LLPipe#(LgLLBankNum, LLChildNum, LLWayNum, LLIndex, LLTag, LLCRqMshrIdx)
);
let m <- mkLLPipe;
return m;
endmodule
typedef LLBank#(LgLLBankNum, LLChildNum, LLWayNum, LLIndexSz, LLTagSz, LLCRqNum, LLCRqId, DmaRqId) LLBankWrapper;
(* synthesize *)
module mkLLBankWrapper(LLBankWrapper);
// resp load req with E when it fills cache line from mem
function Bool respE(Bool fromMem) = fromMem;
let m <- mkLLBank(mkLastLvCRqMshr, mkLLPipeline, respE);
return m;
endmodule

92
src_Core/RISCY_OOO/coherence/src/LruReplace.bsv
View File

@@ -1,92 +0,0 @@
// Copyright (c) 2017 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Vector::*;
import CCTypes::*;
import RWBramCore::*;
// True LRU
// vec[0] -- MRU, vec[wayNum-1] -- LRU
typedef Vector#(wayNum, Bit#(TLog#(wayNum))) TrueLruRepInfo#(numeric type wayNum);
module mkTrueLruReplace(ReplacePolicy#(wayNum, TrueLruRepInfo#(wayNum))) provisos(
Add#(1, a__, wayNum),
Alias#(wayT, Bit#(TLog#(wayNum))),
Alias#(repT, TrueLruRepInfo#(wayNum))
);
// rand rep as fall back if LRU way is locked
Reg#(wayT) randWay <- mkReg(0);
rule tick;
randWay <= randWay == fromInteger(valueOf(wayNum) - 1) ? 0 : randWay + 1;
endrule
method repT initRepInfo;
return genWith(fromInteger);
endmethod
method Maybe#(wayT) getReplaceWay(
Vector#(wayNum, Bool) unlocked,
Vector#(wayNum, Bool) invalid,
repT repInfo
);
// first search for invalid & unlocked way
function Bool isInvUnlock(Integer i);
return unlocked[i] && invalid[i];
endfunction
Vector#(wayNum, Integer) idxVec = genVector;
Maybe#(wayT) repWay = searchIndex(isInvUnlock, idxVec);
if(!isValid(repWay)) begin
// check whether LRU way is unlocked
wayT lruWay = repInfo[valueof(wayNum) - 1];
if(unlocked[lruWay]) begin
repWay = Valid (lruWay);
end
else begin
// check if a random way is unlocked
if(unlocked[randWay]) begin
repWay = Valid (randWay);
end
else begin
// just find a unlocked way
repWay = searchIndex(id, unlocked);
end
end
end
return repWay;
endmethod
method repT updateRepInfo(repT repInfo, wayT hitWay);
repT newInfo = repInfo;
// find which vector index contains hitWay, and shift rep info
if(findElem(hitWay, repInfo) matches tagged Valid .idx) begin
newInfo[0] = hitWay;
for(Integer i = 0; i < valueof(wayNum) - 1; i = i+1) begin
if(fromInteger(i) < idx) begin
newInfo[i + 1] = repInfo[i];
end
end
end
return newInfo;
endmethod
endmodule