From 90d9d7cbc7079236dbb0017a3bd623989db0a3c6 Mon Sep 17 00:00:00 2001 From: jon Date: Thu, 30 Apr 2020 15:32:26 +0100 Subject: [PATCH] Move back to considering the instruction width when checking PCC. --- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/Exec.bsv | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index faeb6d2..b12b427 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -231,7 +231,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); Maybe#(Trap) trap = tagged Invalid; let csr_state = csrf.decodeInfo; let pending_interrupt = csrf.pending_interrupt; - let new_exception = checkForException(x.dInst, x.regs, csr_state, x.pc); + let new_exception = checkForException(x.dInst, x.regs, csr_state, x.pc, x.orig_inst[1:0]==2'b11); // If Fpu regs are accessed, trap if mstatus_fs is "Off" (2'b00) Bool fpr_access = ( fn_ArchReg_is_FpuReg (x.regs.src1) diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv index 18bd372..a7c5ad2 100755 --- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv @@ -332,7 +332,8 @@ function Maybe#(Trap) checkForException( DecodedInst dInst, ArchRegs regs, CsrDecodeInfo csrState, - CapMem pcc + CapMem pcc, + Bool fourByteInst ); // regs needed to check if x0 is a src Maybe#(Exception) exception = Invalid; let prv = csrState.prv; @@ -395,7 +396,7 @@ function Maybe#(Trap) checkForException( end // Check that the end of the instruction is in bounds of PCC. - CapPipe pcc_end = cast(addPc(pcc, 2)); + CapPipe pcc_end = cast(addPc(pcc, (fourByteInst?4:2))); Maybe#(CSR_XCapCause) capException = Invalid; if (!isInBounds(pcc_end, True)) capException = Valid(CSR_XCapCause{cheri_exc_reg: {1'b1,pack(SCR_PCC)}, cheri_exc_code: LengthViolation});