From 913d14406edb14da961a94a4bf8a293a6d49c32a Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Wed, 14 Apr 2021 14:55:18 +0100 Subject: [PATCH] Add explicit PCC and cap JALRs --- src_Core/ISA/ISA_Decls_CHERI.bsv | 6 ++++-- src_Core/RISCY_OOO/procs/lib/Decode.bsv | 16 ++++++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src_Core/ISA/ISA_Decls_CHERI.bsv b/src_Core/ISA/ISA_Decls_CHERI.bsv index 0cf2497..3dbd9dd 100755 --- a/src_Core/ISA/ISA_Decls_CHERI.bsv +++ b/src_Core/ISA/ISA_Decls_CHERI.bsv @@ -177,14 +177,16 @@ Bit #(5) f5rs2_cap_CRRL = 5'h08; Bit #(5) f5rs2_cap_CRAM = 5'h09; Bit #(5) f5rs2_cap_CMove = 5'h0a; Bit #(5) f5rs2_cap_CClearTag = 5'h0b; -Bit #(5) f5rs2_cap_CJALR = 5'h0c; +Bit #(5) f5rs2_cap_JALR_CAP = 5'h0c; Bit #(5) f5rs2_cap_CClearReg = 5'h0d; // 5'h0e unused Bit #(5) f5rs2_cap_CGetAddr = 5'h0f; Bit #(5) f5rs2_cap_CClearFPReg = 5'h10; Bit #(5) f5rs2_cap_CSealEntry = 5'h11; Bit #(5) f5rs2_cap_CLoadTags = 5'h12; -// 5'h13-5'h1f unused (5'h1f reserved for 1-reg instructions) +// 5'h13 unused +Bit #(5) f5rs2_cap_JALR_PCC = 5'h14; +// 5'h15-5'h1f unused (5'h1f reserved for 1-reg instructions) // ================================================================ // f7_cap_{Load, Store} opcode subdivision diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv index 28510fc..401af3d 100755 --- a/src_Core/RISCY_OOO/procs/lib/Decode.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Decode.bsv @@ -1365,7 +1365,7 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); regs.src1 = Valid(tagged Gpr rs1); dInst.capFunc = CapInspect (GetPerm); end - f5rs2_cap_CJALR: begin + f5rs2_cap_JALR_CAP: begin dInst.capChecks.src1_tag = True; dInst.capChecks.src1_permit_x = True; dInst.capChecks.src1_unsealed_or_sentry = True; @@ -1380,7 +1380,19 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); dInst.execFunc = tagged Br AT; regs.dst = Valid(tagged Gpr rd); regs.src1 = Valid(tagged Gpr rs1); - end + end + f5rs2_cap_JALR_PCC: begin + dInst.capChecks.check_enable = True; + dInst.capChecks.check_authority_src = Pcc; + dInst.capChecks.check_low_src = Src1Addr; + dInst.capChecks.check_high_src = Src1AddrPlus2; + dInst.capChecks.check_inclusive = True; + + dInst.iType = Jr; + dInst.execFunc = tagged Br AT; + regs.dst = Valid(tagged Gpr rd); + regs.src1 = Valid(tagged Gpr rs1); + end f5rs2_cap_CGetType: begin dInst.iType = Cap; regs.dst = Valid(tagged Gpr rd);