From 93180fbe252e3436def3c0dfca6d725e5b05d1cc Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Fri, 17 Feb 2023 11:16:20 +0000 Subject: [PATCH] Revert "Use wide to narrow AXI4 shim" This reverts commit be91801982c21fe75927603093d5b44bdf6939d9. --- src_SSITH_P3/src_BSV/P3_Core.bsv | 19 ++++++++++--------- src_Testbench/SoC/SoC_Top.bsv | 22 ++++++++++++---------- 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index a20f371..12b2411 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -32,7 +32,6 @@ import Vector :: *; import GetPut_Aux :: *; import Routable :: *; -import BlueBasics :: *; import BlueAXI4 :: *; import SourceSink :: *; import WindCoreInterface :: *; @@ -167,13 +166,15 @@ module mkP3_Core (P3_Core_IFC); <- mkCoreW_reset (dm_power_on_reset, reset_by ndm_reset); match {.otherRst, .corew} = both; // AXI4 Narrower Master in front of cached memory master - NumProxy #(4) proxyInDepth = error ("don't look inside a proxy"); - NumProxy #(4) proxyOutDepth = error ("don't look inside a proxy"); - Tuple2 #( AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) - , AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) ) - wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth); - match {.wideS, .narrowM} = wideS_narrowM; - mkConnection(corew.manager_0, wideS); + AXI4_Shim#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) + manager_0_narrow <- mkAXI4ShimFF; + AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,4), 0, 0, 0, 0, 0) + manager_0_wide_a <- toWider_AXI4_Slave(manager_0_narrow.slave); + AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,2), 0, 0, 0, 0, 0) + manager_0_wide_b <- toWider_AXI4_Slave(manager_0_wide_a); + AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) + manager_0_wide <- toWider_AXI4_Slave(manager_0_wide_b); + mkConnection(corew.manager_0,manager_0_wide); `ifdef INCLUDE_GDB_CONTROL @@ -270,7 +271,7 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ // INTERFACE - let master0_sig <- toAXI4_Master_Sig (narrowM); + let master0_sig <- toAXI4_Master_Sig (manager_0_narrow.master); let master1_sig <- toAXI4_Master_Sig (corew.manager_1); // ---------------------------------------------------------------- // Core CPU interfaces diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index af9779c..78b843d 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -46,8 +46,8 @@ import Vector :: *; import Cur_Cycle :: *; import GetPut_Aux :: *; import Routable :: *; -import BlueBasics :: *; -import BlueAXI4 :: *; +import AXI4 :: *; +import AXI4Lite :: *; // ================================================================ // Project imports @@ -163,13 +163,15 @@ module mkSoC_Top #(Reset dm_power_on_reset) mem0_controller_axi4_deburster <- mkBurstToNoBurst; // AXI4 Narrower Master in front of cached memory master - NumProxy #(4) proxyInDepth = error ("don't look inside a proxy"); - NumProxy #(4) proxyOutDepth = error ("don't look inside a proxy"); - Tuple2 #( AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) - , AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) ) - wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth); - match {.wideS, .narrowM} = wideS_narrowM; - mkConnection(corew.manager_0, wideS); + AXI4_Shim#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) + manager_0_narrow <- mkAXI4ShimFF; + AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,4), 0, 0, 0, 0, 0) + manager_0_wide_a <- toWider_AXI4_Slave(manager_0_narrow.slave); + AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,2), 0, 0, 0, 0, 0) + manager_0_wide_b <- toWider_AXI4_Slave(manager_0_wide_a); + AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) + manager_0_wide <- toWider_AXI4_Slave(manager_0_wide_b); + mkConnection(corew.manager_0,manager_0_wide); // SoC IPs UART_IFC uart0 <- mkUART; @@ -188,7 +190,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) master_vector = newVector; // CPU IMem master to fabric - master_vector[imem_master_num] = narrowM; + master_vector[imem_master_num] = manager_0_narrow.master; // CPU DMem master to fabric master_vector[dmem_master_num] = corew.manager_1;