From 947cf8ed7b7d336aaa8124b841a2af0ea7daccc7 Mon Sep 17 00:00:00 2001
From: Alexandre Joannou <aj443@cam.ac.uk>
Date: Mon, 11 Oct 2021 12:30:35 +0100
Subject: [PATCH] NonPipelined API update

---
 src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv | 2 +-
 src_Core/RISCY_OOO/procs/lib/Fpu.bsv              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv
index e93e1f1..ed8587e 100644
--- a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv
+++ b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv
@@ -75,7 +75,7 @@ module mkIntDivUnsignedSim(IntDivUnsignedImport);
 
     FIFO#(IntDivUser) userFF <- mkFIFO;
     Server#(Tuple2#(UInt#(128),UInt#(64)),Tuple2#(UInt#(64),UInt#(64)))
-      nonpipediv <- mkNonPipelinedDividerBlah (4);
+      nonpipediv <- mkNonPipelinedDivider (4);
 
     rule compute;
         dividendQ.deq;
diff --git a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv
index 95b478a..fd61e18 100644
--- a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv
@@ -97,7 +97,7 @@ module mkDoubleDiv(Server#(Tuple3#(Double, Double, FpuRoundMode), Tuple2#(Double
     let fpu <- mkXilinxFpDiv;
 `else
     //let int_div <- mkDivider(1); // [sizhuo] size in RVFpu: 2
-    let int_div <- mkNonPipelinedDividerBlah(3);
+    let int_div <- mkNonPipelinedDivider(3);
     let fpu <- mkFloatingPointDivider(int_div);
 `endif
     return fpu;