From 95f554dad1c0b6f33c4e1a9bd71584a101025403 Mon Sep 17 00:00:00 2001
From: Alexandre Joannou <aj443@cam.ac.uk>
Date: Tue, 16 Aug 2022 12:44:00 +0000
Subject: [PATCH] removed coreW from component.xml

---
 src_SSITH_P3/xilinx_ip/component.xml | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml
index d89e99e..bd8f871 100644
--- a/src_SSITH_P3/xilinx_ip/component.xml
+++ b/src_SSITH_P3/xilinx_ip/component.xml
@@ -2236,11 +2236,6 @@
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
       </spirit:file>
-      <spirit:file>
-        <spirit:name>../Verilog_RTL/mkCoreW.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
       <spirit:file>
         <spirit:name>../Verilog_RTL/mkTagController.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>