diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index d03270c..400b249 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -50,7 +50,7 @@ TOPMODULE ?= mkTop_HW_Side # bsc compilation flags BSC_COMPILATION_FLAGS += \ - -keep-fires -aggressive-conditions -no-warn-action-shadowing -no-show-timestamps -check-assert \ + -keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \ -suppress-warnings G0020 \ +RTS -K128M -RTS -show-range-conflict diff --git a/builds/Resources/Include_verilator.mk b/builds/Resources/Include_verilator.mk index 7779335..fa61599 100644 --- a/builds/Resources/Include_verilator.mk +++ b/builds/Resources/Include_verilator.mk @@ -61,7 +61,8 @@ simulator: $(VERILATOR_FLAGS) \ --cc $(TOPMODULE)_edited.v \ --exe sim_main.cpp \ - $(REPO)/src_Testbench/Top/C_Imported_Functions.c + $(REPO)/src_Testbench/Top/C_Imported_Functions.c \ + $(REPO)/src_Verifier/BSV-RVFI-DII/SocketPacketUtils/socket_packet_utils.c @echo "INFO: Linking verilated files" cp -p $(VERILATOR_RESOURCES)/sim_main.cpp obj_dir/sim_main.cpp cd obj_dir; \ diff --git a/builds/Resources/Verilator_resources/import_DPI_C_decls.v b/builds/Resources/Verilator_resources/import_DPI_C_decls.v index 906bbfd..84b9151 100644 --- a/builds/Resources/Verilator_resources/import_DPI_C_decls.v +++ b/builds/Resources/Verilator_resources/import_DPI_C_decls.v @@ -66,3 +66,20 @@ import "DPI-C" function byte unsigned c_debug_client_response_send (int unsigned data); // ================================================================ + +import "DPI-C" +function int serv_socket_get8(longint unsigned ptr); + +import "DPI-C" +function int unsigned serv_socket_put8(longint unsigned ptr, byte unsigned data); + +import "DPI-C" +function longint unsigned serv_socket_create_nameless(int unsigned dflt_port); + +import "DPI-C" +function longint unsigned serv_socket_create(chandle name, int unsigned dflt_port); + +import "DPI-C" +function void serv_socket_init(longint unsigned ptr); + +// ================================================================ diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 0796cfa..3a4a004 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -82,6 +82,10 @@ import RenameStage::*; import CommitStage::*; import Bypass::*; +`ifdef RVFI_DII +import Toooba_RVFI_DII_Bridge::*; +`endif + import CsrFile :: *; interface CoreReq; @@ -132,12 +136,16 @@ interface Core; // debug rename interface CoreRenameDebug renameDebug; - // Bluespec: external interrupt requests targeting Machine and Supervisor modes + // Bluespec: external interrupt requests targeting Machine and Supervisor modes method Action setMEIP (Bit #(1) v); method Action setSEIP (Bit #(1) v); - // Bluespec: external interrupt to enter debug mode + // Bluespec: external interrupt to enter debug mode method Action setDEIP (Bit #(1) v); + +`ifdef RVFI_DII + interface Toooba_RVFI_DII_Server rvfi_dii_server; +`endif endinterface // fixpoint to instantiate modules @@ -164,6 +172,15 @@ module mkCore#(CoreId coreId)(Core); FetchStage fetchStage <- mkFetchStage; ITlb iTlb = fetchStage.iTlbIfc; ICoCache iMem = fetchStage.iMemIfc; + + // ================================================================ + // If using Direct Instruction Injection then make a + // bridge that can insert instructions as if it were + // an instruction cache. +`ifdef RVFI_DII + Toooba_RVFI_DII_Bridge_IFC rvfi_bridge <- mkTooobaRVFIDIIBridge; + mkConnection(rvfi_bridge.dii, fetchStage.dii); +`endif // back end RFileSynth rf <- mkRFileSynth; @@ -512,6 +529,10 @@ module mkCore#(CoreId coreId)(Core); endinterface); CommitStage commitStage <- mkCommitStage(commitInput); +`ifdef RVFI + mkConnection(commitStage.rvfi, rvfi_bridge.rvfi); +`endif + // send rob enq time to reservation stations (* fire_when_enabled, no_implicit_conditions *) rule sendRobEnqTime; @@ -968,6 +989,10 @@ module mkCore#(CoreId coreId)(Core); interface checkStarted = nullGet; `endif endinterface + +`ifdef RVFI_DII + interface Toooba_RVFI_DII_Server rvfi_dii_server = rvfi_bridge.rvfi_dii_server; +`endif // rename debug interface CoreRenameDebug renameDebug; diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index 70be811..e07285f 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -355,6 +355,10 @@ module mkProc (Proc_IFC); interface Get trace_data_out = toGet (f_trace_data); `endif +`ifdef RVFI_DII + interface Toooba_RVFI_DII_Server rvfi_dii_server = core[0].rvfi_dii_server; +`endif + // ---------------- // Optional interface to Debug Module diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index 48e7f49..1fd6d68 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -24,6 +24,10 @@ import DM_CPU_Req_Rsp :: *; import TV_Info :: *; `endif +`ifdef RVFI_DII +import Types :: *; +`endif + // ================================================================ // CPU interface @@ -81,6 +85,10 @@ interface Proc_IFC; interface Get #(Trace_Data) trace_data_out; `endif +`ifdef RVFI_DII + interface Toooba_RVFI_DII_Server rvfi_dii_server; +`endif + // ---------------- // Optional interface to Debug Module diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 4272b1b..36af1f6 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -488,6 +488,10 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); endinterface `endif +`ifdef RVFI_DII + interface Toooba_RVFI_DII_Server rvfi_dii_server = proc.rvfi_dii_server; +`endif + // ---------------------------------------------------------------- // Optional DM interfaces diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv index 84b2968..83c33cc 100644 --- a/src_Core/Core/CoreW_IFC.bsv +++ b/src_Core/Core/CoreW_IFC.bsv @@ -40,6 +40,10 @@ import TV_Info :: *; import Debug_Module :: *; `endif +`ifdef RVFI_DII +import Types :: *; +`endif + // ================================================================ // The CoreW interface @@ -86,6 +90,10 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources); interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get; `endif +`ifdef RVFI_DII + interface Toooba_RVFI_DII_Server rvfi_dii_server; +`endif + // ---------------------------------------------------------------- // Optional Debug Module interfaces diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index dc142d3..b4638df 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -39,6 +39,10 @@ import StoreBuffer::*; import VerificationPacket::*; import RenameDebugIF::*; +`ifdef RVFI +import RVFI_DII :: *; +`endif + typedef struct { // info about the inst blocking at ROB head Addr pc; @@ -112,6 +116,10 @@ interface CommitStage; // rename debug method Action startRenameDebug; interface Get#(RenameErrInfo) renameErr; +`ifdef RVFI + // RVFI trace report. Not an input? + method Get#(Rvfi_Traces) rvfi; +`endif endinterface // we apply actions the end of commit rule @@ -122,8 +130,33 @@ typedef struct { Trap trap; } CommitTrap deriving(Bits, Eq, FShow); +`ifdef RVFI +function RVFI_DII_Execution#(DataSz,DataSz) genRVFI(ToReorderBuffer rot); + return RVFI_DII_Execution { + rvfi_order: 0, // Instruction number? InstID maybe? + rvfi_trap: isValid(rot.trap), + rvfi_halt: False, + rvfi_intr: ?, + rvfi_insn: rot.orig_inst, + rvfi_rs1_addr: rot.orig_inst[19:15], + rvfi_rs2_addr: rot.orig_inst[24:20], + rvfi_rs1_data: ?, + rvfi_rs2_data: ?, + rvfi_pc_rdata: rot.pc, + rvfi_pc_wdata: rot.pc + 4, + rvfi_mem_wdata: 0, + rvfi_rd_addr: rot.orig_inst[11:7], + rvfi_rd_wdata: ?, + rvfi_mem_addr: 0, + rvfi_mem_rmask: 0, + rvfi_mem_wmask: 0, + rvfi_mem_rdata: 0 + }; +endfunction +`endif + module mkCommitStage#(CommitInput inIfc)(CommitStage); - Bool verbose = False; + Bool verbose = True; // Bluespec: for lightweight verbosity trace Integer verbosity = 1; @@ -180,6 +213,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); Count#(Data) flushCacheCnt <- mkCount(0); `endif +`ifdef RVFI + // RVFI trace report. Not an input? + FIFO#(Rvfi_Traces) rvfiQ <- mkFIFO; +`endif + // deadlock check `ifdef CHECK_DEADLOCK // timer to check deadlock @@ -375,6 +413,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); $display ("CommitStage.doCommitTrap_flush: deq_data: ", fshow (x)); $display ("CommitStage.doCommitTrap_flush: commitTrap: ", fshow (commitTrap_val)); end +`ifdef RVFI + Rvfi_Traces rvfis = replicate(RVFI_DII_Execution{rvfi_order: -1}); + rvfis[0] = genRVFI(x); + rvfiQ.enq(rvfis); +`endif // flush everything. Only increment epoch and stall fetch when we haven // not done it yet (we may have already done them at rename stage) @@ -475,6 +518,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); " iType:", fshow (x.iType), " [doCommitSystemInst]"); rg_instret <= rg_instret + 1; end +`ifdef RVFI + Rvfi_Traces rvfis = replicate(RVFI_DII_Execution{rvfi_order: -1}); + rvfis[0] = genRVFI(x); + rvfiQ.enq(rvfis); +`endif // we claim a phy reg for every inst, so commit its renaming regRenamingTable.commit[0].commit; @@ -616,6 +664,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); SupCnt amoCnt = 0; `endif +`ifdef RVFI + Rvfi_Traces rvfis = replicate(RVFI_DII_Execution{rvfi_order: -1}); +`endif + Bit #(64) instret = 0; // compute what actions to take @@ -631,6 +683,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); end else begin if (verbose) $display("[doCommitNormalInst - %d] ", i, fshow(inst_tag), " ; ", fshow(x)); +`ifdef RVFI + rvfis[i] = genRVFI(x); +`endif if (verbosity > 0) begin $display("instret:%0d PC:0x%0h instr:0x%08h", rg_instret + instret, x.pc, x.orig_inst, @@ -733,6 +788,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); supComUserCnt.incr(1); end end +`endif +`ifdef RVFI + rvfiQ.enq(rvfis); `endif endrule @@ -766,6 +824,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); endcase); endmethod +`ifdef RVFI + method rvfi = toGet(rvfiQ); +`endif + `ifdef CHECK_DEADLOCK interface commitInstStuck = toGet(commitInstStuckQ); interface commitUserInstStuck = toGet(commitUserInstStuckQ); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index 7424031..c282cc5 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -31,6 +31,7 @@ import Connectable::*; import Decode::*; import Ehr::*; import Fifo::*; +import FIFOF::*; import GetPut::*; import MemoryTypes::*; import Types::*; @@ -48,6 +49,10 @@ import ITlb::*; import CCTypes::*; import L1CoCache::*; import MMIOInst::*; +`ifdef RVFI_DII +import RVFI_DII::*; +import Types::*; +`endif // ================================================================ // For fv_decode_C function and related types and definitions @@ -86,6 +91,9 @@ interface FetchStage; // debug method FetchDebugState getFetchState; +`ifdef RVFI_DII + interface Client#(Dii_Id, InstsAndIDs) dii; +`endif // performance interface Perf#(DecStagePerfType) perf; @@ -296,7 +304,7 @@ module mkFetchStage(FetchStage); // Fetch1 < Fetch3 to avoid bypassing path on PC and epochs Bool verbose = False; - Integer verbosity = 0; + Integer verbosity = 1; // Basic State Elements Reg#(Bool) started <- mkReg(False); @@ -324,10 +332,10 @@ module mkFetchStage(FetchStage); Reg#(Bool) decode_epoch <- mkReg(False); Reg#(Epoch) f_main_epoch <- mkReg(0); // fetch estimate of main epoch - // Regs to hold the first half of an instruction that straddles a cache line boundary - Reg #(Bool) rg_pending_straddle <- mkReg (False); - Reg #(Addr) rg_half_inst_pc <- mkRegU; // The PC of the straddling instruction - Reg #(Bit #(16)) rg_half_inst_lsbs <- mkRegU; // The 16 lsbs of the straddling instruction + // Regs to hold the first half of an instruction that straddles a cache line boundary + Reg #(Bool) rg_pending_straddle <- mkReg (False); + Reg #(Addr) rg_half_inst_pc <- mkRegU; // The PC of the straddling instruction + Reg #(Bit #(16)) rg_half_inst_lsbs <- mkRegU; // The 16 lsbs of the straddling instruction // Pipeline Stage FIFOs Fifo#(2, Tuple2#(Bit#(TLog#(SupSize)),Fetch1ToFetch2)) f12f2 <- mkCFFifo; @@ -385,6 +393,25 @@ module mkFetchStage(FetchStage); endrule `endif +`ifdef RVFI_DII + Fifo#(2, Dii_Id) dii_instIds <- mkCFFifo; + Fifo#(2, InstsAndIDs) dii_insts <- mkCFFifo; + FIFOF#(Dii_Id) flush_id <- mkUGFIFOF1; // Next sequence number to request when trapping + Reg#(Dii_Id) dii_id_next <- mkReg(0); + + rule feed_dii; + if (flush_id.notEmpty) begin + dii_instIds.enq(flush_id.first); + if (verbosity > 0) $display("Requested from %d DII", flush_id.first); + flush_id.deq; + end else begin + dii_instIds.enq(dii_id_next); + if (verbosity > 0) $display("Requested from %d DII", dii_id_next); + dii_id_next <= dii_id_next + 1; + end + endrule +`endif + // Predict the next fetch-PC based only on current PC (without // knowing the instructions). // Note: this chains calls to nextAddrPred. If this is a critical-path problem, @@ -509,11 +536,11 @@ module mkFetchStage(FetchStage); main_epoch: in.main_epoch }; f22f3.enq(tuple2(nbSup,out)); - if (verbosity > 0) begin - $display ("----------------"); - $display ("Fetch2: TLB response pyhs_pc 0x%0h cause ", phys_pc, fshow (cause)); - $display ("Fetch2: f2_tof3.enq: nbSup %0d out ", nbSup, fshow (out)); - end + if (verbosity > 0) begin + $display ("----------------"); + $display ("Fetch2: TLB response pyhs_pc 0x%0h cause ", phys_pc, fshow (cause)); + $display ("Fetch2: f2_tof3.enq: nbSup %0d out ", nbSup, fshow (out)); + end endrule // Break out of i$ @@ -521,7 +548,7 @@ module mkFetchStage(FetchStage); let {nbSup, fetch3In} = f22f3.first; f22f3.deq(); if (verbosity > 0) - $display("Fetch3: fetch3In: ", fshow (fetch3In)); + $display("Fetch3: fetch3In: ", fshow (fetch3In)); // Get ICache/MMIO response if no exception // In case of exception, we still need to process at least inst_data[0] @@ -538,6 +565,13 @@ module mkFetchStage(FetchStage); inst_d <- mem_server.response.get; end end + +`ifdef RVFI_DII + InstsAndIDs ii <- toGet(dii_insts).get(); + inst_d = ii.insts; + if (verbosity > 0) + $display("Got from DII: ", fshow (inst_d)); +`endif if (fetch3In.decode_epoch != decode_epoch) begin // Just drop it. @@ -945,5 +979,12 @@ module mkFetchStage(FetchStage); method Bool respValid = perfReqQ.notEmpty; `endif endinterface + +`ifdef RVFI_DII + interface Client dii; + interface Get request = toGet(dii_instIds); + interface Put response = toPut(dii_insts); + endinterface +`endif endmodule diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv index 8570554..b28d241 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv @@ -36,6 +36,7 @@ `define a True `define f True `define d True +`define c True //`define NUM_CORES 1 // defined in make file diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv index a3ce618..b1c6bc7 100644 --- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv @@ -99,7 +99,7 @@ typedef struct { instance DefaultValue#(RiscVISASubset); function RiscVISASubset defaultValue = RiscVISASubset { s: True, u: True, - m: `m , a: `a , f: `f , d: `d + m: `m , a: `a , f: `f , d: `d, c: `c }; endinstance diff --git a/src_Core/RISCY_OOO/procs/lib/Types.bsv b/src_Core/RISCY_OOO/procs/lib/Types.bsv index 5fc7855..e6f0a34 100644 --- a/src_Core/RISCY_OOO/procs/lib/Types.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Types.bsv @@ -21,8 +21,15 @@ // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. +`include "ProcConfig.bsv" + import Vector::*; import Assert::*; +import ClientServer::*; +import GetPut::*; +`ifdef RVFI_DII +import RVFI_DII_Types::*; +`endif typedef 64 AddrSz; typedef Bit#(AddrSz) Addr; @@ -71,3 +78,20 @@ function Action doAssert(Bool b, String s) = action if(!b) $fdisplay(stderr, "\n `else function Action doAssert(Bool b, String s) = dynamicAssert(b, s); `endif + +`ifdef RVFI_DII +typedef 8 SEQ_LEN; +typedef UInt#(SEQ_LEN) Dii_Id; +typedef Vector#(`sizeSup, RVFI_DII_Execution #(DataSz,DataSz)) Rvfi_Traces; + +typedef struct { + Vector#(`sizeSup, Maybe#(Instruction)) insts; + Vector#(`sizeSup, Dii_Id) ids; +} InstsAndIDs deriving(Bits, Eq, FShow); + +interface Toooba_RVFI_DII_Server; + interface Get#(Dii_Id) seqReq; + interface Put#(Tuple2#(Bit#(32), Dii_Id)) inst; + interface Get#(RVFI_DII_Execution#(DataSz, DataSz)) trace_report; +endinterface +`endif diff --git a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v index 71be41e..7aac7c0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v index b9fa4af..580b173 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v index e1e9a5b..a4c7e30 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkBht.v b/src_SSITH_P3/Verilog_RTL/mkBht.v index d689f0a..bbc0dff 100644 --- a/src_SSITH_P3/Verilog_RTL/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL/mkBht.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index c6c37b4..2e619cf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -4060,33 +4060,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - addr__h287289, - curData__h190139, - rVal1__h605870, - rVal1__h629405, - trap_val__h693220, - x__h194349; + addr__h287287, + curData__h190137, + rVal1__h605871, + rVal1__h629404, + trap_val__h693218, + x__h194347; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211, - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212, - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209, - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210, - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197, - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198, - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199, - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200, - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201, - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202, - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213, - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214, - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215, - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216, - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217, - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218, - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207, - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208, + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211, + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212, + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209, + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210, + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197, + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198, + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199, + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200, + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201, + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202, + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213, + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214, + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215, + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216, + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217, + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218, + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207, + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624, @@ -4098,45 +4098,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78, - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79, - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80, - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81, - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111, - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112, - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41, - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42, - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109, - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110, - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39, - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40, - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113, - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114, - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43, - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44, - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115, - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116, - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45, - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46, - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76, - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77, - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74, - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75, - _theResult___fst_sfd__h343285, - _theResult___fst_sfd__h352008, - _theResult___fst_sfd__h360590, - _theResult___fst_sfd__h369774, - _theResult___fst_sfd__h378410, - _theResult___fst_sfd__h388977, - _theResult___fst_sfd__h397698, - _theResult___fst_sfd__h406280, - _theResult___fst_sfd__h415464, - _theResult___fst_sfd__h424100, - _theResult___fst_sfd__h434665, - _theResult___fst_sfd__h443386, - _theResult___fst_sfd__h451968, - _theResult___fst_sfd__h461152, - _theResult___fst_sfd__h469788; + reg [22 : 0] CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78, + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79, + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80, + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81, + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111, + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112, + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41, + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42, + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109, + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110, + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39, + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40, + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113, + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114, + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43, + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44, + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115, + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116, + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45, + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46, + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76, + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77, + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74, + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75, + _theResult___fst_sfd__h343283, + _theResult___fst_sfd__h352006, + _theResult___fst_sfd__h360588, + _theResult___fst_sfd__h369772, + _theResult___fst_sfd__h378408, + _theResult___fst_sfd__h388975, + _theResult___fst_sfd__h397696, + _theResult___fst_sfd__h406278, + _theResult___fst_sfd__h415462, + _theResult___fst_sfd__h424098, + _theResult___fst_sfd__h434663, + _theResult___fst_sfd__h443384, + _theResult___fst_sfd__h451966, + _theResult___fst_sfd__h461150, + _theResult___fst_sfd__h469786; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4160,24 +4160,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203, - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204, - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205, - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206, - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175, - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176, - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177, - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178, - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179, - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180, - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152, - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153, - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183, - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184, - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181, - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182, - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135, - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136, + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203, + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204, + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205, + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206, + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175, + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176, + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177, + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178, + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179, + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180, + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152, + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153, + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183, + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184, + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181, + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182, + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135, + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553, @@ -4187,47 +4187,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790; - reg [7 : 0] CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67, - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68, - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72, - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73, - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96, - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97, - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26, - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27, - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94, - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95, - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24, - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25, - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102, - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103, - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32, - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33, - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107, - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108, - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37, - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38, - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61, - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62, - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59, - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60, + reg [7 : 0] CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67, + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68, + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72, + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73, + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96, + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97, + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26, + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27, + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94, + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95, + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24, + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25, + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102, + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103, + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32, + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33, + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107, + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108, + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37, + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38, + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61, + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62, + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59, + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h343284, - _theResult___fst_exp__h352007, - _theResult___fst_exp__h360589, - _theResult___fst_exp__h369773, - _theResult___fst_exp__h378409, - _theResult___fst_exp__h388976, - _theResult___fst_exp__h397697, - _theResult___fst_exp__h406279, - _theResult___fst_exp__h415463, - _theResult___fst_exp__h424099, - _theResult___fst_exp__h434664, - _theResult___fst_exp__h443385, - _theResult___fst_exp__h451967, - _theResult___fst_exp__h461151, - _theResult___fst_exp__h469787; + _theResult___fst_exp__h343282, + _theResult___fst_exp__h352005, + _theResult___fst_exp__h360587, + _theResult___fst_exp__h369771, + _theResult___fst_exp__h378407, + _theResult___fst_exp__h388974, + _theResult___fst_exp__h397695, + _theResult___fst_exp__h406277, + _theResult___fst_exp__h415461, + _theResult___fst_exp__h424097, + _theResult___fst_exp__h434662, + _theResult___fst_exp__h443383, + _theResult___fst_exp__h451965, + _theResult___fst_exp__h461149, + _theResult___fst_exp__h469785; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262, @@ -4245,8 +4245,8 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995, - i__h692204, - i__h692364; + i__h692202, + i__h692362; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266, @@ -4260,8 +4260,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695, - x__h283068, - x__h288838; + x__h283066, + x__h288836; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, @@ -4292,46 +4292,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, @@ -4448,152 +4448,152 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663, - _theResult___fst__h600261, - _theResult___snd__h600262, - a___1__h599980, - a___1__h600266, - a__h599839, + _theResult___fst__h600259, + _theResult___snd__h600260, + a___1__h599978, + a___1__h600264, + a__h599837, amoExec___d880, - b___1__h599981, - b___1__h600311, - b__h599840, - base__h694791, - base__h694994, - data___1__h472207, - data___1__h473015, - data__h472481, - fcsr_csr__read__h606148, - fflags_csr__read__h606123, - frm_csr__read__h606134, - mcause_csr__read__h607795, - mcounteren_csr__read__h607540, - medeleg_csr__read__h607140, - mideleg_csr__read__h607235, - mie_csr__read__h607366, - mip_csr__read__h608035, - mstatus_csr__read__h606992, - mtvec_csr__read__h607448, - n___1__h195752, - n__h191677, - n__read__h608139, - n__read__h608330, + b___1__h599979, + b___1__h600309, + b__h599838, + base__h694789, + base__h694992, + data___1__h472205, + data___1__h473013, + data__h472479, + fcsr_csr__read__h606149, + fflags_csr__read__h606124, + frm_csr__read__h606135, + mcause_csr__read__h607796, + mcounteren_csr__read__h607541, + medeleg_csr__read__h607141, + mideleg_csr__read__h607236, + mie_csr__read__h607367, + mip_csr__read__h608036, + mstatus_csr__read__h606993, + mtvec_csr__read__h607449, + n___1__h195750, + n__h191675, + n__read__h608140, + n__read__h608331, n__read__h6134, - n__read__h703199, - next_pc__h702542, - q___1__h473080, - rVal1__h478961, - rVal2__h478962, - r___1__h473106, - res_data__h335089, - res_data__h335094, - res_data__h380784, - res_data__h380789, - res_data__h426472, - res_data__h426477, - resp_addr__h289193, + n__read__h703197, + next_pc__h702540, + q___1__h473078, + rVal1__h478959, + rVal2__h478960, + r___1__h473104, + res_data__h335087, + res_data__h335092, + res_data__h380782, + res_data__h380787, + res_data__h426470, + res_data__h426475, + resp_addr__h289191, robdeqPort_0_deq_data_BITS_95_TO_32__q261, - satp_csr__read__h606849, - scause_csr__read__h606647, - scounteren_csr__read__h606509, - shiftData__h180516, - sie_csr__read__h606413, - sip_csr__read__h606786, - sstatus_csr__read__h606344, - stvec_csr__read__h606456, + satp_csr__read__h606850, + scause_csr__read__h606648, + scounteren_csr__read__h606510, + shiftData__h180514, + sie_csr__read__h606414, + sip_csr__read__h606787, + sstatus_csr__read__h606345, + stvec_csr__read__h606457, upd__h3639, upd__h4956, - v__h604754, - v__h628444, - vaddr__h180511, + v__h604755, + v__h628443, + vaddr__h180509, x__h152890, x__h156437, x__h159251, x__h161099, x__h17672, - x__h180425, - x__h180426, + x__h180423, + x__h180424, x__h20210, - x__h284513, - x__h286367, + x__h284511, + x__h286365, x__h45579, + x__h478868, + x__h478869, x__h478870, - x__h478871, - x__h478872, x__h48115, - x__h613033, x__h613034, - x__h634256, - x__h634257, - x__h688725, - x_addr__h311296, - x_quotient__h472395, - x_reg_ifc__read__h606253, - x_remainder__h472396, - y__h705650, - y_avValue__h179513, - y_avValue__h180119, - y_avValue__h476006, - y_avValue__h476614, - y_avValue__h477216, - y_avValue__h605660, - y_avValue__h610922, - y_avValue__h629197, - y_avValue__h632155, - y_avValue__h693067, - y_avValue__h694828, - y_avValue_snd_snd_snd_snd_snd__h705150, - y_avValue_snd_snd_snd_snd_snd__h705703, - y_avValue_snd_snd_snd_snd_snd__h705732; + x__h613035, + x__h634254, + x__h634255, + x__h688723, + x_addr__h311294, + x_quotient__h472393, + x_reg_ifc__read__h606254, + x_remainder__h472394, + y__h705648, + y_avValue__h179511, + y_avValue__h180117, + y_avValue__h476004, + y_avValue__h476612, + y_avValue__h477214, + y_avValue__h605661, + y_avValue__h610923, + y_avValue__h629196, + y_avValue__h632153, + y_avValue__h693065, + y_avValue__h694826, + y_avValue_snd_snd_snd_snd_snd__h705148, + y_avValue_snd_snd_snd_snd_snd__h705701, + y_avValue_snd_snd_snd_snd_snd__h705730; wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869, - r1__read__h608837, - r1__read__h609241, - r1__read__h609771, - r1__read__h609776, - r1__read__h609795, - r1__read__h610048, - r1__read__h610226, - r1__read__h610344, - r1__read__h610349, - r1__read__h610368; - wire [61 : 0] r1__read__h608839, - r1__read__h609243, - r1__read__h609778, - r1__read__h609797, - r1__read__h610050, - r1__read__h610202, - r1__read__h610228, - r1__read__h610351, - r1__read__h610370; - wire [60 : 0] r1__read__h610052, - r1__read__h610204, - r1__read__h610230, - r1__read__h610372; - wire [59 : 0] r1__read__h608841, - r1__read__h609245, - r1__read__h609789, - r1__read__h609799, - r1__read__h610054, - r1__read__h610232, - r1__read__h610362, - r1__read__h610374; - wire [58 : 0] r1__read__h608843, - r1__read__h609247, - r1__read__h609801, - r1__read__h610056, - r1__read__h610234, - r1__read__h610376; + r1__read__h608838, + r1__read__h609242, + r1__read__h609772, + r1__read__h609777, + r1__read__h609796, + r1__read__h610049, + r1__read__h610227, + r1__read__h610345, + r1__read__h610350, + r1__read__h610369; + wire [61 : 0] r1__read__h608840, + r1__read__h609244, + r1__read__h609779, + r1__read__h609798, + r1__read__h610051, + r1__read__h610203, + r1__read__h610229, + r1__read__h610352, + r1__read__h610371; + wire [60 : 0] r1__read__h610053, + r1__read__h610205, + r1__read__h610231, + r1__read__h610373; + wire [59 : 0] r1__read__h608842, + r1__read__h609246, + r1__read__h609790, + r1__read__h609800, + r1__read__h610055, + r1__read__h610233, + r1__read__h610363, + r1__read__h610375; + wire [58 : 0] r1__read__h608844, + r1__read__h609248, + r1__read__h609802, + r1__read__h610057, + r1__read__h610235, + r1__read__h610377; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - r1__read__h608845, - r1__read__h609249, - r1__read__h609803, - r1__read__h610058, - r1__read__h610206, - r1__read__h610236, - r1__read__h610378, - y__h252026; + r1__read__h608846, + r1__read__h609250, + r1__read__h609804, + r1__read__h610059, + r1__read__h610207, + r1__read__h610237, + r1__read__h610379, + y__h252024; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90, @@ -4621,187 +4621,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355, - _theResult____h343302, - _theResult____h360941, - _theResult____h388994, - _theResult____h406631, - _theResult____h434682, - _theResult____h452319, - _theResult____h500017, - _theResult____h538818, - _theResult____h578019, - _theResult___snd__h351424, + _theResult____h343300, + _theResult____h360939, + _theResult____h388992, + _theResult____h406629, + _theResult____h434680, + _theResult____h452317, + _theResult____h500015, + _theResult____h538816, + _theResult____h578017, + _theResult___snd__h351422, + _theResult___snd__h351433, _theResult___snd__h351435, - _theResult___snd__h351437, - _theResult___snd__h351447, - _theResult___snd__h351453, - _theResult___snd__h351476, + _theResult___snd__h351445, + _theResult___snd__h351451, + _theResult___snd__h351474, + _theResult___snd__h360018, _theResult___snd__h360020, - _theResult___snd__h360022, - _theResult___snd__h360029, - _theResult___snd__h360035, - _theResult___snd__h360058, - _theResult___snd__h369190, + _theResult___snd__h360027, + _theResult___snd__h360033, + _theResult___snd__h360056, + _theResult___snd__h369188, + _theResult___snd__h369199, _theResult___snd__h369201, - _theResult___snd__h369203, - _theResult___snd__h369213, - _theResult___snd__h369219, - _theResult___snd__h369242, - _theResult___snd__h377810, - _theResult___snd__h377824, - _theResult___snd__h377830, - _theResult___snd__h377848, - _theResult___snd__h397114, + _theResult___snd__h369211, + _theResult___snd__h369217, + _theResult___snd__h369240, + _theResult___snd__h377808, + _theResult___snd__h377822, + _theResult___snd__h377828, + _theResult___snd__h377846, + _theResult___snd__h397112, + _theResult___snd__h397123, _theResult___snd__h397125, - _theResult___snd__h397127, - _theResult___snd__h397137, - _theResult___snd__h397143, - _theResult___snd__h397166, + _theResult___snd__h397135, + _theResult___snd__h397141, + _theResult___snd__h397164, + _theResult___snd__h405708, _theResult___snd__h405710, - _theResult___snd__h405712, - _theResult___snd__h405719, - _theResult___snd__h405725, - _theResult___snd__h405748, - _theResult___snd__h414880, + _theResult___snd__h405717, + _theResult___snd__h405723, + _theResult___snd__h405746, + _theResult___snd__h414878, + _theResult___snd__h414889, _theResult___snd__h414891, - _theResult___snd__h414893, - _theResult___snd__h414903, - _theResult___snd__h414909, - _theResult___snd__h414932, - _theResult___snd__h423500, - _theResult___snd__h423514, - _theResult___snd__h423520, - _theResult___snd__h423538, - _theResult___snd__h442802, + _theResult___snd__h414901, + _theResult___snd__h414907, + _theResult___snd__h414930, + _theResult___snd__h423498, + _theResult___snd__h423512, + _theResult___snd__h423518, + _theResult___snd__h423536, + _theResult___snd__h442800, + _theResult___snd__h442811, _theResult___snd__h442813, - _theResult___snd__h442815, - _theResult___snd__h442825, - _theResult___snd__h442831, - _theResult___snd__h442854, + _theResult___snd__h442823, + _theResult___snd__h442829, + _theResult___snd__h442852, + _theResult___snd__h451396, _theResult___snd__h451398, - _theResult___snd__h451400, - _theResult___snd__h451407, - _theResult___snd__h451413, - _theResult___snd__h451436, - _theResult___snd__h460568, + _theResult___snd__h451405, + _theResult___snd__h451411, + _theResult___snd__h451434, + _theResult___snd__h460566, + _theResult___snd__h460577, _theResult___snd__h460579, - _theResult___snd__h460581, - _theResult___snd__h460591, - _theResult___snd__h460597, - _theResult___snd__h460620, - _theResult___snd__h469188, - _theResult___snd__h469202, - _theResult___snd__h469208, - _theResult___snd__h469226, + _theResult___snd__h460589, + _theResult___snd__h460595, + _theResult___snd__h460618, + _theResult___snd__h469186, + _theResult___snd__h469200, + _theResult___snd__h469206, + _theResult___snd__h469224, + _theResult___snd__h498625, _theResult___snd__h498627, - _theResult___snd__h498629, - _theResult___snd__h498636, - _theResult___snd__h498642, - _theResult___snd__h498665, - _theResult___snd__h508264, + _theResult___snd__h498634, + _theResult___snd__h498640, + _theResult___snd__h498663, + _theResult___snd__h508262, + _theResult___snd__h508273, _theResult___snd__h508275, - _theResult___snd__h508277, - _theResult___snd__h508287, - _theResult___snd__h508293, - _theResult___snd__h508316, - _theResult___snd__h517032, - _theResult___snd__h517046, - _theResult___snd__h517052, - _theResult___snd__h517070, + _theResult___snd__h508285, + _theResult___snd__h508291, + _theResult___snd__h508314, + _theResult___snd__h517030, + _theResult___snd__h517044, + _theResult___snd__h517050, + _theResult___snd__h517068, + _theResult___snd__h537426, _theResult___snd__h537428, - _theResult___snd__h537430, - _theResult___snd__h537437, - _theResult___snd__h537443, - _theResult___snd__h537466, - _theResult___snd__h547065, + _theResult___snd__h537435, + _theResult___snd__h537441, + _theResult___snd__h537464, + _theResult___snd__h547063, + _theResult___snd__h547074, _theResult___snd__h547076, - _theResult___snd__h547078, - _theResult___snd__h547088, - _theResult___snd__h547094, - _theResult___snd__h547117, - _theResult___snd__h555833, - _theResult___snd__h555847, - _theResult___snd__h555853, - _theResult___snd__h555871, + _theResult___snd__h547086, + _theResult___snd__h547092, + _theResult___snd__h547115, + _theResult___snd__h555831, + _theResult___snd__h555845, + _theResult___snd__h555851, + _theResult___snd__h555869, + _theResult___snd__h576627, _theResult___snd__h576629, - _theResult___snd__h576631, - _theResult___snd__h576638, - _theResult___snd__h576644, - _theResult___snd__h576667, - _theResult___snd__h586266, + _theResult___snd__h576636, + _theResult___snd__h576642, + _theResult___snd__h576665, + _theResult___snd__h586264, + _theResult___snd__h586275, _theResult___snd__h586277, - _theResult___snd__h586279, - _theResult___snd__h586289, - _theResult___snd__h586295, - _theResult___snd__h586318, - _theResult___snd__h595034, - _theResult___snd__h595048, - _theResult___snd__h595054, - _theResult___snd__h595072, - r1__read__h610060, - r1__read__h610208, - r1__read__h610238, - r1__read__h610380, - result__h361554, - result__h407244, - result__h452932, - result__h500630, - result__h539431, - result__h578632, - sfd__h335697, - sfd__h381392, - sfd__h427080, - sfd__h479675, - sfd__h518617, - sfd__h557818, - sfdin__h351407, - sfdin__h369173, - sfdin__h397097, - sfdin__h414863, - sfdin__h442785, - sfdin__h460551, - sfdin__h508247, - sfdin__h547048, - sfdin__h586249, - x__h361651, - x__h407341, - x__h453029, - x__h500725, - x__h539526, - x__h578727; - wire [55 : 0] r1__read__h608847, - r1__read__h609251, - r1__read__h609805, - r1__read__h610062, - r1__read__h610240, - r1__read__h610382; - wire [54 : 0] r1__read__h608849, - r1__read__h609253, - r1__read__h609807, - r1__read__h610064, - r1__read__h610242, - r1__read__h610384; - wire [53 : 0] r1__read__h610185, - r1__read__h610210, - r1__read__h610244, - r1__read__h610386, - sfd__h498694, - sfd__h508345, - sfd__h517105, - sfd__h537495, - sfd__h547146, - sfd__h555906, - sfd__h576696, - sfd__h586347, - sfd__h595107, - value__h343924, - value__h389614, - value__h435302; - wire [52 : 0] r1__read__h610066, - r1__read__h610187, - r1__read__h610212, - r1__read__h610246, - r1__read__h610388; + _theResult___snd__h586287, + _theResult___snd__h586293, + _theResult___snd__h586316, + _theResult___snd__h595032, + _theResult___snd__h595046, + _theResult___snd__h595052, + _theResult___snd__h595070, + r1__read__h610061, + r1__read__h610209, + r1__read__h610239, + r1__read__h610381, + result__h361552, + result__h407242, + result__h452930, + result__h500628, + result__h539429, + result__h578630, + sfd__h335695, + sfd__h381390, + sfd__h427078, + sfd__h479673, + sfd__h518615, + sfd__h557816, + sfdin__h351405, + sfdin__h369171, + sfdin__h397095, + sfdin__h414861, + sfdin__h442783, + sfdin__h460549, + sfdin__h508245, + sfdin__h547046, + sfdin__h586247, + x__h361649, + x__h407339, + x__h453027, + x__h500723, + x__h539524, + x__h578725; + wire [55 : 0] r1__read__h608848, + r1__read__h609252, + r1__read__h609806, + r1__read__h610063, + r1__read__h610241, + r1__read__h610383; + wire [54 : 0] r1__read__h608850, + r1__read__h609254, + r1__read__h609808, + r1__read__h610065, + r1__read__h610243, + r1__read__h610385; + wire [53 : 0] r1__read__h610186, + r1__read__h610211, + r1__read__h610245, + r1__read__h610387, + sfd__h498692, + sfd__h508343, + sfd__h517103, + sfd__h537493, + sfd__h547144, + sfd__h555904, + sfd__h576694, + sfd__h586345, + sfd__h595105, + value__h343922, + value__h389612, + value__h435300; + wire [52 : 0] r1__read__h610067, + r1__read__h610188, + r1__read__h610213, + r1__read__h610247, + r1__read__h610389; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132, @@ -4820,110 +4820,110 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857, - _theResult___fst_sfd__h483604, - _theResult___fst_sfd__h499432, - _theResult___fst_sfd__h499435, - _theResult___fst_sfd__h509083, - _theResult___fst_sfd__h509086, - _theResult___fst_sfd__h517867, - _theResult___fst_sfd__h517870, - _theResult___fst_sfd__h517879, - _theResult___fst_sfd__h517885, - _theResult___fst_sfd__h522405, - _theResult___fst_sfd__h538233, - _theResult___fst_sfd__h538236, - _theResult___fst_sfd__h547884, - _theResult___fst_sfd__h547887, - _theResult___fst_sfd__h556668, - _theResult___fst_sfd__h556671, - _theResult___fst_sfd__h556680, - _theResult___fst_sfd__h556686, - _theResult___fst_sfd__h561606, - _theResult___fst_sfd__h577434, - _theResult___fst_sfd__h577437, - _theResult___fst_sfd__h587085, - _theResult___fst_sfd__h587088, - _theResult___fst_sfd__h595869, - _theResult___fst_sfd__h595872, - _theResult___fst_sfd__h595881, - _theResult___fst_sfd__h595887, - _theResult___sfd__h499332, - _theResult___sfd__h508983, - _theResult___sfd__h517767, - _theResult___sfd__h538133, - _theResult___sfd__h547784, - _theResult___sfd__h556568, - _theResult___sfd__h577334, - _theResult___sfd__h586985, - _theResult___sfd__h595769, - _theResult___snd_fst_sfd__h479629, - _theResult___snd_fst_sfd__h499438, - _theResult___snd_fst_sfd__h517873, - _theResult___snd_fst_sfd__h518571, - _theResult___snd_fst_sfd__h538239, - _theResult___snd_fst_sfd__h556674, - _theResult___snd_fst_sfd__h557772, - _theResult___snd_fst_sfd__h577440, - _theResult___snd_fst_sfd__h595875, - out___1_sfd__h479378, - out___1_sfd__h518320, - out___1_sfd__h557521, - out_sfd__h499335, - out_sfd__h508986, - out_sfd__h517770, - out_sfd__h538136, - out_sfd__h547787, - out_sfd__h556571, - out_sfd__h577337, - out_sfd__h586988, - out_sfd__h595772, - r1__read__h610390; - wire [50 : 0] r1__read__h608851, r1__read__h610068; - wire [49 : 0] r1__read__h610189, r1__read__h610392; - wire [48 : 0] r1__read__h608853, r1__read__h610070, r1__read__h610191; - wire [46 : 0] r1__read__h608855, r1__read__h610072; - wire [45 : 0] r1__read__h608857, r1__read__h610074; - wire [44 : 0] r1__read__h608859, r1__read__h610076; - wire [43 : 0] r1__read__h608861, r1__read__h610078; - wire [42 : 0] r1__read__h610080; - wire [41 : 0] r1__read__h610082; - wire [40 : 0] r1__read__h610084; + _theResult___fst_sfd__h483602, + _theResult___fst_sfd__h499430, + _theResult___fst_sfd__h499433, + _theResult___fst_sfd__h509081, + _theResult___fst_sfd__h509084, + _theResult___fst_sfd__h517865, + _theResult___fst_sfd__h517868, + _theResult___fst_sfd__h517877, + _theResult___fst_sfd__h517883, + _theResult___fst_sfd__h522403, + _theResult___fst_sfd__h538231, + _theResult___fst_sfd__h538234, + _theResult___fst_sfd__h547882, + _theResult___fst_sfd__h547885, + _theResult___fst_sfd__h556666, + _theResult___fst_sfd__h556669, + _theResult___fst_sfd__h556678, + _theResult___fst_sfd__h556684, + _theResult___fst_sfd__h561604, + _theResult___fst_sfd__h577432, + _theResult___fst_sfd__h577435, + _theResult___fst_sfd__h587083, + _theResult___fst_sfd__h587086, + _theResult___fst_sfd__h595867, + _theResult___fst_sfd__h595870, + _theResult___fst_sfd__h595879, + _theResult___fst_sfd__h595885, + _theResult___sfd__h499330, + _theResult___sfd__h508981, + _theResult___sfd__h517765, + _theResult___sfd__h538131, + _theResult___sfd__h547782, + _theResult___sfd__h556566, + _theResult___sfd__h577332, + _theResult___sfd__h586983, + _theResult___sfd__h595767, + _theResult___snd_fst_sfd__h479627, + _theResult___snd_fst_sfd__h499436, + _theResult___snd_fst_sfd__h517871, + _theResult___snd_fst_sfd__h518569, + _theResult___snd_fst_sfd__h538237, + _theResult___snd_fst_sfd__h556672, + _theResult___snd_fst_sfd__h557770, + _theResult___snd_fst_sfd__h577438, + _theResult___snd_fst_sfd__h595873, + out___1_sfd__h479376, + out___1_sfd__h518318, + out___1_sfd__h557519, + out_sfd__h499333, + out_sfd__h508984, + out_sfd__h517768, + out_sfd__h538134, + out_sfd__h547785, + out_sfd__h556569, + out_sfd__h577335, + out_sfd__h586986, + out_sfd__h595770, + r1__read__h610391; + wire [50 : 0] r1__read__h608852, r1__read__h610069; + wire [49 : 0] r1__read__h610190, r1__read__h610393; + wire [48 : 0] r1__read__h608854, r1__read__h610071, r1__read__h610192; + wire [46 : 0] r1__read__h608856, r1__read__h610073; + wire [45 : 0] r1__read__h608858, r1__read__h610075; + wire [44 : 0] r1__read__h608860, r1__read__h610077; + wire [43 : 0] r1__read__h608862, r1__read__h610079; + wire [42 : 0] r1__read__h610081; + wire [41 : 0] r1__read__h610083; + wire [40 : 0] r1__read__h610085; wire [37 : 0] IF_fetchStage_pipelines_0_first__2605_BIT_160__ETC___d13871, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4, - data72481_BITS_31_TO_0__q5, - imm__h649454, - r1__read__h608863, - r1__read__h610086, - x__h190902, - x__h335101, - x__h380796, - x__h426484, + data72479_BITS_31_TO_0__q5, + imm__h649452, + r1__read__h608864, + r1__read__h610087, + x__h190900, + x__h335099, + x__h380794, + x__h426482, x__h75524, x_data__h65373, - x_data_imm__h667949, - x_data_imm__h682692; - wire [29 : 0] r1__read__h608865, r1__read__h610088; - wire [27 : 0] r1__read__h610090; + x_data_imm__h667947, + x_data_imm__h682690; + wire [29 : 0] r1__read__h608866, r1__read__h610089; + wire [27 : 0] r1__read__h610091; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13903, - sfd__h351505, - sfd__h360087, - sfd__h369271, - sfd__h377883, - sfd__h397195, - sfd__h405777, - sfd__h414961, - sfd__h423573, - sfd__h442883, - sfd__h451465, - sfd__h460649, - sfd__h469261, - value__h484233, - value__h523034, - value__h562235; + sfd__h351503, + sfd__h360085, + sfd__h369269, + sfd__h377881, + sfd__h397193, + sfd__h405775, + sfd__h414959, + sfd__h423571, + sfd__h442881, + sfd__h451463, + sfd__h460647, + sfd__h469259, + value__h484231, + value__h523032, + value__h562233; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345, @@ -4948,72 +4948,72 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804, - _theResult___fst_sfd__h352011, - _theResult___fst_sfd__h360593, - _theResult___fst_sfd__h369777, - _theResult___fst_sfd__h378413, - _theResult___fst_sfd__h378422, - _theResult___fst_sfd__h378428, - _theResult___fst_sfd__h397701, - _theResult___fst_sfd__h406283, - _theResult___fst_sfd__h415467, - _theResult___fst_sfd__h424103, - _theResult___fst_sfd__h424112, - _theResult___fst_sfd__h424118, - _theResult___fst_sfd__h443389, - _theResult___fst_sfd__h451971, - _theResult___fst_sfd__h461155, - _theResult___fst_sfd__h469791, - _theResult___fst_sfd__h469800, - _theResult___fst_sfd__h469806, - _theResult___sfd__h351930, - _theResult___sfd__h360512, - _theResult___sfd__h369696, - _theResult___sfd__h378332, - _theResult___sfd__h378434, - _theResult___sfd__h397620, - _theResult___sfd__h406202, - _theResult___sfd__h415386, - _theResult___sfd__h424022, - _theResult___sfd__h424124, - _theResult___sfd__h443308, - _theResult___sfd__h451890, - _theResult___sfd__h461074, - _theResult___sfd__h469710, - _theResult___sfd__h469812, - _theResult___snd_fst_sfd__h335647, - _theResult___snd_fst_sfd__h360596, - _theResult___snd_fst_sfd__h378416, - _theResult___snd_fst_sfd__h381342, - _theResult___snd_fst_sfd__h406286, - _theResult___snd_fst_sfd__h424106, - _theResult___snd_fst_sfd__h427030, - _theResult___snd_fst_sfd__h451974, - _theResult___snd_fst_sfd__h469794, - out_f_sfd__h378711, - out_f_sfd__h424401, - out_f_sfd__h470089, - out_sfd__h351933, - out_sfd__h360515, - out_sfd__h369699, - out_sfd__h378335, - out_sfd__h397623, - out_sfd__h406205, - out_sfd__h415389, - out_sfd__h424025, - out_sfd__h443311, - out_sfd__h451893, - out_sfd__h461077, - out_sfd__h469713; - wire [19 : 0] r1__read__h610025; + _theResult___fst_sfd__h352009, + _theResult___fst_sfd__h360591, + _theResult___fst_sfd__h369775, + _theResult___fst_sfd__h378411, + _theResult___fst_sfd__h378420, + _theResult___fst_sfd__h378426, + _theResult___fst_sfd__h397699, + _theResult___fst_sfd__h406281, + _theResult___fst_sfd__h415465, + _theResult___fst_sfd__h424101, + _theResult___fst_sfd__h424110, + _theResult___fst_sfd__h424116, + _theResult___fst_sfd__h443387, + _theResult___fst_sfd__h451969, + _theResult___fst_sfd__h461153, + _theResult___fst_sfd__h469789, + _theResult___fst_sfd__h469798, + _theResult___fst_sfd__h469804, + _theResult___sfd__h351928, + _theResult___sfd__h360510, + _theResult___sfd__h369694, + _theResult___sfd__h378330, + _theResult___sfd__h378432, + _theResult___sfd__h397618, + _theResult___sfd__h406200, + _theResult___sfd__h415384, + _theResult___sfd__h424020, + _theResult___sfd__h424122, + _theResult___sfd__h443306, + _theResult___sfd__h451888, + _theResult___sfd__h461072, + _theResult___sfd__h469708, + _theResult___sfd__h469810, + _theResult___snd_fst_sfd__h335645, + _theResult___snd_fst_sfd__h360594, + _theResult___snd_fst_sfd__h378414, + _theResult___snd_fst_sfd__h381340, + _theResult___snd_fst_sfd__h406284, + _theResult___snd_fst_sfd__h424104, + _theResult___snd_fst_sfd__h427028, + _theResult___snd_fst_sfd__h451972, + _theResult___snd_fst_sfd__h469792, + out_f_sfd__h378709, + out_f_sfd__h424399, + out_f_sfd__h470087, + out_sfd__h351931, + out_sfd__h360513, + out_sfd__h369697, + out_sfd__h378333, + out_sfd__h397621, + out_sfd__h406203, + out_sfd__h415387, + out_sfd__h424023, + out_sfd__h443309, + out_sfd__h451891, + out_sfd__h461075, + out_sfd__h469711; + wire [19 : 0] r1__read__h610026; wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674, - _theResult____h645398, - enabled_ints___1__h645895, - enabled_ints__h645942, - pend_ints__h645396, - y__h645907; + _theResult____h645396, + enabled_ints___1__h645893, + enabled_ints__h645940, + pend_ints__h645394, + y__h645905; wire [12 : 0] fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - r1__read_BITS_12_TO_0___h645918; + r1__read_BITS_12_TO_0___h645916; wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648, @@ -5043,24 +5043,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334, - renaming_spec_bits__h675348, - result__h641105, - result__h641156, - spec_bits__h678443, - w__h641100, - x__h361684, - x__h407374, - x__h453062, - x__h500758, - x__h539559, - x__h578760, - x__h641104, - x__h641155, - y__h641134, - y__h678456, - y_avValue_fst__h671840, - y_avValue_snd_fst__h672114, - y_avValue_snd_fst__h672149; + renaming_spec_bits__h675346, + result__h641103, + result__h641154, + spec_bits__h678441, + w__h641098, + x__h361682, + x__h407372, + x__h453060, + x__h500756, + x__h539557, + x__h578758, + x__h641102, + x__h641153, + y__h641132, + y__h678454, + y_avValue_fst__h671838, + y_avValue_snd_fst__h672112, + y_avValue_snd_fst__h672147; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048, @@ -5082,103 +5082,103 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172, - _theResult___exp__h499331, - _theResult___exp__h508982, - _theResult___exp__h517766, - _theResult___exp__h538132, - _theResult___exp__h547783, - _theResult___exp__h556567, - _theResult___exp__h577333, - _theResult___exp__h586984, - _theResult___exp__h595768, - _theResult___fst_exp__h483603, - _theResult___fst_exp__h498667, - _theResult___fst_exp__h498673, - _theResult___fst_exp__h498676, - _theResult___fst_exp__h499431, - _theResult___fst_exp__h499434, - _theResult___fst_exp__h508253, - _theResult___fst_exp__h508318, - _theResult___fst_exp__h508324, - _theResult___fst_exp__h508327, - _theResult___fst_exp__h509082, - _theResult___fst_exp__h509085, - _theResult___fst_exp__h517038, - _theResult___fst_exp__h517077, - _theResult___fst_exp__h517083, - _theResult___fst_exp__h517086, - _theResult___fst_exp__h517866, - _theResult___fst_exp__h517869, - _theResult___fst_exp__h517878, - _theResult___fst_exp__h517881, - _theResult___fst_exp__h522404, - _theResult___fst_exp__h537468, - _theResult___fst_exp__h537474, - _theResult___fst_exp__h537477, - _theResult___fst_exp__h538232, - _theResult___fst_exp__h538235, - _theResult___fst_exp__h547054, - _theResult___fst_exp__h547119, - _theResult___fst_exp__h547125, - _theResult___fst_exp__h547128, - _theResult___fst_exp__h547883, - _theResult___fst_exp__h547886, - _theResult___fst_exp__h555839, - _theResult___fst_exp__h555878, - _theResult___fst_exp__h555884, - _theResult___fst_exp__h555887, - _theResult___fst_exp__h556667, - _theResult___fst_exp__h556670, - _theResult___fst_exp__h556679, - _theResult___fst_exp__h556682, - _theResult___fst_exp__h561605, - _theResult___fst_exp__h576669, - _theResult___fst_exp__h576675, - _theResult___fst_exp__h576678, - _theResult___fst_exp__h577433, - _theResult___fst_exp__h577436, - _theResult___fst_exp__h586255, - _theResult___fst_exp__h586320, - _theResult___fst_exp__h586326, - _theResult___fst_exp__h586329, - _theResult___fst_exp__h587084, - _theResult___fst_exp__h587087, - _theResult___fst_exp__h595040, - _theResult___fst_exp__h595079, - _theResult___fst_exp__h595085, - _theResult___fst_exp__h595088, - _theResult___fst_exp__h595868, - _theResult___fst_exp__h595871, - _theResult___fst_exp__h595880, - _theResult___fst_exp__h595883, - _theResult___snd_fst_exp__h499437, - _theResult___snd_fst_exp__h517872, - _theResult___snd_fst_exp__h538238, - _theResult___snd_fst_exp__h556673, - _theResult___snd_fst_exp__h577439, - _theResult___snd_fst_exp__h595874, + _theResult___exp__h499329, + _theResult___exp__h508980, + _theResult___exp__h517764, + _theResult___exp__h538130, + _theResult___exp__h547781, + _theResult___exp__h556565, + _theResult___exp__h577331, + _theResult___exp__h586982, + _theResult___exp__h595766, + _theResult___fst_exp__h483601, + _theResult___fst_exp__h498665, + _theResult___fst_exp__h498671, + _theResult___fst_exp__h498674, + _theResult___fst_exp__h499429, + _theResult___fst_exp__h499432, + _theResult___fst_exp__h508251, + _theResult___fst_exp__h508316, + _theResult___fst_exp__h508322, + _theResult___fst_exp__h508325, + _theResult___fst_exp__h509080, + _theResult___fst_exp__h509083, + _theResult___fst_exp__h517036, + _theResult___fst_exp__h517075, + _theResult___fst_exp__h517081, + _theResult___fst_exp__h517084, + _theResult___fst_exp__h517864, + _theResult___fst_exp__h517867, + _theResult___fst_exp__h517876, + _theResult___fst_exp__h517879, + _theResult___fst_exp__h522402, + _theResult___fst_exp__h537466, + _theResult___fst_exp__h537472, + _theResult___fst_exp__h537475, + _theResult___fst_exp__h538230, + _theResult___fst_exp__h538233, + _theResult___fst_exp__h547052, + _theResult___fst_exp__h547117, + _theResult___fst_exp__h547123, + _theResult___fst_exp__h547126, + _theResult___fst_exp__h547881, + _theResult___fst_exp__h547884, + _theResult___fst_exp__h555837, + _theResult___fst_exp__h555876, + _theResult___fst_exp__h555882, + _theResult___fst_exp__h555885, + _theResult___fst_exp__h556665, + _theResult___fst_exp__h556668, + _theResult___fst_exp__h556677, + _theResult___fst_exp__h556680, + _theResult___fst_exp__h561603, + _theResult___fst_exp__h576667, + _theResult___fst_exp__h576673, + _theResult___fst_exp__h576676, + _theResult___fst_exp__h577431, + _theResult___fst_exp__h577434, + _theResult___fst_exp__h586253, + _theResult___fst_exp__h586318, + _theResult___fst_exp__h586324, + _theResult___fst_exp__h586327, + _theResult___fst_exp__h587082, + _theResult___fst_exp__h587085, + _theResult___fst_exp__h595038, + _theResult___fst_exp__h595077, + _theResult___fst_exp__h595083, + _theResult___fst_exp__h595086, + _theResult___fst_exp__h595866, + _theResult___fst_exp__h595869, + _theResult___fst_exp__h595878, + _theResult___fst_exp__h595881, + _theResult___snd_fst_exp__h499435, + _theResult___snd_fst_exp__h517870, + _theResult___snd_fst_exp__h538236, + _theResult___snd_fst_exp__h556671, + _theResult___snd_fst_exp__h577437, + _theResult___snd_fst_exp__h595872, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98, csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, - din_inc___2_exp__h517926, - din_inc___2_exp__h517961, - din_inc___2_exp__h517987, - din_inc___2_exp__h556727, - din_inc___2_exp__h556762, - din_inc___2_exp__h556788, - din_inc___2_exp__h595928, - din_inc___2_exp__h595963, - din_inc___2_exp__h595989, - out_exp__h499334, - out_exp__h508985, - out_exp__h517769, - out_exp__h538135, - out_exp__h547786, - out_exp__h556570, - out_exp__h577336, - out_exp__h586987, - out_exp__h595771; + din_inc___2_exp__h517924, + din_inc___2_exp__h517959, + din_inc___2_exp__h517985, + din_inc___2_exp__h556725, + din_inc___2_exp__h556760, + din_inc___2_exp__h556786, + din_inc___2_exp__h595926, + din_inc___2_exp__h595961, + din_inc___2_exp__h595987, + out_exp__h499332, + out_exp__h508983, + out_exp__h517767, + out_exp__h538133, + out_exp__h547784, + out_exp__h556568, + out_exp__h577334, + out_exp__h586985, + out_exp__h595769; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652; @@ -5209,121 +5209,121 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104, - _theResult___exp__h351929, - _theResult___exp__h360511, - _theResult___exp__h369695, - _theResult___exp__h378331, - _theResult___exp__h378433, - _theResult___exp__h397619, - _theResult___exp__h406201, - _theResult___exp__h415385, - _theResult___exp__h424021, - _theResult___exp__h424123, - _theResult___exp__h443307, - _theResult___exp__h451889, - _theResult___exp__h461073, - _theResult___exp__h469709, - _theResult___exp__h469811, - _theResult___fst_exp__h351413, - _theResult___fst_exp__h351478, - _theResult___fst_exp__h351484, - _theResult___fst_exp__h351487, - _theResult___fst_exp__h352010, - _theResult___fst_exp__h360060, - _theResult___fst_exp__h360066, - _theResult___fst_exp__h360069, - _theResult___fst_exp__h360592, - _theResult___fst_exp__h369179, - _theResult___fst_exp__h369244, - _theResult___fst_exp__h369250, - _theResult___fst_exp__h369253, - _theResult___fst_exp__h369776, - _theResult___fst_exp__h377816, - _theResult___fst_exp__h377855, - _theResult___fst_exp__h377861, - _theResult___fst_exp__h377864, - _theResult___fst_exp__h378412, - _theResult___fst_exp__h378421, - _theResult___fst_exp__h378424, - _theResult___fst_exp__h397103, - _theResult___fst_exp__h397168, - _theResult___fst_exp__h397174, - _theResult___fst_exp__h397177, - _theResult___fst_exp__h397700, - _theResult___fst_exp__h405750, - _theResult___fst_exp__h405756, - _theResult___fst_exp__h405759, - _theResult___fst_exp__h406282, - _theResult___fst_exp__h414869, - _theResult___fst_exp__h414934, - _theResult___fst_exp__h414940, - _theResult___fst_exp__h414943, - _theResult___fst_exp__h415466, - _theResult___fst_exp__h423506, - _theResult___fst_exp__h423545, - _theResult___fst_exp__h423551, - _theResult___fst_exp__h423554, - _theResult___fst_exp__h424102, - _theResult___fst_exp__h424111, - _theResult___fst_exp__h424114, - _theResult___fst_exp__h442791, - _theResult___fst_exp__h442856, - _theResult___fst_exp__h442862, - _theResult___fst_exp__h442865, - _theResult___fst_exp__h443388, - _theResult___fst_exp__h451438, - _theResult___fst_exp__h451444, - _theResult___fst_exp__h451447, - _theResult___fst_exp__h451970, - _theResult___fst_exp__h460557, - _theResult___fst_exp__h460622, - _theResult___fst_exp__h460628, - _theResult___fst_exp__h460631, - _theResult___fst_exp__h461154, - _theResult___fst_exp__h469194, - _theResult___fst_exp__h469233, - _theResult___fst_exp__h469239, - _theResult___fst_exp__h469242, - _theResult___fst_exp__h469790, - _theResult___fst_exp__h469799, - _theResult___fst_exp__h469802, - _theResult___snd_fst_exp__h360595, - _theResult___snd_fst_exp__h378415, - _theResult___snd_fst_exp__h406285, - _theResult___snd_fst_exp__h424105, - _theResult___snd_fst_exp__h451973, - _theResult___snd_fst_exp__h469793, + _theResult___exp__h351927, + _theResult___exp__h360509, + _theResult___exp__h369693, + _theResult___exp__h378329, + _theResult___exp__h378431, + _theResult___exp__h397617, + _theResult___exp__h406199, + _theResult___exp__h415383, + _theResult___exp__h424019, + _theResult___exp__h424121, + _theResult___exp__h443305, + _theResult___exp__h451887, + _theResult___exp__h461071, + _theResult___exp__h469707, + _theResult___exp__h469809, + _theResult___fst_exp__h351411, + _theResult___fst_exp__h351476, + _theResult___fst_exp__h351482, + _theResult___fst_exp__h351485, + _theResult___fst_exp__h352008, + _theResult___fst_exp__h360058, + _theResult___fst_exp__h360064, + _theResult___fst_exp__h360067, + _theResult___fst_exp__h360590, + _theResult___fst_exp__h369177, + _theResult___fst_exp__h369242, + _theResult___fst_exp__h369248, + _theResult___fst_exp__h369251, + _theResult___fst_exp__h369774, + _theResult___fst_exp__h377814, + _theResult___fst_exp__h377853, + _theResult___fst_exp__h377859, + _theResult___fst_exp__h377862, + _theResult___fst_exp__h378410, + _theResult___fst_exp__h378419, + _theResult___fst_exp__h378422, + _theResult___fst_exp__h397101, + _theResult___fst_exp__h397166, + _theResult___fst_exp__h397172, + _theResult___fst_exp__h397175, + _theResult___fst_exp__h397698, + _theResult___fst_exp__h405748, + _theResult___fst_exp__h405754, + _theResult___fst_exp__h405757, + _theResult___fst_exp__h406280, + _theResult___fst_exp__h414867, + _theResult___fst_exp__h414932, + _theResult___fst_exp__h414938, + _theResult___fst_exp__h414941, + _theResult___fst_exp__h415464, + _theResult___fst_exp__h423504, + _theResult___fst_exp__h423543, + _theResult___fst_exp__h423549, + _theResult___fst_exp__h423552, + _theResult___fst_exp__h424100, + _theResult___fst_exp__h424109, + _theResult___fst_exp__h424112, + _theResult___fst_exp__h442789, + _theResult___fst_exp__h442854, + _theResult___fst_exp__h442860, + _theResult___fst_exp__h442863, + _theResult___fst_exp__h443386, + _theResult___fst_exp__h451436, + _theResult___fst_exp__h451442, + _theResult___fst_exp__h451445, + _theResult___fst_exp__h451968, + _theResult___fst_exp__h460555, + _theResult___fst_exp__h460620, + _theResult___fst_exp__h460626, + _theResult___fst_exp__h460629, + _theResult___fst_exp__h461152, + _theResult___fst_exp__h469192, + _theResult___fst_exp__h469231, + _theResult___fst_exp__h469237, + _theResult___fst_exp__h469240, + _theResult___fst_exp__h469788, + _theResult___fst_exp__h469797, + _theResult___fst_exp__h469800, + _theResult___snd_fst_exp__h360593, + _theResult___snd_fst_exp__h378413, + _theResult___snd_fst_exp__h406283, + _theResult___snd_fst_exp__h424103, + _theResult___snd_fst_exp__h451971, + _theResult___snd_fst_exp__h469791, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145, - din_inc___2_exp__h378446, - din_inc___2_exp__h378470, - din_inc___2_exp__h378500, - din_inc___2_exp__h378524, - din_inc___2_exp__h424136, - din_inc___2_exp__h424160, - din_inc___2_exp__h424190, - din_inc___2_exp__h424214, - din_inc___2_exp__h469824, - din_inc___2_exp__h469848, - din_inc___2_exp__h469878, - din_inc___2_exp__h469902, - out_exp__h351932, - out_exp__h360514, - out_exp__h369698, - out_exp__h378334, - out_exp__h397622, - out_exp__h406204, - out_exp__h415388, - out_exp__h424024, - out_exp__h443310, - out_exp__h451892, - out_exp__h461076, - out_exp__h469712, - out_f_exp__h378710, - out_f_exp__h424400, - out_f_exp__h470088, - x__h608822; + din_inc___2_exp__h378444, + din_inc___2_exp__h378468, + din_inc___2_exp__h378498, + din_inc___2_exp__h378522, + din_inc___2_exp__h424134, + din_inc___2_exp__h424158, + din_inc___2_exp__h424188, + din_inc___2_exp__h424212, + din_inc___2_exp__h469822, + din_inc___2_exp__h469846, + din_inc___2_exp__h469876, + din_inc___2_exp__h469900, + out_exp__h351930, + out_exp__h360512, + out_exp__h369696, + out_exp__h378332, + out_exp__h397620, + out_exp__h406202, + out_exp__h415386, + out_exp__h424022, + out_exp__h443308, + out_exp__h451890, + out_exp__h461074, + out_exp__h469710, + out_f_exp__h378708, + out_f_exp__h424398, + out_f_exp__h470086, + x__h608823; wire [6 : 0] csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12642; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635, @@ -5345,8 +5345,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890, - x__h180648, - x__h694806; + x__h180646, + x__h694804; wire [4 : 0] IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165, @@ -5366,18 +5366,18 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804, checkForException___d12839, checkForException___d13458, - fflags__h705627, - res_fflags__h335090, - res_fflags__h380785, - res_fflags__h426473, - rs1__h649453, + fflags__h705625, + res_fflags__h335088, + res_fflags__h380783, + res_fflags__h426471, + rs1__h649451, x__h152884, x__h156431, x__h159247, - x__h284501, - y_avValue_snd_fst__h705134, - y_avValue_snd_fst__h705687, - y_avValue_snd_fst__h705716; + x__h284499, + y_avValue_snd_fst__h705132, + y_avValue_snd_fst__h705685, + y_avValue_snd_fst__h705714; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851, @@ -5404,74 +5404,74 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d13074, - cause_code__h692189, - vm_mode_reg__read__h610031; + cause_code__h692187, + vm_mode_reg__read__h610032; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h293743, - next_deqP___1__h294022, - v__h293163, - v__h293394, - x__h299373, - x_decodeInfo_frm__h649137; + _theResult_____2__h293741, + next_deqP___1__h294020, + v__h293161, + v__h293392, + x__h299371, + x_decodeInfo_frm__h649135; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771, - IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66, - IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91, - IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21, - IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101, - IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31, - IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148, - IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58, - IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71, - IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93, - IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23, - IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106, - IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36, - IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127, - guard__h343312, - guard__h352021, - guard__h360951, - guard__h369787, - guard__h389004, - guard__h397711, - guard__h406641, - guard__h415477, - guard__h434692, - guard__h443399, - guard__h452329, - guard__h461165, - guard__h490715, - guard__h500027, - guard__h509096, - guard__h529516, - guard__h538828, - guard__h547897, - guard__h568717, - guard__h578029, - guard__h587098, - prv__h707142, - prv__h707186, - r1__read_BITS_13_TO_12___h649322, + IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66, + IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91, + IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21, + IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101, + IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31, + IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148, + IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56, + IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58, + IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71, + IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93, + IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23, + IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106, + IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36, + IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127, + guard__h343310, + guard__h352019, + guard__h360949, + guard__h369785, + guard__h389002, + guard__h397709, + guard__h406639, + guard__h415475, + guard__h434690, + guard__h443397, + guard__h452327, + guard__h461163, + guard__h490713, + guard__h500025, + guard__h509094, + guard__h529514, + guard__h538826, + guard__h547895, + guard__h568715, + guard__h578027, + guard__h587096, + prv__h707140, + prv__h707184, + r1__read_BITS_13_TO_12___h649320, sbIdx__h156310, - v__h600774, - v__h600784, - v__h601419, - x__h702602, - x__h705875, - y_avValue_snd_snd_snd_fst__h705144, - y_avValue_snd_snd_snd_fst__h705697, - y_avValue_snd_snd_snd_fst__h705726; + v__h600772, + v__h600782, + v__h601417, + x__h702600, + x__h705873, + y_avValue_snd_snd_snd_fst__h705142, + y_avValue_snd_snd_snd_fst__h705695, + y_avValue_snd_snd_snd_fst__h705724; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457, @@ -5872,7 +5872,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo26, + _dfoo28, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -5898,11 +5898,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h301739, - _theResult_____2__h307733, - _theResult_____2__h315587, - _theResult_____2__h325931, - _theResult_____2__h329156, + _theResult_____2__h301737, + _theResult_____2__h307731, + _theResult_____2__h315585, + _theResult_____2__h325929, + _theResult_____2__h329154, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140, coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114, @@ -6036,14 +6036,14 @@ module mkCore(CLK, fetchStage_pipelines_1_first__2614_BITS_194_TO_ETC___d13720, fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555, fetchStage_pipelines_1_first__2614_BIT_68_3335_ETC___d13724, - guard__h361549, - guard__h407239, - guard__h452927, - guard__h500625, - guard__h539426, - guard__h578627, - idx__h675479, - k__h661045, + guard__h361547, + guard__h407237, + guard__h452925, + guard__h500623, + guard__h539424, + guard__h578625, + idx__h675477, + k__h661043, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6055,13 +6055,13 @@ module mkCore(CLK, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h75409, - next_deqP___1__h302018, - next_deqP___1__h308299, - next_deqP___1__h316153, - next_deqP___1__h326210, - next_deqP___1__h329435, - r1__read_BIT_20___h649950, - r__h608869, + next_deqP___1__h302016, + next_deqP___1__h308297, + next_deqP___1__h316151, + next_deqP___1__h326208, + next_deqP___1__h329433, + r1__read_BIT_20___h649948, + r__h608870, regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688, regRenamingTable_RDY_rename_1_getRename__3744__ETC___d13762, regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258, @@ -6082,17 +6082,17 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631, - v__h296508, - v__h297026, - v__h307022, - v__h307253, - v__h310898, - v__h311129, - v__h325499, - v__h325730, - v__h328724, - v__h328955, - x__h600275; + v__h296506, + v__h297024, + v__h307020, + v__h307251, + v__h310896, + v__h311127, + v__h325497, + v__h325728, + v__h328722, + v__h328953, + x__h600273; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -10783,7 +10783,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -10795,7 +10795,7 @@ module mkCore(CLK, assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = @@ -10803,7 +10803,7 @@ module mkCore(CLK, (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -10860,7 +10860,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h688725, + x__h688723, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259 : @@ -10868,9 +10868,9 @@ module mkCore(CLK, assign MUX_commitStage_rg_instret$write_1__VAL_1 = commitStage_rg_instret + 64'd1 ; assign MUX_commitStage_rg_instret$write_1__VAL_2 = - commitStage_rg_instret + y__h705650 ; + commitStage_rg_instret + y__h705648 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h661045 == 1'd0 && + (k__h661043 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -10891,7 +10891,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -10994,7 +10994,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, @@ -11008,10 +11008,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h283068 } ; + x__h283066 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h284513, + x__h284511, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11019,7 +11019,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h287289, + addr__h287287, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11061,7 +11061,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h289193, + resp_addr__h289191, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11141,7 +11141,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h194349 } ; + x__h194347 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11176,8 +11176,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h190139 : - { {32{x__h190902[31]}}, x__h190902 } } ; + curData__h190137 : + { {32{x__h190900[31]}}, x__h190900 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[325:321], @@ -11206,7 +11206,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h705627 ; + csrf_fflags_reg | fflags__h705625 ; always@(IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 or robdeqPort_0_deq_data_BITS_95_TO_32__q261) begin @@ -11232,9 +11232,9 @@ module mkCore(CLK, csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h703199 + 64'd1 ; + n__read__h703197 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h703199 + { 62'd0, x__h705875 } ; + n__read__h703197 + { 62'd0, x__h705873 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == @@ -11242,7 +11242,7 @@ module mkCore(CLK, MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h693220 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h693218 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || @@ -11258,7 +11258,7 @@ module mkCore(CLK, MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h702602 : + x__h702600 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? @@ -11278,15 +11278,15 @@ module mkCore(CLK, MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? - y_avValue__h693067 : - y_avValue__h694828 ; + y_avValue__h693065 : + y_avValue__h694826 ; always@(rob$deqPort_0_deq_data or - next_pc__h702542 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h702540 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702542; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702540; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11321,23 +11321,23 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h473015 : - data__h472481 ; + data___1__h473013 : + data__h472479 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h335094 : - res_data__h335089 ; + res_data__h335092 : + res_data__h335087 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h380789 : - res_data__h380784 ; + res_data__h380787 : + res_data__h380782 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h426477 : - res_data__h426472 ; + res_data__h426475 : + res_data__h426470 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h472207 : + data___1__h472205 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? @@ -11416,15 +11416,15 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h335090 ; + res_fflags__h335088 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h380785 ; + res_fflags__h380783 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h426473 ; + res_fflags__h426471 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -11739,8 +11739,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h601419 : - v__h600774 ; + v__h601417 : + v__h600772 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -11847,7 +11847,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h293743 ; + _theResult_____2__h293741 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -11869,7 +11869,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h293163 ; + v__h293161 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -11915,7 +11915,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - _theResult_____2__h301739 ; + _theResult_____2__h301737 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -11933,7 +11933,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - v__h296508 ; + v__h296506 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12033,7 +12033,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - _theResult_____2__h307733 ; + _theResult_____2__h307731 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12051,7 +12051,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - v__h307022 ; + v__h307020 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12072,7 +12072,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h311296, + { x_addr__h311294, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12102,7 +12102,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - _theResult_____2__h315587 ; + _theResult_____2__h315585 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12120,7 +12120,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - v__h310898 ; + v__h310896 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12197,7 +12197,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - _theResult_____2__h329156 ; + _theResult_____2__h329154 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12215,7 +12215,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - v__h328724 ; + v__h328722 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12258,7 +12258,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - _theResult_____2__h325931 ; + _theResult_____2__h325929 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12276,7 +12276,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - v__h325499 ; + v__h325497 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12554,7 +12554,7 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__SEL_1 && MUX_csrf_ie_vec_1$write_1__VAL_1 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12570,7 +12570,7 @@ module mkCore(CLK, // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = MUX_csrf_ie_vec_3$write_1__SEL_2 ? - cause_code__h692189 : + cause_code__h692187 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12787,7 +12787,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : csrf_ie_vec_1 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12815,7 +12815,7 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = MUX_csrf_ie_vec_1$write_1__SEL_2 ? - cause_code__h692189 : + cause_code__h692187 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12933,7 +12933,7 @@ module mkCore(CLK, MUX_csrf_spp_reg$write_1__VAL_1 : csrf_prv_reg[0] ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -13472,8 +13472,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h634256, - x__h634257, + x__h634254, + x__h634255, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -13762,8 +13762,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h613033, x__h613034, + x__h613035, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -13805,7 +13805,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h661045 == 1'd1 && + (k__h661043 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -13826,7 +13826,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -13924,7 +13924,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h661045 == 1'd1 && + (k__h661043 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd1 && @@ -14310,19 +14310,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h600261 : - a__h599839 ; + _theResult___fst__h600259 : + a__h599837 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h599840 == 64'd0, - a__h599839, + { b__h599838 == 64'd0, + a__h599837, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h600275, - a__h599839[63], + x__h600273, + a__h599837[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h600262 : - b__h599840 ; + _theResult___snd__h600260 : + b__h599838 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14383,20 +14383,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599839 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599840 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599837 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599838 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h599839 ; + a__h599837 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h599840 ; + b__h599838 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h599839 ; + a__h599837 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h599840 ; + b__h599838 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -14425,9 +14425,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], + x__h478868, + x__h478869, x__h478870, - x__h478871, - x__h478872, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -14479,7 +14479,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14633,8 +14633,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h284501, - x__h284513, + { x__h284499, + x__h284511, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, @@ -14645,13 +14645,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - x__h286367, + x__h286365, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h283068 ; + x__h283066 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -15288,13 +15288,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h180511[2:0], - vaddr__h180511, + coreFix_memExe_lsq$getOrigBE << vaddr__h180509[2:0], + vaddr__h180509, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h180511[2:0] != 3'd0 : + vaddr__h180509[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h180511[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180511[0]), + vaddr__h180509[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180509[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15324,8 +15324,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h707186, - prv__h707186 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h707184, + prv__h707184 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15450,7 +15450,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675348 ; + renaming_spec_bits__h675346 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? @@ -15470,7 +15470,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675348 ; + renaming_spec_bits__h675346 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15550,7 +15550,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h180516 ; + shiftData__h180514 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -15650,8 +15650,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h180425, - x__h180426, + x__h180423, + x__h180424, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15915,7 +15915,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16624,7 +16624,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h675348 ; + renaming_spec_bits__h675346 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -16883,7 +16883,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, 7'd32, - renaming_spec_bits__h675348 } ; + renaming_spec_bits__h675346 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17385,10 +17385,10 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h190139), + .amoExec_current_data(curData__h190137), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h191677)); + .amoExec(n__h191675)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, @@ -17425,7 +17425,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 }, fetchStage$pipelines_0_first[160], - x_data_imm__h667949 } }), + x_data_imm__h667947 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17434,12 +17434,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649137, - r1__read_BITS_13_TO_12___h649322 != + .checkForException_csrState({ x_decodeInfo_frm__h649135, + r1__read_BITS_13_TO_12___h649320 != 2'd0, - { prv__h707142, + { prv__h707140, csrf_tvm_reg, - { r1__read_BIT_20___h649950, + { r1__read_BIT_20___h649948, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17455,7 +17455,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, { fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, fetchStage$pipelines_1_first[160], - x_data_imm__h682692 } }), + x_data_imm__h682690 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17464,12 +17464,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649137, - r1__read_BITS_13_TO_12___h649322 != + .checkForException_csrState({ x_decodeInfo_frm__h649135, + r1__read_BITS_13_TO_12___h649320 != 2'd0, - { prv__h707142, + { prv__h707140, csrf_tvm_reg, - { r1__read_BIT_20___h649950, + { r1__read_BIT_20___h649948, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17484,139 +17484,139 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h478961), - .execFpuSimple_rVal2(rVal2__h478962), + .execFpuSimple_rVal1(rVal1__h478959), + .execFpuSimple_rVal2(rVal2__h478960), .execFpuSimple(execFpuSimple___d11034)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ? - _theResult___snd__h351476 : - _theResult____h343302 ; + _theResult___snd__h351474 : + _theResult____h343300 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ? - _theResult___snd__h397166 : - _theResult____h388994 ; + _theResult___snd__h397164 : + _theResult____h388992 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ? - _theResult___snd__h442854 : - _theResult____h434682 ; + _theResult___snd__h442852 : + _theResult____h434680 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 ? - _theResult___snd__h508316 : - _theResult____h500017 ; + _theResult___snd__h508314 : + _theResult____h500015 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599 ? - _theResult___snd__h586318 : - _theResult____h578019 ; + _theResult___snd__h586316 : + _theResult____h578017 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 ? - _theResult___snd__h547117 : - _theResult____h538818 ; + _theResult___snd__h547115 : + _theResult____h538816 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ? - _theResult___snd__h460620 : - _theResult____h452319 ; + _theResult___snd__h460618 : + _theResult____h452317 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ? - _theResult___snd__h369242 : - _theResult____h360941 ; + _theResult___snd__h369240 : + _theResult____h360939 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ? - _theResult___snd__h414932 : - _theResult____h406631 ; + _theResult___snd__h414930 : + _theResult____h406629 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ? - _theResult___snd__h451436 : - _theResult___snd__h469226 ; + _theResult___snd__h451434 : + _theResult___snd__h469224 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ? - _theResult___snd__h360058 : + _theResult___snd__h360056 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ? - _theResult___snd__h360058 : - _theResult___snd__h377848 ; + _theResult___snd__h360056 : + _theResult___snd__h377846 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ? - _theResult___snd__h405748 : + _theResult___snd__h405746 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ? - _theResult___snd__h405748 : - _theResult___snd__h423538 ; + _theResult___snd__h405746 : + _theResult___snd__h423536 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ? - _theResult___snd__h451436 : + _theResult___snd__h451434 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 ? - _theResult___snd__h498665 : + _theResult___snd__h498663 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939 ? - _theResult___snd__h498665 : - _theResult___snd__h517070 ; + _theResult___snd__h498663 : + _theResult___snd__h517068 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302 ? - _theResult___snd__h576667 : + _theResult___snd__h576665 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649 ? - _theResult___snd__h576667 : - _theResult___snd__h595072 ; + _theResult___snd__h576665 : + _theResult___snd__h595070 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 ? - _theResult___snd__h537466 : + _theResult___snd__h537464 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412 ? - _theResult___snd__h537466 : - _theResult___snd__h555871 ; + _theResult___snd__h537464 : + _theResult___snd__h555869 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351413 == 8'd255) ? + ((_theResult___fst_exp__h351411 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) : - ((_theResult___fst_exp__h360069 == 8'd255) ? + ((_theResult___fst_exp__h360067 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351413 == 8'd255) ? + ((_theResult___fst_exp__h351411 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) : - ((_theResult___fst_exp__h360069 == 8'd255) ? + ((_theResult___fst_exp__h360067 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397103 == 8'd255) ? + ((_theResult___fst_exp__h397101 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) : - ((_theResult___fst_exp__h405759 == 8'd255) ? + ((_theResult___fst_exp__h405757 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397103 == 8'd255) ? + ((_theResult___fst_exp__h397101 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) : - ((_theResult___fst_exp__h405759 == 8'd255) ? + ((_theResult___fst_exp__h405757 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442791 == 8'd255) ? + ((_theResult___fst_exp__h442789 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) : - ((_theResult___fst_exp__h451447 == 8'd255) ? + ((_theResult___fst_exp__h451445 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442791 == 8'd255) ? + ((_theResult___fst_exp__h442789 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) : - ((_theResult___fst_exp__h451447 == 8'd255) ? + ((_theResult___fst_exp__h451445 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ; assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10657 = @@ -17632,1571 +17632,1571 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892) : !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 = - (_theResult____h343302[56] ? + (_theResult____h343300[56] ? 6'd0 : - (_theResult____h343302[55] ? + (_theResult____h343300[55] ? 6'd1 : - (_theResult____h343302[54] ? + (_theResult____h343300[54] ? 6'd2 : - (_theResult____h343302[53] ? + (_theResult____h343300[53] ? 6'd3 : - (_theResult____h343302[52] ? + (_theResult____h343300[52] ? 6'd4 : - (_theResult____h343302[51] ? + (_theResult____h343300[51] ? 6'd5 : - (_theResult____h343302[50] ? + (_theResult____h343300[50] ? 6'd6 : - (_theResult____h343302[49] ? + (_theResult____h343300[49] ? 6'd7 : - (_theResult____h343302[48] ? + (_theResult____h343300[48] ? 6'd8 : - (_theResult____h343302[47] ? + (_theResult____h343300[47] ? 6'd9 : - (_theResult____h343302[46] ? + (_theResult____h343300[46] ? 6'd10 : - (_theResult____h343302[45] ? + (_theResult____h343300[45] ? 6'd11 : - (_theResult____h343302[44] ? + (_theResult____h343300[44] ? 6'd12 : - (_theResult____h343302[43] ? + (_theResult____h343300[43] ? 6'd13 : - (_theResult____h343302[42] ? + (_theResult____h343300[42] ? 6'd14 : - (_theResult____h343302[41] ? + (_theResult____h343300[41] ? 6'd15 : - (_theResult____h343302[40] ? + (_theResult____h343300[40] ? 6'd16 : - (_theResult____h343302[39] ? + (_theResult____h343300[39] ? 6'd17 : - (_theResult____h343302[38] ? + (_theResult____h343300[38] ? 6'd18 : - (_theResult____h343302[37] ? + (_theResult____h343300[37] ? 6'd19 : - (_theResult____h343302[36] ? + (_theResult____h343300[36] ? 6'd20 : - (_theResult____h343302[35] ? + (_theResult____h343300[35] ? 6'd21 : - (_theResult____h343302[34] ? + (_theResult____h343300[34] ? 6'd22 : - (_theResult____h343302[33] ? + (_theResult____h343300[33] ? 6'd23 : - (_theResult____h343302[32] ? + (_theResult____h343300[32] ? 6'd24 : - (_theResult____h343302[31] ? + (_theResult____h343300[31] ? 6'd25 : - (_theResult____h343302[30] ? + (_theResult____h343300[30] ? 6'd26 : - (_theResult____h343302[29] ? + (_theResult____h343300[29] ? 6'd27 : - (_theResult____h343302[28] ? + (_theResult____h343300[28] ? 6'd28 : - (_theResult____h343302[27] ? + (_theResult____h343300[27] ? 6'd29 : - (_theResult____h343302[26] ? + (_theResult____h343300[26] ? 6'd30 : - (_theResult____h343302[25] ? + (_theResult____h343300[25] ? 6'd31 : - (_theResult____h343302[24] ? + (_theResult____h343300[24] ? 6'd32 : - (_theResult____h343302[23] ? + (_theResult____h343300[23] ? 6'd33 : - (_theResult____h343302[22] ? + (_theResult____h343300[22] ? 6'd34 : - (_theResult____h343302[21] ? + (_theResult____h343300[21] ? 6'd35 : - (_theResult____h343302[20] ? + (_theResult____h343300[20] ? 6'd36 : - (_theResult____h343302[19] ? + (_theResult____h343300[19] ? 6'd37 : - (_theResult____h343302[18] ? + (_theResult____h343300[18] ? 6'd38 : - (_theResult____h343302[17] ? + (_theResult____h343300[17] ? 6'd39 : - (_theResult____h343302[16] ? + (_theResult____h343300[16] ? 6'd40 : - (_theResult____h343302[15] ? + (_theResult____h343300[15] ? 6'd41 : - (_theResult____h343302[14] ? + (_theResult____h343300[14] ? 6'd42 : - (_theResult____h343302[13] ? + (_theResult____h343300[13] ? 6'd43 : - (_theResult____h343302[12] ? + (_theResult____h343300[12] ? 6'd44 : - (_theResult____h343302[11] ? + (_theResult____h343300[11] ? 6'd45 : - (_theResult____h343302[10] ? + (_theResult____h343300[10] ? 6'd46 : - (_theResult____h343302[9] ? + (_theResult____h343300[9] ? 6'd47 : - (_theResult____h343302[8] ? + (_theResult____h343300[8] ? 6'd48 : - (_theResult____h343302[7] ? + (_theResult____h343300[7] ? 6'd49 : - (_theResult____h343302[6] ? + (_theResult____h343300[6] ? 6'd50 : - (_theResult____h343302[5] ? + (_theResult____h343300[5] ? 6'd51 : - (_theResult____h343302[4] ? + (_theResult____h343300[4] ? 6'd52 : - (_theResult____h343302[3] ? + (_theResult____h343300[3] ? 6'd53 : - (_theResult____h343302[2] ? + (_theResult____h343300[2] ? 6'd54 : - (_theResult____h343302[1] ? + (_theResult____h343300[1] ? 6'd55 : - (_theResult____h343302[0] ? + (_theResult____h343300[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 = - (_theResult____h388994[56] ? + (_theResult____h388992[56] ? 6'd0 : - (_theResult____h388994[55] ? + (_theResult____h388992[55] ? 6'd1 : - (_theResult____h388994[54] ? + (_theResult____h388992[54] ? 6'd2 : - (_theResult____h388994[53] ? + (_theResult____h388992[53] ? 6'd3 : - (_theResult____h388994[52] ? + (_theResult____h388992[52] ? 6'd4 : - (_theResult____h388994[51] ? + (_theResult____h388992[51] ? 6'd5 : - (_theResult____h388994[50] ? + (_theResult____h388992[50] ? 6'd6 : - (_theResult____h388994[49] ? + (_theResult____h388992[49] ? 6'd7 : - (_theResult____h388994[48] ? + (_theResult____h388992[48] ? 6'd8 : - (_theResult____h388994[47] ? + (_theResult____h388992[47] ? 6'd9 : - (_theResult____h388994[46] ? + (_theResult____h388992[46] ? 6'd10 : - (_theResult____h388994[45] ? + (_theResult____h388992[45] ? 6'd11 : - (_theResult____h388994[44] ? + (_theResult____h388992[44] ? 6'd12 : - (_theResult____h388994[43] ? + (_theResult____h388992[43] ? 6'd13 : - (_theResult____h388994[42] ? + (_theResult____h388992[42] ? 6'd14 : - (_theResult____h388994[41] ? + (_theResult____h388992[41] ? 6'd15 : - (_theResult____h388994[40] ? + (_theResult____h388992[40] ? 6'd16 : - (_theResult____h388994[39] ? + (_theResult____h388992[39] ? 6'd17 : - (_theResult____h388994[38] ? + (_theResult____h388992[38] ? 6'd18 : - (_theResult____h388994[37] ? + (_theResult____h388992[37] ? 6'd19 : - (_theResult____h388994[36] ? + (_theResult____h388992[36] ? 6'd20 : - (_theResult____h388994[35] ? + (_theResult____h388992[35] ? 6'd21 : - (_theResult____h388994[34] ? + (_theResult____h388992[34] ? 6'd22 : - (_theResult____h388994[33] ? + (_theResult____h388992[33] ? 6'd23 : - (_theResult____h388994[32] ? + (_theResult____h388992[32] ? 6'd24 : - (_theResult____h388994[31] ? + (_theResult____h388992[31] ? 6'd25 : - (_theResult____h388994[30] ? + (_theResult____h388992[30] ? 6'd26 : - (_theResult____h388994[29] ? + (_theResult____h388992[29] ? 6'd27 : - (_theResult____h388994[28] ? + (_theResult____h388992[28] ? 6'd28 : - (_theResult____h388994[27] ? + (_theResult____h388992[27] ? 6'd29 : - (_theResult____h388994[26] ? + (_theResult____h388992[26] ? 6'd30 : - (_theResult____h388994[25] ? + (_theResult____h388992[25] ? 6'd31 : - (_theResult____h388994[24] ? + (_theResult____h388992[24] ? 6'd32 : - (_theResult____h388994[23] ? + (_theResult____h388992[23] ? 6'd33 : - (_theResult____h388994[22] ? + (_theResult____h388992[22] ? 6'd34 : - (_theResult____h388994[21] ? + (_theResult____h388992[21] ? 6'd35 : - (_theResult____h388994[20] ? + (_theResult____h388992[20] ? 6'd36 : - (_theResult____h388994[19] ? + (_theResult____h388992[19] ? 6'd37 : - (_theResult____h388994[18] ? + (_theResult____h388992[18] ? 6'd38 : - (_theResult____h388994[17] ? + (_theResult____h388992[17] ? 6'd39 : - (_theResult____h388994[16] ? + (_theResult____h388992[16] ? 6'd40 : - (_theResult____h388994[15] ? + (_theResult____h388992[15] ? 6'd41 : - (_theResult____h388994[14] ? + (_theResult____h388992[14] ? 6'd42 : - (_theResult____h388994[13] ? + (_theResult____h388992[13] ? 6'd43 : - (_theResult____h388994[12] ? + (_theResult____h388992[12] ? 6'd44 : - (_theResult____h388994[11] ? + (_theResult____h388992[11] ? 6'd45 : - (_theResult____h388994[10] ? + (_theResult____h388992[10] ? 6'd46 : - (_theResult____h388994[9] ? + (_theResult____h388992[9] ? 6'd47 : - (_theResult____h388994[8] ? + (_theResult____h388992[8] ? 6'd48 : - (_theResult____h388994[7] ? + (_theResult____h388992[7] ? 6'd49 : - (_theResult____h388994[6] ? + (_theResult____h388992[6] ? 6'd50 : - (_theResult____h388994[5] ? + (_theResult____h388992[5] ? 6'd51 : - (_theResult____h388994[4] ? + (_theResult____h388992[4] ? 6'd52 : - (_theResult____h388994[3] ? + (_theResult____h388992[3] ? 6'd53 : - (_theResult____h388994[2] ? + (_theResult____h388992[2] ? 6'd54 : - (_theResult____h388994[1] ? + (_theResult____h388992[1] ? 6'd55 : - (_theResult____h388994[0] ? + (_theResult____h388992[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 = - (_theResult____h434682[56] ? + (_theResult____h434680[56] ? 6'd0 : - (_theResult____h434682[55] ? + (_theResult____h434680[55] ? 6'd1 : - (_theResult____h434682[54] ? + (_theResult____h434680[54] ? 6'd2 : - (_theResult____h434682[53] ? + (_theResult____h434680[53] ? 6'd3 : - (_theResult____h434682[52] ? + (_theResult____h434680[52] ? 6'd4 : - (_theResult____h434682[51] ? + (_theResult____h434680[51] ? 6'd5 : - (_theResult____h434682[50] ? + (_theResult____h434680[50] ? 6'd6 : - (_theResult____h434682[49] ? + (_theResult____h434680[49] ? 6'd7 : - (_theResult____h434682[48] ? + (_theResult____h434680[48] ? 6'd8 : - (_theResult____h434682[47] ? + (_theResult____h434680[47] ? 6'd9 : - (_theResult____h434682[46] ? + (_theResult____h434680[46] ? 6'd10 : - (_theResult____h434682[45] ? + (_theResult____h434680[45] ? 6'd11 : - (_theResult____h434682[44] ? + (_theResult____h434680[44] ? 6'd12 : - (_theResult____h434682[43] ? + (_theResult____h434680[43] ? 6'd13 : - (_theResult____h434682[42] ? + (_theResult____h434680[42] ? 6'd14 : - (_theResult____h434682[41] ? + (_theResult____h434680[41] ? 6'd15 : - (_theResult____h434682[40] ? + (_theResult____h434680[40] ? 6'd16 : - (_theResult____h434682[39] ? + (_theResult____h434680[39] ? 6'd17 : - (_theResult____h434682[38] ? + (_theResult____h434680[38] ? 6'd18 : - (_theResult____h434682[37] ? + (_theResult____h434680[37] ? 6'd19 : - (_theResult____h434682[36] ? + (_theResult____h434680[36] ? 6'd20 : - (_theResult____h434682[35] ? + (_theResult____h434680[35] ? 6'd21 : - (_theResult____h434682[34] ? + (_theResult____h434680[34] ? 6'd22 : - (_theResult____h434682[33] ? + (_theResult____h434680[33] ? 6'd23 : - (_theResult____h434682[32] ? + (_theResult____h434680[32] ? 6'd24 : - (_theResult____h434682[31] ? + (_theResult____h434680[31] ? 6'd25 : - (_theResult____h434682[30] ? + (_theResult____h434680[30] ? 6'd26 : - (_theResult____h434682[29] ? + (_theResult____h434680[29] ? 6'd27 : - (_theResult____h434682[28] ? + (_theResult____h434680[28] ? 6'd28 : - (_theResult____h434682[27] ? + (_theResult____h434680[27] ? 6'd29 : - (_theResult____h434682[26] ? + (_theResult____h434680[26] ? 6'd30 : - (_theResult____h434682[25] ? + (_theResult____h434680[25] ? 6'd31 : - (_theResult____h434682[24] ? + (_theResult____h434680[24] ? 6'd32 : - (_theResult____h434682[23] ? + (_theResult____h434680[23] ? 6'd33 : - (_theResult____h434682[22] ? + (_theResult____h434680[22] ? 6'd34 : - (_theResult____h434682[21] ? + (_theResult____h434680[21] ? 6'd35 : - (_theResult____h434682[20] ? + (_theResult____h434680[20] ? 6'd36 : - (_theResult____h434682[19] ? + (_theResult____h434680[19] ? 6'd37 : - (_theResult____h434682[18] ? + (_theResult____h434680[18] ? 6'd38 : - (_theResult____h434682[17] ? + (_theResult____h434680[17] ? 6'd39 : - (_theResult____h434682[16] ? + (_theResult____h434680[16] ? 6'd40 : - (_theResult____h434682[15] ? + (_theResult____h434680[15] ? 6'd41 : - (_theResult____h434682[14] ? + (_theResult____h434680[14] ? 6'd42 : - (_theResult____h434682[13] ? + (_theResult____h434680[13] ? 6'd43 : - (_theResult____h434682[12] ? + (_theResult____h434680[12] ? 6'd44 : - (_theResult____h434682[11] ? + (_theResult____h434680[11] ? 6'd45 : - (_theResult____h434682[10] ? + (_theResult____h434680[10] ? 6'd46 : - (_theResult____h434682[9] ? + (_theResult____h434680[9] ? 6'd47 : - (_theResult____h434682[8] ? + (_theResult____h434680[8] ? 6'd48 : - (_theResult____h434682[7] ? + (_theResult____h434680[7] ? 6'd49 : - (_theResult____h434682[6] ? + (_theResult____h434680[6] ? 6'd50 : - (_theResult____h434682[5] ? + (_theResult____h434680[5] ? 6'd51 : - (_theResult____h434682[4] ? + (_theResult____h434680[4] ? 6'd52 : - (_theResult____h434682[3] ? + (_theResult____h434680[3] ? 6'd53 : - (_theResult____h434682[2] ? + (_theResult____h434680[2] ? 6'd54 : - (_theResult____h434682[1] ? + (_theResult____h434680[1] ? 6'd55 : - (_theResult____h434682[0] ? + (_theResult____h434680[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 = - (_theResult____h538818[56] ? + (_theResult____h538816[56] ? 6'd0 : - (_theResult____h538818[55] ? + (_theResult____h538816[55] ? 6'd1 : - (_theResult____h538818[54] ? + (_theResult____h538816[54] ? 6'd2 : - (_theResult____h538818[53] ? + (_theResult____h538816[53] ? 6'd3 : - (_theResult____h538818[52] ? + (_theResult____h538816[52] ? 6'd4 : - (_theResult____h538818[51] ? + (_theResult____h538816[51] ? 6'd5 : - (_theResult____h538818[50] ? + (_theResult____h538816[50] ? 6'd6 : - (_theResult____h538818[49] ? + (_theResult____h538816[49] ? 6'd7 : - (_theResult____h538818[48] ? + (_theResult____h538816[48] ? 6'd8 : - (_theResult____h538818[47] ? + (_theResult____h538816[47] ? 6'd9 : - (_theResult____h538818[46] ? + (_theResult____h538816[46] ? 6'd10 : - (_theResult____h538818[45] ? + (_theResult____h538816[45] ? 6'd11 : - (_theResult____h538818[44] ? + (_theResult____h538816[44] ? 6'd12 : - (_theResult____h538818[43] ? + (_theResult____h538816[43] ? 6'd13 : - (_theResult____h538818[42] ? + (_theResult____h538816[42] ? 6'd14 : - (_theResult____h538818[41] ? + (_theResult____h538816[41] ? 6'd15 : - (_theResult____h538818[40] ? + (_theResult____h538816[40] ? 6'd16 : - (_theResult____h538818[39] ? + (_theResult____h538816[39] ? 6'd17 : - (_theResult____h538818[38] ? + (_theResult____h538816[38] ? 6'd18 : - (_theResult____h538818[37] ? + (_theResult____h538816[37] ? 6'd19 : - (_theResult____h538818[36] ? + (_theResult____h538816[36] ? 6'd20 : - (_theResult____h538818[35] ? + (_theResult____h538816[35] ? 6'd21 : - (_theResult____h538818[34] ? + (_theResult____h538816[34] ? 6'd22 : - (_theResult____h538818[33] ? + (_theResult____h538816[33] ? 6'd23 : - (_theResult____h538818[32] ? + (_theResult____h538816[32] ? 6'd24 : - (_theResult____h538818[31] ? + (_theResult____h538816[31] ? 6'd25 : - (_theResult____h538818[30] ? + (_theResult____h538816[30] ? 6'd26 : - (_theResult____h538818[29] ? + (_theResult____h538816[29] ? 6'd27 : - (_theResult____h538818[28] ? + (_theResult____h538816[28] ? 6'd28 : - (_theResult____h538818[27] ? + (_theResult____h538816[27] ? 6'd29 : - (_theResult____h538818[26] ? + (_theResult____h538816[26] ? 6'd30 : - (_theResult____h538818[25] ? + (_theResult____h538816[25] ? 6'd31 : - (_theResult____h538818[24] ? + (_theResult____h538816[24] ? 6'd32 : - (_theResult____h538818[23] ? + (_theResult____h538816[23] ? 6'd33 : - (_theResult____h538818[22] ? + (_theResult____h538816[22] ? 6'd34 : - (_theResult____h538818[21] ? + (_theResult____h538816[21] ? 6'd35 : - (_theResult____h538818[20] ? + (_theResult____h538816[20] ? 6'd36 : - (_theResult____h538818[19] ? + (_theResult____h538816[19] ? 6'd37 : - (_theResult____h538818[18] ? + (_theResult____h538816[18] ? 6'd38 : - (_theResult____h538818[17] ? + (_theResult____h538816[17] ? 6'd39 : - (_theResult____h538818[16] ? + (_theResult____h538816[16] ? 6'd40 : - (_theResult____h538818[15] ? + (_theResult____h538816[15] ? 6'd41 : - (_theResult____h538818[14] ? + (_theResult____h538816[14] ? 6'd42 : - (_theResult____h538818[13] ? + (_theResult____h538816[13] ? 6'd43 : - (_theResult____h538818[12] ? + (_theResult____h538816[12] ? 6'd44 : - (_theResult____h538818[11] ? + (_theResult____h538816[11] ? 6'd45 : - (_theResult____h538818[10] ? + (_theResult____h538816[10] ? 6'd46 : - (_theResult____h538818[9] ? + (_theResult____h538816[9] ? 6'd47 : - (_theResult____h538818[8] ? + (_theResult____h538816[8] ? 6'd48 : - (_theResult____h538818[7] ? + (_theResult____h538816[7] ? 6'd49 : - (_theResult____h538818[6] ? + (_theResult____h538816[6] ? 6'd50 : - (_theResult____h538818[5] ? + (_theResult____h538816[5] ? 6'd51 : - (_theResult____h538818[4] ? + (_theResult____h538816[4] ? 6'd52 : - (_theResult____h538818[3] ? + (_theResult____h538816[3] ? 6'd53 : - (_theResult____h538818[2] ? + (_theResult____h538816[2] ? 6'd54 : - (_theResult____h538818[1] ? + (_theResult____h538816[1] ? 6'd55 : - (_theResult____h538818[0] ? + (_theResult____h538816[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 = - (_theResult____h500017[56] ? + (_theResult____h500015[56] ? 6'd0 : - (_theResult____h500017[55] ? + (_theResult____h500015[55] ? 6'd1 : - (_theResult____h500017[54] ? + (_theResult____h500015[54] ? 6'd2 : - (_theResult____h500017[53] ? + (_theResult____h500015[53] ? 6'd3 : - (_theResult____h500017[52] ? + (_theResult____h500015[52] ? 6'd4 : - (_theResult____h500017[51] ? + (_theResult____h500015[51] ? 6'd5 : - (_theResult____h500017[50] ? + (_theResult____h500015[50] ? 6'd6 : - (_theResult____h500017[49] ? + (_theResult____h500015[49] ? 6'd7 : - (_theResult____h500017[48] ? + (_theResult____h500015[48] ? 6'd8 : - (_theResult____h500017[47] ? + (_theResult____h500015[47] ? 6'd9 : - (_theResult____h500017[46] ? + (_theResult____h500015[46] ? 6'd10 : - (_theResult____h500017[45] ? + (_theResult____h500015[45] ? 6'd11 : - (_theResult____h500017[44] ? + (_theResult____h500015[44] ? 6'd12 : - (_theResult____h500017[43] ? + (_theResult____h500015[43] ? 6'd13 : - (_theResult____h500017[42] ? + (_theResult____h500015[42] ? 6'd14 : - (_theResult____h500017[41] ? + (_theResult____h500015[41] ? 6'd15 : - (_theResult____h500017[40] ? + (_theResult____h500015[40] ? 6'd16 : - (_theResult____h500017[39] ? + (_theResult____h500015[39] ? 6'd17 : - (_theResult____h500017[38] ? + (_theResult____h500015[38] ? 6'd18 : - (_theResult____h500017[37] ? + (_theResult____h500015[37] ? 6'd19 : - (_theResult____h500017[36] ? + (_theResult____h500015[36] ? 6'd20 : - (_theResult____h500017[35] ? + (_theResult____h500015[35] ? 6'd21 : - (_theResult____h500017[34] ? + (_theResult____h500015[34] ? 6'd22 : - (_theResult____h500017[33] ? + (_theResult____h500015[33] ? 6'd23 : - (_theResult____h500017[32] ? + (_theResult____h500015[32] ? 6'd24 : - (_theResult____h500017[31] ? + (_theResult____h500015[31] ? 6'd25 : - (_theResult____h500017[30] ? + (_theResult____h500015[30] ? 6'd26 : - (_theResult____h500017[29] ? + (_theResult____h500015[29] ? 6'd27 : - (_theResult____h500017[28] ? + (_theResult____h500015[28] ? 6'd28 : - (_theResult____h500017[27] ? + (_theResult____h500015[27] ? 6'd29 : - (_theResult____h500017[26] ? + (_theResult____h500015[26] ? 6'd30 : - (_theResult____h500017[25] ? + (_theResult____h500015[25] ? 6'd31 : - (_theResult____h500017[24] ? + (_theResult____h500015[24] ? 6'd32 : - (_theResult____h500017[23] ? + (_theResult____h500015[23] ? 6'd33 : - (_theResult____h500017[22] ? + (_theResult____h500015[22] ? 6'd34 : - (_theResult____h500017[21] ? + (_theResult____h500015[21] ? 6'd35 : - (_theResult____h500017[20] ? + (_theResult____h500015[20] ? 6'd36 : - (_theResult____h500017[19] ? + (_theResult____h500015[19] ? 6'd37 : - (_theResult____h500017[18] ? + (_theResult____h500015[18] ? 6'd38 : - (_theResult____h500017[17] ? + (_theResult____h500015[17] ? 6'd39 : - (_theResult____h500017[16] ? + (_theResult____h500015[16] ? 6'd40 : - (_theResult____h500017[15] ? + (_theResult____h500015[15] ? 6'd41 : - (_theResult____h500017[14] ? + (_theResult____h500015[14] ? 6'd42 : - (_theResult____h500017[13] ? + (_theResult____h500015[13] ? 6'd43 : - (_theResult____h500017[12] ? + (_theResult____h500015[12] ? 6'd44 : - (_theResult____h500017[11] ? + (_theResult____h500015[11] ? 6'd45 : - (_theResult____h500017[10] ? + (_theResult____h500015[10] ? 6'd46 : - (_theResult____h500017[9] ? + (_theResult____h500015[9] ? 6'd47 : - (_theResult____h500017[8] ? + (_theResult____h500015[8] ? 6'd48 : - (_theResult____h500017[7] ? + (_theResult____h500015[7] ? 6'd49 : - (_theResult____h500017[6] ? + (_theResult____h500015[6] ? 6'd50 : - (_theResult____h500017[5] ? + (_theResult____h500015[5] ? 6'd51 : - (_theResult____h500017[4] ? + (_theResult____h500015[4] ? 6'd52 : - (_theResult____h500017[3] ? + (_theResult____h500015[3] ? 6'd53 : - (_theResult____h500017[2] ? + (_theResult____h500015[2] ? 6'd54 : - (_theResult____h500017[1] ? + (_theResult____h500015[1] ? 6'd55 : - (_theResult____h500017[0] ? + (_theResult____h500015[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 = - (_theResult____h578019[56] ? + (_theResult____h578017[56] ? 6'd0 : - (_theResult____h578019[55] ? + (_theResult____h578017[55] ? 6'd1 : - (_theResult____h578019[54] ? + (_theResult____h578017[54] ? 6'd2 : - (_theResult____h578019[53] ? + (_theResult____h578017[53] ? 6'd3 : - (_theResult____h578019[52] ? + (_theResult____h578017[52] ? 6'd4 : - (_theResult____h578019[51] ? + (_theResult____h578017[51] ? 6'd5 : - (_theResult____h578019[50] ? + (_theResult____h578017[50] ? 6'd6 : - (_theResult____h578019[49] ? + (_theResult____h578017[49] ? 6'd7 : - (_theResult____h578019[48] ? + (_theResult____h578017[48] ? 6'd8 : - (_theResult____h578019[47] ? + (_theResult____h578017[47] ? 6'd9 : - (_theResult____h578019[46] ? + (_theResult____h578017[46] ? 6'd10 : - (_theResult____h578019[45] ? + (_theResult____h578017[45] ? 6'd11 : - (_theResult____h578019[44] ? + (_theResult____h578017[44] ? 6'd12 : - (_theResult____h578019[43] ? + (_theResult____h578017[43] ? 6'd13 : - (_theResult____h578019[42] ? + (_theResult____h578017[42] ? 6'd14 : - (_theResult____h578019[41] ? + (_theResult____h578017[41] ? 6'd15 : - (_theResult____h578019[40] ? + (_theResult____h578017[40] ? 6'd16 : - (_theResult____h578019[39] ? + (_theResult____h578017[39] ? 6'd17 : - (_theResult____h578019[38] ? + (_theResult____h578017[38] ? 6'd18 : - (_theResult____h578019[37] ? + (_theResult____h578017[37] ? 6'd19 : - (_theResult____h578019[36] ? + (_theResult____h578017[36] ? 6'd20 : - (_theResult____h578019[35] ? + (_theResult____h578017[35] ? 6'd21 : - (_theResult____h578019[34] ? + (_theResult____h578017[34] ? 6'd22 : - (_theResult____h578019[33] ? + (_theResult____h578017[33] ? 6'd23 : - (_theResult____h578019[32] ? + (_theResult____h578017[32] ? 6'd24 : - (_theResult____h578019[31] ? + (_theResult____h578017[31] ? 6'd25 : - (_theResult____h578019[30] ? + (_theResult____h578017[30] ? 6'd26 : - (_theResult____h578019[29] ? + (_theResult____h578017[29] ? 6'd27 : - (_theResult____h578019[28] ? + (_theResult____h578017[28] ? 6'd28 : - (_theResult____h578019[27] ? + (_theResult____h578017[27] ? 6'd29 : - (_theResult____h578019[26] ? + (_theResult____h578017[26] ? 6'd30 : - (_theResult____h578019[25] ? + (_theResult____h578017[25] ? 6'd31 : - (_theResult____h578019[24] ? + (_theResult____h578017[24] ? 6'd32 : - (_theResult____h578019[23] ? + (_theResult____h578017[23] ? 6'd33 : - (_theResult____h578019[22] ? + (_theResult____h578017[22] ? 6'd34 : - (_theResult____h578019[21] ? + (_theResult____h578017[21] ? 6'd35 : - (_theResult____h578019[20] ? + (_theResult____h578017[20] ? 6'd36 : - (_theResult____h578019[19] ? + (_theResult____h578017[19] ? 6'd37 : - (_theResult____h578019[18] ? + (_theResult____h578017[18] ? 6'd38 : - (_theResult____h578019[17] ? + (_theResult____h578017[17] ? 6'd39 : - (_theResult____h578019[16] ? + (_theResult____h578017[16] ? 6'd40 : - (_theResult____h578019[15] ? + (_theResult____h578017[15] ? 6'd41 : - (_theResult____h578019[14] ? + (_theResult____h578017[14] ? 6'd42 : - (_theResult____h578019[13] ? + (_theResult____h578017[13] ? 6'd43 : - (_theResult____h578019[12] ? + (_theResult____h578017[12] ? 6'd44 : - (_theResult____h578019[11] ? + (_theResult____h578017[11] ? 6'd45 : - (_theResult____h578019[10] ? + (_theResult____h578017[10] ? 6'd46 : - (_theResult____h578019[9] ? + (_theResult____h578017[9] ? 6'd47 : - (_theResult____h578019[8] ? + (_theResult____h578017[8] ? 6'd48 : - (_theResult____h578019[7] ? + (_theResult____h578017[7] ? 6'd49 : - (_theResult____h578019[6] ? + (_theResult____h578017[6] ? 6'd50 : - (_theResult____h578019[5] ? + (_theResult____h578017[5] ? 6'd51 : - (_theResult____h578019[4] ? + (_theResult____h578017[4] ? 6'd52 : - (_theResult____h578019[3] ? + (_theResult____h578017[3] ? 6'd53 : - (_theResult____h578019[2] ? + (_theResult____h578017[2] ? 6'd54 : - (_theResult____h578019[1] ? + (_theResult____h578017[1] ? 6'd55 : - (_theResult____h578019[0] ? + (_theResult____h578017[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 = - (_theResult____h360941[56] ? + (_theResult____h360939[56] ? 6'd0 : - (_theResult____h360941[55] ? + (_theResult____h360939[55] ? 6'd1 : - (_theResult____h360941[54] ? + (_theResult____h360939[54] ? 6'd2 : - (_theResult____h360941[53] ? + (_theResult____h360939[53] ? 6'd3 : - (_theResult____h360941[52] ? + (_theResult____h360939[52] ? 6'd4 : - (_theResult____h360941[51] ? + (_theResult____h360939[51] ? 6'd5 : - (_theResult____h360941[50] ? + (_theResult____h360939[50] ? 6'd6 : - (_theResult____h360941[49] ? + (_theResult____h360939[49] ? 6'd7 : - (_theResult____h360941[48] ? + (_theResult____h360939[48] ? 6'd8 : - (_theResult____h360941[47] ? + (_theResult____h360939[47] ? 6'd9 : - (_theResult____h360941[46] ? + (_theResult____h360939[46] ? 6'd10 : - (_theResult____h360941[45] ? + (_theResult____h360939[45] ? 6'd11 : - (_theResult____h360941[44] ? + (_theResult____h360939[44] ? 6'd12 : - (_theResult____h360941[43] ? + (_theResult____h360939[43] ? 6'd13 : - (_theResult____h360941[42] ? + (_theResult____h360939[42] ? 6'd14 : - (_theResult____h360941[41] ? + (_theResult____h360939[41] ? 6'd15 : - (_theResult____h360941[40] ? + (_theResult____h360939[40] ? 6'd16 : - (_theResult____h360941[39] ? + (_theResult____h360939[39] ? 6'd17 : - (_theResult____h360941[38] ? + (_theResult____h360939[38] ? 6'd18 : - (_theResult____h360941[37] ? + (_theResult____h360939[37] ? 6'd19 : - (_theResult____h360941[36] ? + (_theResult____h360939[36] ? 6'd20 : - (_theResult____h360941[35] ? + (_theResult____h360939[35] ? 6'd21 : - (_theResult____h360941[34] ? + (_theResult____h360939[34] ? 6'd22 : - (_theResult____h360941[33] ? + (_theResult____h360939[33] ? 6'd23 : - (_theResult____h360941[32] ? + (_theResult____h360939[32] ? 6'd24 : - (_theResult____h360941[31] ? + (_theResult____h360939[31] ? 6'd25 : - (_theResult____h360941[30] ? + (_theResult____h360939[30] ? 6'd26 : - (_theResult____h360941[29] ? + (_theResult____h360939[29] ? 6'd27 : - (_theResult____h360941[28] ? + (_theResult____h360939[28] ? 6'd28 : - (_theResult____h360941[27] ? + (_theResult____h360939[27] ? 6'd29 : - (_theResult____h360941[26] ? + (_theResult____h360939[26] ? 6'd30 : - (_theResult____h360941[25] ? + (_theResult____h360939[25] ? 6'd31 : - (_theResult____h360941[24] ? + (_theResult____h360939[24] ? 6'd32 : - (_theResult____h360941[23] ? + (_theResult____h360939[23] ? 6'd33 : - (_theResult____h360941[22] ? + (_theResult____h360939[22] ? 6'd34 : - (_theResult____h360941[21] ? + (_theResult____h360939[21] ? 6'd35 : - (_theResult____h360941[20] ? + (_theResult____h360939[20] ? 6'd36 : - (_theResult____h360941[19] ? + (_theResult____h360939[19] ? 6'd37 : - (_theResult____h360941[18] ? + (_theResult____h360939[18] ? 6'd38 : - (_theResult____h360941[17] ? + (_theResult____h360939[17] ? 6'd39 : - (_theResult____h360941[16] ? + (_theResult____h360939[16] ? 6'd40 : - (_theResult____h360941[15] ? + (_theResult____h360939[15] ? 6'd41 : - (_theResult____h360941[14] ? + (_theResult____h360939[14] ? 6'd42 : - (_theResult____h360941[13] ? + (_theResult____h360939[13] ? 6'd43 : - (_theResult____h360941[12] ? + (_theResult____h360939[12] ? 6'd44 : - (_theResult____h360941[11] ? + (_theResult____h360939[11] ? 6'd45 : - (_theResult____h360941[10] ? + (_theResult____h360939[10] ? 6'd46 : - (_theResult____h360941[9] ? + (_theResult____h360939[9] ? 6'd47 : - (_theResult____h360941[8] ? + (_theResult____h360939[8] ? 6'd48 : - (_theResult____h360941[7] ? + (_theResult____h360939[7] ? 6'd49 : - (_theResult____h360941[6] ? + (_theResult____h360939[6] ? 6'd50 : - (_theResult____h360941[5] ? + (_theResult____h360939[5] ? 6'd51 : - (_theResult____h360941[4] ? + (_theResult____h360939[4] ? 6'd52 : - (_theResult____h360941[3] ? + (_theResult____h360939[3] ? 6'd53 : - (_theResult____h360941[2] ? + (_theResult____h360939[2] ? 6'd54 : - (_theResult____h360941[1] ? + (_theResult____h360939[1] ? 6'd55 : - (_theResult____h360941[0] ? + (_theResult____h360939[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 = - (_theResult____h406631[56] ? + (_theResult____h406629[56] ? 6'd0 : - (_theResult____h406631[55] ? + (_theResult____h406629[55] ? 6'd1 : - (_theResult____h406631[54] ? + (_theResult____h406629[54] ? 6'd2 : - (_theResult____h406631[53] ? + (_theResult____h406629[53] ? 6'd3 : - (_theResult____h406631[52] ? + (_theResult____h406629[52] ? 6'd4 : - (_theResult____h406631[51] ? + (_theResult____h406629[51] ? 6'd5 : - (_theResult____h406631[50] ? + (_theResult____h406629[50] ? 6'd6 : - (_theResult____h406631[49] ? + (_theResult____h406629[49] ? 6'd7 : - (_theResult____h406631[48] ? + (_theResult____h406629[48] ? 6'd8 : - (_theResult____h406631[47] ? + (_theResult____h406629[47] ? 6'd9 : - (_theResult____h406631[46] ? + (_theResult____h406629[46] ? 6'd10 : - (_theResult____h406631[45] ? + (_theResult____h406629[45] ? 6'd11 : - (_theResult____h406631[44] ? + (_theResult____h406629[44] ? 6'd12 : - (_theResult____h406631[43] ? + (_theResult____h406629[43] ? 6'd13 : - (_theResult____h406631[42] ? + (_theResult____h406629[42] ? 6'd14 : - (_theResult____h406631[41] ? + (_theResult____h406629[41] ? 6'd15 : - (_theResult____h406631[40] ? + (_theResult____h406629[40] ? 6'd16 : - (_theResult____h406631[39] ? + (_theResult____h406629[39] ? 6'd17 : - (_theResult____h406631[38] ? + (_theResult____h406629[38] ? 6'd18 : - (_theResult____h406631[37] ? + (_theResult____h406629[37] ? 6'd19 : - (_theResult____h406631[36] ? + (_theResult____h406629[36] ? 6'd20 : - (_theResult____h406631[35] ? + (_theResult____h406629[35] ? 6'd21 : - (_theResult____h406631[34] ? + (_theResult____h406629[34] ? 6'd22 : - (_theResult____h406631[33] ? + (_theResult____h406629[33] ? 6'd23 : - (_theResult____h406631[32] ? + (_theResult____h406629[32] ? 6'd24 : - (_theResult____h406631[31] ? + (_theResult____h406629[31] ? 6'd25 : - (_theResult____h406631[30] ? + (_theResult____h406629[30] ? 6'd26 : - (_theResult____h406631[29] ? + (_theResult____h406629[29] ? 6'd27 : - (_theResult____h406631[28] ? + (_theResult____h406629[28] ? 6'd28 : - (_theResult____h406631[27] ? + (_theResult____h406629[27] ? 6'd29 : - (_theResult____h406631[26] ? + (_theResult____h406629[26] ? 6'd30 : - (_theResult____h406631[25] ? + (_theResult____h406629[25] ? 6'd31 : - (_theResult____h406631[24] ? + (_theResult____h406629[24] ? 6'd32 : - (_theResult____h406631[23] ? + (_theResult____h406629[23] ? 6'd33 : - (_theResult____h406631[22] ? + (_theResult____h406629[22] ? 6'd34 : - (_theResult____h406631[21] ? + (_theResult____h406629[21] ? 6'd35 : - (_theResult____h406631[20] ? + (_theResult____h406629[20] ? 6'd36 : - (_theResult____h406631[19] ? + (_theResult____h406629[19] ? 6'd37 : - (_theResult____h406631[18] ? + (_theResult____h406629[18] ? 6'd38 : - (_theResult____h406631[17] ? + (_theResult____h406629[17] ? 6'd39 : - (_theResult____h406631[16] ? + (_theResult____h406629[16] ? 6'd40 : - (_theResult____h406631[15] ? + (_theResult____h406629[15] ? 6'd41 : - (_theResult____h406631[14] ? + (_theResult____h406629[14] ? 6'd42 : - (_theResult____h406631[13] ? + (_theResult____h406629[13] ? 6'd43 : - (_theResult____h406631[12] ? + (_theResult____h406629[12] ? 6'd44 : - (_theResult____h406631[11] ? + (_theResult____h406629[11] ? 6'd45 : - (_theResult____h406631[10] ? + (_theResult____h406629[10] ? 6'd46 : - (_theResult____h406631[9] ? + (_theResult____h406629[9] ? 6'd47 : - (_theResult____h406631[8] ? + (_theResult____h406629[8] ? 6'd48 : - (_theResult____h406631[7] ? + (_theResult____h406629[7] ? 6'd49 : - (_theResult____h406631[6] ? + (_theResult____h406629[6] ? 6'd50 : - (_theResult____h406631[5] ? + (_theResult____h406629[5] ? 6'd51 : - (_theResult____h406631[4] ? + (_theResult____h406629[4] ? 6'd52 : - (_theResult____h406631[3] ? + (_theResult____h406629[3] ? 6'd53 : - (_theResult____h406631[2] ? + (_theResult____h406629[2] ? 6'd54 : - (_theResult____h406631[1] ? + (_theResult____h406629[1] ? 6'd55 : - (_theResult____h406631[0] ? + (_theResult____h406629[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 = - (_theResult____h452319[56] ? + (_theResult____h452317[56] ? 6'd0 : - (_theResult____h452319[55] ? + (_theResult____h452317[55] ? 6'd1 : - (_theResult____h452319[54] ? + (_theResult____h452317[54] ? 6'd2 : - (_theResult____h452319[53] ? + (_theResult____h452317[53] ? 6'd3 : - (_theResult____h452319[52] ? + (_theResult____h452317[52] ? 6'd4 : - (_theResult____h452319[51] ? + (_theResult____h452317[51] ? 6'd5 : - (_theResult____h452319[50] ? + (_theResult____h452317[50] ? 6'd6 : - (_theResult____h452319[49] ? + (_theResult____h452317[49] ? 6'd7 : - (_theResult____h452319[48] ? + (_theResult____h452317[48] ? 6'd8 : - (_theResult____h452319[47] ? + (_theResult____h452317[47] ? 6'd9 : - (_theResult____h452319[46] ? + (_theResult____h452317[46] ? 6'd10 : - (_theResult____h452319[45] ? + (_theResult____h452317[45] ? 6'd11 : - (_theResult____h452319[44] ? + (_theResult____h452317[44] ? 6'd12 : - (_theResult____h452319[43] ? + (_theResult____h452317[43] ? 6'd13 : - (_theResult____h452319[42] ? + (_theResult____h452317[42] ? 6'd14 : - (_theResult____h452319[41] ? + (_theResult____h452317[41] ? 6'd15 : - (_theResult____h452319[40] ? + (_theResult____h452317[40] ? 6'd16 : - (_theResult____h452319[39] ? + (_theResult____h452317[39] ? 6'd17 : - (_theResult____h452319[38] ? + (_theResult____h452317[38] ? 6'd18 : - (_theResult____h452319[37] ? + (_theResult____h452317[37] ? 6'd19 : - (_theResult____h452319[36] ? + (_theResult____h452317[36] ? 6'd20 : - (_theResult____h452319[35] ? + (_theResult____h452317[35] ? 6'd21 : - (_theResult____h452319[34] ? + (_theResult____h452317[34] ? 6'd22 : - (_theResult____h452319[33] ? + (_theResult____h452317[33] ? 6'd23 : - (_theResult____h452319[32] ? + (_theResult____h452317[32] ? 6'd24 : - (_theResult____h452319[31] ? + (_theResult____h452317[31] ? 6'd25 : - (_theResult____h452319[30] ? + (_theResult____h452317[30] ? 6'd26 : - (_theResult____h452319[29] ? + (_theResult____h452317[29] ? 6'd27 : - (_theResult____h452319[28] ? + (_theResult____h452317[28] ? 6'd28 : - (_theResult____h452319[27] ? + (_theResult____h452317[27] ? 6'd29 : - (_theResult____h452319[26] ? + (_theResult____h452317[26] ? 6'd30 : - (_theResult____h452319[25] ? + (_theResult____h452317[25] ? 6'd31 : - (_theResult____h452319[24] ? + (_theResult____h452317[24] ? 6'd32 : - (_theResult____h452319[23] ? + (_theResult____h452317[23] ? 6'd33 : - (_theResult____h452319[22] ? + (_theResult____h452317[22] ? 6'd34 : - (_theResult____h452319[21] ? + (_theResult____h452317[21] ? 6'd35 : - (_theResult____h452319[20] ? + (_theResult____h452317[20] ? 6'd36 : - (_theResult____h452319[19] ? + (_theResult____h452317[19] ? 6'd37 : - (_theResult____h452319[18] ? + (_theResult____h452317[18] ? 6'd38 : - (_theResult____h452319[17] ? + (_theResult____h452317[17] ? 6'd39 : - (_theResult____h452319[16] ? + (_theResult____h452317[16] ? 6'd40 : - (_theResult____h452319[15] ? + (_theResult____h452317[15] ? 6'd41 : - (_theResult____h452319[14] ? + (_theResult____h452317[14] ? 6'd42 : - (_theResult____h452319[13] ? + (_theResult____h452317[13] ? 6'd43 : - (_theResult____h452319[12] ? + (_theResult____h452317[12] ? 6'd44 : - (_theResult____h452319[11] ? + (_theResult____h452317[11] ? 6'd45 : - (_theResult____h452319[10] ? + (_theResult____h452317[10] ? 6'd46 : - (_theResult____h452319[9] ? + (_theResult____h452317[9] ? 6'd47 : - (_theResult____h452319[8] ? + (_theResult____h452317[8] ? 6'd48 : - (_theResult____h452319[7] ? + (_theResult____h452317[7] ? 6'd49 : - (_theResult____h452319[6] ? + (_theResult____h452317[6] ? 6'd50 : - (_theResult____h452319[5] ? + (_theResult____h452317[5] ? 6'd51 : - (_theResult____h452319[4] ? + (_theResult____h452317[4] ? 6'd52 : - (_theResult____h452319[3] ? + (_theResult____h452317[3] ? 6'd53 : - (_theResult____h452319[2] ? + (_theResult____h452317[2] ? 6'd54 : - (_theResult____h452319[1] ? + (_theResult____h452317[1] ? 6'd55 : - (_theResult____h452319[0] ? + (_theResult____h452317[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10404 = - (_theResult___fst_exp__h547054 == 11'd2047) ? + (_theResult___fst_exp__h547052 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10669 = - (_theResult___fst_exp__h547054 == 11'd2047) ? + (_theResult___fst_exp__h547052 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8931 = - (_theResult___fst_exp__h508253 == 11'd2047) ? + (_theResult___fst_exp__h508251 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9641 = - (_theResult___fst_exp__h586255 == 11'd2047) ? + (_theResult___fst_exp__h586253 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9907 = - (_theResult___fst_exp__h586255 == 11'd2047) ? + (_theResult___fst_exp__h586253 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 = - (guard__h343312 == 2'b0 || + (guard__h343310 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h351413 : - _theResult___exp__h351929 ; + _theResult___fst_exp__h351411 : + _theResult___exp__h351927 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 = - (guard__h343312 == 2'b0) ? - _theResult___fst_exp__h351413 : + (guard__h343310 == 2'b0) ? + _theResult___fst_exp__h351411 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h351929 : - _theResult___fst_exp__h351413) ; + _theResult___exp__h351927 : + _theResult___fst_exp__h351411) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 = - (guard__h343312 == 2'b0 || + (guard__h343310 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h351407[56:34] : - _theResult___sfd__h351930 ; + sfdin__h351405[56:34] : + _theResult___sfd__h351928 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 = - (guard__h343312 == 2'b0) ? - sfdin__h351407[56:34] : + (guard__h343310 == 2'b0) ? + sfdin__h351405[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h351930 : - sfdin__h351407[56:34]) ; + _theResult___sfd__h351928 : + sfdin__h351405[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 = - (guard__h389004 == 2'b0 || + (guard__h389002 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h397103 : - _theResult___exp__h397619 ; + _theResult___fst_exp__h397101 : + _theResult___exp__h397617 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 = - (guard__h389004 == 2'b0) ? - _theResult___fst_exp__h397103 : + (guard__h389002 == 2'b0) ? + _theResult___fst_exp__h397101 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h397619 : - _theResult___fst_exp__h397103) ; + _theResult___exp__h397617 : + _theResult___fst_exp__h397101) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 = - (guard__h389004 == 2'b0 || + (guard__h389002 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h397097[56:34] : - _theResult___sfd__h397620 ; + sfdin__h397095[56:34] : + _theResult___sfd__h397618 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 = - (guard__h389004 == 2'b0) ? - sfdin__h397097[56:34] : + (guard__h389002 == 2'b0) ? + sfdin__h397095[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h397620 : - sfdin__h397097[56:34]) ; + _theResult___sfd__h397618 : + sfdin__h397095[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 = - (guard__h434692 == 2'b0 || + (guard__h434690 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h442791 : - _theResult___exp__h443307 ; + _theResult___fst_exp__h442789 : + _theResult___exp__h443305 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 = - (guard__h434692 == 2'b0) ? - _theResult___fst_exp__h442791 : + (guard__h434690 == 2'b0) ? + _theResult___fst_exp__h442789 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h443307 : - _theResult___fst_exp__h442791) ; + _theResult___exp__h443305 : + _theResult___fst_exp__h442789) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 = - (guard__h434692 == 2'b0 || + (guard__h434690 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h442785[56:34] : - _theResult___sfd__h443308 ; + sfdin__h442783[56:34] : + _theResult___sfd__h443306 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 = - (guard__h434692 == 2'b0) ? - sfdin__h442785[56:34] : + (guard__h434690 == 2'b0) ? + sfdin__h442783[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h443308 : - sfdin__h442785[56:34]) ; + _theResult___sfd__h443306 : + sfdin__h442783[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 = - (guard__h538828 == 2'b0 || + (guard__h538826 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h547054 : - _theResult___exp__h547783 ; + _theResult___fst_exp__h547052 : + _theResult___exp__h547781 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 = - (guard__h538828 == 2'b0) ? - _theResult___fst_exp__h547054 : + (guard__h538826 == 2'b0) ? + _theResult___fst_exp__h547052 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h547783 : - _theResult___fst_exp__h547054) ; + _theResult___exp__h547781 : + _theResult___fst_exp__h547052) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 = - (guard__h538828 == 2'b0 || + (guard__h538826 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h547048[56:5] : - _theResult___sfd__h547784 ; + sfdin__h547046[56:5] : + _theResult___sfd__h547782 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 = - (guard__h538828 == 2'b0) ? - sfdin__h547048[56:5] : + (guard__h538826 == 2'b0) ? + sfdin__h547046[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h547784 : - sfdin__h547048[56:5]) ; + _theResult___sfd__h547782 : + sfdin__h547046[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 = - (guard__h500027 == 2'b0 || + (guard__h500025 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h508253 : - _theResult___exp__h508982 ; + _theResult___fst_exp__h508251 : + _theResult___exp__h508980 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 = - (guard__h500027 == 2'b0) ? - _theResult___fst_exp__h508253 : + (guard__h500025 == 2'b0) ? + _theResult___fst_exp__h508251 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h508982 : - _theResult___fst_exp__h508253) ; + _theResult___exp__h508980 : + _theResult___fst_exp__h508251) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 = - (guard__h500027 == 2'b0 || + (guard__h500025 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h508247[56:5] : - _theResult___sfd__h508983 ; + sfdin__h508245[56:5] : + _theResult___sfd__h508981 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 = - (guard__h500027 == 2'b0) ? - sfdin__h508247[56:5] : + (guard__h500025 == 2'b0) ? + sfdin__h508245[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h508983 : - sfdin__h508247[56:5]) ; + _theResult___sfd__h508981 : + sfdin__h508245[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 = - (guard__h578029 == 2'b0 || + (guard__h578027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h586255 : - _theResult___exp__h586984 ; + _theResult___fst_exp__h586253 : + _theResult___exp__h586982 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 = - (guard__h578029 == 2'b0) ? - _theResult___fst_exp__h586255 : + (guard__h578027 == 2'b0) ? + _theResult___fst_exp__h586253 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h586984 : - _theResult___fst_exp__h586255) ; + _theResult___exp__h586982 : + _theResult___fst_exp__h586253) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 = - (guard__h578029 == 2'b0 || + (guard__h578027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h586249[56:5] : - _theResult___sfd__h586985 ; + sfdin__h586247[56:5] : + _theResult___sfd__h586983 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 = - (guard__h578029 == 2'b0) ? - sfdin__h586249[56:5] : + (guard__h578027 == 2'b0) ? + sfdin__h586247[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h586985 : - sfdin__h586249[56:5]) ; + _theResult___sfd__h586983 : + sfdin__h586247[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 = - (guard__h360951 == 2'b0 || + (guard__h360949 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h369179 : - _theResult___exp__h369695 ; + _theResult___fst_exp__h369177 : + _theResult___exp__h369693 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 = - (guard__h360951 == 2'b0) ? - _theResult___fst_exp__h369179 : + (guard__h360949 == 2'b0) ? + _theResult___fst_exp__h369177 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h369695 : - _theResult___fst_exp__h369179) ; + _theResult___exp__h369693 : + _theResult___fst_exp__h369177) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 = - (guard__h360951 == 2'b0 || + (guard__h360949 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h369173[56:34] : - _theResult___sfd__h369696 ; + sfdin__h369171[56:34] : + _theResult___sfd__h369694 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 = - (guard__h360951 == 2'b0) ? - sfdin__h369173[56:34] : + (guard__h360949 == 2'b0) ? + sfdin__h369171[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h369696 : - sfdin__h369173[56:34]) ; + _theResult___sfd__h369694 : + sfdin__h369171[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 = - (guard__h406641 == 2'b0 || + (guard__h406639 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h414869 : - _theResult___exp__h415385 ; + _theResult___fst_exp__h414867 : + _theResult___exp__h415383 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 = - (guard__h406641 == 2'b0) ? - _theResult___fst_exp__h414869 : + (guard__h406639 == 2'b0) ? + _theResult___fst_exp__h414867 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h415385 : - _theResult___fst_exp__h414869) ; + _theResult___exp__h415383 : + _theResult___fst_exp__h414867) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 = - (guard__h406641 == 2'b0 || + (guard__h406639 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h414863[56:34] : - _theResult___sfd__h415386 ; + sfdin__h414861[56:34] : + _theResult___sfd__h415384 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 = - (guard__h406641 == 2'b0) ? - sfdin__h414863[56:34] : + (guard__h406639 == 2'b0) ? + sfdin__h414861[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h415386 : - sfdin__h414863[56:34]) ; + _theResult___sfd__h415384 : + sfdin__h414861[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 = - (guard__h452329 == 2'b0 || + (guard__h452327 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h460557 : - _theResult___exp__h461073 ; + _theResult___fst_exp__h460555 : + _theResult___exp__h461071 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 = - (guard__h452329 == 2'b0) ? - _theResult___fst_exp__h460557 : + (guard__h452327 == 2'b0) ? + _theResult___fst_exp__h460555 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h461073 : - _theResult___fst_exp__h460557) ; + _theResult___exp__h461071 : + _theResult___fst_exp__h460555) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 = - (guard__h452329 == 2'b0 || + (guard__h452327 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h460551[56:34] : - _theResult___sfd__h461074 ; + sfdin__h460549[56:34] : + _theResult___sfd__h461072 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 = - (guard__h452329 == 2'b0) ? - sfdin__h460551[56:34] : + (guard__h452327 == 2'b0) ? + sfdin__h460549[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h461074 : - sfdin__h460551[56:34]) ; + _theResult___sfd__h461072 : + sfdin__h460549[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 = - (guard__h352021 == 2'b0 || + (guard__h352019 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h360069 : - _theResult___exp__h360511 ; + _theResult___fst_exp__h360067 : + _theResult___exp__h360509 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 = - (guard__h352021 == 2'b0) ? - _theResult___fst_exp__h360069 : + (guard__h352019 == 2'b0) ? + _theResult___fst_exp__h360067 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h360511 : - _theResult___fst_exp__h360069) ; + _theResult___exp__h360509 : + _theResult___fst_exp__h360067) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 = - (guard__h369787 == 2'b0 || + (guard__h369785 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h377864 : - _theResult___exp__h378331 ; + _theResult___fst_exp__h377862 : + _theResult___exp__h378329 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 = - (guard__h369787 == 2'b0) ? - _theResult___fst_exp__h377864 : + (guard__h369785 == 2'b0) ? + _theResult___fst_exp__h377862 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h378331 : - _theResult___fst_exp__h377864) ; + _theResult___exp__h378329 : + _theResult___fst_exp__h377862) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 = - (guard__h352021 == 2'b0 || + (guard__h352019 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h360020[56:34] : - _theResult___sfd__h360512 ; + _theResult___snd__h360018[56:34] : + _theResult___sfd__h360510 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 = - (guard__h352021 == 2'b0) ? - _theResult___snd__h360020[56:34] : + (guard__h352019 == 2'b0) ? + _theResult___snd__h360018[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h360512 : - _theResult___snd__h360020[56:34]) ; + _theResult___sfd__h360510 : + _theResult___snd__h360018[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 = - (guard__h369787 == 2'b0 || + (guard__h369785 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h377810[56:34] : - _theResult___sfd__h378332 ; + _theResult___snd__h377808[56:34] : + _theResult___sfd__h378330 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 = - (guard__h369787 == 2'b0) ? - _theResult___snd__h377810[56:34] : + (guard__h369785 == 2'b0) ? + _theResult___snd__h377808[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h378332 : - _theResult___snd__h377810[56:34]) ; + _theResult___sfd__h378330 : + _theResult___snd__h377808[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 = - (guard__h397711 == 2'b0 || + (guard__h397709 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h405759 : - _theResult___exp__h406201 ; + _theResult___fst_exp__h405757 : + _theResult___exp__h406199 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 = - (guard__h397711 == 2'b0) ? - _theResult___fst_exp__h405759 : + (guard__h397709 == 2'b0) ? + _theResult___fst_exp__h405757 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h406201 : - _theResult___fst_exp__h405759) ; + _theResult___exp__h406199 : + _theResult___fst_exp__h405757) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 = - (guard__h415477 == 2'b0 || + (guard__h415475 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h423554 : - _theResult___exp__h424021 ; + _theResult___fst_exp__h423552 : + _theResult___exp__h424019 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 = - (guard__h415477 == 2'b0) ? - _theResult___fst_exp__h423554 : + (guard__h415475 == 2'b0) ? + _theResult___fst_exp__h423552 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h424021 : - _theResult___fst_exp__h423554) ; + _theResult___exp__h424019 : + _theResult___fst_exp__h423552) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 = - (guard__h397711 == 2'b0 || + (guard__h397709 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h405710[56:34] : - _theResult___sfd__h406202 ; + _theResult___snd__h405708[56:34] : + _theResult___sfd__h406200 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 = - (guard__h397711 == 2'b0) ? - _theResult___snd__h405710[56:34] : + (guard__h397709 == 2'b0) ? + _theResult___snd__h405708[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h406202 : - _theResult___snd__h405710[56:34]) ; + _theResult___sfd__h406200 : + _theResult___snd__h405708[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 = - (guard__h415477 == 2'b0 || + (guard__h415475 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h423500[56:34] : - _theResult___sfd__h424022 ; + _theResult___snd__h423498[56:34] : + _theResult___sfd__h424020 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 = - (guard__h415477 == 2'b0) ? - _theResult___snd__h423500[56:34] : + (guard__h415475 == 2'b0) ? + _theResult___snd__h423498[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h424022 : - _theResult___snd__h423500[56:34]) ; + _theResult___sfd__h424020 : + _theResult___snd__h423498[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 = - (guard__h443399 == 2'b0 || + (guard__h443397 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h451447 : - _theResult___exp__h451889 ; + _theResult___fst_exp__h451445 : + _theResult___exp__h451887 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 = - (guard__h443399 == 2'b0) ? - _theResult___fst_exp__h451447 : + (guard__h443397 == 2'b0) ? + _theResult___fst_exp__h451445 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h451889 : - _theResult___fst_exp__h451447) ; + _theResult___exp__h451887 : + _theResult___fst_exp__h451445) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 = - (guard__h461165 == 2'b0 || + (guard__h461163 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h469242 : - _theResult___exp__h469709 ; + _theResult___fst_exp__h469240 : + _theResult___exp__h469707 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 = - (guard__h461165 == 2'b0) ? - _theResult___fst_exp__h469242 : + (guard__h461163 == 2'b0) ? + _theResult___fst_exp__h469240 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h469709 : - _theResult___fst_exp__h469242) ; + _theResult___exp__h469707 : + _theResult___fst_exp__h469240) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 = - (guard__h443399 == 2'b0 || + (guard__h443397 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h451398[56:34] : - _theResult___sfd__h451890 ; + _theResult___snd__h451396[56:34] : + _theResult___sfd__h451888 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 = - (guard__h443399 == 2'b0) ? - _theResult___snd__h451398[56:34] : + (guard__h443397 == 2'b0) ? + _theResult___snd__h451396[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h451890 : - _theResult___snd__h451398[56:34]) ; + _theResult___sfd__h451888 : + _theResult___snd__h451396[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 = - (guard__h461165 == 2'b0 || + (guard__h461163 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h469188[56:34] : - _theResult___sfd__h469710 ; + _theResult___snd__h469186[56:34] : + _theResult___sfd__h469708 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 = - (guard__h461165 == 2'b0) ? - _theResult___snd__h469188[56:34] : + (guard__h461163 == 2'b0) ? + _theResult___snd__h469186[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h469710 : - _theResult___snd__h469188[56:34]) ; + _theResult___sfd__h469708 : + _theResult___snd__h469186[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 = - (guard__h529516 == 2'b0 || + (guard__h529514 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h537477 : - _theResult___exp__h538132 ; + _theResult___fst_exp__h537475 : + _theResult___exp__h538130 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 = - (guard__h529516 == 2'b0) ? - _theResult___fst_exp__h537477 : + (guard__h529514 == 2'b0) ? + _theResult___fst_exp__h537475 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h538132 : - _theResult___fst_exp__h537477) ; + _theResult___exp__h538130 : + _theResult___fst_exp__h537475) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 = - (guard__h547897 == 2'b0 || + (guard__h547895 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h555887 : - _theResult___exp__h556567 ; + _theResult___fst_exp__h555885 : + _theResult___exp__h556565 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 = - (guard__h547897 == 2'b0) ? - _theResult___fst_exp__h555887 : + (guard__h547895 == 2'b0) ? + _theResult___fst_exp__h555885 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h556567 : - _theResult___fst_exp__h555887) ; + _theResult___exp__h556565 : + _theResult___fst_exp__h555885) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 = - (guard__h529516 == 2'b0 || + (guard__h529514 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h537428[56:5] : - _theResult___sfd__h538133 ; + _theResult___snd__h537426[56:5] : + _theResult___sfd__h538131 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 = - (guard__h529516 == 2'b0) ? - _theResult___snd__h537428[56:5] : + (guard__h529514 == 2'b0) ? + _theResult___snd__h537426[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h538133 : - _theResult___snd__h537428[56:5]) ; + _theResult___sfd__h538131 : + _theResult___snd__h537426[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 = - (guard__h547897 == 2'b0 || + (guard__h547895 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h555833[56:5] : - _theResult___sfd__h556568 ; + _theResult___snd__h555831[56:5] : + _theResult___sfd__h556566 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 = - (guard__h547897 == 2'b0) ? - _theResult___snd__h555833[56:5] : + (guard__h547895 == 2'b0) ? + _theResult___snd__h555831[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h556568 : - _theResult___snd__h555833[56:5]) ; + _theResult___sfd__h556566 : + _theResult___snd__h555831[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 = - (guard__h490715 == 2'b0 || + (guard__h490713 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h498676 : - _theResult___exp__h499331 ; + _theResult___fst_exp__h498674 : + _theResult___exp__h499329 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 = - (guard__h490715 == 2'b0) ? - _theResult___fst_exp__h498676 : + (guard__h490713 == 2'b0) ? + _theResult___fst_exp__h498674 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h499331 : - _theResult___fst_exp__h498676) ; + _theResult___exp__h499329 : + _theResult___fst_exp__h498674) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 = - (guard__h509096 == 2'b0 || + (guard__h509094 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h517086 : - _theResult___exp__h517766 ; + _theResult___fst_exp__h517084 : + _theResult___exp__h517764 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 = - (guard__h509096 == 2'b0) ? - _theResult___fst_exp__h517086 : + (guard__h509094 == 2'b0) ? + _theResult___fst_exp__h517084 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h517766 : - _theResult___fst_exp__h517086) ; + _theResult___exp__h517764 : + _theResult___fst_exp__h517084) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 = - (guard__h490715 == 2'b0 || + (guard__h490713 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h498627[56:5] : - _theResult___sfd__h499332 ; + _theResult___snd__h498625[56:5] : + _theResult___sfd__h499330 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 = - (guard__h490715 == 2'b0) ? - _theResult___snd__h498627[56:5] : + (guard__h490713 == 2'b0) ? + _theResult___snd__h498625[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h499332 : - _theResult___snd__h498627[56:5]) ; + _theResult___sfd__h499330 : + _theResult___snd__h498625[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 = - (guard__h509096 == 2'b0 || + (guard__h509094 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h517032[56:5] : - _theResult___sfd__h517767 ; + _theResult___snd__h517030[56:5] : + _theResult___sfd__h517765 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 = - (guard__h509096 == 2'b0) ? - _theResult___snd__h517032[56:5] : + (guard__h509094 == 2'b0) ? + _theResult___snd__h517030[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h517767 : - _theResult___snd__h517032[56:5]) ; + _theResult___sfd__h517765 : + _theResult___snd__h517030[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 = - (guard__h568717 == 2'b0 || + (guard__h568715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h576678 : - _theResult___exp__h577333 ; + _theResult___fst_exp__h576676 : + _theResult___exp__h577331 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 = - (guard__h568717 == 2'b0) ? - _theResult___fst_exp__h576678 : + (guard__h568715 == 2'b0) ? + _theResult___fst_exp__h576676 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h577333 : - _theResult___fst_exp__h576678) ; + _theResult___exp__h577331 : + _theResult___fst_exp__h576676) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 = - (guard__h587098 == 2'b0 || + (guard__h587096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h595088 : - _theResult___exp__h595768 ; + _theResult___fst_exp__h595086 : + _theResult___exp__h595766 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 = - (guard__h587098 == 2'b0) ? - _theResult___fst_exp__h595088 : + (guard__h587096 == 2'b0) ? + _theResult___fst_exp__h595086 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h595768 : - _theResult___fst_exp__h595088) ; + _theResult___exp__h595766 : + _theResult___fst_exp__h595086) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 = - (guard__h568717 == 2'b0 || + (guard__h568715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h576629[56:5] : - _theResult___sfd__h577334 ; + _theResult___snd__h576627[56:5] : + _theResult___sfd__h577332 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 = - (guard__h568717 == 2'b0) ? - _theResult___snd__h576629[56:5] : + (guard__h568715 == 2'b0) ? + _theResult___snd__h576627[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h577334 : - _theResult___snd__h576629[56:5]) ; + _theResult___sfd__h577332 : + _theResult___snd__h576627[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 = - (guard__h587098 == 2'b0 || + (guard__h587096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h595034[56:5] : - _theResult___sfd__h595769 ; + _theResult___snd__h595032[56:5] : + _theResult___sfd__h595767 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 = - (guard__h587098 == 2'b0) ? - _theResult___snd__h595034[56:5] : + (guard__h587096 == 2'b0) ? + _theResult___snd__h595032[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h595769 : - _theResult___snd__h595034[56:5]) ; + _theResult___sfd__h595767 : + _theResult___snd__h595032[56:5]) ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674 = - (_theResult____h645398 == 15'd0 && + (_theResult____h645396 == 15'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h645942 : - _theResult____h645398 ; + enabled_ints__h645940 : + _theResult____h645396 ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12881 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || @@ -19255,67 +19255,67 @@ module mkCore(CLK, checkForException___d13458[4] || csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13547 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10450 = - (_theResult___fst_exp__h555887 == 11'd2047) ? + (_theResult___fst_exp__h555885 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10654 = - (_theResult___fst_exp__h537477 == 11'd2047) ? + (_theResult___fst_exp__h537475 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10681 = - (_theResult___fst_exp__h555887 == 11'd2047) ? + (_theResult___fst_exp__h555885 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8977 = - (_theResult___fst_exp__h517086 == 11'd2047) ? + (_theResult___fst_exp__h517084 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9687 = - (_theResult___fst_exp__h595088 == 11'd2047) ? + (_theResult___fst_exp__h595086 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892 = - (_theResult___fst_exp__h576678 == 11'd2047) ? + (_theResult___fst_exp__h576676 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9919 = - (_theResult___fst_exp__h595088 == 11'd2047) ? + (_theResult___fst_exp__h595086 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 = IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ? @@ -19521,35 +19521,35 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10109 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 || - _theResult___fst_exp__h537477 == 11'd2047) ? + _theResult___fst_exp__h537475 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8636 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 || - _theResult___fst_exp__h498676 == 11'd2047) ? + _theResult___fst_exp__h498674 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9346 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 || - _theResult___fst_exp__h576678 == 11'd2047) ? + _theResult___fst_exp__h576676 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] ? @@ -19987,35 +19987,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369179 == 8'd255) ? + ((_theResult___fst_exp__h369177 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) : - ((_theResult___fst_exp__h377864 == 8'd255) ? + ((_theResult___fst_exp__h377862 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369179 == 8'd255) ? + ((_theResult___fst_exp__h369177 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) : - ((_theResult___fst_exp__h377864 == 8'd255) ? + ((_theResult___fst_exp__h377862 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] : - _theResult___fst_exp__h378412 == 8'd255 && - _theResult___fst_sfd__h378413 == 23'd0 ; + _theResult___fst_exp__h378410 == 8'd255 && + _theResult___fst_sfd__h378411 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] : - _theResult___fst_exp__h377864 == 8'd0 && - guard__h369787 != 2'b0 ; + _theResult___fst_exp__h377862 == 8'd0 && + guard__h369785 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] : - _theResult___fst_exp__h377864 != 8'd255 && - guard__h369787 != 2'b0 ; + _theResult___fst_exp__h377862 != 8'd255 && + guard__h369785 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? @@ -20025,35 +20025,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414869 == 8'd255) ? + ((_theResult___fst_exp__h414867 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) : - ((_theResult___fst_exp__h423554 == 8'd255) ? + ((_theResult___fst_exp__h423552 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414869 == 8'd255) ? + ((_theResult___fst_exp__h414867 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) : - ((_theResult___fst_exp__h423554 == 8'd255) ? + ((_theResult___fst_exp__h423552 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] : - _theResult___fst_exp__h424102 == 8'd255 && - _theResult___fst_sfd__h424103 == 23'd0 ; + _theResult___fst_exp__h424100 == 8'd255 && + _theResult___fst_sfd__h424101 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] : - _theResult___fst_exp__h423554 == 8'd0 && - guard__h415477 != 2'b0 ; + _theResult___fst_exp__h423552 == 8'd0 && + guard__h415475 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] : - _theResult___fst_exp__h423554 != 8'd255 && - guard__h415477 != 2'b0 ; + _theResult___fst_exp__h423552 != 8'd255 && + guard__h415475 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? @@ -20063,35 +20063,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460557 == 8'd255) ? + ((_theResult___fst_exp__h460555 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) : - ((_theResult___fst_exp__h469242 == 8'd255) ? + ((_theResult___fst_exp__h469240 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460557 == 8'd255) ? + ((_theResult___fst_exp__h460555 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) : - ((_theResult___fst_exp__h469242 == 8'd255) ? + ((_theResult___fst_exp__h469240 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] : - _theResult___fst_exp__h469790 == 8'd255 && - _theResult___fst_sfd__h469791 == 23'd0 ; + _theResult___fst_exp__h469788 == 8'd255 && + _theResult___fst_sfd__h469789 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] : - _theResult___fst_exp__h469242 == 8'd0 && - guard__h461165 != 2'b0 ; + _theResult___fst_exp__h469240 == 8'd0 && + guard__h461163 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] : - _theResult___fst_exp__h469242 != 8'd255 && - guard__h461165 != 2'b0 ; + _theResult___fst_exp__h469240 != 8'd255 && + guard__h461163 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? @@ -20114,48 +20114,48 @@ module mkCore(CLK, assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10878 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[2] : - _theResult___fst_exp__h517869 == 11'd2047 && - _theResult___fst_sfd__h517870 == 52'd0 ; + _theResult___fst_exp__h517867 == 11'd2047 && + _theResult___fst_sfd__h517868 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10892 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[2] : - _theResult___fst_exp__h556670 == 11'd2047 && - _theResult___fst_sfd__h556671 == 52'd0 ; + _theResult___fst_exp__h556668 == 11'd2047 && + _theResult___fst_sfd__h556669 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10907 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[2] : - _theResult___fst_exp__h595871 == 11'd2047 && - _theResult___fst_sfd__h595872 == 52'd0 ; + _theResult___fst_exp__h595869 == 11'd2047 && + _theResult___fst_sfd__h595870 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10924 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[1] : - _theResult___fst_exp__h517086 == 11'd0 && - guard__h509096 != 2'b0 ; + _theResult___fst_exp__h517084 == 11'd0 && + guard__h509094 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10936 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[1] : - _theResult___fst_exp__h555887 == 11'd0 && - guard__h547897 != 2'b0 ; + _theResult___fst_exp__h555885 == 11'd0 && + guard__h547895 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10949 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[1] : - _theResult___fst_exp__h595088 == 11'd0 && - guard__h587098 != 2'b0 ; + _theResult___fst_exp__h595086 == 11'd0 && + guard__h587096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10966 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[0] : - _theResult___fst_exp__h517086 != 11'd2047 && - guard__h509096 != 2'b0 ; + _theResult___fst_exp__h517084 != 11'd2047 && + guard__h509094 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10978 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[0] : - _theResult___fst_exp__h555887 != 11'd2047 && - guard__h547897 != 2'b0 ; + _theResult___fst_exp__h555885 != 11'd2047 && + guard__h547895 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10991 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[0] : - _theResult___fst_exp__h595088 != 11'd2047 && - guard__h587098 != 2'b0 ; + _theResult___fst_exp__h595086 != 11'd2047 && + guard__h587096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? @@ -20877,11 +20877,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h556682, + _theResult___fst_exp__h556680, (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ? - _theResult___snd_fst_sfd__h518571 : - _theResult___fst_sfd__h556686 } ; + _theResult___snd_fst_sfd__h518569 : + _theResult___fst_sfd__h556684 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] : @@ -21079,11 +21079,11 @@ module mkCore(CLK, { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8981, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h517881, + _theResult___fst_exp__h517879, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ? - _theResult___snd_fst_sfd__h479629 : - _theResult___fst_sfd__h517885 } ; + _theResult___snd_fst_sfd__h479627 : + _theResult___fst_sfd__h517883 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] : @@ -21152,11 +21152,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h595883, + _theResult___fst_exp__h595881, (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ? - _theResult___snd_fst_sfd__h557772 : - _theResult___fst_sfd__h595887 } ; + _theResult___snd_fst_sfd__h557770 : + _theResult___fst_sfd__h595885 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] : @@ -21180,8 +21180,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h641105 : - w__h641100 ; + result__h641103 : + w__h641098 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -21203,39 +21203,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21288,7 +21288,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h194349 : + x__h194347 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? 64'd0 : 64'd1) ; @@ -21300,7 +21300,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 = - _theResult_____2__h293743 == v__h293163 ; + _theResult_____2__h293741 == v__h293161 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21309,7 +21309,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 = - _theResult_____2__h301739 == v__h296508 ; + _theResult_____2__h301737 == v__h296506 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21338,7 +21338,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h299373 } ; + x__h299371 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -21436,35 +21436,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -21492,7 +21492,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 = - _theResult_____2__h307733 == v__h307022 ; + _theResult_____2__h307731 == v__h307020 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21501,7 +21501,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 = - _theResult_____2__h315587 == v__h310898 ; + _theResult_____2__h315585 == v__h310896 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21653,7 +21653,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 = - _theResult_____2__h329156 == v__h328724 ; + _theResult_____2__h329154 == v__h328722 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -21702,7 +21702,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 = - _theResult_____2__h325931 == v__h325499 ; + _theResult_____2__h325929 == v__h325497 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -21849,60 +21849,60 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h705150 : + y_avValue_snd_snd_snd_snd_snd__h705148 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705134 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705132 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h705144 : + y_avValue_snd_snd_snd_fst__h705142 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 = rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__4562_BIT_25_456_ETC___d14762 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h508247[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66 = - sfdin__h414863[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91 = - sfdin__h442785[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h547048[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21 = - sfdin__h351407[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101 = - sfdin__h460551[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31 = - sfdin__h369173[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h586249[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56 = - sfdin__h397097[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58 = - _theResult___snd__h405710[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h517032[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71 = - _theResult___snd__h423500[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h537428[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93 = - _theResult___snd__h451398[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h555833[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23 = - _theResult___snd__h360020[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106 = - _theResult___snd__h469188[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h576629[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36 = - _theResult___snd__h377810[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h595034[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h498627[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h508245[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66 = + sfdin__h414861[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91 = + sfdin__h442783[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h547046[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21 = + sfdin__h351405[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101 = + sfdin__h460549[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31 = + sfdin__h369171[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h586247[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56 = + sfdin__h397095[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58 = + _theResult___snd__h405708[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h517030[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71 = + _theResult___snd__h423498[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h537426[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93 = + _theResult___snd__h451396[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h555831[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23 = + _theResult___snd__h360018[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106 = + _theResult___snd__h469186[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h576627[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36 = + _theResult___snd__h377808[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h595032[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h498625[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? @@ -21991,10 +21991,10 @@ module mkCore(CLK, !checkForException___d13458[4] && NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13483 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4555_4556_OR__ETC___d14768 = - (fflags__h705627 & csrf_fflags_reg) != fflags__h705627 || - !r__h608869 && + (fflags__h705625 & csrf_fflags_reg) != fflags__h705625 || + !r__h608870 && (IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 || - fflags__h705627 != 5'd0) ; + fflags__h705625 != 5'd0) ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13263 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -22806,8 +22806,8 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13117 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h649453 == 5'd0 && - imm__h649454 == 32'd0 || + rs1__h649451 == 5'd0 && + imm__h649452 == 32'd0 || IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 = @@ -23142,7 +23142,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - x__h288838 } ; + x__h288836 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -23275,15 +23275,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 = { 3'd0, - _theResult___fst_exp__h351413 == 8'd0 && - (sfdin__h351407[56:34] == 23'd0 || guard__h343312 != 2'b0), + _theResult___fst_exp__h351411 == 8'd0 && + (sfdin__h351405[56:34] == 23'd0 || guard__h343310 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h352010 == 8'd255 && - _theResult___fst_sfd__h352011 == 23'd0, + _theResult___fst_exp__h352008 == 8'd255 && + _theResult___fst_sfd__h352009 == 23'd0, 1'd0, - _theResult___fst_exp__h351413 != 8'd255 && - guard__h343312 != 2'b0 } ; + _theResult___fst_exp__h351411 != 8'd255 && + guard__h343310 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^ @@ -23291,15 +23291,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 = { 3'd0, - _theResult___fst_exp__h397103 == 8'd0 && - (sfdin__h397097[56:34] == 23'd0 || guard__h389004 != 2'b0), + _theResult___fst_exp__h397101 == 8'd0 && + (sfdin__h397095[56:34] == 23'd0 || guard__h389002 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h397700 == 8'd255 && - _theResult___fst_sfd__h397701 == 23'd0, + _theResult___fst_exp__h397698 == 8'd255 && + _theResult___fst_sfd__h397699 == 23'd0, 1'd0, - _theResult___fst_exp__h397103 != 8'd255 && - guard__h389004 != 2'b0 } ; + _theResult___fst_exp__h397101 != 8'd255 && + guard__h389002 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^ @@ -23307,15 +23307,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 = { 3'd0, - _theResult___fst_exp__h442791 == 8'd0 && - (sfdin__h442785[56:34] == 23'd0 || guard__h434692 != 2'b0), + _theResult___fst_exp__h442789 == 8'd0 && + (sfdin__h442783[56:34] == 23'd0 || guard__h434690 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h443388 == 8'd255 && - _theResult___fst_sfd__h443389 == 23'd0, + _theResult___fst_exp__h443386 == 8'd255 && + _theResult___fst_sfd__h443387 == 23'd0, 1'd0, - _theResult___fst_exp__h442791 != 8'd255 && - guard__h434692 != 2'b0 } ; + _theResult___fst_exp__h442789 != 8'd255 && + guard__h434690 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ^ @@ -23323,37 +23323,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736 = { 3'd0, - _theResult___fst_exp__h508253 == 11'd0 && - (sfdin__h508247[56:5] == 52'd0 || guard__h500027 != 2'b0), + _theResult___fst_exp__h508251 == 11'd0 && + (sfdin__h508245[56:5] == 52'd0 || guard__h500025 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h509085 == 11'd2047 && - _theResult___fst_sfd__h509086 == 52'd0, + _theResult___fst_exp__h509083 == 11'd2047 && + _theResult___fst_sfd__h509084 == 52'd0, 1'd0, - _theResult___fst_exp__h508253 != 11'd2047 && - guard__h500027 != 2'b0 } ; + _theResult___fst_exp__h508251 != 11'd2047 && + guard__h500025 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777 = { 3'd0, - _theResult___fst_exp__h547054 == 11'd0 && - (sfdin__h547048[56:5] == 52'd0 || guard__h538828 != 2'b0), + _theResult___fst_exp__h547052 == 11'd0 && + (sfdin__h547046[56:5] == 52'd0 || guard__h538826 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h547886 == 11'd2047 && - _theResult___fst_sfd__h547887 == 52'd0, + _theResult___fst_exp__h547884 == 11'd2047 && + _theResult___fst_sfd__h547885 == 52'd0, 1'd0, - _theResult___fst_exp__h547054 != 11'd2047 && - guard__h538828 != 2'b0 } ; + _theResult___fst_exp__h547052 != 11'd2047 && + guard__h538826 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821 = { 3'd0, - _theResult___fst_exp__h586255 == 11'd0 && - (sfdin__h586249[56:5] == 52'd0 || guard__h578029 != 2'b0), + _theResult___fst_exp__h586253 == 11'd0 && + (sfdin__h586247[56:5] == 52'd0 || guard__h578027 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h587087 == 11'd2047 && - _theResult___fst_sfd__h587088 == 52'd0, + _theResult___fst_exp__h587085 == 11'd2047 && + _theResult___fst_sfd__h587086 == 52'd0, 1'd0, - _theResult___fst_exp__h586255 != 11'd2047 && - guard__h578029 != 2'b0 } ; + _theResult___fst_exp__h586253 != 11'd2047 && + guard__h578027 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ^ @@ -23371,15 +23371,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 = { 3'd0, - _theResult___fst_exp__h369179 == 8'd0 && - (sfdin__h369173[56:34] == 23'd0 || guard__h360951 != 2'b0), + _theResult___fst_exp__h369177 == 8'd0 && + (sfdin__h369171[56:34] == 23'd0 || guard__h360949 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h369776 == 8'd255 && - _theResult___fst_sfd__h369777 == 23'd0, + _theResult___fst_exp__h369774 == 8'd255 && + _theResult___fst_sfd__h369775 == 23'd0, 1'd0, - _theResult___fst_exp__h369179 != 8'd255 && - guard__h360951 != 2'b0 } ; + _theResult___fst_exp__h369177 != 8'd255 && + guard__h360949 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^ @@ -23387,15 +23387,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 = { 3'd0, - _theResult___fst_exp__h414869 == 8'd0 && - (sfdin__h414863[56:34] == 23'd0 || guard__h406641 != 2'b0), + _theResult___fst_exp__h414867 == 8'd0 && + (sfdin__h414861[56:34] == 23'd0 || guard__h406639 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h415466 == 8'd255 && - _theResult___fst_sfd__h415467 == 23'd0, + _theResult___fst_exp__h415464 == 8'd255 && + _theResult___fst_sfd__h415465 == 23'd0, 1'd0, - _theResult___fst_exp__h414869 != 8'd255 && - guard__h406641 != 2'b0 } ; + _theResult___fst_exp__h414867 != 8'd255 && + guard__h406639 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^ @@ -23403,15 +23403,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 = { 3'd0, - _theResult___fst_exp__h460557 == 8'd0 && - (sfdin__h460551[56:34] == 23'd0 || guard__h452329 != 2'b0), + _theResult___fst_exp__h460555 == 8'd0 && + (sfdin__h460549[56:34] == 23'd0 || guard__h452327 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h461154 == 8'd255 && - _theResult___fst_sfd__h461155 == 23'd0, + _theResult___fst_exp__h461152 == 8'd255 && + _theResult___fst_sfd__h461153 == 23'd0, 1'd0, - _theResult___fst_exp__h460557 != 8'd255 && - guard__h452329 != 2'b0 } ; + _theResult___fst_exp__h460555 != 8'd255 && + guard__h452327 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^ @@ -23425,15 +23425,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 = { 3'd0, - _theResult___fst_exp__h360069 == 8'd0 && - guard__h352021 != 2'b0, + _theResult___fst_exp__h360067 == 8'd0 && + guard__h352019 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h360592 == 8'd255 && - _theResult___fst_sfd__h360593 == 23'd0, + _theResult___fst_exp__h360590 == 8'd255 && + _theResult___fst_sfd__h360591 == 23'd0, 1'd0, - _theResult___fst_exp__h360069 != 8'd255 && - guard__h352021 != 2'b0 } ; + _theResult___fst_exp__h360067 != 8'd255 && + guard__h352019 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ @@ -23447,15 +23447,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 = { 3'd0, - _theResult___fst_exp__h405759 == 8'd0 && - guard__h397711 != 2'b0, + _theResult___fst_exp__h405757 == 8'd0 && + guard__h397709 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h406282 == 8'd255 && - _theResult___fst_sfd__h406283 == 23'd0, + _theResult___fst_exp__h406280 == 8'd255 && + _theResult___fst_sfd__h406281 == 23'd0, 1'd0, - _theResult___fst_exp__h405759 != 8'd255 && - guard__h397711 != 2'b0 } ; + _theResult___fst_exp__h405757 != 8'd255 && + guard__h397709 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ @@ -23469,15 +23469,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 = { 3'd0, - _theResult___fst_exp__h451447 == 8'd0 && - guard__h443399 != 2'b0, + _theResult___fst_exp__h451445 == 8'd0 && + guard__h443397 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h451970 == 8'd255 && - _theResult___fst_sfd__h451971 == 23'd0, + _theResult___fst_exp__h451968 == 8'd255 && + _theResult___fst_sfd__h451969 == 23'd0, 1'd0, - _theResult___fst_exp__h451447 != 8'd255 && - guard__h443399 != 2'b0 } ; + _theResult___fst_exp__h451445 != 8'd255 && + guard__h443397 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ^ @@ -23491,37 +23491,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719 = { 3'd0, - _theResult___fst_exp__h498676 == 11'd0 && - guard__h490715 != 2'b0, + _theResult___fst_exp__h498674 == 11'd0 && + guard__h490713 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h499434 == 11'd2047 && - _theResult___fst_sfd__h499435 == 52'd0, + _theResult___fst_exp__h499432 == 11'd2047 && + _theResult___fst_sfd__h499433 == 52'd0, 1'd0, - _theResult___fst_exp__h498676 != 11'd2047 && - guard__h490715 != 2'b0 } ; + _theResult___fst_exp__h498674 != 11'd2047 && + guard__h490713 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760 = { 3'd0, - _theResult___fst_exp__h537477 == 11'd0 && - guard__h529516 != 2'b0, + _theResult___fst_exp__h537475 == 11'd0 && + guard__h529514 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h538235 == 11'd2047 && - _theResult___fst_sfd__h538236 == 52'd0, + _theResult___fst_exp__h538233 == 11'd2047 && + _theResult___fst_sfd__h538234 == 52'd0, 1'd0, - _theResult___fst_exp__h537477 != 11'd2047 && - guard__h529516 != 2'b0 } ; + _theResult___fst_exp__h537475 != 11'd2047 && + guard__h529514 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804 = { 3'd0, - _theResult___fst_exp__h576678 == 11'd0 && - guard__h568717 != 2'b0, + _theResult___fst_exp__h576676 == 11'd0 && + guard__h568715 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h577436 == 11'd2047 && - _theResult___fst_sfd__h577437 == 52'd0, + _theResult___fst_exp__h577434 == 11'd2047 && + _theResult___fst_sfd__h577435 == 52'd0, 1'd0, - _theResult___fst_exp__h576678 != 11'd2047 && - guard__h568717 != 2'b0 } ; + _theResult___fst_exp__h576676 != 11'd2047 && + guard__h568715 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ^ @@ -23547,7 +23547,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2605_BI_ETC___d13675 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2614_BI_ETC___d13760 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -23559,33 +23559,33 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 = - sfd__h335697 >> + sfd__h335695 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 = - sfd__h381392 >> + sfd__h381390 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 = - sfd__h427080 >> + sfd__h427078 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118 = - sfd__h518617 >> + sfd__h518615 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645 = - sfd__h479675 >> + sfd__h479673 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355 = - sfd__h557818 >> + sfd__h557816 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1598_1599_ETC___d14227 = - medeleg_csr__read__h607140[i__h692204] ; + medeleg_csr__read__h607141[i__h692202] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1606_1607_ETC___d14209 = - mideleg_csr__read__h607235[i__h692364] ; + mideleg_csr__read__h607236[i__h692362] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 = 12'd3074 - { 6'd0, @@ -24180,7 +24180,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h661045 == 1'd0 && + k__h661043 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd0 && @@ -24199,7 +24199,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo26 = + assign _dfoo28 = rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd8 || @@ -24287,1430 +24287,1430 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h293743 = + assign _theResult_____2__h293741 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ? - next_deqP___1__h294022 : + next_deqP___1__h294020 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h301739 = + assign _theResult_____2__h301737 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ? - next_deqP___1__h302018 : + next_deqP___1__h302016 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h307733 = + assign _theResult_____2__h307731 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ? - next_deqP___1__h308299 : + next_deqP___1__h308297 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h315587 = + assign _theResult_____2__h315585 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ? - next_deqP___1__h316153 : + next_deqP___1__h316151 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h325931 = + assign _theResult_____2__h325929 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ? - next_deqP___1__h326210 : + next_deqP___1__h326208 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h329156 = + assign _theResult_____2__h329154 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ? - next_deqP___1__h329435 : + next_deqP___1__h329433 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h343302 = - (value__h343924 == 54'd0) ? sfd__h335697 : 57'd1 ; - assign _theResult____h360941 = + assign _theResult____h343300 = + (value__h343922 == 54'd0) ? sfd__h335695 : 57'd1 ; + assign _theResult____h360939 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^ 12'h800) < 12'd2105) ? - result__h361554 : - _theResult____h343302 ; - assign _theResult____h388994 = - (value__h389614 == 54'd0) ? sfd__h381392 : 57'd1 ; - assign _theResult____h406631 = + result__h361552 : + _theResult____h343300 ; + assign _theResult____h388992 = + (value__h389612 == 54'd0) ? sfd__h381390 : 57'd1 ; + assign _theResult____h406629 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^ 12'h800) < 12'd2105) ? - result__h407244 : - _theResult____h388994 ; - assign _theResult____h434682 = - (value__h435302 == 54'd0) ? sfd__h427080 : 57'd1 ; - assign _theResult____h452319 = + result__h407242 : + _theResult____h388992 ; + assign _theResult____h434680 = + (value__h435300 == 54'd0) ? sfd__h427078 : 57'd1 ; + assign _theResult____h452317 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^ 12'h800) < 12'd2105) ? - result__h452932 : - _theResult____h434682 ; - assign _theResult____h500017 = + result__h452930 : + _theResult____h434680 ; + assign _theResult____h500015 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ^ 12'h800) < 12'd2105) ? - result__h500630 : - ((value__h484233 == 25'd0) ? sfd__h479675 : 57'd1) ; - assign _theResult____h538818 = + result__h500628 : + ((value__h484231 == 25'd0) ? sfd__h479673 : 57'd1) ; + assign _theResult____h538816 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ^ 12'h800) < 12'd2105) ? - result__h539431 : - ((value__h523034 == 25'd0) ? sfd__h518617 : 57'd1) ; - assign _theResult____h578019 = + result__h539429 : + ((value__h523032 == 25'd0) ? sfd__h518615 : 57'd1) ; + assign _theResult____h578017 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ^ 12'h800) < 12'd2105) ? - result__h578632 : - ((value__h562235 == 25'd0) ? sfd__h557818 : 57'd1) ; - assign _theResult____h645398 = + result__h578630 : + ((value__h562233 == 25'd0) ? sfd__h557816 : 57'd1) ; + assign _theResult____h645396 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h645895 : + enabled_ints___1__h645893 : 15'd0 ; - assign _theResult___exp__h351929 = - sfd__h351505[24] ? - ((_theResult___fst_exp__h351413 == 8'd254) ? + assign _theResult___exp__h351927 = + sfd__h351503[24] ? + ((_theResult___fst_exp__h351411 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378446) : - ((_theResult___fst_exp__h351413 == 8'd0 && - sfd__h351505[24:23] == 2'b01) ? + din_inc___2_exp__h378444) : + ((_theResult___fst_exp__h351411 == 8'd0 && + sfd__h351503[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h351413) ; - assign _theResult___exp__h360511 = - sfd__h360087[24] ? - ((_theResult___fst_exp__h360069 == 8'd254) ? + _theResult___fst_exp__h351411) ; + assign _theResult___exp__h360509 = + sfd__h360085[24] ? + ((_theResult___fst_exp__h360067 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378470) : - ((_theResult___fst_exp__h360069 == 8'd0 && - sfd__h360087[24:23] == 2'b01) ? + din_inc___2_exp__h378468) : + ((_theResult___fst_exp__h360067 == 8'd0 && + sfd__h360085[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h360069) ; - assign _theResult___exp__h369695 = - sfd__h369271[24] ? - ((_theResult___fst_exp__h369179 == 8'd254) ? + _theResult___fst_exp__h360067) ; + assign _theResult___exp__h369693 = + sfd__h369269[24] ? + ((_theResult___fst_exp__h369177 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378500) : - ((_theResult___fst_exp__h369179 == 8'd0 && - sfd__h369271[24:23] == 2'b01) ? + din_inc___2_exp__h378498) : + ((_theResult___fst_exp__h369177 == 8'd0 && + sfd__h369269[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h369179) ; - assign _theResult___exp__h378331 = - sfd__h377883[24] ? - ((_theResult___fst_exp__h377864 == 8'd254) ? + _theResult___fst_exp__h369177) ; + assign _theResult___exp__h378329 = + sfd__h377881[24] ? + ((_theResult___fst_exp__h377862 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378524) : - ((_theResult___fst_exp__h377864 == 8'd0 && - sfd__h377883[24:23] == 2'b01) ? + din_inc___2_exp__h378522) : + ((_theResult___fst_exp__h377862 == 8'd0 && + sfd__h377881[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h377864) ; - assign _theResult___exp__h378433 = + _theResult___fst_exp__h377862) ; + assign _theResult___exp__h378431 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378424 ; - assign _theResult___exp__h397619 = - sfd__h397195[24] ? - ((_theResult___fst_exp__h397103 == 8'd254) ? + _theResult___fst_exp__h378422 ; + assign _theResult___exp__h397617 = + sfd__h397193[24] ? + ((_theResult___fst_exp__h397101 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424136) : - ((_theResult___fst_exp__h397103 == 8'd0 && - sfd__h397195[24:23] == 2'b01) ? + din_inc___2_exp__h424134) : + ((_theResult___fst_exp__h397101 == 8'd0 && + sfd__h397193[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h397103) ; - assign _theResult___exp__h406201 = - sfd__h405777[24] ? - ((_theResult___fst_exp__h405759 == 8'd254) ? + _theResult___fst_exp__h397101) ; + assign _theResult___exp__h406199 = + sfd__h405775[24] ? + ((_theResult___fst_exp__h405757 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424160) : - ((_theResult___fst_exp__h405759 == 8'd0 && - sfd__h405777[24:23] == 2'b01) ? + din_inc___2_exp__h424158) : + ((_theResult___fst_exp__h405757 == 8'd0 && + sfd__h405775[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h405759) ; - assign _theResult___exp__h415385 = - sfd__h414961[24] ? - ((_theResult___fst_exp__h414869 == 8'd254) ? + _theResult___fst_exp__h405757) ; + assign _theResult___exp__h415383 = + sfd__h414959[24] ? + ((_theResult___fst_exp__h414867 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424190) : - ((_theResult___fst_exp__h414869 == 8'd0 && - sfd__h414961[24:23] == 2'b01) ? + din_inc___2_exp__h424188) : + ((_theResult___fst_exp__h414867 == 8'd0 && + sfd__h414959[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h414869) ; - assign _theResult___exp__h424021 = - sfd__h423573[24] ? - ((_theResult___fst_exp__h423554 == 8'd254) ? + _theResult___fst_exp__h414867) ; + assign _theResult___exp__h424019 = + sfd__h423571[24] ? + ((_theResult___fst_exp__h423552 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424214) : - ((_theResult___fst_exp__h423554 == 8'd0 && - sfd__h423573[24:23] == 2'b01) ? + din_inc___2_exp__h424212) : + ((_theResult___fst_exp__h423552 == 8'd0 && + sfd__h423571[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h423554) ; - assign _theResult___exp__h424123 = + _theResult___fst_exp__h423552) ; + assign _theResult___exp__h424121 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424114 ; - assign _theResult___exp__h443307 = - sfd__h442883[24] ? - ((_theResult___fst_exp__h442791 == 8'd254) ? + _theResult___fst_exp__h424112 ; + assign _theResult___exp__h443305 = + sfd__h442881[24] ? + ((_theResult___fst_exp__h442789 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469824) : - ((_theResult___fst_exp__h442791 == 8'd0 && - sfd__h442883[24:23] == 2'b01) ? + din_inc___2_exp__h469822) : + ((_theResult___fst_exp__h442789 == 8'd0 && + sfd__h442881[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h442791) ; - assign _theResult___exp__h451889 = - sfd__h451465[24] ? - ((_theResult___fst_exp__h451447 == 8'd254) ? + _theResult___fst_exp__h442789) ; + assign _theResult___exp__h451887 = + sfd__h451463[24] ? + ((_theResult___fst_exp__h451445 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469848) : - ((_theResult___fst_exp__h451447 == 8'd0 && - sfd__h451465[24:23] == 2'b01) ? + din_inc___2_exp__h469846) : + ((_theResult___fst_exp__h451445 == 8'd0 && + sfd__h451463[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h451447) ; - assign _theResult___exp__h461073 = - sfd__h460649[24] ? - ((_theResult___fst_exp__h460557 == 8'd254) ? + _theResult___fst_exp__h451445) ; + assign _theResult___exp__h461071 = + sfd__h460647[24] ? + ((_theResult___fst_exp__h460555 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469878) : - ((_theResult___fst_exp__h460557 == 8'd0 && - sfd__h460649[24:23] == 2'b01) ? + din_inc___2_exp__h469876) : + ((_theResult___fst_exp__h460555 == 8'd0 && + sfd__h460647[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h460557) ; - assign _theResult___exp__h469709 = - sfd__h469261[24] ? - ((_theResult___fst_exp__h469242 == 8'd254) ? + _theResult___fst_exp__h460555) ; + assign _theResult___exp__h469707 = + sfd__h469259[24] ? + ((_theResult___fst_exp__h469240 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469902) : - ((_theResult___fst_exp__h469242 == 8'd0 && - sfd__h469261[24:23] == 2'b01) ? + din_inc___2_exp__h469900) : + ((_theResult___fst_exp__h469240 == 8'd0 && + sfd__h469259[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h469242) ; - assign _theResult___exp__h469811 = + _theResult___fst_exp__h469240) ; + assign _theResult___exp__h469809 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469802 ; - assign _theResult___exp__h499331 = - sfd__h498694[53] ? - ((_theResult___fst_exp__h498676 == 11'd2046) ? + _theResult___fst_exp__h469800 ; + assign _theResult___exp__h499329 = + sfd__h498692[53] ? + ((_theResult___fst_exp__h498674 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517926) : - ((_theResult___fst_exp__h498676 == 11'd0 && - sfd__h498694[53:52] == 2'b01) ? + din_inc___2_exp__h517924) : + ((_theResult___fst_exp__h498674 == 11'd0 && + sfd__h498692[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h498676) ; - assign _theResult___exp__h508982 = - sfd__h508345[53] ? - ((_theResult___fst_exp__h508253 == 11'd2046) ? + _theResult___fst_exp__h498674) ; + assign _theResult___exp__h508980 = + sfd__h508343[53] ? + ((_theResult___fst_exp__h508251 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517961) : - ((_theResult___fst_exp__h508253 == 11'd0 && - sfd__h508345[53:52] == 2'b01) ? + din_inc___2_exp__h517959) : + ((_theResult___fst_exp__h508251 == 11'd0 && + sfd__h508343[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h508253) ; - assign _theResult___exp__h517766 = - sfd__h517105[53] ? - ((_theResult___fst_exp__h517086 == 11'd2046) ? + _theResult___fst_exp__h508251) ; + assign _theResult___exp__h517764 = + sfd__h517103[53] ? + ((_theResult___fst_exp__h517084 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517987) : - ((_theResult___fst_exp__h517086 == 11'd0 && - sfd__h517105[53:52] == 2'b01) ? + din_inc___2_exp__h517985) : + ((_theResult___fst_exp__h517084 == 11'd0 && + sfd__h517103[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h517086) ; - assign _theResult___exp__h538132 = - sfd__h537495[53] ? - ((_theResult___fst_exp__h537477 == 11'd2046) ? + _theResult___fst_exp__h517084) ; + assign _theResult___exp__h538130 = + sfd__h537493[53] ? + ((_theResult___fst_exp__h537475 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556727) : - ((_theResult___fst_exp__h537477 == 11'd0 && - sfd__h537495[53:52] == 2'b01) ? + din_inc___2_exp__h556725) : + ((_theResult___fst_exp__h537475 == 11'd0 && + sfd__h537493[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h537477) ; - assign _theResult___exp__h547783 = - sfd__h547146[53] ? - ((_theResult___fst_exp__h547054 == 11'd2046) ? + _theResult___fst_exp__h537475) ; + assign _theResult___exp__h547781 = + sfd__h547144[53] ? + ((_theResult___fst_exp__h547052 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556762) : - ((_theResult___fst_exp__h547054 == 11'd0 && - sfd__h547146[53:52] == 2'b01) ? + din_inc___2_exp__h556760) : + ((_theResult___fst_exp__h547052 == 11'd0 && + sfd__h547144[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h547054) ; - assign _theResult___exp__h556567 = - sfd__h555906[53] ? - ((_theResult___fst_exp__h555887 == 11'd2046) ? + _theResult___fst_exp__h547052) ; + assign _theResult___exp__h556565 = + sfd__h555904[53] ? + ((_theResult___fst_exp__h555885 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556788) : - ((_theResult___fst_exp__h555887 == 11'd0 && - sfd__h555906[53:52] == 2'b01) ? + din_inc___2_exp__h556786) : + ((_theResult___fst_exp__h555885 == 11'd0 && + sfd__h555904[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h555887) ; - assign _theResult___exp__h577333 = - sfd__h576696[53] ? - ((_theResult___fst_exp__h576678 == 11'd2046) ? + _theResult___fst_exp__h555885) ; + assign _theResult___exp__h577331 = + sfd__h576694[53] ? + ((_theResult___fst_exp__h576676 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595928) : - ((_theResult___fst_exp__h576678 == 11'd0 && - sfd__h576696[53:52] == 2'b01) ? + din_inc___2_exp__h595926) : + ((_theResult___fst_exp__h576676 == 11'd0 && + sfd__h576694[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h576678) ; - assign _theResult___exp__h586984 = - sfd__h586347[53] ? - ((_theResult___fst_exp__h586255 == 11'd2046) ? + _theResult___fst_exp__h576676) ; + assign _theResult___exp__h586982 = + sfd__h586345[53] ? + ((_theResult___fst_exp__h586253 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595963) : - ((_theResult___fst_exp__h586255 == 11'd0 && - sfd__h586347[53:52] == 2'b01) ? + din_inc___2_exp__h595961) : + ((_theResult___fst_exp__h586253 == 11'd0 && + sfd__h586345[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h586255) ; - assign _theResult___exp__h595768 = - sfd__h595107[53] ? - ((_theResult___fst_exp__h595088 == 11'd2046) ? + _theResult___fst_exp__h586253) ; + assign _theResult___exp__h595766 = + sfd__h595105[53] ? + ((_theResult___fst_exp__h595086 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595989) : - ((_theResult___fst_exp__h595088 == 11'd0 && - sfd__h595107[53:52] == 2'b01) ? + din_inc___2_exp__h595987) : + ((_theResult___fst_exp__h595086 == 11'd0 && + sfd__h595105[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h595088) ; - assign _theResult___fst__h600261 = - a__h599839[63] ? a___1__h600266 : a__h599839 ; - assign _theResult___fst_exp__h351413 = - _theResult____h343302[56] ? + _theResult___fst_exp__h595086) ; + assign _theResult___fst__h600259 = + a__h599837[63] ? a___1__h600264 : a__h599837 ; + assign _theResult___fst_exp__h351411 = + _theResult____h343300[56] ? 8'd2 : - _theResult___fst_exp__h351487 ; - assign _theResult___fst_exp__h351478 = + _theResult___fst_exp__h351485 ; + assign _theResult___fst_exp__h351476 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ; - assign _theResult___fst_exp__h351484 = - (!_theResult____h343302[56] && !_theResult____h343302[55] && - !_theResult____h343302[54] && - !_theResult____h343302[53] && - !_theResult____h343302[52] && - !_theResult____h343302[51] && - !_theResult____h343302[50] && - !_theResult____h343302[49] && - !_theResult____h343302[48] && - !_theResult____h343302[47] && - !_theResult____h343302[46] && - !_theResult____h343302[45] && - !_theResult____h343302[44] && - !_theResult____h343302[43] && - !_theResult____h343302[42] && - !_theResult____h343302[41] && - !_theResult____h343302[40] && - !_theResult____h343302[39] && - !_theResult____h343302[38] && - !_theResult____h343302[37] && - !_theResult____h343302[36] && - !_theResult____h343302[35] && - !_theResult____h343302[34] && - !_theResult____h343302[33] && - !_theResult____h343302[32] && - !_theResult____h343302[31] && - !_theResult____h343302[30] && - !_theResult____h343302[29] && - !_theResult____h343302[28] && - !_theResult____h343302[27] && - !_theResult____h343302[26] && - !_theResult____h343302[25] && - !_theResult____h343302[24] && - !_theResult____h343302[23] && - !_theResult____h343302[22] && - !_theResult____h343302[21] && - !_theResult____h343302[20] && - !_theResult____h343302[19] && - !_theResult____h343302[18] && - !_theResult____h343302[17] && - !_theResult____h343302[16] && - !_theResult____h343302[15] && - !_theResult____h343302[14] && - !_theResult____h343302[13] && - !_theResult____h343302[12] && - !_theResult____h343302[11] && - !_theResult____h343302[10] && - !_theResult____h343302[9] && - !_theResult____h343302[8] && - !_theResult____h343302[7] && - !_theResult____h343302[6] && - !_theResult____h343302[5] && - !_theResult____h343302[4] && - !_theResult____h343302[3] && - !_theResult____h343302[2] && - !_theResult____h343302[1] && - !_theResult____h343302[0] || + assign _theResult___fst_exp__h351482 = + (!_theResult____h343300[56] && !_theResult____h343300[55] && + !_theResult____h343300[54] && + !_theResult____h343300[53] && + !_theResult____h343300[52] && + !_theResult____h343300[51] && + !_theResult____h343300[50] && + !_theResult____h343300[49] && + !_theResult____h343300[48] && + !_theResult____h343300[47] && + !_theResult____h343300[46] && + !_theResult____h343300[45] && + !_theResult____h343300[44] && + !_theResult____h343300[43] && + !_theResult____h343300[42] && + !_theResult____h343300[41] && + !_theResult____h343300[40] && + !_theResult____h343300[39] && + !_theResult____h343300[38] && + !_theResult____h343300[37] && + !_theResult____h343300[36] && + !_theResult____h343300[35] && + !_theResult____h343300[34] && + !_theResult____h343300[33] && + !_theResult____h343300[32] && + !_theResult____h343300[31] && + !_theResult____h343300[30] && + !_theResult____h343300[29] && + !_theResult____h343300[28] && + !_theResult____h343300[27] && + !_theResult____h343300[26] && + !_theResult____h343300[25] && + !_theResult____h343300[24] && + !_theResult____h343300[23] && + !_theResult____h343300[22] && + !_theResult____h343300[21] && + !_theResult____h343300[20] && + !_theResult____h343300[19] && + !_theResult____h343300[18] && + !_theResult____h343300[17] && + !_theResult____h343300[16] && + !_theResult____h343300[15] && + !_theResult____h343300[14] && + !_theResult____h343300[13] && + !_theResult____h343300[12] && + !_theResult____h343300[11] && + !_theResult____h343300[10] && + !_theResult____h343300[9] && + !_theResult____h343300[8] && + !_theResult____h343300[7] && + !_theResult____h343300[6] && + !_theResult____h343300[5] && + !_theResult____h343300[4] && + !_theResult____h343300[3] && + !_theResult____h343300[2] && + !_theResult____h343300[1] && + !_theResult____h343300[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ? 8'd0 : - _theResult___fst_exp__h351478 ; - assign _theResult___fst_exp__h351487 = - (!_theResult____h343302[56] && _theResult____h343302[55]) ? + _theResult___fst_exp__h351476 ; + assign _theResult___fst_exp__h351485 = + (!_theResult____h343300[56] && _theResult____h343300[55]) ? 8'd1 : - _theResult___fst_exp__h351484 ; - assign _theResult___fst_exp__h352010 = - (_theResult___fst_exp__h351413 == 8'd255) ? - _theResult___fst_exp__h351413 : - _theResult___fst_exp__h352007 ; - assign _theResult___fst_exp__h360060 = + _theResult___fst_exp__h351482 ; + assign _theResult___fst_exp__h352008 = + (_theResult___fst_exp__h351411 == 8'd255) ? + _theResult___fst_exp__h351411 : + _theResult___fst_exp__h352005 ; + assign _theResult___fst_exp__h360058 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h360066 = + assign _theResult___fst_exp__h360064 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ? 8'd0 : - _theResult___fst_exp__h360060 ; - assign _theResult___fst_exp__h360069 = + _theResult___fst_exp__h360058 ; + assign _theResult___fst_exp__h360067 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h360066 : + _theResult___fst_exp__h360064 : 8'd129 ; - assign _theResult___fst_exp__h360592 = - (_theResult___fst_exp__h360069 == 8'd255) ? - _theResult___fst_exp__h360069 : - _theResult___fst_exp__h360589 ; - assign _theResult___fst_exp__h369179 = - _theResult____h360941[56] ? + assign _theResult___fst_exp__h360590 = + (_theResult___fst_exp__h360067 == 8'd255) ? + _theResult___fst_exp__h360067 : + _theResult___fst_exp__h360587 ; + assign _theResult___fst_exp__h369177 = + _theResult____h360939[56] ? 8'd2 : - _theResult___fst_exp__h369253 ; - assign _theResult___fst_exp__h369244 = + _theResult___fst_exp__h369251 ; + assign _theResult___fst_exp__h369242 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ; - assign _theResult___fst_exp__h369250 = - (!_theResult____h360941[56] && !_theResult____h360941[55] && - !_theResult____h360941[54] && - !_theResult____h360941[53] && - !_theResult____h360941[52] && - !_theResult____h360941[51] && - !_theResult____h360941[50] && - !_theResult____h360941[49] && - !_theResult____h360941[48] && - !_theResult____h360941[47] && - !_theResult____h360941[46] && - !_theResult____h360941[45] && - !_theResult____h360941[44] && - !_theResult____h360941[43] && - !_theResult____h360941[42] && - !_theResult____h360941[41] && - !_theResult____h360941[40] && - !_theResult____h360941[39] && - !_theResult____h360941[38] && - !_theResult____h360941[37] && - !_theResult____h360941[36] && - !_theResult____h360941[35] && - !_theResult____h360941[34] && - !_theResult____h360941[33] && - !_theResult____h360941[32] && - !_theResult____h360941[31] && - !_theResult____h360941[30] && - !_theResult____h360941[29] && - !_theResult____h360941[28] && - !_theResult____h360941[27] && - !_theResult____h360941[26] && - !_theResult____h360941[25] && - !_theResult____h360941[24] && - !_theResult____h360941[23] && - !_theResult____h360941[22] && - !_theResult____h360941[21] && - !_theResult____h360941[20] && - !_theResult____h360941[19] && - !_theResult____h360941[18] && - !_theResult____h360941[17] && - !_theResult____h360941[16] && - !_theResult____h360941[15] && - !_theResult____h360941[14] && - !_theResult____h360941[13] && - !_theResult____h360941[12] && - !_theResult____h360941[11] && - !_theResult____h360941[10] && - !_theResult____h360941[9] && - !_theResult____h360941[8] && - !_theResult____h360941[7] && - !_theResult____h360941[6] && - !_theResult____h360941[5] && - !_theResult____h360941[4] && - !_theResult____h360941[3] && - !_theResult____h360941[2] && - !_theResult____h360941[1] && - !_theResult____h360941[0] || + assign _theResult___fst_exp__h369248 = + (!_theResult____h360939[56] && !_theResult____h360939[55] && + !_theResult____h360939[54] && + !_theResult____h360939[53] && + !_theResult____h360939[52] && + !_theResult____h360939[51] && + !_theResult____h360939[50] && + !_theResult____h360939[49] && + !_theResult____h360939[48] && + !_theResult____h360939[47] && + !_theResult____h360939[46] && + !_theResult____h360939[45] && + !_theResult____h360939[44] && + !_theResult____h360939[43] && + !_theResult____h360939[42] && + !_theResult____h360939[41] && + !_theResult____h360939[40] && + !_theResult____h360939[39] && + !_theResult____h360939[38] && + !_theResult____h360939[37] && + !_theResult____h360939[36] && + !_theResult____h360939[35] && + !_theResult____h360939[34] && + !_theResult____h360939[33] && + !_theResult____h360939[32] && + !_theResult____h360939[31] && + !_theResult____h360939[30] && + !_theResult____h360939[29] && + !_theResult____h360939[28] && + !_theResult____h360939[27] && + !_theResult____h360939[26] && + !_theResult____h360939[25] && + !_theResult____h360939[24] && + !_theResult____h360939[23] && + !_theResult____h360939[22] && + !_theResult____h360939[21] && + !_theResult____h360939[20] && + !_theResult____h360939[19] && + !_theResult____h360939[18] && + !_theResult____h360939[17] && + !_theResult____h360939[16] && + !_theResult____h360939[15] && + !_theResult____h360939[14] && + !_theResult____h360939[13] && + !_theResult____h360939[12] && + !_theResult____h360939[11] && + !_theResult____h360939[10] && + !_theResult____h360939[9] && + !_theResult____h360939[8] && + !_theResult____h360939[7] && + !_theResult____h360939[6] && + !_theResult____h360939[5] && + !_theResult____h360939[4] && + !_theResult____h360939[3] && + !_theResult____h360939[2] && + !_theResult____h360939[1] && + !_theResult____h360939[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ? 8'd0 : - _theResult___fst_exp__h369244 ; - assign _theResult___fst_exp__h369253 = - (!_theResult____h360941[56] && _theResult____h360941[55]) ? + _theResult___fst_exp__h369242 ; + assign _theResult___fst_exp__h369251 = + (!_theResult____h360939[56] && _theResult____h360939[55]) ? 8'd1 : - _theResult___fst_exp__h369250 ; - assign _theResult___fst_exp__h369776 = - (_theResult___fst_exp__h369179 == 8'd255) ? - _theResult___fst_exp__h369179 : - _theResult___fst_exp__h369773 ; - assign _theResult___fst_exp__h377816 = + _theResult___fst_exp__h369248 ; + assign _theResult___fst_exp__h369774 = + (_theResult___fst_exp__h369177 == 8'd255) ? + _theResult___fst_exp__h369177 : + _theResult___fst_exp__h369771 ; + assign _theResult___fst_exp__h377814 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ; - assign _theResult___fst_exp__h377855 = + assign _theResult___fst_exp__h377853 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h377861 = + assign _theResult___fst_exp__h377859 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ? 8'd0 : - _theResult___fst_exp__h377855 ; - assign _theResult___fst_exp__h377864 = + _theResult___fst_exp__h377853 ; + assign _theResult___fst_exp__h377862 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h377861 : - _theResult___fst_exp__h377816 ; - assign _theResult___fst_exp__h378412 = - (_theResult___fst_exp__h377864 == 8'd255) ? - _theResult___fst_exp__h377864 : - _theResult___fst_exp__h378409 ; - assign _theResult___fst_exp__h378421 = + _theResult___fst_exp__h377859 : + _theResult___fst_exp__h377814 ; + assign _theResult___fst_exp__h378410 = + (_theResult___fst_exp__h377862 == 8'd255) ? + _theResult___fst_exp__h377862 : + _theResult___fst_exp__h378407 ; + assign _theResult___fst_exp__h378419 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_exp__h360595 : - _theResult___fst_exp__h343284) : + _theResult___snd_fst_exp__h360593 : + _theResult___fst_exp__h343282) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_exp__h378415 : - _theResult___fst_exp__h343284) ; - assign _theResult___fst_exp__h378424 = + _theResult___snd_fst_exp__h378413 : + _theResult___fst_exp__h343282) ; + assign _theResult___fst_exp__h378422 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h378421 ; - assign _theResult___fst_exp__h397103 = - _theResult____h388994[56] ? + _theResult___fst_exp__h378419 ; + assign _theResult___fst_exp__h397101 = + _theResult____h388992[56] ? 8'd2 : - _theResult___fst_exp__h397177 ; - assign _theResult___fst_exp__h397168 = + _theResult___fst_exp__h397175 ; + assign _theResult___fst_exp__h397166 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ; - assign _theResult___fst_exp__h397174 = - (!_theResult____h388994[56] && !_theResult____h388994[55] && - !_theResult____h388994[54] && - !_theResult____h388994[53] && - !_theResult____h388994[52] && - !_theResult____h388994[51] && - !_theResult____h388994[50] && - !_theResult____h388994[49] && - !_theResult____h388994[48] && - !_theResult____h388994[47] && - !_theResult____h388994[46] && - !_theResult____h388994[45] && - !_theResult____h388994[44] && - !_theResult____h388994[43] && - !_theResult____h388994[42] && - !_theResult____h388994[41] && - !_theResult____h388994[40] && - !_theResult____h388994[39] && - !_theResult____h388994[38] && - !_theResult____h388994[37] && - !_theResult____h388994[36] && - !_theResult____h388994[35] && - !_theResult____h388994[34] && - !_theResult____h388994[33] && - !_theResult____h388994[32] && - !_theResult____h388994[31] && - !_theResult____h388994[30] && - !_theResult____h388994[29] && - !_theResult____h388994[28] && - !_theResult____h388994[27] && - !_theResult____h388994[26] && - !_theResult____h388994[25] && - !_theResult____h388994[24] && - !_theResult____h388994[23] && - !_theResult____h388994[22] && - !_theResult____h388994[21] && - !_theResult____h388994[20] && - !_theResult____h388994[19] && - !_theResult____h388994[18] && - !_theResult____h388994[17] && - !_theResult____h388994[16] && - !_theResult____h388994[15] && - !_theResult____h388994[14] && - !_theResult____h388994[13] && - !_theResult____h388994[12] && - !_theResult____h388994[11] && - !_theResult____h388994[10] && - !_theResult____h388994[9] && - !_theResult____h388994[8] && - !_theResult____h388994[7] && - !_theResult____h388994[6] && - !_theResult____h388994[5] && - !_theResult____h388994[4] && - !_theResult____h388994[3] && - !_theResult____h388994[2] && - !_theResult____h388994[1] && - !_theResult____h388994[0] || + assign _theResult___fst_exp__h397172 = + (!_theResult____h388992[56] && !_theResult____h388992[55] && + !_theResult____h388992[54] && + !_theResult____h388992[53] && + !_theResult____h388992[52] && + !_theResult____h388992[51] && + !_theResult____h388992[50] && + !_theResult____h388992[49] && + !_theResult____h388992[48] && + !_theResult____h388992[47] && + !_theResult____h388992[46] && + !_theResult____h388992[45] && + !_theResult____h388992[44] && + !_theResult____h388992[43] && + !_theResult____h388992[42] && + !_theResult____h388992[41] && + !_theResult____h388992[40] && + !_theResult____h388992[39] && + !_theResult____h388992[38] && + !_theResult____h388992[37] && + !_theResult____h388992[36] && + !_theResult____h388992[35] && + !_theResult____h388992[34] && + !_theResult____h388992[33] && + !_theResult____h388992[32] && + !_theResult____h388992[31] && + !_theResult____h388992[30] && + !_theResult____h388992[29] && + !_theResult____h388992[28] && + !_theResult____h388992[27] && + !_theResult____h388992[26] && + !_theResult____h388992[25] && + !_theResult____h388992[24] && + !_theResult____h388992[23] && + !_theResult____h388992[22] && + !_theResult____h388992[21] && + !_theResult____h388992[20] && + !_theResult____h388992[19] && + !_theResult____h388992[18] && + !_theResult____h388992[17] && + !_theResult____h388992[16] && + !_theResult____h388992[15] && + !_theResult____h388992[14] && + !_theResult____h388992[13] && + !_theResult____h388992[12] && + !_theResult____h388992[11] && + !_theResult____h388992[10] && + !_theResult____h388992[9] && + !_theResult____h388992[8] && + !_theResult____h388992[7] && + !_theResult____h388992[6] && + !_theResult____h388992[5] && + !_theResult____h388992[4] && + !_theResult____h388992[3] && + !_theResult____h388992[2] && + !_theResult____h388992[1] && + !_theResult____h388992[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ? 8'd0 : - _theResult___fst_exp__h397168 ; - assign _theResult___fst_exp__h397177 = - (!_theResult____h388994[56] && _theResult____h388994[55]) ? + _theResult___fst_exp__h397166 ; + assign _theResult___fst_exp__h397175 = + (!_theResult____h388992[56] && _theResult____h388992[55]) ? 8'd1 : - _theResult___fst_exp__h397174 ; - assign _theResult___fst_exp__h397700 = - (_theResult___fst_exp__h397103 == 8'd255) ? - _theResult___fst_exp__h397103 : - _theResult___fst_exp__h397697 ; - assign _theResult___fst_exp__h405750 = + _theResult___fst_exp__h397172 ; + assign _theResult___fst_exp__h397698 = + (_theResult___fst_exp__h397101 == 8'd255) ? + _theResult___fst_exp__h397101 : + _theResult___fst_exp__h397695 ; + assign _theResult___fst_exp__h405748 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h405756 = + assign _theResult___fst_exp__h405754 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ? 8'd0 : - _theResult___fst_exp__h405750 ; - assign _theResult___fst_exp__h405759 = + _theResult___fst_exp__h405748 ; + assign _theResult___fst_exp__h405757 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h405756 : + _theResult___fst_exp__h405754 : 8'd129 ; - assign _theResult___fst_exp__h406282 = - (_theResult___fst_exp__h405759 == 8'd255) ? - _theResult___fst_exp__h405759 : - _theResult___fst_exp__h406279 ; - assign _theResult___fst_exp__h414869 = - _theResult____h406631[56] ? + assign _theResult___fst_exp__h406280 = + (_theResult___fst_exp__h405757 == 8'd255) ? + _theResult___fst_exp__h405757 : + _theResult___fst_exp__h406277 ; + assign _theResult___fst_exp__h414867 = + _theResult____h406629[56] ? 8'd2 : - _theResult___fst_exp__h414943 ; - assign _theResult___fst_exp__h414934 = + _theResult___fst_exp__h414941 ; + assign _theResult___fst_exp__h414932 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ; - assign _theResult___fst_exp__h414940 = - (!_theResult____h406631[56] && !_theResult____h406631[55] && - !_theResult____h406631[54] && - !_theResult____h406631[53] && - !_theResult____h406631[52] && - !_theResult____h406631[51] && - !_theResult____h406631[50] && - !_theResult____h406631[49] && - !_theResult____h406631[48] && - !_theResult____h406631[47] && - !_theResult____h406631[46] && - !_theResult____h406631[45] && - !_theResult____h406631[44] && - !_theResult____h406631[43] && - !_theResult____h406631[42] && - !_theResult____h406631[41] && - !_theResult____h406631[40] && - !_theResult____h406631[39] && - !_theResult____h406631[38] && - !_theResult____h406631[37] && - !_theResult____h406631[36] && - !_theResult____h406631[35] && - !_theResult____h406631[34] && - !_theResult____h406631[33] && - !_theResult____h406631[32] && - !_theResult____h406631[31] && - !_theResult____h406631[30] && - !_theResult____h406631[29] && - !_theResult____h406631[28] && - !_theResult____h406631[27] && - !_theResult____h406631[26] && - !_theResult____h406631[25] && - !_theResult____h406631[24] && - !_theResult____h406631[23] && - !_theResult____h406631[22] && - !_theResult____h406631[21] && - !_theResult____h406631[20] && - !_theResult____h406631[19] && - !_theResult____h406631[18] && - !_theResult____h406631[17] && - !_theResult____h406631[16] && - !_theResult____h406631[15] && - !_theResult____h406631[14] && - !_theResult____h406631[13] && - !_theResult____h406631[12] && - !_theResult____h406631[11] && - !_theResult____h406631[10] && - !_theResult____h406631[9] && - !_theResult____h406631[8] && - !_theResult____h406631[7] && - !_theResult____h406631[6] && - !_theResult____h406631[5] && - !_theResult____h406631[4] && - !_theResult____h406631[3] && - !_theResult____h406631[2] && - !_theResult____h406631[1] && - !_theResult____h406631[0] || + assign _theResult___fst_exp__h414938 = + (!_theResult____h406629[56] && !_theResult____h406629[55] && + !_theResult____h406629[54] && + !_theResult____h406629[53] && + !_theResult____h406629[52] && + !_theResult____h406629[51] && + !_theResult____h406629[50] && + !_theResult____h406629[49] && + !_theResult____h406629[48] && + !_theResult____h406629[47] && + !_theResult____h406629[46] && + !_theResult____h406629[45] && + !_theResult____h406629[44] && + !_theResult____h406629[43] && + !_theResult____h406629[42] && + !_theResult____h406629[41] && + !_theResult____h406629[40] && + !_theResult____h406629[39] && + !_theResult____h406629[38] && + !_theResult____h406629[37] && + !_theResult____h406629[36] && + !_theResult____h406629[35] && + !_theResult____h406629[34] && + !_theResult____h406629[33] && + !_theResult____h406629[32] && + !_theResult____h406629[31] && + !_theResult____h406629[30] && + !_theResult____h406629[29] && + !_theResult____h406629[28] && + !_theResult____h406629[27] && + !_theResult____h406629[26] && + !_theResult____h406629[25] && + !_theResult____h406629[24] && + !_theResult____h406629[23] && + !_theResult____h406629[22] && + !_theResult____h406629[21] && + !_theResult____h406629[20] && + !_theResult____h406629[19] && + !_theResult____h406629[18] && + !_theResult____h406629[17] && + !_theResult____h406629[16] && + !_theResult____h406629[15] && + !_theResult____h406629[14] && + !_theResult____h406629[13] && + !_theResult____h406629[12] && + !_theResult____h406629[11] && + !_theResult____h406629[10] && + !_theResult____h406629[9] && + !_theResult____h406629[8] && + !_theResult____h406629[7] && + !_theResult____h406629[6] && + !_theResult____h406629[5] && + !_theResult____h406629[4] && + !_theResult____h406629[3] && + !_theResult____h406629[2] && + !_theResult____h406629[1] && + !_theResult____h406629[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ? 8'd0 : - _theResult___fst_exp__h414934 ; - assign _theResult___fst_exp__h414943 = - (!_theResult____h406631[56] && _theResult____h406631[55]) ? + _theResult___fst_exp__h414932 ; + assign _theResult___fst_exp__h414941 = + (!_theResult____h406629[56] && _theResult____h406629[55]) ? 8'd1 : - _theResult___fst_exp__h414940 ; - assign _theResult___fst_exp__h415466 = - (_theResult___fst_exp__h414869 == 8'd255) ? - _theResult___fst_exp__h414869 : - _theResult___fst_exp__h415463 ; - assign _theResult___fst_exp__h423506 = + _theResult___fst_exp__h414938 ; + assign _theResult___fst_exp__h415464 = + (_theResult___fst_exp__h414867 == 8'd255) ? + _theResult___fst_exp__h414867 : + _theResult___fst_exp__h415461 ; + assign _theResult___fst_exp__h423504 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ; - assign _theResult___fst_exp__h423545 = + assign _theResult___fst_exp__h423543 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h423551 = + assign _theResult___fst_exp__h423549 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ? 8'd0 : - _theResult___fst_exp__h423545 ; - assign _theResult___fst_exp__h423554 = + _theResult___fst_exp__h423543 ; + assign _theResult___fst_exp__h423552 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h423551 : - _theResult___fst_exp__h423506 ; - assign _theResult___fst_exp__h424102 = - (_theResult___fst_exp__h423554 == 8'd255) ? - _theResult___fst_exp__h423554 : - _theResult___fst_exp__h424099 ; - assign _theResult___fst_exp__h424111 = + _theResult___fst_exp__h423549 : + _theResult___fst_exp__h423504 ; + assign _theResult___fst_exp__h424100 = + (_theResult___fst_exp__h423552 == 8'd255) ? + _theResult___fst_exp__h423552 : + _theResult___fst_exp__h424097 ; + assign _theResult___fst_exp__h424109 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_exp__h406285 : - _theResult___fst_exp__h388976) : + _theResult___snd_fst_exp__h406283 : + _theResult___fst_exp__h388974) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_exp__h424105 : - _theResult___fst_exp__h388976) ; - assign _theResult___fst_exp__h424114 = + _theResult___snd_fst_exp__h424103 : + _theResult___fst_exp__h388974) ; + assign _theResult___fst_exp__h424112 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h424111 ; - assign _theResult___fst_exp__h442791 = - _theResult____h434682[56] ? + _theResult___fst_exp__h424109 ; + assign _theResult___fst_exp__h442789 = + _theResult____h434680[56] ? 8'd2 : - _theResult___fst_exp__h442865 ; - assign _theResult___fst_exp__h442856 = + _theResult___fst_exp__h442863 ; + assign _theResult___fst_exp__h442854 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ; - assign _theResult___fst_exp__h442862 = - (!_theResult____h434682[56] && !_theResult____h434682[55] && - !_theResult____h434682[54] && - !_theResult____h434682[53] && - !_theResult____h434682[52] && - !_theResult____h434682[51] && - !_theResult____h434682[50] && - !_theResult____h434682[49] && - !_theResult____h434682[48] && - !_theResult____h434682[47] && - !_theResult____h434682[46] && - !_theResult____h434682[45] && - !_theResult____h434682[44] && - !_theResult____h434682[43] && - !_theResult____h434682[42] && - !_theResult____h434682[41] && - !_theResult____h434682[40] && - !_theResult____h434682[39] && - !_theResult____h434682[38] && - !_theResult____h434682[37] && - !_theResult____h434682[36] && - !_theResult____h434682[35] && - !_theResult____h434682[34] && - !_theResult____h434682[33] && - !_theResult____h434682[32] && - !_theResult____h434682[31] && - !_theResult____h434682[30] && - !_theResult____h434682[29] && - !_theResult____h434682[28] && - !_theResult____h434682[27] && - !_theResult____h434682[26] && - !_theResult____h434682[25] && - !_theResult____h434682[24] && - !_theResult____h434682[23] && - !_theResult____h434682[22] && - !_theResult____h434682[21] && - !_theResult____h434682[20] && - !_theResult____h434682[19] && - !_theResult____h434682[18] && - !_theResult____h434682[17] && - !_theResult____h434682[16] && - !_theResult____h434682[15] && - !_theResult____h434682[14] && - !_theResult____h434682[13] && - !_theResult____h434682[12] && - !_theResult____h434682[11] && - !_theResult____h434682[10] && - !_theResult____h434682[9] && - !_theResult____h434682[8] && - !_theResult____h434682[7] && - !_theResult____h434682[6] && - !_theResult____h434682[5] && - !_theResult____h434682[4] && - !_theResult____h434682[3] && - !_theResult____h434682[2] && - !_theResult____h434682[1] && - !_theResult____h434682[0] || + assign _theResult___fst_exp__h442860 = + (!_theResult____h434680[56] && !_theResult____h434680[55] && + !_theResult____h434680[54] && + !_theResult____h434680[53] && + !_theResult____h434680[52] && + !_theResult____h434680[51] && + !_theResult____h434680[50] && + !_theResult____h434680[49] && + !_theResult____h434680[48] && + !_theResult____h434680[47] && + !_theResult____h434680[46] && + !_theResult____h434680[45] && + !_theResult____h434680[44] && + !_theResult____h434680[43] && + !_theResult____h434680[42] && + !_theResult____h434680[41] && + !_theResult____h434680[40] && + !_theResult____h434680[39] && + !_theResult____h434680[38] && + !_theResult____h434680[37] && + !_theResult____h434680[36] && + !_theResult____h434680[35] && + !_theResult____h434680[34] && + !_theResult____h434680[33] && + !_theResult____h434680[32] && + !_theResult____h434680[31] && + !_theResult____h434680[30] && + !_theResult____h434680[29] && + !_theResult____h434680[28] && + !_theResult____h434680[27] && + !_theResult____h434680[26] && + !_theResult____h434680[25] && + !_theResult____h434680[24] && + !_theResult____h434680[23] && + !_theResult____h434680[22] && + !_theResult____h434680[21] && + !_theResult____h434680[20] && + !_theResult____h434680[19] && + !_theResult____h434680[18] && + !_theResult____h434680[17] && + !_theResult____h434680[16] && + !_theResult____h434680[15] && + !_theResult____h434680[14] && + !_theResult____h434680[13] && + !_theResult____h434680[12] && + !_theResult____h434680[11] && + !_theResult____h434680[10] && + !_theResult____h434680[9] && + !_theResult____h434680[8] && + !_theResult____h434680[7] && + !_theResult____h434680[6] && + !_theResult____h434680[5] && + !_theResult____h434680[4] && + !_theResult____h434680[3] && + !_theResult____h434680[2] && + !_theResult____h434680[1] && + !_theResult____h434680[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ? 8'd0 : - _theResult___fst_exp__h442856 ; - assign _theResult___fst_exp__h442865 = - (!_theResult____h434682[56] && _theResult____h434682[55]) ? + _theResult___fst_exp__h442854 ; + assign _theResult___fst_exp__h442863 = + (!_theResult____h434680[56] && _theResult____h434680[55]) ? 8'd1 : - _theResult___fst_exp__h442862 ; - assign _theResult___fst_exp__h443388 = - (_theResult___fst_exp__h442791 == 8'd255) ? - _theResult___fst_exp__h442791 : - _theResult___fst_exp__h443385 ; - assign _theResult___fst_exp__h451438 = + _theResult___fst_exp__h442860 ; + assign _theResult___fst_exp__h443386 = + (_theResult___fst_exp__h442789 == 8'd255) ? + _theResult___fst_exp__h442789 : + _theResult___fst_exp__h443383 ; + assign _theResult___fst_exp__h451436 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h451444 = + assign _theResult___fst_exp__h451442 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ? 8'd0 : - _theResult___fst_exp__h451438 ; - assign _theResult___fst_exp__h451447 = + _theResult___fst_exp__h451436 ; + assign _theResult___fst_exp__h451445 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h451444 : + _theResult___fst_exp__h451442 : 8'd129 ; - assign _theResult___fst_exp__h451970 = - (_theResult___fst_exp__h451447 == 8'd255) ? - _theResult___fst_exp__h451447 : - _theResult___fst_exp__h451967 ; - assign _theResult___fst_exp__h460557 = - _theResult____h452319[56] ? + assign _theResult___fst_exp__h451968 = + (_theResult___fst_exp__h451445 == 8'd255) ? + _theResult___fst_exp__h451445 : + _theResult___fst_exp__h451965 ; + assign _theResult___fst_exp__h460555 = + _theResult____h452317[56] ? 8'd2 : - _theResult___fst_exp__h460631 ; - assign _theResult___fst_exp__h460622 = + _theResult___fst_exp__h460629 ; + assign _theResult___fst_exp__h460620 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ; - assign _theResult___fst_exp__h460628 = - (!_theResult____h452319[56] && !_theResult____h452319[55] && - !_theResult____h452319[54] && - !_theResult____h452319[53] && - !_theResult____h452319[52] && - !_theResult____h452319[51] && - !_theResult____h452319[50] && - !_theResult____h452319[49] && - !_theResult____h452319[48] && - !_theResult____h452319[47] && - !_theResult____h452319[46] && - !_theResult____h452319[45] && - !_theResult____h452319[44] && - !_theResult____h452319[43] && - !_theResult____h452319[42] && - !_theResult____h452319[41] && - !_theResult____h452319[40] && - !_theResult____h452319[39] && - !_theResult____h452319[38] && - !_theResult____h452319[37] && - !_theResult____h452319[36] && - !_theResult____h452319[35] && - !_theResult____h452319[34] && - !_theResult____h452319[33] && - !_theResult____h452319[32] && - !_theResult____h452319[31] && - !_theResult____h452319[30] && - !_theResult____h452319[29] && - !_theResult____h452319[28] && - !_theResult____h452319[27] && - !_theResult____h452319[26] && - !_theResult____h452319[25] && - !_theResult____h452319[24] && - !_theResult____h452319[23] && - !_theResult____h452319[22] && - !_theResult____h452319[21] && - !_theResult____h452319[20] && - !_theResult____h452319[19] && - !_theResult____h452319[18] && - !_theResult____h452319[17] && - !_theResult____h452319[16] && - !_theResult____h452319[15] && - !_theResult____h452319[14] && - !_theResult____h452319[13] && - !_theResult____h452319[12] && - !_theResult____h452319[11] && - !_theResult____h452319[10] && - !_theResult____h452319[9] && - !_theResult____h452319[8] && - !_theResult____h452319[7] && - !_theResult____h452319[6] && - !_theResult____h452319[5] && - !_theResult____h452319[4] && - !_theResult____h452319[3] && - !_theResult____h452319[2] && - !_theResult____h452319[1] && - !_theResult____h452319[0] || + assign _theResult___fst_exp__h460626 = + (!_theResult____h452317[56] && !_theResult____h452317[55] && + !_theResult____h452317[54] && + !_theResult____h452317[53] && + !_theResult____h452317[52] && + !_theResult____h452317[51] && + !_theResult____h452317[50] && + !_theResult____h452317[49] && + !_theResult____h452317[48] && + !_theResult____h452317[47] && + !_theResult____h452317[46] && + !_theResult____h452317[45] && + !_theResult____h452317[44] && + !_theResult____h452317[43] && + !_theResult____h452317[42] && + !_theResult____h452317[41] && + !_theResult____h452317[40] && + !_theResult____h452317[39] && + !_theResult____h452317[38] && + !_theResult____h452317[37] && + !_theResult____h452317[36] && + !_theResult____h452317[35] && + !_theResult____h452317[34] && + !_theResult____h452317[33] && + !_theResult____h452317[32] && + !_theResult____h452317[31] && + !_theResult____h452317[30] && + !_theResult____h452317[29] && + !_theResult____h452317[28] && + !_theResult____h452317[27] && + !_theResult____h452317[26] && + !_theResult____h452317[25] && + !_theResult____h452317[24] && + !_theResult____h452317[23] && + !_theResult____h452317[22] && + !_theResult____h452317[21] && + !_theResult____h452317[20] && + !_theResult____h452317[19] && + !_theResult____h452317[18] && + !_theResult____h452317[17] && + !_theResult____h452317[16] && + !_theResult____h452317[15] && + !_theResult____h452317[14] && + !_theResult____h452317[13] && + !_theResult____h452317[12] && + !_theResult____h452317[11] && + !_theResult____h452317[10] && + !_theResult____h452317[9] && + !_theResult____h452317[8] && + !_theResult____h452317[7] && + !_theResult____h452317[6] && + !_theResult____h452317[5] && + !_theResult____h452317[4] && + !_theResult____h452317[3] && + !_theResult____h452317[2] && + !_theResult____h452317[1] && + !_theResult____h452317[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ? 8'd0 : - _theResult___fst_exp__h460622 ; - assign _theResult___fst_exp__h460631 = - (!_theResult____h452319[56] && _theResult____h452319[55]) ? + _theResult___fst_exp__h460620 ; + assign _theResult___fst_exp__h460629 = + (!_theResult____h452317[56] && _theResult____h452317[55]) ? 8'd1 : - _theResult___fst_exp__h460628 ; - assign _theResult___fst_exp__h461154 = - (_theResult___fst_exp__h460557 == 8'd255) ? - _theResult___fst_exp__h460557 : - _theResult___fst_exp__h461151 ; - assign _theResult___fst_exp__h469194 = + _theResult___fst_exp__h460626 ; + assign _theResult___fst_exp__h461152 = + (_theResult___fst_exp__h460555 == 8'd255) ? + _theResult___fst_exp__h460555 : + _theResult___fst_exp__h461149 ; + assign _theResult___fst_exp__h469192 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ; - assign _theResult___fst_exp__h469233 = + assign _theResult___fst_exp__h469231 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h469239 = + assign _theResult___fst_exp__h469237 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ? 8'd0 : - _theResult___fst_exp__h469233 ; - assign _theResult___fst_exp__h469242 = + _theResult___fst_exp__h469231 ; + assign _theResult___fst_exp__h469240 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h469239 : - _theResult___fst_exp__h469194 ; - assign _theResult___fst_exp__h469790 = - (_theResult___fst_exp__h469242 == 8'd255) ? - _theResult___fst_exp__h469242 : - _theResult___fst_exp__h469787 ; - assign _theResult___fst_exp__h469799 = + _theResult___fst_exp__h469237 : + _theResult___fst_exp__h469192 ; + assign _theResult___fst_exp__h469788 = + (_theResult___fst_exp__h469240 == 8'd255) ? + _theResult___fst_exp__h469240 : + _theResult___fst_exp__h469785 ; + assign _theResult___fst_exp__h469797 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_exp__h451973 : - _theResult___fst_exp__h434664) : + _theResult___snd_fst_exp__h451971 : + _theResult___fst_exp__h434662) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_exp__h469793 : - _theResult___fst_exp__h434664) ; - assign _theResult___fst_exp__h469802 = + _theResult___snd_fst_exp__h469791 : + _theResult___fst_exp__h434662) ; + assign _theResult___fst_exp__h469800 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h469799 ; - assign _theResult___fst_exp__h483603 = + _theResult___fst_exp__h469797 ; + assign _theResult___fst_exp__h483601 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ; - assign _theResult___fst_exp__h498667 = + assign _theResult___fst_exp__h498665 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h498673 = + assign _theResult___fst_exp__h498671 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577) ? 11'd0 : - _theResult___fst_exp__h498667 ; - assign _theResult___fst_exp__h498676 = + _theResult___fst_exp__h498665 ; + assign _theResult___fst_exp__h498674 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h498673 : + _theResult___fst_exp__h498671 : 11'd897 ; - assign _theResult___fst_exp__h499431 = + assign _theResult___fst_exp__h499429 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 : + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 ; - assign _theResult___fst_exp__h499434 = - (_theResult___fst_exp__h498676 == 11'd2047) ? - _theResult___fst_exp__h498676 : - _theResult___fst_exp__h499431 ; - assign _theResult___fst_exp__h508253 = - _theResult____h500017[56] ? + assign _theResult___fst_exp__h499432 = + (_theResult___fst_exp__h498674 == 11'd2047) ? + _theResult___fst_exp__h498674 : + _theResult___fst_exp__h499429 ; + assign _theResult___fst_exp__h508251 = + _theResult____h500015[56] ? 11'd2 : - _theResult___fst_exp__h508327 ; - assign _theResult___fst_exp__h508318 = + _theResult___fst_exp__h508325 ; + assign _theResult___fst_exp__h508316 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ; - assign _theResult___fst_exp__h508324 = - (!_theResult____h500017[56] && !_theResult____h500017[55] && - !_theResult____h500017[54] && - !_theResult____h500017[53] && - !_theResult____h500017[52] && - !_theResult____h500017[51] && - !_theResult____h500017[50] && - !_theResult____h500017[49] && - !_theResult____h500017[48] && - !_theResult____h500017[47] && - !_theResult____h500017[46] && - !_theResult____h500017[45] && - !_theResult____h500017[44] && - !_theResult____h500017[43] && - !_theResult____h500017[42] && - !_theResult____h500017[41] && - !_theResult____h500017[40] && - !_theResult____h500017[39] && - !_theResult____h500017[38] && - !_theResult____h500017[37] && - !_theResult____h500017[36] && - !_theResult____h500017[35] && - !_theResult____h500017[34] && - !_theResult____h500017[33] && - !_theResult____h500017[32] && - !_theResult____h500017[31] && - !_theResult____h500017[30] && - !_theResult____h500017[29] && - !_theResult____h500017[28] && - !_theResult____h500017[27] && - !_theResult____h500017[26] && - !_theResult____h500017[25] && - !_theResult____h500017[24] && - !_theResult____h500017[23] && - !_theResult____h500017[22] && - !_theResult____h500017[21] && - !_theResult____h500017[20] && - !_theResult____h500017[19] && - !_theResult____h500017[18] && - !_theResult____h500017[17] && - !_theResult____h500017[16] && - !_theResult____h500017[15] && - !_theResult____h500017[14] && - !_theResult____h500017[13] && - !_theResult____h500017[12] && - !_theResult____h500017[11] && - !_theResult____h500017[10] && - !_theResult____h500017[9] && - !_theResult____h500017[8] && - !_theResult____h500017[7] && - !_theResult____h500017[6] && - !_theResult____h500017[5] && - !_theResult____h500017[4] && - !_theResult____h500017[3] && - !_theResult____h500017[2] && - !_theResult____h500017[1] && - !_theResult____h500017[0] || + assign _theResult___fst_exp__h508322 = + (!_theResult____h500015[56] && !_theResult____h500015[55] && + !_theResult____h500015[54] && + !_theResult____h500015[53] && + !_theResult____h500015[52] && + !_theResult____h500015[51] && + !_theResult____h500015[50] && + !_theResult____h500015[49] && + !_theResult____h500015[48] && + !_theResult____h500015[47] && + !_theResult____h500015[46] && + !_theResult____h500015[45] && + !_theResult____h500015[44] && + !_theResult____h500015[43] && + !_theResult____h500015[42] && + !_theResult____h500015[41] && + !_theResult____h500015[40] && + !_theResult____h500015[39] && + !_theResult____h500015[38] && + !_theResult____h500015[37] && + !_theResult____h500015[36] && + !_theResult____h500015[35] && + !_theResult____h500015[34] && + !_theResult____h500015[33] && + !_theResult____h500015[32] && + !_theResult____h500015[31] && + !_theResult____h500015[30] && + !_theResult____h500015[29] && + !_theResult____h500015[28] && + !_theResult____h500015[27] && + !_theResult____h500015[26] && + !_theResult____h500015[25] && + !_theResult____h500015[24] && + !_theResult____h500015[23] && + !_theResult____h500015[22] && + !_theResult____h500015[21] && + !_theResult____h500015[20] && + !_theResult____h500015[19] && + !_theResult____h500015[18] && + !_theResult____h500015[17] && + !_theResult____h500015[16] && + !_theResult____h500015[15] && + !_theResult____h500015[14] && + !_theResult____h500015[13] && + !_theResult____h500015[12] && + !_theResult____h500015[11] && + !_theResult____h500015[10] && + !_theResult____h500015[9] && + !_theResult____h500015[8] && + !_theResult____h500015[7] && + !_theResult____h500015[6] && + !_theResult____h500015[5] && + !_theResult____h500015[4] && + !_theResult____h500015[3] && + !_theResult____h500015[2] && + !_theResult____h500015[1] && + !_theResult____h500015[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889) ? 11'd0 : - _theResult___fst_exp__h508318 ; - assign _theResult___fst_exp__h508327 = - (!_theResult____h500017[56] && _theResult____h500017[55]) ? + _theResult___fst_exp__h508316 ; + assign _theResult___fst_exp__h508325 = + (!_theResult____h500015[56] && _theResult____h500015[55]) ? 11'd1 : - _theResult___fst_exp__h508324 ; - assign _theResult___fst_exp__h509082 = + _theResult___fst_exp__h508322 ; + assign _theResult___fst_exp__h509080 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 : + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 ; - assign _theResult___fst_exp__h509085 = - (_theResult___fst_exp__h508253 == 11'd2047) ? - _theResult___fst_exp__h508253 : - _theResult___fst_exp__h509082 ; - assign _theResult___fst_exp__h517038 = + assign _theResult___fst_exp__h509083 = + (_theResult___fst_exp__h508251 == 11'd2047) ? + _theResult___fst_exp__h508251 : + _theResult___fst_exp__h509080 ; + assign _theResult___fst_exp__h517036 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ; - assign _theResult___fst_exp__h517077 = + assign _theResult___fst_exp__h517075 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h517083 = + assign _theResult___fst_exp__h517081 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939) ? 11'd0 : - _theResult___fst_exp__h517077 ; - assign _theResult___fst_exp__h517086 = + _theResult___fst_exp__h517075 ; + assign _theResult___fst_exp__h517084 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h517083 : - _theResult___fst_exp__h517038 ; - assign _theResult___fst_exp__h517866 = + _theResult___fst_exp__h517081 : + _theResult___fst_exp__h517036 ; + assign _theResult___fst_exp__h517864 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 : + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 ; - assign _theResult___fst_exp__h517869 = - (_theResult___fst_exp__h517086 == 11'd2047) ? - _theResult___fst_exp__h517086 : - _theResult___fst_exp__h517866 ; - assign _theResult___fst_exp__h517878 = + assign _theResult___fst_exp__h517867 = + (_theResult___fst_exp__h517084 == 11'd2047) ? + _theResult___fst_exp__h517084 : + _theResult___fst_exp__h517864 ; + assign _theResult___fst_exp__h517876 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_exp__h499437 : - _theResult___fst_exp__h483603) : + _theResult___snd_fst_exp__h499435 : + _theResult___fst_exp__h483601) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_exp__h517872 : - _theResult___fst_exp__h483603) ; - assign _theResult___fst_exp__h517881 = + _theResult___snd_fst_exp__h517870 : + _theResult___fst_exp__h483601) ; + assign _theResult___fst_exp__h517879 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h517878 ; - assign _theResult___fst_exp__h522404 = + _theResult___fst_exp__h517876 ; + assign _theResult___fst_exp__h522402 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_exp__h537468 = + assign _theResult___fst_exp__h537466 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h537474 = + assign _theResult___fst_exp__h537472 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065) ? 11'd0 : - _theResult___fst_exp__h537468 ; - assign _theResult___fst_exp__h537477 = + _theResult___fst_exp__h537466 ; + assign _theResult___fst_exp__h537475 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h537474 : + _theResult___fst_exp__h537472 : 11'd897 ; - assign _theResult___fst_exp__h538232 = + assign _theResult___fst_exp__h538230 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 : + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 ; - assign _theResult___fst_exp__h538235 = - (_theResult___fst_exp__h537477 == 11'd2047) ? - _theResult___fst_exp__h537477 : - _theResult___fst_exp__h538232 ; - assign _theResult___fst_exp__h547054 = - _theResult____h538818[56] ? + assign _theResult___fst_exp__h538233 = + (_theResult___fst_exp__h537475 == 11'd2047) ? + _theResult___fst_exp__h537475 : + _theResult___fst_exp__h538230 ; + assign _theResult___fst_exp__h547052 = + _theResult____h538816[56] ? 11'd2 : - _theResult___fst_exp__h547128 ; - assign _theResult___fst_exp__h547119 = + _theResult___fst_exp__h547126 ; + assign _theResult___fst_exp__h547117 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ; - assign _theResult___fst_exp__h547125 = - (!_theResult____h538818[56] && !_theResult____h538818[55] && - !_theResult____h538818[54] && - !_theResult____h538818[53] && - !_theResult____h538818[52] && - !_theResult____h538818[51] && - !_theResult____h538818[50] && - !_theResult____h538818[49] && - !_theResult____h538818[48] && - !_theResult____h538818[47] && - !_theResult____h538818[46] && - !_theResult____h538818[45] && - !_theResult____h538818[44] && - !_theResult____h538818[43] && - !_theResult____h538818[42] && - !_theResult____h538818[41] && - !_theResult____h538818[40] && - !_theResult____h538818[39] && - !_theResult____h538818[38] && - !_theResult____h538818[37] && - !_theResult____h538818[36] && - !_theResult____h538818[35] && - !_theResult____h538818[34] && - !_theResult____h538818[33] && - !_theResult____h538818[32] && - !_theResult____h538818[31] && - !_theResult____h538818[30] && - !_theResult____h538818[29] && - !_theResult____h538818[28] && - !_theResult____h538818[27] && - !_theResult____h538818[26] && - !_theResult____h538818[25] && - !_theResult____h538818[24] && - !_theResult____h538818[23] && - !_theResult____h538818[22] && - !_theResult____h538818[21] && - !_theResult____h538818[20] && - !_theResult____h538818[19] && - !_theResult____h538818[18] && - !_theResult____h538818[17] && - !_theResult____h538818[16] && - !_theResult____h538818[15] && - !_theResult____h538818[14] && - !_theResult____h538818[13] && - !_theResult____h538818[12] && - !_theResult____h538818[11] && - !_theResult____h538818[10] && - !_theResult____h538818[9] && - !_theResult____h538818[8] && - !_theResult____h538818[7] && - !_theResult____h538818[6] && - !_theResult____h538818[5] && - !_theResult____h538818[4] && - !_theResult____h538818[3] && - !_theResult____h538818[2] && - !_theResult____h538818[1] && - !_theResult____h538818[0] || + assign _theResult___fst_exp__h547123 = + (!_theResult____h538816[56] && !_theResult____h538816[55] && + !_theResult____h538816[54] && + !_theResult____h538816[53] && + !_theResult____h538816[52] && + !_theResult____h538816[51] && + !_theResult____h538816[50] && + !_theResult____h538816[49] && + !_theResult____h538816[48] && + !_theResult____h538816[47] && + !_theResult____h538816[46] && + !_theResult____h538816[45] && + !_theResult____h538816[44] && + !_theResult____h538816[43] && + !_theResult____h538816[42] && + !_theResult____h538816[41] && + !_theResult____h538816[40] && + !_theResult____h538816[39] && + !_theResult____h538816[38] && + !_theResult____h538816[37] && + !_theResult____h538816[36] && + !_theResult____h538816[35] && + !_theResult____h538816[34] && + !_theResult____h538816[33] && + !_theResult____h538816[32] && + !_theResult____h538816[31] && + !_theResult____h538816[30] && + !_theResult____h538816[29] && + !_theResult____h538816[28] && + !_theResult____h538816[27] && + !_theResult____h538816[26] && + !_theResult____h538816[25] && + !_theResult____h538816[24] && + !_theResult____h538816[23] && + !_theResult____h538816[22] && + !_theResult____h538816[21] && + !_theResult____h538816[20] && + !_theResult____h538816[19] && + !_theResult____h538816[18] && + !_theResult____h538816[17] && + !_theResult____h538816[16] && + !_theResult____h538816[15] && + !_theResult____h538816[14] && + !_theResult____h538816[13] && + !_theResult____h538816[12] && + !_theResult____h538816[11] && + !_theResult____h538816[10] && + !_theResult____h538816[9] && + !_theResult____h538816[8] && + !_theResult____h538816[7] && + !_theResult____h538816[6] && + !_theResult____h538816[5] && + !_theResult____h538816[4] && + !_theResult____h538816[3] && + !_theResult____h538816[2] && + !_theResult____h538816[1] && + !_theResult____h538816[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362) ? 11'd0 : - _theResult___fst_exp__h547119 ; - assign _theResult___fst_exp__h547128 = - (!_theResult____h538818[56] && _theResult____h538818[55]) ? + _theResult___fst_exp__h547117 ; + assign _theResult___fst_exp__h547126 = + (!_theResult____h538816[56] && _theResult____h538816[55]) ? 11'd1 : - _theResult___fst_exp__h547125 ; - assign _theResult___fst_exp__h547883 = + _theResult___fst_exp__h547123 ; + assign _theResult___fst_exp__h547881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 : + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 ; - assign _theResult___fst_exp__h547886 = - (_theResult___fst_exp__h547054 == 11'd2047) ? - _theResult___fst_exp__h547054 : - _theResult___fst_exp__h547883 ; - assign _theResult___fst_exp__h555839 = + assign _theResult___fst_exp__h547884 = + (_theResult___fst_exp__h547052 == 11'd2047) ? + _theResult___fst_exp__h547052 : + _theResult___fst_exp__h547881 ; + assign _theResult___fst_exp__h555837 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ; - assign _theResult___fst_exp__h555878 = + assign _theResult___fst_exp__h555876 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h555884 = + assign _theResult___fst_exp__h555882 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412) ? 11'd0 : - _theResult___fst_exp__h555878 ; - assign _theResult___fst_exp__h555887 = + _theResult___fst_exp__h555876 ; + assign _theResult___fst_exp__h555885 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h555884 : - _theResult___fst_exp__h555839 ; - assign _theResult___fst_exp__h556667 = + _theResult___fst_exp__h555882 : + _theResult___fst_exp__h555837 ; + assign _theResult___fst_exp__h556665 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 : + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 ; - assign _theResult___fst_exp__h556670 = - (_theResult___fst_exp__h555887 == 11'd2047) ? - _theResult___fst_exp__h555887 : - _theResult___fst_exp__h556667 ; - assign _theResult___fst_exp__h556679 = + assign _theResult___fst_exp__h556668 = + (_theResult___fst_exp__h555885 == 11'd2047) ? + _theResult___fst_exp__h555885 : + _theResult___fst_exp__h556665 ; + assign _theResult___fst_exp__h556677 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_exp__h538238 : - _theResult___fst_exp__h522404) : + _theResult___snd_fst_exp__h538236 : + _theResult___fst_exp__h522402) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_exp__h556673 : - _theResult___fst_exp__h522404) ; - assign _theResult___fst_exp__h556682 = + _theResult___snd_fst_exp__h556671 : + _theResult___fst_exp__h522402) ; + assign _theResult___fst_exp__h556680 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h556679 ; - assign _theResult___fst_exp__h561605 = + _theResult___fst_exp__h556677 ; + assign _theResult___fst_exp__h561603 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_exp__h576669 = + assign _theResult___fst_exp__h576667 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h576675 = + assign _theResult___fst_exp__h576673 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302) ? 11'd0 : - _theResult___fst_exp__h576669 ; - assign _theResult___fst_exp__h576678 = + _theResult___fst_exp__h576667 ; + assign _theResult___fst_exp__h576676 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h576675 : + _theResult___fst_exp__h576673 : 11'd897 ; - assign _theResult___fst_exp__h577433 = + assign _theResult___fst_exp__h577431 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 : + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 ; - assign _theResult___fst_exp__h577436 = - (_theResult___fst_exp__h576678 == 11'd2047) ? - _theResult___fst_exp__h576678 : - _theResult___fst_exp__h577433 ; - assign _theResult___fst_exp__h586255 = - _theResult____h578019[56] ? + assign _theResult___fst_exp__h577434 = + (_theResult___fst_exp__h576676 == 11'd2047) ? + _theResult___fst_exp__h576676 : + _theResult___fst_exp__h577431 ; + assign _theResult___fst_exp__h586253 = + _theResult____h578017[56] ? 11'd2 : - _theResult___fst_exp__h586329 ; - assign _theResult___fst_exp__h586320 = + _theResult___fst_exp__h586327 ; + assign _theResult___fst_exp__h586318 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 } ; - assign _theResult___fst_exp__h586326 = - (!_theResult____h578019[56] && !_theResult____h578019[55] && - !_theResult____h578019[54] && - !_theResult____h578019[53] && - !_theResult____h578019[52] && - !_theResult____h578019[51] && - !_theResult____h578019[50] && - !_theResult____h578019[49] && - !_theResult____h578019[48] && - !_theResult____h578019[47] && - !_theResult____h578019[46] && - !_theResult____h578019[45] && - !_theResult____h578019[44] && - !_theResult____h578019[43] && - !_theResult____h578019[42] && - !_theResult____h578019[41] && - !_theResult____h578019[40] && - !_theResult____h578019[39] && - !_theResult____h578019[38] && - !_theResult____h578019[37] && - !_theResult____h578019[36] && - !_theResult____h578019[35] && - !_theResult____h578019[34] && - !_theResult____h578019[33] && - !_theResult____h578019[32] && - !_theResult____h578019[31] && - !_theResult____h578019[30] && - !_theResult____h578019[29] && - !_theResult____h578019[28] && - !_theResult____h578019[27] && - !_theResult____h578019[26] && - !_theResult____h578019[25] && - !_theResult____h578019[24] && - !_theResult____h578019[23] && - !_theResult____h578019[22] && - !_theResult____h578019[21] && - !_theResult____h578019[20] && - !_theResult____h578019[19] && - !_theResult____h578019[18] && - !_theResult____h578019[17] && - !_theResult____h578019[16] && - !_theResult____h578019[15] && - !_theResult____h578019[14] && - !_theResult____h578019[13] && - !_theResult____h578019[12] && - !_theResult____h578019[11] && - !_theResult____h578019[10] && - !_theResult____h578019[9] && - !_theResult____h578019[8] && - !_theResult____h578019[7] && - !_theResult____h578019[6] && - !_theResult____h578019[5] && - !_theResult____h578019[4] && - !_theResult____h578019[3] && - !_theResult____h578019[2] && - !_theResult____h578019[1] && - !_theResult____h578019[0] || + assign _theResult___fst_exp__h586324 = + (!_theResult____h578017[56] && !_theResult____h578017[55] && + !_theResult____h578017[54] && + !_theResult____h578017[53] && + !_theResult____h578017[52] && + !_theResult____h578017[51] && + !_theResult____h578017[50] && + !_theResult____h578017[49] && + !_theResult____h578017[48] && + !_theResult____h578017[47] && + !_theResult____h578017[46] && + !_theResult____h578017[45] && + !_theResult____h578017[44] && + !_theResult____h578017[43] && + !_theResult____h578017[42] && + !_theResult____h578017[41] && + !_theResult____h578017[40] && + !_theResult____h578017[39] && + !_theResult____h578017[38] && + !_theResult____h578017[37] && + !_theResult____h578017[36] && + !_theResult____h578017[35] && + !_theResult____h578017[34] && + !_theResult____h578017[33] && + !_theResult____h578017[32] && + !_theResult____h578017[31] && + !_theResult____h578017[30] && + !_theResult____h578017[29] && + !_theResult____h578017[28] && + !_theResult____h578017[27] && + !_theResult____h578017[26] && + !_theResult____h578017[25] && + !_theResult____h578017[24] && + !_theResult____h578017[23] && + !_theResult____h578017[22] && + !_theResult____h578017[21] && + !_theResult____h578017[20] && + !_theResult____h578017[19] && + !_theResult____h578017[18] && + !_theResult____h578017[17] && + !_theResult____h578017[16] && + !_theResult____h578017[15] && + !_theResult____h578017[14] && + !_theResult____h578017[13] && + !_theResult____h578017[12] && + !_theResult____h578017[11] && + !_theResult____h578017[10] && + !_theResult____h578017[9] && + !_theResult____h578017[8] && + !_theResult____h578017[7] && + !_theResult____h578017[6] && + !_theResult____h578017[5] && + !_theResult____h578017[4] && + !_theResult____h578017[3] && + !_theResult____h578017[2] && + !_theResult____h578017[1] && + !_theResult____h578017[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599) ? 11'd0 : - _theResult___fst_exp__h586320 ; - assign _theResult___fst_exp__h586329 = - (!_theResult____h578019[56] && _theResult____h578019[55]) ? + _theResult___fst_exp__h586318 ; + assign _theResult___fst_exp__h586327 = + (!_theResult____h578017[56] && _theResult____h578017[55]) ? 11'd1 : - _theResult___fst_exp__h586326 ; - assign _theResult___fst_exp__h587084 = + _theResult___fst_exp__h586324 ; + assign _theResult___fst_exp__h587082 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 : + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 ; - assign _theResult___fst_exp__h587087 = - (_theResult___fst_exp__h586255 == 11'd2047) ? - _theResult___fst_exp__h586255 : - _theResult___fst_exp__h587084 ; - assign _theResult___fst_exp__h595040 = + assign _theResult___fst_exp__h587085 = + (_theResult___fst_exp__h586253 == 11'd2047) ? + _theResult___fst_exp__h586253 : + _theResult___fst_exp__h587082 ; + assign _theResult___fst_exp__h595038 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ; - assign _theResult___fst_exp__h595079 = + assign _theResult___fst_exp__h595077 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h595085 = + assign _theResult___fst_exp__h595083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649) ? 11'd0 : - _theResult___fst_exp__h595079 ; - assign _theResult___fst_exp__h595088 = + _theResult___fst_exp__h595077 ; + assign _theResult___fst_exp__h595086 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h595085 : - _theResult___fst_exp__h595040 ; - assign _theResult___fst_exp__h595868 = + _theResult___fst_exp__h595083 : + _theResult___fst_exp__h595038 ; + assign _theResult___fst_exp__h595866 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 : + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 ; - assign _theResult___fst_exp__h595871 = - (_theResult___fst_exp__h595088 == 11'd2047) ? - _theResult___fst_exp__h595088 : - _theResult___fst_exp__h595868 ; - assign _theResult___fst_exp__h595880 = + assign _theResult___fst_exp__h595869 = + (_theResult___fst_exp__h595086 == 11'd2047) ? + _theResult___fst_exp__h595086 : + _theResult___fst_exp__h595866 ; + assign _theResult___fst_exp__h595878 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_exp__h577439 : - _theResult___fst_exp__h561605) : + _theResult___snd_fst_exp__h577437 : + _theResult___fst_exp__h561603) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_exp__h595874 : - _theResult___fst_exp__h561605) ; - assign _theResult___fst_exp__h595883 = + _theResult___snd_fst_exp__h595872 : + _theResult___fst_exp__h561603) ; + assign _theResult___fst_exp__h595881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h595880 ; - assign _theResult___fst_sfd__h352011 = - (_theResult___fst_exp__h351413 == 8'd255) ? - sfdin__h351407[56:34] : - _theResult___fst_sfd__h352008 ; - assign _theResult___fst_sfd__h360593 = - (_theResult___fst_exp__h360069 == 8'd255) ? - _theResult___snd__h360020[56:34] : - _theResult___fst_sfd__h360590 ; - assign _theResult___fst_sfd__h369777 = - (_theResult___fst_exp__h369179 == 8'd255) ? - sfdin__h369173[56:34] : - _theResult___fst_sfd__h369774 ; - assign _theResult___fst_sfd__h378413 = - (_theResult___fst_exp__h377864 == 8'd255) ? - _theResult___snd__h377810[56:34] : - _theResult___fst_sfd__h378410 ; - assign _theResult___fst_sfd__h378422 = + _theResult___fst_exp__h595878 ; + assign _theResult___fst_sfd__h352009 = + (_theResult___fst_exp__h351411 == 8'd255) ? + sfdin__h351405[56:34] : + _theResult___fst_sfd__h352006 ; + assign _theResult___fst_sfd__h360591 = + (_theResult___fst_exp__h360067 == 8'd255) ? + _theResult___snd__h360018[56:34] : + _theResult___fst_sfd__h360588 ; + assign _theResult___fst_sfd__h369775 = + (_theResult___fst_exp__h369177 == 8'd255) ? + sfdin__h369171[56:34] : + _theResult___fst_sfd__h369772 ; + assign _theResult___fst_sfd__h378411 = + (_theResult___fst_exp__h377862 == 8'd255) ? + _theResult___snd__h377808[56:34] : + _theResult___fst_sfd__h378408 ; + assign _theResult___fst_sfd__h378420 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_sfd__h360596 : - _theResult___fst_sfd__h343285) : + _theResult___snd_fst_sfd__h360594 : + _theResult___fst_sfd__h343283) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_sfd__h378416 : - _theResult___fst_sfd__h343285) ; - assign _theResult___fst_sfd__h378428 = + _theResult___snd_fst_sfd__h378414 : + _theResult___fst_sfd__h343283) ; + assign _theResult___fst_sfd__h378426 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -25718,33 +25718,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h378422 ; - assign _theResult___fst_sfd__h397701 = - (_theResult___fst_exp__h397103 == 8'd255) ? - sfdin__h397097[56:34] : - _theResult___fst_sfd__h397698 ; - assign _theResult___fst_sfd__h406283 = - (_theResult___fst_exp__h405759 == 8'd255) ? - _theResult___snd__h405710[56:34] : - _theResult___fst_sfd__h406280 ; - assign _theResult___fst_sfd__h415467 = - (_theResult___fst_exp__h414869 == 8'd255) ? - sfdin__h414863[56:34] : - _theResult___fst_sfd__h415464 ; - assign _theResult___fst_sfd__h424103 = - (_theResult___fst_exp__h423554 == 8'd255) ? - _theResult___snd__h423500[56:34] : - _theResult___fst_sfd__h424100 ; - assign _theResult___fst_sfd__h424112 = + _theResult___fst_sfd__h378420 ; + assign _theResult___fst_sfd__h397699 = + (_theResult___fst_exp__h397101 == 8'd255) ? + sfdin__h397095[56:34] : + _theResult___fst_sfd__h397696 ; + assign _theResult___fst_sfd__h406281 = + (_theResult___fst_exp__h405757 == 8'd255) ? + _theResult___snd__h405708[56:34] : + _theResult___fst_sfd__h406278 ; + assign _theResult___fst_sfd__h415465 = + (_theResult___fst_exp__h414867 == 8'd255) ? + sfdin__h414861[56:34] : + _theResult___fst_sfd__h415462 ; + assign _theResult___fst_sfd__h424101 = + (_theResult___fst_exp__h423552 == 8'd255) ? + _theResult___snd__h423498[56:34] : + _theResult___fst_sfd__h424098 ; + assign _theResult___fst_sfd__h424110 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_sfd__h406286 : - _theResult___fst_sfd__h388977) : + _theResult___snd_fst_sfd__h406284 : + _theResult___fst_sfd__h388975) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_sfd__h424106 : - _theResult___fst_sfd__h388977) ; - assign _theResult___fst_sfd__h424118 = + _theResult___snd_fst_sfd__h424104 : + _theResult___fst_sfd__h388975) ; + assign _theResult___fst_sfd__h424116 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -25752,33 +25752,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h424112 ; - assign _theResult___fst_sfd__h443389 = - (_theResult___fst_exp__h442791 == 8'd255) ? - sfdin__h442785[56:34] : - _theResult___fst_sfd__h443386 ; - assign _theResult___fst_sfd__h451971 = - (_theResult___fst_exp__h451447 == 8'd255) ? - _theResult___snd__h451398[56:34] : - _theResult___fst_sfd__h451968 ; - assign _theResult___fst_sfd__h461155 = - (_theResult___fst_exp__h460557 == 8'd255) ? - sfdin__h460551[56:34] : - _theResult___fst_sfd__h461152 ; - assign _theResult___fst_sfd__h469791 = - (_theResult___fst_exp__h469242 == 8'd255) ? - _theResult___snd__h469188[56:34] : - _theResult___fst_sfd__h469788 ; - assign _theResult___fst_sfd__h469800 = + _theResult___fst_sfd__h424110 ; + assign _theResult___fst_sfd__h443387 = + (_theResult___fst_exp__h442789 == 8'd255) ? + sfdin__h442783[56:34] : + _theResult___fst_sfd__h443384 ; + assign _theResult___fst_sfd__h451969 = + (_theResult___fst_exp__h451445 == 8'd255) ? + _theResult___snd__h451396[56:34] : + _theResult___fst_sfd__h451966 ; + assign _theResult___fst_sfd__h461153 = + (_theResult___fst_exp__h460555 == 8'd255) ? + sfdin__h460549[56:34] : + _theResult___fst_sfd__h461150 ; + assign _theResult___fst_sfd__h469789 = + (_theResult___fst_exp__h469240 == 8'd255) ? + _theResult___snd__h469186[56:34] : + _theResult___fst_sfd__h469786 ; + assign _theResult___fst_sfd__h469798 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_sfd__h451974 : - _theResult___fst_sfd__h434665) : + _theResult___snd_fst_sfd__h451972 : + _theResult___fst_sfd__h434663) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_sfd__h469794 : - _theResult___fst_sfd__h434665) ; - assign _theResult___fst_sfd__h469806 = + _theResult___snd_fst_sfd__h469792 : + _theResult___fst_sfd__h434663) ; + assign _theResult___fst_sfd__h469804 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -25786,1320 +25786,1320 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h469800 ; - assign _theResult___fst_sfd__h483604 = + _theResult___fst_sfd__h469798 ; + assign _theResult___fst_sfd__h483602 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_sfd__h499432 = + assign _theResult___fst_sfd__h499430 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 : + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 ; - assign _theResult___fst_sfd__h499435 = - (_theResult___fst_exp__h498676 == 11'd2047) ? - _theResult___snd__h498627[56:5] : - _theResult___fst_sfd__h499432 ; - assign _theResult___fst_sfd__h509083 = + assign _theResult___fst_sfd__h499433 = + (_theResult___fst_exp__h498674 == 11'd2047) ? + _theResult___snd__h498625[56:5] : + _theResult___fst_sfd__h499430 ; + assign _theResult___fst_sfd__h509081 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 : + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 ; - assign _theResult___fst_sfd__h509086 = - (_theResult___fst_exp__h508253 == 11'd2047) ? - sfdin__h508247[56:5] : - _theResult___fst_sfd__h509083 ; - assign _theResult___fst_sfd__h517867 = + assign _theResult___fst_sfd__h509084 = + (_theResult___fst_exp__h508251 == 11'd2047) ? + sfdin__h508245[56:5] : + _theResult___fst_sfd__h509081 ; + assign _theResult___fst_sfd__h517865 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 : + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 ; - assign _theResult___fst_sfd__h517870 = - (_theResult___fst_exp__h517086 == 11'd2047) ? - _theResult___snd__h517032[56:5] : - _theResult___fst_sfd__h517867 ; - assign _theResult___fst_sfd__h517879 = + assign _theResult___fst_sfd__h517868 = + (_theResult___fst_exp__h517084 == 11'd2047) ? + _theResult___snd__h517030[56:5] : + _theResult___fst_sfd__h517865 ; + assign _theResult___fst_sfd__h517877 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_sfd__h499438 : - _theResult___fst_sfd__h483604) : + _theResult___snd_fst_sfd__h499436 : + _theResult___fst_sfd__h483602) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_sfd__h517873 : - _theResult___fst_sfd__h483604) ; - assign _theResult___fst_sfd__h517885 = + _theResult___snd_fst_sfd__h517871 : + _theResult___fst_sfd__h483602) ; + assign _theResult___fst_sfd__h517883 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h517879 ; - assign _theResult___fst_sfd__h522405 = + _theResult___fst_sfd__h517877 ; + assign _theResult___fst_sfd__h522403 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_sfd__h538233 = + assign _theResult___fst_sfd__h538231 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 : + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 ; - assign _theResult___fst_sfd__h538236 = - (_theResult___fst_exp__h537477 == 11'd2047) ? - _theResult___snd__h537428[56:5] : - _theResult___fst_sfd__h538233 ; - assign _theResult___fst_sfd__h547884 = + assign _theResult___fst_sfd__h538234 = + (_theResult___fst_exp__h537475 == 11'd2047) ? + _theResult___snd__h537426[56:5] : + _theResult___fst_sfd__h538231 ; + assign _theResult___fst_sfd__h547882 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 ; - assign _theResult___fst_sfd__h547887 = - (_theResult___fst_exp__h547054 == 11'd2047) ? - sfdin__h547048[56:5] : - _theResult___fst_sfd__h547884 ; - assign _theResult___fst_sfd__h556668 = + assign _theResult___fst_sfd__h547885 = + (_theResult___fst_exp__h547052 == 11'd2047) ? + sfdin__h547046[56:5] : + _theResult___fst_sfd__h547882 ; + assign _theResult___fst_sfd__h556666 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 : + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 ; - assign _theResult___fst_sfd__h556671 = - (_theResult___fst_exp__h555887 == 11'd2047) ? - _theResult___snd__h555833[56:5] : - _theResult___fst_sfd__h556668 ; - assign _theResult___fst_sfd__h556680 = + assign _theResult___fst_sfd__h556669 = + (_theResult___fst_exp__h555885 == 11'd2047) ? + _theResult___snd__h555831[56:5] : + _theResult___fst_sfd__h556666 ; + assign _theResult___fst_sfd__h556678 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_sfd__h538239 : - _theResult___fst_sfd__h522405) : + _theResult___snd_fst_sfd__h538237 : + _theResult___fst_sfd__h522403) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_sfd__h556674 : - _theResult___fst_sfd__h522405) ; - assign _theResult___fst_sfd__h556686 = + _theResult___snd_fst_sfd__h556672 : + _theResult___fst_sfd__h522403) ; + assign _theResult___fst_sfd__h556684 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h556680 ; - assign _theResult___fst_sfd__h561606 = + _theResult___fst_sfd__h556678 ; + assign _theResult___fst_sfd__h561604 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_sfd__h577434 = + assign _theResult___fst_sfd__h577432 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 : + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 ; - assign _theResult___fst_sfd__h577437 = - (_theResult___fst_exp__h576678 == 11'd2047) ? - _theResult___snd__h576629[56:5] : - _theResult___fst_sfd__h577434 ; - assign _theResult___fst_sfd__h587085 = + assign _theResult___fst_sfd__h577435 = + (_theResult___fst_exp__h576676 == 11'd2047) ? + _theResult___snd__h576627[56:5] : + _theResult___fst_sfd__h577432 ; + assign _theResult___fst_sfd__h587083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 ; - assign _theResult___fst_sfd__h587088 = - (_theResult___fst_exp__h586255 == 11'd2047) ? - sfdin__h586249[56:5] : - _theResult___fst_sfd__h587085 ; - assign _theResult___fst_sfd__h595869 = + assign _theResult___fst_sfd__h587086 = + (_theResult___fst_exp__h586253 == 11'd2047) ? + sfdin__h586247[56:5] : + _theResult___fst_sfd__h587083 ; + assign _theResult___fst_sfd__h595867 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 : + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 ; - assign _theResult___fst_sfd__h595872 = - (_theResult___fst_exp__h595088 == 11'd2047) ? - _theResult___snd__h595034[56:5] : - _theResult___fst_sfd__h595869 ; - assign _theResult___fst_sfd__h595881 = + assign _theResult___fst_sfd__h595870 = + (_theResult___fst_exp__h595086 == 11'd2047) ? + _theResult___snd__h595032[56:5] : + _theResult___fst_sfd__h595867 ; + assign _theResult___fst_sfd__h595879 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_sfd__h577440 : - _theResult___fst_sfd__h561606) : + _theResult___snd_fst_sfd__h577438 : + _theResult___fst_sfd__h561604) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_sfd__h595875 : - _theResult___fst_sfd__h561606) ; - assign _theResult___fst_sfd__h595887 = + _theResult___snd_fst_sfd__h595873 : + _theResult___fst_sfd__h561604) ; + assign _theResult___fst_sfd__h595885 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h595881 ; - assign _theResult___sfd__h351930 = - sfd__h351505[24] ? - ((_theResult___fst_exp__h351413 == 8'd254) ? + _theResult___fst_sfd__h595879 ; + assign _theResult___sfd__h351928 = + sfd__h351503[24] ? + ((_theResult___fst_exp__h351411 == 8'd254) ? 23'd0 : - sfd__h351505[23:1]) : - sfd__h351505[22:0] ; - assign _theResult___sfd__h360512 = - sfd__h360087[24] ? - ((_theResult___fst_exp__h360069 == 8'd254) ? + sfd__h351503[23:1]) : + sfd__h351503[22:0] ; + assign _theResult___sfd__h360510 = + sfd__h360085[24] ? + ((_theResult___fst_exp__h360067 == 8'd254) ? 23'd0 : - sfd__h360087[23:1]) : - sfd__h360087[22:0] ; - assign _theResult___sfd__h369696 = - sfd__h369271[24] ? - ((_theResult___fst_exp__h369179 == 8'd254) ? + sfd__h360085[23:1]) : + sfd__h360085[22:0] ; + assign _theResult___sfd__h369694 = + sfd__h369269[24] ? + ((_theResult___fst_exp__h369177 == 8'd254) ? 23'd0 : - sfd__h369271[23:1]) : - sfd__h369271[22:0] ; - assign _theResult___sfd__h378332 = - sfd__h377883[24] ? - ((_theResult___fst_exp__h377864 == 8'd254) ? + sfd__h369269[23:1]) : + sfd__h369269[22:0] ; + assign _theResult___sfd__h378330 = + sfd__h377881[24] ? + ((_theResult___fst_exp__h377862 == 8'd254) ? 23'd0 : - sfd__h377883[23:1]) : - sfd__h377883[22:0] ; - assign _theResult___sfd__h378434 = + sfd__h377881[23:1]) : + sfd__h377881[22:0] ; + assign _theResult___sfd__h378432 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h335647 : - _theResult___fst_sfd__h378428 ; - assign _theResult___sfd__h397620 = - sfd__h397195[24] ? - ((_theResult___fst_exp__h397103 == 8'd254) ? + _theResult___snd_fst_sfd__h335645 : + _theResult___fst_sfd__h378426 ; + assign _theResult___sfd__h397618 = + sfd__h397193[24] ? + ((_theResult___fst_exp__h397101 == 8'd254) ? 23'd0 : - sfd__h397195[23:1]) : - sfd__h397195[22:0] ; - assign _theResult___sfd__h406202 = - sfd__h405777[24] ? - ((_theResult___fst_exp__h405759 == 8'd254) ? + sfd__h397193[23:1]) : + sfd__h397193[22:0] ; + assign _theResult___sfd__h406200 = + sfd__h405775[24] ? + ((_theResult___fst_exp__h405757 == 8'd254) ? 23'd0 : - sfd__h405777[23:1]) : - sfd__h405777[22:0] ; - assign _theResult___sfd__h415386 = - sfd__h414961[24] ? - ((_theResult___fst_exp__h414869 == 8'd254) ? + sfd__h405775[23:1]) : + sfd__h405775[22:0] ; + assign _theResult___sfd__h415384 = + sfd__h414959[24] ? + ((_theResult___fst_exp__h414867 == 8'd254) ? 23'd0 : - sfd__h414961[23:1]) : - sfd__h414961[22:0] ; - assign _theResult___sfd__h424022 = - sfd__h423573[24] ? - ((_theResult___fst_exp__h423554 == 8'd254) ? + sfd__h414959[23:1]) : + sfd__h414959[22:0] ; + assign _theResult___sfd__h424020 = + sfd__h423571[24] ? + ((_theResult___fst_exp__h423552 == 8'd254) ? 23'd0 : - sfd__h423573[23:1]) : - sfd__h423573[22:0] ; - assign _theResult___sfd__h424124 = + sfd__h423571[23:1]) : + sfd__h423571[22:0] ; + assign _theResult___sfd__h424122 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h381342 : - _theResult___fst_sfd__h424118 ; - assign _theResult___sfd__h443308 = - sfd__h442883[24] ? - ((_theResult___fst_exp__h442791 == 8'd254) ? + _theResult___snd_fst_sfd__h381340 : + _theResult___fst_sfd__h424116 ; + assign _theResult___sfd__h443306 = + sfd__h442881[24] ? + ((_theResult___fst_exp__h442789 == 8'd254) ? 23'd0 : - sfd__h442883[23:1]) : - sfd__h442883[22:0] ; - assign _theResult___sfd__h451890 = - sfd__h451465[24] ? - ((_theResult___fst_exp__h451447 == 8'd254) ? + sfd__h442881[23:1]) : + sfd__h442881[22:0] ; + assign _theResult___sfd__h451888 = + sfd__h451463[24] ? + ((_theResult___fst_exp__h451445 == 8'd254) ? 23'd0 : - sfd__h451465[23:1]) : - sfd__h451465[22:0] ; - assign _theResult___sfd__h461074 = - sfd__h460649[24] ? - ((_theResult___fst_exp__h460557 == 8'd254) ? + sfd__h451463[23:1]) : + sfd__h451463[22:0] ; + assign _theResult___sfd__h461072 = + sfd__h460647[24] ? + ((_theResult___fst_exp__h460555 == 8'd254) ? 23'd0 : - sfd__h460649[23:1]) : - sfd__h460649[22:0] ; - assign _theResult___sfd__h469710 = - sfd__h469261[24] ? - ((_theResult___fst_exp__h469242 == 8'd254) ? + sfd__h460647[23:1]) : + sfd__h460647[22:0] ; + assign _theResult___sfd__h469708 = + sfd__h469259[24] ? + ((_theResult___fst_exp__h469240 == 8'd254) ? 23'd0 : - sfd__h469261[23:1]) : - sfd__h469261[22:0] ; - assign _theResult___sfd__h469812 = + sfd__h469259[23:1]) : + sfd__h469259[22:0] ; + assign _theResult___sfd__h469810 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h427030 : - _theResult___fst_sfd__h469806 ; - assign _theResult___sfd__h499332 = - sfd__h498694[53] ? - ((_theResult___fst_exp__h498676 == 11'd2046) ? + _theResult___snd_fst_sfd__h427028 : + _theResult___fst_sfd__h469804 ; + assign _theResult___sfd__h499330 = + sfd__h498692[53] ? + ((_theResult___fst_exp__h498674 == 11'd2046) ? 52'd0 : - sfd__h498694[52:1]) : - sfd__h498694[51:0] ; - assign _theResult___sfd__h508983 = - sfd__h508345[53] ? - ((_theResult___fst_exp__h508253 == 11'd2046) ? + sfd__h498692[52:1]) : + sfd__h498692[51:0] ; + assign _theResult___sfd__h508981 = + sfd__h508343[53] ? + ((_theResult___fst_exp__h508251 == 11'd2046) ? 52'd0 : - sfd__h508345[52:1]) : - sfd__h508345[51:0] ; - assign _theResult___sfd__h517767 = - sfd__h517105[53] ? - ((_theResult___fst_exp__h517086 == 11'd2046) ? + sfd__h508343[52:1]) : + sfd__h508343[51:0] ; + assign _theResult___sfd__h517765 = + sfd__h517103[53] ? + ((_theResult___fst_exp__h517084 == 11'd2046) ? 52'd0 : - sfd__h517105[52:1]) : - sfd__h517105[51:0] ; - assign _theResult___sfd__h538133 = - sfd__h537495[53] ? - ((_theResult___fst_exp__h537477 == 11'd2046) ? + sfd__h517103[52:1]) : + sfd__h517103[51:0] ; + assign _theResult___sfd__h538131 = + sfd__h537493[53] ? + ((_theResult___fst_exp__h537475 == 11'd2046) ? 52'd0 : - sfd__h537495[52:1]) : - sfd__h537495[51:0] ; - assign _theResult___sfd__h547784 = - sfd__h547146[53] ? - ((_theResult___fst_exp__h547054 == 11'd2046) ? + sfd__h537493[52:1]) : + sfd__h537493[51:0] ; + assign _theResult___sfd__h547782 = + sfd__h547144[53] ? + ((_theResult___fst_exp__h547052 == 11'd2046) ? 52'd0 : - sfd__h547146[52:1]) : - sfd__h547146[51:0] ; - assign _theResult___sfd__h556568 = - sfd__h555906[53] ? - ((_theResult___fst_exp__h555887 == 11'd2046) ? + sfd__h547144[52:1]) : + sfd__h547144[51:0] ; + assign _theResult___sfd__h556566 = + sfd__h555904[53] ? + ((_theResult___fst_exp__h555885 == 11'd2046) ? 52'd0 : - sfd__h555906[52:1]) : - sfd__h555906[51:0] ; - assign _theResult___sfd__h577334 = - sfd__h576696[53] ? - ((_theResult___fst_exp__h576678 == 11'd2046) ? + sfd__h555904[52:1]) : + sfd__h555904[51:0] ; + assign _theResult___sfd__h577332 = + sfd__h576694[53] ? + ((_theResult___fst_exp__h576676 == 11'd2046) ? 52'd0 : - sfd__h576696[52:1]) : - sfd__h576696[51:0] ; - assign _theResult___sfd__h586985 = - sfd__h586347[53] ? - ((_theResult___fst_exp__h586255 == 11'd2046) ? + sfd__h576694[52:1]) : + sfd__h576694[51:0] ; + assign _theResult___sfd__h586983 = + sfd__h586345[53] ? + ((_theResult___fst_exp__h586253 == 11'd2046) ? 52'd0 : - sfd__h586347[52:1]) : - sfd__h586347[51:0] ; - assign _theResult___sfd__h595769 = - sfd__h595107[53] ? - ((_theResult___fst_exp__h595088 == 11'd2046) ? + sfd__h586345[52:1]) : + sfd__h586345[51:0] ; + assign _theResult___sfd__h595767 = + sfd__h595105[53] ? + ((_theResult___fst_exp__h595086 == 11'd2046) ? 52'd0 : - sfd__h595107[52:1]) : - sfd__h595107[51:0] ; - assign _theResult___snd__h351424 = { _theResult____h343302[55:0], 1'd0 } ; - assign _theResult___snd__h351435 = - (!_theResult____h343302[56] && _theResult____h343302[55]) ? - _theResult___snd__h351437 : - _theResult___snd__h351447 ; - assign _theResult___snd__h351437 = { _theResult____h343302[54:0], 2'd0 } ; - assign _theResult___snd__h351447 = - (!_theResult____h343302[56] && !_theResult____h343302[55] && - !_theResult____h343302[54] && - !_theResult____h343302[53] && - !_theResult____h343302[52] && - !_theResult____h343302[51] && - !_theResult____h343302[50] && - !_theResult____h343302[49] && - !_theResult____h343302[48] && - !_theResult____h343302[47] && - !_theResult____h343302[46] && - !_theResult____h343302[45] && - !_theResult____h343302[44] && - !_theResult____h343302[43] && - !_theResult____h343302[42] && - !_theResult____h343302[41] && - !_theResult____h343302[40] && - !_theResult____h343302[39] && - !_theResult____h343302[38] && - !_theResult____h343302[37] && - !_theResult____h343302[36] && - !_theResult____h343302[35] && - !_theResult____h343302[34] && - !_theResult____h343302[33] && - !_theResult____h343302[32] && - !_theResult____h343302[31] && - !_theResult____h343302[30] && - !_theResult____h343302[29] && - !_theResult____h343302[28] && - !_theResult____h343302[27] && - !_theResult____h343302[26] && - !_theResult____h343302[25] && - !_theResult____h343302[24] && - !_theResult____h343302[23] && - !_theResult____h343302[22] && - !_theResult____h343302[21] && - !_theResult____h343302[20] && - !_theResult____h343302[19] && - !_theResult____h343302[18] && - !_theResult____h343302[17] && - !_theResult____h343302[16] && - !_theResult____h343302[15] && - !_theResult____h343302[14] && - !_theResult____h343302[13] && - !_theResult____h343302[12] && - !_theResult____h343302[11] && - !_theResult____h343302[10] && - !_theResult____h343302[9] && - !_theResult____h343302[8] && - !_theResult____h343302[7] && - !_theResult____h343302[6] && - !_theResult____h343302[5] && - !_theResult____h343302[4] && - !_theResult____h343302[3] && - !_theResult____h343302[2] && - !_theResult____h343302[1] && - !_theResult____h343302[0]) ? - _theResult____h343302 : - _theResult___snd__h351453 ; - assign _theResult___snd__h351453 = + sfd__h595105[52:1]) : + sfd__h595105[51:0] ; + assign _theResult___snd__h351422 = { _theResult____h343300[55:0], 1'd0 } ; + assign _theResult___snd__h351433 = + (!_theResult____h343300[56] && _theResult____h343300[55]) ? + _theResult___snd__h351435 : + _theResult___snd__h351445 ; + assign _theResult___snd__h351435 = { _theResult____h343300[54:0], 2'd0 } ; + assign _theResult___snd__h351445 = + (!_theResult____h343300[56] && !_theResult____h343300[55] && + !_theResult____h343300[54] && + !_theResult____h343300[53] && + !_theResult____h343300[52] && + !_theResult____h343300[51] && + !_theResult____h343300[50] && + !_theResult____h343300[49] && + !_theResult____h343300[48] && + !_theResult____h343300[47] && + !_theResult____h343300[46] && + !_theResult____h343300[45] && + !_theResult____h343300[44] && + !_theResult____h343300[43] && + !_theResult____h343300[42] && + !_theResult____h343300[41] && + !_theResult____h343300[40] && + !_theResult____h343300[39] && + !_theResult____h343300[38] && + !_theResult____h343300[37] && + !_theResult____h343300[36] && + !_theResult____h343300[35] && + !_theResult____h343300[34] && + !_theResult____h343300[33] && + !_theResult____h343300[32] && + !_theResult____h343300[31] && + !_theResult____h343300[30] && + !_theResult____h343300[29] && + !_theResult____h343300[28] && + !_theResult____h343300[27] && + !_theResult____h343300[26] && + !_theResult____h343300[25] && + !_theResult____h343300[24] && + !_theResult____h343300[23] && + !_theResult____h343300[22] && + !_theResult____h343300[21] && + !_theResult____h343300[20] && + !_theResult____h343300[19] && + !_theResult____h343300[18] && + !_theResult____h343300[17] && + !_theResult____h343300[16] && + !_theResult____h343300[15] && + !_theResult____h343300[14] && + !_theResult____h343300[13] && + !_theResult____h343300[12] && + !_theResult____h343300[11] && + !_theResult____h343300[10] && + !_theResult____h343300[9] && + !_theResult____h343300[8] && + !_theResult____h343300[7] && + !_theResult____h343300[6] && + !_theResult____h343300[5] && + !_theResult____h343300[4] && + !_theResult____h343300[3] && + !_theResult____h343300[2] && + !_theResult____h343300[1] && + !_theResult____h343300[0]) ? + _theResult____h343300 : + _theResult___snd__h351451 ; + assign _theResult___snd__h351451 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20[54:0], 2'd0 } ; - assign _theResult___snd__h351476 = - _theResult____h343302 << + assign _theResult___snd__h351474 = + _theResult____h343300 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ; - assign _theResult___snd__h360020 = + assign _theResult___snd__h360018 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h360029 : - _theResult___snd__h360022 ; - assign _theResult___snd__h360022 = + _theResult___snd__h360027 : + _theResult___snd__h360020 ; + assign _theResult___snd__h360020 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h360029 = + assign _theResult___snd__h360027 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335697 : - _theResult___snd__h360035 ; - assign _theResult___snd__h360035 = + sfd__h335695 : + _theResult___snd__h360033 ; + assign _theResult___snd__h360033 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22[54:0], 2'd0 } ; - assign _theResult___snd__h360058 = - sfd__h335697 << + assign _theResult___snd__h360056 = + sfd__h335695 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ; - assign _theResult___snd__h369190 = { _theResult____h360941[55:0], 1'd0 } ; - assign _theResult___snd__h369201 = - (!_theResult____h360941[56] && _theResult____h360941[55]) ? - _theResult___snd__h369203 : - _theResult___snd__h369213 ; - assign _theResult___snd__h369203 = { _theResult____h360941[54:0], 2'd0 } ; - assign _theResult___snd__h369213 = - (!_theResult____h360941[56] && !_theResult____h360941[55] && - !_theResult____h360941[54] && - !_theResult____h360941[53] && - !_theResult____h360941[52] && - !_theResult____h360941[51] && - !_theResult____h360941[50] && - !_theResult____h360941[49] && - !_theResult____h360941[48] && - !_theResult____h360941[47] && - !_theResult____h360941[46] && - !_theResult____h360941[45] && - !_theResult____h360941[44] && - !_theResult____h360941[43] && - !_theResult____h360941[42] && - !_theResult____h360941[41] && - !_theResult____h360941[40] && - !_theResult____h360941[39] && - !_theResult____h360941[38] && - !_theResult____h360941[37] && - !_theResult____h360941[36] && - !_theResult____h360941[35] && - !_theResult____h360941[34] && - !_theResult____h360941[33] && - !_theResult____h360941[32] && - !_theResult____h360941[31] && - !_theResult____h360941[30] && - !_theResult____h360941[29] && - !_theResult____h360941[28] && - !_theResult____h360941[27] && - !_theResult____h360941[26] && - !_theResult____h360941[25] && - !_theResult____h360941[24] && - !_theResult____h360941[23] && - !_theResult____h360941[22] && - !_theResult____h360941[21] && - !_theResult____h360941[20] && - !_theResult____h360941[19] && - !_theResult____h360941[18] && - !_theResult____h360941[17] && - !_theResult____h360941[16] && - !_theResult____h360941[15] && - !_theResult____h360941[14] && - !_theResult____h360941[13] && - !_theResult____h360941[12] && - !_theResult____h360941[11] && - !_theResult____h360941[10] && - !_theResult____h360941[9] && - !_theResult____h360941[8] && - !_theResult____h360941[7] && - !_theResult____h360941[6] && - !_theResult____h360941[5] && - !_theResult____h360941[4] && - !_theResult____h360941[3] && - !_theResult____h360941[2] && - !_theResult____h360941[1] && - !_theResult____h360941[0]) ? - _theResult____h360941 : - _theResult___snd__h369219 ; - assign _theResult___snd__h369219 = + assign _theResult___snd__h369188 = { _theResult____h360939[55:0], 1'd0 } ; + assign _theResult___snd__h369199 = + (!_theResult____h360939[56] && _theResult____h360939[55]) ? + _theResult___snd__h369201 : + _theResult___snd__h369211 ; + assign _theResult___snd__h369201 = { _theResult____h360939[54:0], 2'd0 } ; + assign _theResult___snd__h369211 = + (!_theResult____h360939[56] && !_theResult____h360939[55] && + !_theResult____h360939[54] && + !_theResult____h360939[53] && + !_theResult____h360939[52] && + !_theResult____h360939[51] && + !_theResult____h360939[50] && + !_theResult____h360939[49] && + !_theResult____h360939[48] && + !_theResult____h360939[47] && + !_theResult____h360939[46] && + !_theResult____h360939[45] && + !_theResult____h360939[44] && + !_theResult____h360939[43] && + !_theResult____h360939[42] && + !_theResult____h360939[41] && + !_theResult____h360939[40] && + !_theResult____h360939[39] && + !_theResult____h360939[38] && + !_theResult____h360939[37] && + !_theResult____h360939[36] && + !_theResult____h360939[35] && + !_theResult____h360939[34] && + !_theResult____h360939[33] && + !_theResult____h360939[32] && + !_theResult____h360939[31] && + !_theResult____h360939[30] && + !_theResult____h360939[29] && + !_theResult____h360939[28] && + !_theResult____h360939[27] && + !_theResult____h360939[26] && + !_theResult____h360939[25] && + !_theResult____h360939[24] && + !_theResult____h360939[23] && + !_theResult____h360939[22] && + !_theResult____h360939[21] && + !_theResult____h360939[20] && + !_theResult____h360939[19] && + !_theResult____h360939[18] && + !_theResult____h360939[17] && + !_theResult____h360939[16] && + !_theResult____h360939[15] && + !_theResult____h360939[14] && + !_theResult____h360939[13] && + !_theResult____h360939[12] && + !_theResult____h360939[11] && + !_theResult____h360939[10] && + !_theResult____h360939[9] && + !_theResult____h360939[8] && + !_theResult____h360939[7] && + !_theResult____h360939[6] && + !_theResult____h360939[5] && + !_theResult____h360939[4] && + !_theResult____h360939[3] && + !_theResult____h360939[2] && + !_theResult____h360939[1] && + !_theResult____h360939[0]) ? + _theResult____h360939 : + _theResult___snd__h369217 ; + assign _theResult___snd__h369217 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h369242 = - _theResult____h360941 << + assign _theResult___snd__h369240 = + _theResult____h360939 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ; - assign _theResult___snd__h377810 = + assign _theResult___snd__h377808 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h377824 : - _theResult___snd__h360022 ; - assign _theResult___snd__h377824 = + _theResult___snd__h377822 : + _theResult___snd__h360020 ; + assign _theResult___snd__h377822 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335697 : - _theResult___snd__h377830 ; - assign _theResult___snd__h377830 = + sfd__h335695 : + _theResult___snd__h377828 ; + assign _theResult___snd__h377828 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35[54:0], 2'd0 } ; - assign _theResult___snd__h377848 = - sfd__h335697 << + assign _theResult___snd__h377846 = + sfd__h335695 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ; - assign _theResult___snd__h397114 = { _theResult____h388994[55:0], 1'd0 } ; - assign _theResult___snd__h397125 = - (!_theResult____h388994[56] && _theResult____h388994[55]) ? - _theResult___snd__h397127 : - _theResult___snd__h397137 ; - assign _theResult___snd__h397127 = { _theResult____h388994[54:0], 2'd0 } ; - assign _theResult___snd__h397137 = - (!_theResult____h388994[56] && !_theResult____h388994[55] && - !_theResult____h388994[54] && - !_theResult____h388994[53] && - !_theResult____h388994[52] && - !_theResult____h388994[51] && - !_theResult____h388994[50] && - !_theResult____h388994[49] && - !_theResult____h388994[48] && - !_theResult____h388994[47] && - !_theResult____h388994[46] && - !_theResult____h388994[45] && - !_theResult____h388994[44] && - !_theResult____h388994[43] && - !_theResult____h388994[42] && - !_theResult____h388994[41] && - !_theResult____h388994[40] && - !_theResult____h388994[39] && - !_theResult____h388994[38] && - !_theResult____h388994[37] && - !_theResult____h388994[36] && - !_theResult____h388994[35] && - !_theResult____h388994[34] && - !_theResult____h388994[33] && - !_theResult____h388994[32] && - !_theResult____h388994[31] && - !_theResult____h388994[30] && - !_theResult____h388994[29] && - !_theResult____h388994[28] && - !_theResult____h388994[27] && - !_theResult____h388994[26] && - !_theResult____h388994[25] && - !_theResult____h388994[24] && - !_theResult____h388994[23] && - !_theResult____h388994[22] && - !_theResult____h388994[21] && - !_theResult____h388994[20] && - !_theResult____h388994[19] && - !_theResult____h388994[18] && - !_theResult____h388994[17] && - !_theResult____h388994[16] && - !_theResult____h388994[15] && - !_theResult____h388994[14] && - !_theResult____h388994[13] && - !_theResult____h388994[12] && - !_theResult____h388994[11] && - !_theResult____h388994[10] && - !_theResult____h388994[9] && - !_theResult____h388994[8] && - !_theResult____h388994[7] && - !_theResult____h388994[6] && - !_theResult____h388994[5] && - !_theResult____h388994[4] && - !_theResult____h388994[3] && - !_theResult____h388994[2] && - !_theResult____h388994[1] && - !_theResult____h388994[0]) ? - _theResult____h388994 : - _theResult___snd__h397143 ; - assign _theResult___snd__h397143 = + assign _theResult___snd__h397112 = { _theResult____h388992[55:0], 1'd0 } ; + assign _theResult___snd__h397123 = + (!_theResult____h388992[56] && _theResult____h388992[55]) ? + _theResult___snd__h397125 : + _theResult___snd__h397135 ; + assign _theResult___snd__h397125 = { _theResult____h388992[54:0], 2'd0 } ; + assign _theResult___snd__h397135 = + (!_theResult____h388992[56] && !_theResult____h388992[55] && + !_theResult____h388992[54] && + !_theResult____h388992[53] && + !_theResult____h388992[52] && + !_theResult____h388992[51] && + !_theResult____h388992[50] && + !_theResult____h388992[49] && + !_theResult____h388992[48] && + !_theResult____h388992[47] && + !_theResult____h388992[46] && + !_theResult____h388992[45] && + !_theResult____h388992[44] && + !_theResult____h388992[43] && + !_theResult____h388992[42] && + !_theResult____h388992[41] && + !_theResult____h388992[40] && + !_theResult____h388992[39] && + !_theResult____h388992[38] && + !_theResult____h388992[37] && + !_theResult____h388992[36] && + !_theResult____h388992[35] && + !_theResult____h388992[34] && + !_theResult____h388992[33] && + !_theResult____h388992[32] && + !_theResult____h388992[31] && + !_theResult____h388992[30] && + !_theResult____h388992[29] && + !_theResult____h388992[28] && + !_theResult____h388992[27] && + !_theResult____h388992[26] && + !_theResult____h388992[25] && + !_theResult____h388992[24] && + !_theResult____h388992[23] && + !_theResult____h388992[22] && + !_theResult____h388992[21] && + !_theResult____h388992[20] && + !_theResult____h388992[19] && + !_theResult____h388992[18] && + !_theResult____h388992[17] && + !_theResult____h388992[16] && + !_theResult____h388992[15] && + !_theResult____h388992[14] && + !_theResult____h388992[13] && + !_theResult____h388992[12] && + !_theResult____h388992[11] && + !_theResult____h388992[10] && + !_theResult____h388992[9] && + !_theResult____h388992[8] && + !_theResult____h388992[7] && + !_theResult____h388992[6] && + !_theResult____h388992[5] && + !_theResult____h388992[4] && + !_theResult____h388992[3] && + !_theResult____h388992[2] && + !_theResult____h388992[1] && + !_theResult____h388992[0]) ? + _theResult____h388992 : + _theResult___snd__h397141 ; + assign _theResult___snd__h397141 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55[54:0], 2'd0 } ; - assign _theResult___snd__h397166 = - _theResult____h388994 << + assign _theResult___snd__h397164 = + _theResult____h388992 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ; - assign _theResult___snd__h405710 = + assign _theResult___snd__h405708 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h405719 : - _theResult___snd__h405712 ; - assign _theResult___snd__h405712 = + _theResult___snd__h405717 : + _theResult___snd__h405710 ; + assign _theResult___snd__h405710 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h405719 = + assign _theResult___snd__h405717 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381392 : - _theResult___snd__h405725 ; - assign _theResult___snd__h405725 = + sfd__h381390 : + _theResult___snd__h405723 ; + assign _theResult___snd__h405723 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57[54:0], 2'd0 } ; - assign _theResult___snd__h405748 = - sfd__h381392 << + assign _theResult___snd__h405746 = + sfd__h381390 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ; - assign _theResult___snd__h414880 = { _theResult____h406631[55:0], 1'd0 } ; - assign _theResult___snd__h414891 = - (!_theResult____h406631[56] && _theResult____h406631[55]) ? - _theResult___snd__h414893 : - _theResult___snd__h414903 ; - assign _theResult___snd__h414893 = { _theResult____h406631[54:0], 2'd0 } ; - assign _theResult___snd__h414903 = - (!_theResult____h406631[56] && !_theResult____h406631[55] && - !_theResult____h406631[54] && - !_theResult____h406631[53] && - !_theResult____h406631[52] && - !_theResult____h406631[51] && - !_theResult____h406631[50] && - !_theResult____h406631[49] && - !_theResult____h406631[48] && - !_theResult____h406631[47] && - !_theResult____h406631[46] && - !_theResult____h406631[45] && - !_theResult____h406631[44] && - !_theResult____h406631[43] && - !_theResult____h406631[42] && - !_theResult____h406631[41] && - !_theResult____h406631[40] && - !_theResult____h406631[39] && - !_theResult____h406631[38] && - !_theResult____h406631[37] && - !_theResult____h406631[36] && - !_theResult____h406631[35] && - !_theResult____h406631[34] && - !_theResult____h406631[33] && - !_theResult____h406631[32] && - !_theResult____h406631[31] && - !_theResult____h406631[30] && - !_theResult____h406631[29] && - !_theResult____h406631[28] && - !_theResult____h406631[27] && - !_theResult____h406631[26] && - !_theResult____h406631[25] && - !_theResult____h406631[24] && - !_theResult____h406631[23] && - !_theResult____h406631[22] && - !_theResult____h406631[21] && - !_theResult____h406631[20] && - !_theResult____h406631[19] && - !_theResult____h406631[18] && - !_theResult____h406631[17] && - !_theResult____h406631[16] && - !_theResult____h406631[15] && - !_theResult____h406631[14] && - !_theResult____h406631[13] && - !_theResult____h406631[12] && - !_theResult____h406631[11] && - !_theResult____h406631[10] && - !_theResult____h406631[9] && - !_theResult____h406631[8] && - !_theResult____h406631[7] && - !_theResult____h406631[6] && - !_theResult____h406631[5] && - !_theResult____h406631[4] && - !_theResult____h406631[3] && - !_theResult____h406631[2] && - !_theResult____h406631[1] && - !_theResult____h406631[0]) ? - _theResult____h406631 : - _theResult___snd__h414909 ; - assign _theResult___snd__h414909 = + assign _theResult___snd__h414878 = { _theResult____h406629[55:0], 1'd0 } ; + assign _theResult___snd__h414889 = + (!_theResult____h406629[56] && _theResult____h406629[55]) ? + _theResult___snd__h414891 : + _theResult___snd__h414901 ; + assign _theResult___snd__h414891 = { _theResult____h406629[54:0], 2'd0 } ; + assign _theResult___snd__h414901 = + (!_theResult____h406629[56] && !_theResult____h406629[55] && + !_theResult____h406629[54] && + !_theResult____h406629[53] && + !_theResult____h406629[52] && + !_theResult____h406629[51] && + !_theResult____h406629[50] && + !_theResult____h406629[49] && + !_theResult____h406629[48] && + !_theResult____h406629[47] && + !_theResult____h406629[46] && + !_theResult____h406629[45] && + !_theResult____h406629[44] && + !_theResult____h406629[43] && + !_theResult____h406629[42] && + !_theResult____h406629[41] && + !_theResult____h406629[40] && + !_theResult____h406629[39] && + !_theResult____h406629[38] && + !_theResult____h406629[37] && + !_theResult____h406629[36] && + !_theResult____h406629[35] && + !_theResult____h406629[34] && + !_theResult____h406629[33] && + !_theResult____h406629[32] && + !_theResult____h406629[31] && + !_theResult____h406629[30] && + !_theResult____h406629[29] && + !_theResult____h406629[28] && + !_theResult____h406629[27] && + !_theResult____h406629[26] && + !_theResult____h406629[25] && + !_theResult____h406629[24] && + !_theResult____h406629[23] && + !_theResult____h406629[22] && + !_theResult____h406629[21] && + !_theResult____h406629[20] && + !_theResult____h406629[19] && + !_theResult____h406629[18] && + !_theResult____h406629[17] && + !_theResult____h406629[16] && + !_theResult____h406629[15] && + !_theResult____h406629[14] && + !_theResult____h406629[13] && + !_theResult____h406629[12] && + !_theResult____h406629[11] && + !_theResult____h406629[10] && + !_theResult____h406629[9] && + !_theResult____h406629[8] && + !_theResult____h406629[7] && + !_theResult____h406629[6] && + !_theResult____h406629[5] && + !_theResult____h406629[4] && + !_theResult____h406629[3] && + !_theResult____h406629[2] && + !_theResult____h406629[1] && + !_theResult____h406629[0]) ? + _theResult____h406629 : + _theResult___snd__h414907 ; + assign _theResult___snd__h414907 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h414932 = - _theResult____h406631 << + assign _theResult___snd__h414930 = + _theResult____h406629 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ; - assign _theResult___snd__h423500 = + assign _theResult___snd__h423498 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h423514 : - _theResult___snd__h405712 ; - assign _theResult___snd__h423514 = + _theResult___snd__h423512 : + _theResult___snd__h405710 ; + assign _theResult___snd__h423512 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381392 : - _theResult___snd__h423520 ; - assign _theResult___snd__h423520 = + sfd__h381390 : + _theResult___snd__h423518 ; + assign _theResult___snd__h423518 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70[54:0], 2'd0 } ; - assign _theResult___snd__h423538 = - sfd__h381392 << + assign _theResult___snd__h423536 = + sfd__h381390 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ; - assign _theResult___snd__h442802 = { _theResult____h434682[55:0], 1'd0 } ; - assign _theResult___snd__h442813 = - (!_theResult____h434682[56] && _theResult____h434682[55]) ? - _theResult___snd__h442815 : - _theResult___snd__h442825 ; - assign _theResult___snd__h442815 = { _theResult____h434682[54:0], 2'd0 } ; - assign _theResult___snd__h442825 = - (!_theResult____h434682[56] && !_theResult____h434682[55] && - !_theResult____h434682[54] && - !_theResult____h434682[53] && - !_theResult____h434682[52] && - !_theResult____h434682[51] && - !_theResult____h434682[50] && - !_theResult____h434682[49] && - !_theResult____h434682[48] && - !_theResult____h434682[47] && - !_theResult____h434682[46] && - !_theResult____h434682[45] && - !_theResult____h434682[44] && - !_theResult____h434682[43] && - !_theResult____h434682[42] && - !_theResult____h434682[41] && - !_theResult____h434682[40] && - !_theResult____h434682[39] && - !_theResult____h434682[38] && - !_theResult____h434682[37] && - !_theResult____h434682[36] && - !_theResult____h434682[35] && - !_theResult____h434682[34] && - !_theResult____h434682[33] && - !_theResult____h434682[32] && - !_theResult____h434682[31] && - !_theResult____h434682[30] && - !_theResult____h434682[29] && - !_theResult____h434682[28] && - !_theResult____h434682[27] && - !_theResult____h434682[26] && - !_theResult____h434682[25] && - !_theResult____h434682[24] && - !_theResult____h434682[23] && - !_theResult____h434682[22] && - !_theResult____h434682[21] && - !_theResult____h434682[20] && - !_theResult____h434682[19] && - !_theResult____h434682[18] && - !_theResult____h434682[17] && - !_theResult____h434682[16] && - !_theResult____h434682[15] && - !_theResult____h434682[14] && - !_theResult____h434682[13] && - !_theResult____h434682[12] && - !_theResult____h434682[11] && - !_theResult____h434682[10] && - !_theResult____h434682[9] && - !_theResult____h434682[8] && - !_theResult____h434682[7] && - !_theResult____h434682[6] && - !_theResult____h434682[5] && - !_theResult____h434682[4] && - !_theResult____h434682[3] && - !_theResult____h434682[2] && - !_theResult____h434682[1] && - !_theResult____h434682[0]) ? - _theResult____h434682 : - _theResult___snd__h442831 ; - assign _theResult___snd__h442831 = + assign _theResult___snd__h442800 = { _theResult____h434680[55:0], 1'd0 } ; + assign _theResult___snd__h442811 = + (!_theResult____h434680[56] && _theResult____h434680[55]) ? + _theResult___snd__h442813 : + _theResult___snd__h442823 ; + assign _theResult___snd__h442813 = { _theResult____h434680[54:0], 2'd0 } ; + assign _theResult___snd__h442823 = + (!_theResult____h434680[56] && !_theResult____h434680[55] && + !_theResult____h434680[54] && + !_theResult____h434680[53] && + !_theResult____h434680[52] && + !_theResult____h434680[51] && + !_theResult____h434680[50] && + !_theResult____h434680[49] && + !_theResult____h434680[48] && + !_theResult____h434680[47] && + !_theResult____h434680[46] && + !_theResult____h434680[45] && + !_theResult____h434680[44] && + !_theResult____h434680[43] && + !_theResult____h434680[42] && + !_theResult____h434680[41] && + !_theResult____h434680[40] && + !_theResult____h434680[39] && + !_theResult____h434680[38] && + !_theResult____h434680[37] && + !_theResult____h434680[36] && + !_theResult____h434680[35] && + !_theResult____h434680[34] && + !_theResult____h434680[33] && + !_theResult____h434680[32] && + !_theResult____h434680[31] && + !_theResult____h434680[30] && + !_theResult____h434680[29] && + !_theResult____h434680[28] && + !_theResult____h434680[27] && + !_theResult____h434680[26] && + !_theResult____h434680[25] && + !_theResult____h434680[24] && + !_theResult____h434680[23] && + !_theResult____h434680[22] && + !_theResult____h434680[21] && + !_theResult____h434680[20] && + !_theResult____h434680[19] && + !_theResult____h434680[18] && + !_theResult____h434680[17] && + !_theResult____h434680[16] && + !_theResult____h434680[15] && + !_theResult____h434680[14] && + !_theResult____h434680[13] && + !_theResult____h434680[12] && + !_theResult____h434680[11] && + !_theResult____h434680[10] && + !_theResult____h434680[9] && + !_theResult____h434680[8] && + !_theResult____h434680[7] && + !_theResult____h434680[6] && + !_theResult____h434680[5] && + !_theResult____h434680[4] && + !_theResult____h434680[3] && + !_theResult____h434680[2] && + !_theResult____h434680[1] && + !_theResult____h434680[0]) ? + _theResult____h434680 : + _theResult___snd__h442829 ; + assign _theResult___snd__h442829 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90[54:0], 2'd0 } ; - assign _theResult___snd__h442854 = - _theResult____h434682 << + assign _theResult___snd__h442852 = + _theResult____h434680 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ; - assign _theResult___snd__h451398 = + assign _theResult___snd__h451396 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h451407 : - _theResult___snd__h451400 ; - assign _theResult___snd__h451400 = + _theResult___snd__h451405 : + _theResult___snd__h451398 ; + assign _theResult___snd__h451398 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h451407 = + assign _theResult___snd__h451405 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427080 : - _theResult___snd__h451413 ; - assign _theResult___snd__h451413 = + sfd__h427078 : + _theResult___snd__h451411 ; + assign _theResult___snd__h451411 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92[54:0], 2'd0 } ; - assign _theResult___snd__h451436 = - sfd__h427080 << + assign _theResult___snd__h451434 = + sfd__h427078 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ; - assign _theResult___snd__h460568 = { _theResult____h452319[55:0], 1'd0 } ; - assign _theResult___snd__h460579 = - (!_theResult____h452319[56] && _theResult____h452319[55]) ? - _theResult___snd__h460581 : - _theResult___snd__h460591 ; - assign _theResult___snd__h460581 = { _theResult____h452319[54:0], 2'd0 } ; - assign _theResult___snd__h460591 = - (!_theResult____h452319[56] && !_theResult____h452319[55] && - !_theResult____h452319[54] && - !_theResult____h452319[53] && - !_theResult____h452319[52] && - !_theResult____h452319[51] && - !_theResult____h452319[50] && - !_theResult____h452319[49] && - !_theResult____h452319[48] && - !_theResult____h452319[47] && - !_theResult____h452319[46] && - !_theResult____h452319[45] && - !_theResult____h452319[44] && - !_theResult____h452319[43] && - !_theResult____h452319[42] && - !_theResult____h452319[41] && - !_theResult____h452319[40] && - !_theResult____h452319[39] && - !_theResult____h452319[38] && - !_theResult____h452319[37] && - !_theResult____h452319[36] && - !_theResult____h452319[35] && - !_theResult____h452319[34] && - !_theResult____h452319[33] && - !_theResult____h452319[32] && - !_theResult____h452319[31] && - !_theResult____h452319[30] && - !_theResult____h452319[29] && - !_theResult____h452319[28] && - !_theResult____h452319[27] && - !_theResult____h452319[26] && - !_theResult____h452319[25] && - !_theResult____h452319[24] && - !_theResult____h452319[23] && - !_theResult____h452319[22] && - !_theResult____h452319[21] && - !_theResult____h452319[20] && - !_theResult____h452319[19] && - !_theResult____h452319[18] && - !_theResult____h452319[17] && - !_theResult____h452319[16] && - !_theResult____h452319[15] && - !_theResult____h452319[14] && - !_theResult____h452319[13] && - !_theResult____h452319[12] && - !_theResult____h452319[11] && - !_theResult____h452319[10] && - !_theResult____h452319[9] && - !_theResult____h452319[8] && - !_theResult____h452319[7] && - !_theResult____h452319[6] && - !_theResult____h452319[5] && - !_theResult____h452319[4] && - !_theResult____h452319[3] && - !_theResult____h452319[2] && - !_theResult____h452319[1] && - !_theResult____h452319[0]) ? - _theResult____h452319 : - _theResult___snd__h460597 ; - assign _theResult___snd__h460597 = + assign _theResult___snd__h460566 = { _theResult____h452317[55:0], 1'd0 } ; + assign _theResult___snd__h460577 = + (!_theResult____h452317[56] && _theResult____h452317[55]) ? + _theResult___snd__h460579 : + _theResult___snd__h460589 ; + assign _theResult___snd__h460579 = { _theResult____h452317[54:0], 2'd0 } ; + assign _theResult___snd__h460589 = + (!_theResult____h452317[56] && !_theResult____h452317[55] && + !_theResult____h452317[54] && + !_theResult____h452317[53] && + !_theResult____h452317[52] && + !_theResult____h452317[51] && + !_theResult____h452317[50] && + !_theResult____h452317[49] && + !_theResult____h452317[48] && + !_theResult____h452317[47] && + !_theResult____h452317[46] && + !_theResult____h452317[45] && + !_theResult____h452317[44] && + !_theResult____h452317[43] && + !_theResult____h452317[42] && + !_theResult____h452317[41] && + !_theResult____h452317[40] && + !_theResult____h452317[39] && + !_theResult____h452317[38] && + !_theResult____h452317[37] && + !_theResult____h452317[36] && + !_theResult____h452317[35] && + !_theResult____h452317[34] && + !_theResult____h452317[33] && + !_theResult____h452317[32] && + !_theResult____h452317[31] && + !_theResult____h452317[30] && + !_theResult____h452317[29] && + !_theResult____h452317[28] && + !_theResult____h452317[27] && + !_theResult____h452317[26] && + !_theResult____h452317[25] && + !_theResult____h452317[24] && + !_theResult____h452317[23] && + !_theResult____h452317[22] && + !_theResult____h452317[21] && + !_theResult____h452317[20] && + !_theResult____h452317[19] && + !_theResult____h452317[18] && + !_theResult____h452317[17] && + !_theResult____h452317[16] && + !_theResult____h452317[15] && + !_theResult____h452317[14] && + !_theResult____h452317[13] && + !_theResult____h452317[12] && + !_theResult____h452317[11] && + !_theResult____h452317[10] && + !_theResult____h452317[9] && + !_theResult____h452317[8] && + !_theResult____h452317[7] && + !_theResult____h452317[6] && + !_theResult____h452317[5] && + !_theResult____h452317[4] && + !_theResult____h452317[3] && + !_theResult____h452317[2] && + !_theResult____h452317[1] && + !_theResult____h452317[0]) ? + _theResult____h452317 : + _theResult___snd__h460595 ; + assign _theResult___snd__h460595 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h460620 = - _theResult____h452319 << + assign _theResult___snd__h460618 = + _theResult____h452317 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ; - assign _theResult___snd__h469188 = + assign _theResult___snd__h469186 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h469202 : - _theResult___snd__h451400 ; - assign _theResult___snd__h469202 = + _theResult___snd__h469200 : + _theResult___snd__h451398 ; + assign _theResult___snd__h469200 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427080 : - _theResult___snd__h469208 ; - assign _theResult___snd__h469208 = + sfd__h427078 : + _theResult___snd__h469206 ; + assign _theResult___snd__h469206 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105[54:0], 2'd0 } ; - assign _theResult___snd__h469226 = - sfd__h427080 << + assign _theResult___snd__h469224 = + sfd__h427078 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ; - assign _theResult___snd__h498627 = + assign _theResult___snd__h498625 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h498636 : - _theResult___snd__h498629 ; - assign _theResult___snd__h498629 = + _theResult___snd__h498634 : + _theResult___snd__h498627 ; + assign _theResult___snd__h498627 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ; - assign _theResult___snd__h498636 = + assign _theResult___snd__h498634 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479675 : - _theResult___snd__h498642 ; - assign _theResult___snd__h498642 = + sfd__h479673 : + _theResult___snd__h498640 ; + assign _theResult___snd__h498640 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h498665 = - sfd__h479675 << + assign _theResult___snd__h498663 = + sfd__h479673 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 ; - assign _theResult___snd__h508264 = { _theResult____h500017[55:0], 1'd0 } ; - assign _theResult___snd__h508275 = - (!_theResult____h500017[56] && _theResult____h500017[55]) ? - _theResult___snd__h508277 : - _theResult___snd__h508287 ; - assign _theResult___snd__h508277 = { _theResult____h500017[54:0], 2'd0 } ; - assign _theResult___snd__h508287 = - (!_theResult____h500017[56] && !_theResult____h500017[55] && - !_theResult____h500017[54] && - !_theResult____h500017[53] && - !_theResult____h500017[52] && - !_theResult____h500017[51] && - !_theResult____h500017[50] && - !_theResult____h500017[49] && - !_theResult____h500017[48] && - !_theResult____h500017[47] && - !_theResult____h500017[46] && - !_theResult____h500017[45] && - !_theResult____h500017[44] && - !_theResult____h500017[43] && - !_theResult____h500017[42] && - !_theResult____h500017[41] && - !_theResult____h500017[40] && - !_theResult____h500017[39] && - !_theResult____h500017[38] && - !_theResult____h500017[37] && - !_theResult____h500017[36] && - !_theResult____h500017[35] && - !_theResult____h500017[34] && - !_theResult____h500017[33] && - !_theResult____h500017[32] && - !_theResult____h500017[31] && - !_theResult____h500017[30] && - !_theResult____h500017[29] && - !_theResult____h500017[28] && - !_theResult____h500017[27] && - !_theResult____h500017[26] && - !_theResult____h500017[25] && - !_theResult____h500017[24] && - !_theResult____h500017[23] && - !_theResult____h500017[22] && - !_theResult____h500017[21] && - !_theResult____h500017[20] && - !_theResult____h500017[19] && - !_theResult____h500017[18] && - !_theResult____h500017[17] && - !_theResult____h500017[16] && - !_theResult____h500017[15] && - !_theResult____h500017[14] && - !_theResult____h500017[13] && - !_theResult____h500017[12] && - !_theResult____h500017[11] && - !_theResult____h500017[10] && - !_theResult____h500017[9] && - !_theResult____h500017[8] && - !_theResult____h500017[7] && - !_theResult____h500017[6] && - !_theResult____h500017[5] && - !_theResult____h500017[4] && - !_theResult____h500017[3] && - !_theResult____h500017[2] && - !_theResult____h500017[1] && - !_theResult____h500017[0]) ? - _theResult____h500017 : - _theResult___snd__h508293 ; - assign _theResult___snd__h508293 = + assign _theResult___snd__h508262 = { _theResult____h500015[55:0], 1'd0 } ; + assign _theResult___snd__h508273 = + (!_theResult____h500015[56] && _theResult____h500015[55]) ? + _theResult___snd__h508275 : + _theResult___snd__h508285 ; + assign _theResult___snd__h508275 = { _theResult____h500015[54:0], 2'd0 } ; + assign _theResult___snd__h508285 = + (!_theResult____h500015[56] && !_theResult____h500015[55] && + !_theResult____h500015[54] && + !_theResult____h500015[53] && + !_theResult____h500015[52] && + !_theResult____h500015[51] && + !_theResult____h500015[50] && + !_theResult____h500015[49] && + !_theResult____h500015[48] && + !_theResult____h500015[47] && + !_theResult____h500015[46] && + !_theResult____h500015[45] && + !_theResult____h500015[44] && + !_theResult____h500015[43] && + !_theResult____h500015[42] && + !_theResult____h500015[41] && + !_theResult____h500015[40] && + !_theResult____h500015[39] && + !_theResult____h500015[38] && + !_theResult____h500015[37] && + !_theResult____h500015[36] && + !_theResult____h500015[35] && + !_theResult____h500015[34] && + !_theResult____h500015[33] && + !_theResult____h500015[32] && + !_theResult____h500015[31] && + !_theResult____h500015[30] && + !_theResult____h500015[29] && + !_theResult____h500015[28] && + !_theResult____h500015[27] && + !_theResult____h500015[26] && + !_theResult____h500015[25] && + !_theResult____h500015[24] && + !_theResult____h500015[23] && + !_theResult____h500015[22] && + !_theResult____h500015[21] && + !_theResult____h500015[20] && + !_theResult____h500015[19] && + !_theResult____h500015[18] && + !_theResult____h500015[17] && + !_theResult____h500015[16] && + !_theResult____h500015[15] && + !_theResult____h500015[14] && + !_theResult____h500015[13] && + !_theResult____h500015[12] && + !_theResult____h500015[11] && + !_theResult____h500015[10] && + !_theResult____h500015[9] && + !_theResult____h500015[8] && + !_theResult____h500015[7] && + !_theResult____h500015[6] && + !_theResult____h500015[5] && + !_theResult____h500015[4] && + !_theResult____h500015[3] && + !_theResult____h500015[2] && + !_theResult____h500015[1] && + !_theResult____h500015[0]) ? + _theResult____h500015 : + _theResult___snd__h508291 ; + assign _theResult___snd__h508291 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h508316 = - _theResult____h500017 << + assign _theResult___snd__h508314 = + _theResult____h500015 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 ; - assign _theResult___snd__h517032 = + assign _theResult___snd__h517030 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h517046 : - _theResult___snd__h498629 ; - assign _theResult___snd__h517046 = + _theResult___snd__h517044 : + _theResult___snd__h498627 ; + assign _theResult___snd__h517044 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479675 : - _theResult___snd__h517052 ; - assign _theResult___snd__h517052 = + sfd__h479673 : + _theResult___snd__h517050 ; + assign _theResult___snd__h517050 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h517070 = - sfd__h479675 << + assign _theResult___snd__h517068 = + sfd__h479673 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 ; - assign _theResult___snd__h537428 = + assign _theResult___snd__h537426 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h537437 : - _theResult___snd__h537430 ; - assign _theResult___snd__h537430 = + _theResult___snd__h537435 : + _theResult___snd__h537428 ; + assign _theResult___snd__h537428 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ; - assign _theResult___snd__h537437 = + assign _theResult___snd__h537435 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518617 : - _theResult___snd__h537443 ; - assign _theResult___snd__h537443 = + sfd__h518615 : + _theResult___snd__h537441 ; + assign _theResult___snd__h537441 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h537466 = - sfd__h518617 << + assign _theResult___snd__h537464 = + sfd__h518615 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 ; - assign _theResult___snd__h547065 = { _theResult____h538818[55:0], 1'd0 } ; - assign _theResult___snd__h547076 = - (!_theResult____h538818[56] && _theResult____h538818[55]) ? - _theResult___snd__h547078 : - _theResult___snd__h547088 ; - assign _theResult___snd__h547078 = { _theResult____h538818[54:0], 2'd0 } ; - assign _theResult___snd__h547088 = - (!_theResult____h538818[56] && !_theResult____h538818[55] && - !_theResult____h538818[54] && - !_theResult____h538818[53] && - !_theResult____h538818[52] && - !_theResult____h538818[51] && - !_theResult____h538818[50] && - !_theResult____h538818[49] && - !_theResult____h538818[48] && - !_theResult____h538818[47] && - !_theResult____h538818[46] && - !_theResult____h538818[45] && - !_theResult____h538818[44] && - !_theResult____h538818[43] && - !_theResult____h538818[42] && - !_theResult____h538818[41] && - !_theResult____h538818[40] && - !_theResult____h538818[39] && - !_theResult____h538818[38] && - !_theResult____h538818[37] && - !_theResult____h538818[36] && - !_theResult____h538818[35] && - !_theResult____h538818[34] && - !_theResult____h538818[33] && - !_theResult____h538818[32] && - !_theResult____h538818[31] && - !_theResult____h538818[30] && - !_theResult____h538818[29] && - !_theResult____h538818[28] && - !_theResult____h538818[27] && - !_theResult____h538818[26] && - !_theResult____h538818[25] && - !_theResult____h538818[24] && - !_theResult____h538818[23] && - !_theResult____h538818[22] && - !_theResult____h538818[21] && - !_theResult____h538818[20] && - !_theResult____h538818[19] && - !_theResult____h538818[18] && - !_theResult____h538818[17] && - !_theResult____h538818[16] && - !_theResult____h538818[15] && - !_theResult____h538818[14] && - !_theResult____h538818[13] && - !_theResult____h538818[12] && - !_theResult____h538818[11] && - !_theResult____h538818[10] && - !_theResult____h538818[9] && - !_theResult____h538818[8] && - !_theResult____h538818[7] && - !_theResult____h538818[6] && - !_theResult____h538818[5] && - !_theResult____h538818[4] && - !_theResult____h538818[3] && - !_theResult____h538818[2] && - !_theResult____h538818[1] && - !_theResult____h538818[0]) ? - _theResult____h538818 : - _theResult___snd__h547094 ; - assign _theResult___snd__h547094 = + assign _theResult___snd__h547063 = { _theResult____h538816[55:0], 1'd0 } ; + assign _theResult___snd__h547074 = + (!_theResult____h538816[56] && _theResult____h538816[55]) ? + _theResult___snd__h547076 : + _theResult___snd__h547086 ; + assign _theResult___snd__h547076 = { _theResult____h538816[54:0], 2'd0 } ; + assign _theResult___snd__h547086 = + (!_theResult____h538816[56] && !_theResult____h538816[55] && + !_theResult____h538816[54] && + !_theResult____h538816[53] && + !_theResult____h538816[52] && + !_theResult____h538816[51] && + !_theResult____h538816[50] && + !_theResult____h538816[49] && + !_theResult____h538816[48] && + !_theResult____h538816[47] && + !_theResult____h538816[46] && + !_theResult____h538816[45] && + !_theResult____h538816[44] && + !_theResult____h538816[43] && + !_theResult____h538816[42] && + !_theResult____h538816[41] && + !_theResult____h538816[40] && + !_theResult____h538816[39] && + !_theResult____h538816[38] && + !_theResult____h538816[37] && + !_theResult____h538816[36] && + !_theResult____h538816[35] && + !_theResult____h538816[34] && + !_theResult____h538816[33] && + !_theResult____h538816[32] && + !_theResult____h538816[31] && + !_theResult____h538816[30] && + !_theResult____h538816[29] && + !_theResult____h538816[28] && + !_theResult____h538816[27] && + !_theResult____h538816[26] && + !_theResult____h538816[25] && + !_theResult____h538816[24] && + !_theResult____h538816[23] && + !_theResult____h538816[22] && + !_theResult____h538816[21] && + !_theResult____h538816[20] && + !_theResult____h538816[19] && + !_theResult____h538816[18] && + !_theResult____h538816[17] && + !_theResult____h538816[16] && + !_theResult____h538816[15] && + !_theResult____h538816[14] && + !_theResult____h538816[13] && + !_theResult____h538816[12] && + !_theResult____h538816[11] && + !_theResult____h538816[10] && + !_theResult____h538816[9] && + !_theResult____h538816[8] && + !_theResult____h538816[7] && + !_theResult____h538816[6] && + !_theResult____h538816[5] && + !_theResult____h538816[4] && + !_theResult____h538816[3] && + !_theResult____h538816[2] && + !_theResult____h538816[1] && + !_theResult____h538816[0]) ? + _theResult____h538816 : + _theResult___snd__h547092 ; + assign _theResult___snd__h547092 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h547117 = - _theResult____h538818 << + assign _theResult___snd__h547115 = + _theResult____h538816 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 ; - assign _theResult___snd__h555833 = + assign _theResult___snd__h555831 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h555847 : - _theResult___snd__h537430 ; - assign _theResult___snd__h555847 = + _theResult___snd__h555845 : + _theResult___snd__h537428 ; + assign _theResult___snd__h555845 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518617 : - _theResult___snd__h555853 ; - assign _theResult___snd__h555853 = + sfd__h518615 : + _theResult___snd__h555851 ; + assign _theResult___snd__h555851 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h555871 = - sfd__h518617 << + assign _theResult___snd__h555869 = + sfd__h518615 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 ; - assign _theResult___snd__h576629 = + assign _theResult___snd__h576627 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h576638 : - _theResult___snd__h576631 ; - assign _theResult___snd__h576631 = + _theResult___snd__h576636 : + _theResult___snd__h576629 ; + assign _theResult___snd__h576629 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ; - assign _theResult___snd__h576638 = + assign _theResult___snd__h576636 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557818 : - _theResult___snd__h576644 ; - assign _theResult___snd__h576644 = + sfd__h557816 : + _theResult___snd__h576642 ; + assign _theResult___snd__h576642 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h576667 = - sfd__h557818 << + assign _theResult___snd__h576665 = + sfd__h557816 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 ; - assign _theResult___snd__h586266 = { _theResult____h578019[55:0], 1'd0 } ; - assign _theResult___snd__h586277 = - (!_theResult____h578019[56] && _theResult____h578019[55]) ? - _theResult___snd__h586279 : - _theResult___snd__h586289 ; - assign _theResult___snd__h586279 = { _theResult____h578019[54:0], 2'd0 } ; - assign _theResult___snd__h586289 = - (!_theResult____h578019[56] && !_theResult____h578019[55] && - !_theResult____h578019[54] && - !_theResult____h578019[53] && - !_theResult____h578019[52] && - !_theResult____h578019[51] && - !_theResult____h578019[50] && - !_theResult____h578019[49] && - !_theResult____h578019[48] && - !_theResult____h578019[47] && - !_theResult____h578019[46] && - !_theResult____h578019[45] && - !_theResult____h578019[44] && - !_theResult____h578019[43] && - !_theResult____h578019[42] && - !_theResult____h578019[41] && - !_theResult____h578019[40] && - !_theResult____h578019[39] && - !_theResult____h578019[38] && - !_theResult____h578019[37] && - !_theResult____h578019[36] && - !_theResult____h578019[35] && - !_theResult____h578019[34] && - !_theResult____h578019[33] && - !_theResult____h578019[32] && - !_theResult____h578019[31] && - !_theResult____h578019[30] && - !_theResult____h578019[29] && - !_theResult____h578019[28] && - !_theResult____h578019[27] && - !_theResult____h578019[26] && - !_theResult____h578019[25] && - !_theResult____h578019[24] && - !_theResult____h578019[23] && - !_theResult____h578019[22] && - !_theResult____h578019[21] && - !_theResult____h578019[20] && - !_theResult____h578019[19] && - !_theResult____h578019[18] && - !_theResult____h578019[17] && - !_theResult____h578019[16] && - !_theResult____h578019[15] && - !_theResult____h578019[14] && - !_theResult____h578019[13] && - !_theResult____h578019[12] && - !_theResult____h578019[11] && - !_theResult____h578019[10] && - !_theResult____h578019[9] && - !_theResult____h578019[8] && - !_theResult____h578019[7] && - !_theResult____h578019[6] && - !_theResult____h578019[5] && - !_theResult____h578019[4] && - !_theResult____h578019[3] && - !_theResult____h578019[2] && - !_theResult____h578019[1] && - !_theResult____h578019[0]) ? - _theResult____h578019 : - _theResult___snd__h586295 ; - assign _theResult___snd__h586295 = + assign _theResult___snd__h586264 = { _theResult____h578017[55:0], 1'd0 } ; + assign _theResult___snd__h586275 = + (!_theResult____h578017[56] && _theResult____h578017[55]) ? + _theResult___snd__h586277 : + _theResult___snd__h586287 ; + assign _theResult___snd__h586277 = { _theResult____h578017[54:0], 2'd0 } ; + assign _theResult___snd__h586287 = + (!_theResult____h578017[56] && !_theResult____h578017[55] && + !_theResult____h578017[54] && + !_theResult____h578017[53] && + !_theResult____h578017[52] && + !_theResult____h578017[51] && + !_theResult____h578017[50] && + !_theResult____h578017[49] && + !_theResult____h578017[48] && + !_theResult____h578017[47] && + !_theResult____h578017[46] && + !_theResult____h578017[45] && + !_theResult____h578017[44] && + !_theResult____h578017[43] && + !_theResult____h578017[42] && + !_theResult____h578017[41] && + !_theResult____h578017[40] && + !_theResult____h578017[39] && + !_theResult____h578017[38] && + !_theResult____h578017[37] && + !_theResult____h578017[36] && + !_theResult____h578017[35] && + !_theResult____h578017[34] && + !_theResult____h578017[33] && + !_theResult____h578017[32] && + !_theResult____h578017[31] && + !_theResult____h578017[30] && + !_theResult____h578017[29] && + !_theResult____h578017[28] && + !_theResult____h578017[27] && + !_theResult____h578017[26] && + !_theResult____h578017[25] && + !_theResult____h578017[24] && + !_theResult____h578017[23] && + !_theResult____h578017[22] && + !_theResult____h578017[21] && + !_theResult____h578017[20] && + !_theResult____h578017[19] && + !_theResult____h578017[18] && + !_theResult____h578017[17] && + !_theResult____h578017[16] && + !_theResult____h578017[15] && + !_theResult____h578017[14] && + !_theResult____h578017[13] && + !_theResult____h578017[12] && + !_theResult____h578017[11] && + !_theResult____h578017[10] && + !_theResult____h578017[9] && + !_theResult____h578017[8] && + !_theResult____h578017[7] && + !_theResult____h578017[6] && + !_theResult____h578017[5] && + !_theResult____h578017[4] && + !_theResult____h578017[3] && + !_theResult____h578017[2] && + !_theResult____h578017[1] && + !_theResult____h578017[0]) ? + _theResult____h578017 : + _theResult___snd__h586293 ; + assign _theResult___snd__h586293 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h586318 = - _theResult____h578019 << + assign _theResult___snd__h586316 = + _theResult____h578017 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 ; - assign _theResult___snd__h595034 = + assign _theResult___snd__h595032 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h595048 : - _theResult___snd__h576631 ; - assign _theResult___snd__h595048 = + _theResult___snd__h595046 : + _theResult___snd__h576629 ; + assign _theResult___snd__h595046 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557818 : - _theResult___snd__h595054 ; - assign _theResult___snd__h595054 = + sfd__h557816 : + _theResult___snd__h595052 ; + assign _theResult___snd__h595052 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h595072 = - sfd__h557818 << + assign _theResult___snd__h595070 = + sfd__h557816 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648 ; - assign _theResult___snd__h600262 = - b__h599840[63] ? b___1__h600311 : b__h599840 ; - assign _theResult___snd_fst_exp__h360595 = + assign _theResult___snd__h600260 = + b__h599838[63] ? b___1__h600309 : b__h599838 ; + assign _theResult___snd_fst_exp__h360593 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_exp__h352010 : - _theResult___fst_exp__h360592 ; - assign _theResult___snd_fst_exp__h378415 = + _theResult___fst_exp__h352008 : + _theResult___fst_exp__h360590 ; + assign _theResult___snd_fst_exp__h378413 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_exp__h369776 : - _theResult___fst_exp__h378412 ; - assign _theResult___snd_fst_exp__h406285 = + _theResult___fst_exp__h369774 : + _theResult___fst_exp__h378410 ; + assign _theResult___snd_fst_exp__h406283 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_exp__h397700 : - _theResult___fst_exp__h406282 ; - assign _theResult___snd_fst_exp__h424105 = + _theResult___fst_exp__h397698 : + _theResult___fst_exp__h406280 ; + assign _theResult___snd_fst_exp__h424103 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_exp__h415466 : - _theResult___fst_exp__h424102 ; - assign _theResult___snd_fst_exp__h451973 = + _theResult___fst_exp__h415464 : + _theResult___fst_exp__h424100 ; + assign _theResult___snd_fst_exp__h451971 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_exp__h443388 : - _theResult___fst_exp__h451970 ; - assign _theResult___snd_fst_exp__h469793 = + _theResult___fst_exp__h443386 : + _theResult___fst_exp__h451968 ; + assign _theResult___snd_fst_exp__h469791 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_exp__h461154 : - _theResult___fst_exp__h469790 ; - assign _theResult___snd_fst_exp__h499437 = + _theResult___fst_exp__h461152 : + _theResult___fst_exp__h469788 ; + assign _theResult___snd_fst_exp__h499435 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 11'd0 : - _theResult___fst_exp__h499434 ; - assign _theResult___snd_fst_exp__h517872 = + _theResult___fst_exp__h499432 ; + assign _theResult___snd_fst_exp__h517870 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_exp__h509085 : - _theResult___fst_exp__h517869 ; - assign _theResult___snd_fst_exp__h538238 = + _theResult___fst_exp__h509083 : + _theResult___fst_exp__h517867 ; + assign _theResult___snd_fst_exp__h538236 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 11'd0 : - _theResult___fst_exp__h538235 ; - assign _theResult___snd_fst_exp__h556673 = + _theResult___fst_exp__h538233 ; + assign _theResult___snd_fst_exp__h556671 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_exp__h547886 : - _theResult___fst_exp__h556670 ; - assign _theResult___snd_fst_exp__h577439 = + _theResult___fst_exp__h547884 : + _theResult___fst_exp__h556668 ; + assign _theResult___snd_fst_exp__h577437 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 11'd0 : - _theResult___fst_exp__h577436 ; - assign _theResult___snd_fst_exp__h595874 = + _theResult___fst_exp__h577434 ; + assign _theResult___snd_fst_exp__h595872 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_exp__h587087 : - _theResult___fst_exp__h595871 ; - assign _theResult___snd_fst_sfd__h335647 = + _theResult___fst_exp__h587085 : + _theResult___fst_exp__h595869 ; + assign _theResult___snd_fst_sfd__h335645 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h360596 = + assign _theResult___snd_fst_sfd__h360594 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_sfd__h352011 : - _theResult___fst_sfd__h360593 ; - assign _theResult___snd_fst_sfd__h378416 = + _theResult___fst_sfd__h352009 : + _theResult___fst_sfd__h360591 ; + assign _theResult___snd_fst_sfd__h378414 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_sfd__h369777 : - _theResult___fst_sfd__h378413 ; - assign _theResult___snd_fst_sfd__h381342 = + _theResult___fst_sfd__h369775 : + _theResult___fst_sfd__h378411 ; + assign _theResult___snd_fst_sfd__h381340 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h406286 = + assign _theResult___snd_fst_sfd__h406284 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_sfd__h397701 : - _theResult___fst_sfd__h406283 ; - assign _theResult___snd_fst_sfd__h424106 = + _theResult___fst_sfd__h397699 : + _theResult___fst_sfd__h406281 ; + assign _theResult___snd_fst_sfd__h424104 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_sfd__h415467 : - _theResult___fst_sfd__h424103 ; - assign _theResult___snd_fst_sfd__h427030 = + _theResult___fst_sfd__h415465 : + _theResult___fst_sfd__h424101 ; + assign _theResult___snd_fst_sfd__h427028 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h451974 = + assign _theResult___snd_fst_sfd__h451972 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_sfd__h443389 : - _theResult___fst_sfd__h451971 ; - assign _theResult___snd_fst_sfd__h469794 = + _theResult___fst_sfd__h443387 : + _theResult___fst_sfd__h451969 ; + assign _theResult___snd_fst_sfd__h469792 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_sfd__h461155 : - _theResult___fst_sfd__h469791 ; - assign _theResult___snd_fst_sfd__h479629 = + _theResult___fst_sfd__h461153 : + _theResult___fst_sfd__h469789 ; + assign _theResult___snd_fst_sfd__h479627 = (coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h479378 ; - assign _theResult___snd_fst_sfd__h499438 = + out___1_sfd__h479376 ; + assign _theResult___snd_fst_sfd__h499436 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 52'd0 : - _theResult___fst_sfd__h499435 ; - assign _theResult___snd_fst_sfd__h517873 = + _theResult___fst_sfd__h499433 ; + assign _theResult___snd_fst_sfd__h517871 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_sfd__h509086 : - _theResult___fst_sfd__h517870 ; - assign _theResult___snd_fst_sfd__h518571 = + _theResult___fst_sfd__h509084 : + _theResult___fst_sfd__h517868 ; + assign _theResult___snd_fst_sfd__h518569 = (coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h518320 ; - assign _theResult___snd_fst_sfd__h538239 = + out___1_sfd__h518318 ; + assign _theResult___snd_fst_sfd__h538237 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 52'd0 : - _theResult___fst_sfd__h538236 ; - assign _theResult___snd_fst_sfd__h556674 = + _theResult___fst_sfd__h538234 ; + assign _theResult___snd_fst_sfd__h556672 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_sfd__h547887 : - _theResult___fst_sfd__h556671 ; - assign _theResult___snd_fst_sfd__h557772 = + _theResult___fst_sfd__h547885 : + _theResult___fst_sfd__h556669 ; + assign _theResult___snd_fst_sfd__h557770 = (coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h557521 ; - assign _theResult___snd_fst_sfd__h577440 = + out___1_sfd__h557519 ; + assign _theResult___snd_fst_sfd__h577438 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 52'd0 : - _theResult___fst_sfd__h577437 ; - assign _theResult___snd_fst_sfd__h595875 = + _theResult___fst_sfd__h577435 ; + assign _theResult___snd_fst_sfd__h595873 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_sfd__h587088 : - _theResult___fst_sfd__h595872 ; - assign a___1__h599980 = + _theResult___fst_sfd__h587086 : + _theResult___fst_sfd__h595870 ; + assign a___1__h599978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 } ; - assign a___1__h600266 = 64'd0 - a__h599839 ; - assign a__h599839 = + assign a___1__h600264 = 64'd0 - a__h599837 ; + assign a__h599837 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h599980 : + a___1__h599978 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h599981 = + assign b___1__h599979 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h600311 = 64'd0 - b__h599840 ; - assign b__h599840 = + assign b___1__h600309 = 64'd0 - b__h599838 ; + assign b__h599838 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h599981 : + b___1__h599979 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h694791 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h694994 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h692189 = - commitStage_commitTrap[4] ? i__h692364 : i__h692204 ; + assign base__h694789 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h694992 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h692187 = + commitStage_commitTrap[4] ? i__h692362 : i__h692202 ; assign coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27353,7 +27353,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h252026 ; + y__h252024 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 || @@ -27707,44 +27707,44 @@ module mkCore(CLK, assign csrf_prv_reg_read__2633_ULT_IF_fetchStage_pipe_ETC___d12871 = csrf_prv_reg < IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[9:8] ; - assign data72481_BITS_31_TO_0__q5 = data__h472481[31:0] ; - assign data___1__h472207 = + assign data72479_BITS_31_TO_0__q5 = data__h472479[31:0] ; + assign data___1__h472205 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 } ; - assign data___1__h473015 = - { {32{data72481_BITS_31_TO_0__q5[31]}}, - data72481_BITS_31_TO_0__q5 } ; - assign data__h472481 = + assign data___1__h473013 = + { {32{data72479_BITS_31_TO_0__q5[31]}}, + data72479_BITS_31_TO_0__q5 } ; + assign data__h472479 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h472395 : - x_remainder__h472396 ; - assign din_inc___2_exp__h378446 = _theResult___fst_exp__h351413 + 8'd1 ; - assign din_inc___2_exp__h378470 = _theResult___fst_exp__h360069 + 8'd1 ; - assign din_inc___2_exp__h378500 = _theResult___fst_exp__h369179 + 8'd1 ; - assign din_inc___2_exp__h378524 = _theResult___fst_exp__h377864 + 8'd1 ; - assign din_inc___2_exp__h424136 = _theResult___fst_exp__h397103 + 8'd1 ; - assign din_inc___2_exp__h424160 = _theResult___fst_exp__h405759 + 8'd1 ; - assign din_inc___2_exp__h424190 = _theResult___fst_exp__h414869 + 8'd1 ; - assign din_inc___2_exp__h424214 = _theResult___fst_exp__h423554 + 8'd1 ; - assign din_inc___2_exp__h469824 = _theResult___fst_exp__h442791 + 8'd1 ; - assign din_inc___2_exp__h469848 = _theResult___fst_exp__h451447 + 8'd1 ; - assign din_inc___2_exp__h469878 = _theResult___fst_exp__h460557 + 8'd1 ; - assign din_inc___2_exp__h469902 = _theResult___fst_exp__h469242 + 8'd1 ; - assign din_inc___2_exp__h517926 = _theResult___fst_exp__h498676 + 11'd1 ; - assign din_inc___2_exp__h517961 = _theResult___fst_exp__h508253 + 11'd1 ; - assign din_inc___2_exp__h517987 = _theResult___fst_exp__h517086 + 11'd1 ; - assign din_inc___2_exp__h556727 = _theResult___fst_exp__h537477 + 11'd1 ; - assign din_inc___2_exp__h556762 = _theResult___fst_exp__h547054 + 11'd1 ; - assign din_inc___2_exp__h556788 = _theResult___fst_exp__h555887 + 11'd1 ; - assign din_inc___2_exp__h595928 = _theResult___fst_exp__h576678 + 11'd1 ; - assign din_inc___2_exp__h595963 = _theResult___fst_exp__h586255 + 11'd1 ; - assign din_inc___2_exp__h595989 = _theResult___fst_exp__h595088 + 11'd1 ; - assign enabled_ints___1__h645895 = pend_ints__h645396 & y__h645907 ; - assign enabled_ints__h645942 = - pend_ints__h645396 & - { r1__read_BITS_12_TO_0___h645918, csrf_mideleg_1_0_reg } ; - assign fcsr_csr__read__h606148 = { 56'd0, x__h608822 } ; + x_quotient__h472393 : + x_remainder__h472394 ; + assign din_inc___2_exp__h378444 = _theResult___fst_exp__h351411 + 8'd1 ; + assign din_inc___2_exp__h378468 = _theResult___fst_exp__h360067 + 8'd1 ; + assign din_inc___2_exp__h378498 = _theResult___fst_exp__h369177 + 8'd1 ; + assign din_inc___2_exp__h378522 = _theResult___fst_exp__h377862 + 8'd1 ; + assign din_inc___2_exp__h424134 = _theResult___fst_exp__h397101 + 8'd1 ; + assign din_inc___2_exp__h424158 = _theResult___fst_exp__h405757 + 8'd1 ; + assign din_inc___2_exp__h424188 = _theResult___fst_exp__h414867 + 8'd1 ; + assign din_inc___2_exp__h424212 = _theResult___fst_exp__h423552 + 8'd1 ; + assign din_inc___2_exp__h469822 = _theResult___fst_exp__h442789 + 8'd1 ; + assign din_inc___2_exp__h469846 = _theResult___fst_exp__h451445 + 8'd1 ; + assign din_inc___2_exp__h469876 = _theResult___fst_exp__h460555 + 8'd1 ; + assign din_inc___2_exp__h469900 = _theResult___fst_exp__h469240 + 8'd1 ; + assign din_inc___2_exp__h517924 = _theResult___fst_exp__h498674 + 11'd1 ; + assign din_inc___2_exp__h517959 = _theResult___fst_exp__h508251 + 11'd1 ; + assign din_inc___2_exp__h517985 = _theResult___fst_exp__h517084 + 11'd1 ; + assign din_inc___2_exp__h556725 = _theResult___fst_exp__h537475 + 11'd1 ; + assign din_inc___2_exp__h556760 = _theResult___fst_exp__h547052 + 11'd1 ; + assign din_inc___2_exp__h556786 = _theResult___fst_exp__h555885 + 11'd1 ; + assign din_inc___2_exp__h595926 = _theResult___fst_exp__h576676 + 11'd1 ; + assign din_inc___2_exp__h595961 = _theResult___fst_exp__h586253 + 11'd1 ; + assign din_inc___2_exp__h595987 = _theResult___fst_exp__h595086 + 11'd1 ; + assign enabled_ints___1__h645893 = pend_ints__h645394 & y__h645905 ; + assign enabled_ints__h645940 = + pend_ints__h645394 & + { r1__read_BITS_12_TO_0___h645916, csrf_mideleg_1_0_reg } ; + assign fcsr_csr__read__h606149 = { 56'd0, x__h608823 } ; assign fetchStage_RDY_pipelines_0_first__2602_AND_NOT_ETC___d13210 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -27841,8 +27841,8 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d12869 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h649453 != 5'd0 || - imm__h649454 != 32'd0) && + rs1__h649451 != 5'd0 || + imm__h649452 != 32'd0) && IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 = @@ -27969,82 +27969,82 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13709 ; - assign fflags__h705627 = + assign fflags__h705625 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_fst__h705687 : + y_avValue_snd_fst__h705685 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 ; - assign fflags_csr__read__h606123 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h606134 = { 61'd0, csrf_frm_reg } ; - assign guard__h343312 = - { IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21[1], - { sfdin__h351407[32:0], 23'd0 } != 56'd0 } ; - assign guard__h352021 = - { IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23[1], - { _theResult___snd__h360020[32:0], 23'd0 } != 56'd0 } ; - assign guard__h360951 = - { IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31[1], - { sfdin__h369173[32:0], 23'd0 } != 56'd0 } ; - assign guard__h361549 = x__h361651 != 57'd0 ; - assign guard__h369787 = - { IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36[1], - { _theResult___snd__h377810[32:0], 23'd0 } != 56'd0 } ; - assign guard__h389004 = - { IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56[1], - { sfdin__h397097[32:0], 23'd0 } != 56'd0 } ; - assign guard__h397711 = - { IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58[1], - { _theResult___snd__h405710[32:0], 23'd0 } != 56'd0 } ; - assign guard__h406641 = - { IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66[1], - { sfdin__h414863[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407239 = x__h407341 != 57'd0 ; - assign guard__h415477 = - { IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71[1], - { _theResult___snd__h423500[32:0], 23'd0 } != 56'd0 } ; - assign guard__h434692 = - { IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91[1], - { sfdin__h442785[32:0], 23'd0 } != 56'd0 } ; - assign guard__h443399 = - { IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93[1], - { _theResult___snd__h451398[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452329 = - { IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101[1], - { sfdin__h460551[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452927 = x__h453029 != 57'd0 ; - assign guard__h461165 = - { IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106[1], - { _theResult___snd__h469188[32:0], 23'd0 } != 56'd0 } ; - assign guard__h490715 = - { IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h498627[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500027 = - { IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h508247[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500625 = x__h500725 != 57'd0 ; - assign guard__h509096 = - { IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h517032[3:0], 52'd0 } != 56'd0 } ; - assign guard__h529516 = - { IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h537428[3:0], 52'd0 } != 56'd0 } ; - assign guard__h538828 = - { IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h547048[3:0], 52'd0 } != 56'd0 } ; - assign guard__h539426 = x__h539526 != 57'd0 ; - assign guard__h547897 = - { IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h555833[3:0], 52'd0 } != 56'd0 } ; - assign guard__h568717 = - { IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h576629[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578029 = - { IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h586249[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578627 = x__h578727 != 57'd0 ; - assign guard__h587098 = - { IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h595034[3:0], 52'd0 } != 56'd0 } ; - assign idx__h675479 = + assign fflags_csr__read__h606124 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h606135 = { 61'd0, csrf_frm_reg } ; + assign guard__h343310 = + { IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21[1], + { sfdin__h351405[32:0], 23'd0 } != 56'd0 } ; + assign guard__h352019 = + { IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23[1], + { _theResult___snd__h360018[32:0], 23'd0 } != 56'd0 } ; + assign guard__h360949 = + { IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31[1], + { sfdin__h369171[32:0], 23'd0 } != 56'd0 } ; + assign guard__h361547 = x__h361649 != 57'd0 ; + assign guard__h369785 = + { IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36[1], + { _theResult___snd__h377808[32:0], 23'd0 } != 56'd0 } ; + assign guard__h389002 = + { IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56[1], + { sfdin__h397095[32:0], 23'd0 } != 56'd0 } ; + assign guard__h397709 = + { IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58[1], + { _theResult___snd__h405708[32:0], 23'd0 } != 56'd0 } ; + assign guard__h406639 = + { IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66[1], + { sfdin__h414861[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407237 = x__h407339 != 57'd0 ; + assign guard__h415475 = + { IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71[1], + { _theResult___snd__h423498[32:0], 23'd0 } != 56'd0 } ; + assign guard__h434690 = + { IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91[1], + { sfdin__h442783[32:0], 23'd0 } != 56'd0 } ; + assign guard__h443397 = + { IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93[1], + { _theResult___snd__h451396[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452327 = + { IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101[1], + { sfdin__h460549[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452925 = x__h453027 != 57'd0 ; + assign guard__h461163 = + { IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106[1], + { _theResult___snd__h469186[32:0], 23'd0 } != 56'd0 } ; + assign guard__h490713 = + { IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h498625[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500025 = + { IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h508245[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500623 = x__h500723 != 57'd0 ; + assign guard__h509094 = + { IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h517030[3:0], 52'd0 } != 56'd0 } ; + assign guard__h529514 = + { IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h537426[3:0], 52'd0 } != 56'd0 } ; + assign guard__h538826 = + { IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h547046[3:0], 52'd0 } != 56'd0 } ; + assign guard__h539424 = x__h539524 != 57'd0 ; + assign guard__h547895 = + { IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h555831[3:0], 52'd0 } != 56'd0 } ; + assign guard__h568715 = + { IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h576627[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578027 = + { IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h586247[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578625 = x__h578725 != 57'd0 ; + assign guard__h587096 = + { IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h595032[3:0], 52'd0 } != 56'd0 } ; + assign idx__h675477 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -28052,26 +28052,26 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13523) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign imm__h649454 = + assign imm__h649452 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h661045 = + assign k__h661043 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign mcause_csr__read__h607795 = - { r1__read__h610362, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h607540 = - { r1__read__h610349, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h607140 = - { r1__read__h610185, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h607235 = - { r1__read__h610202, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h607366 = - { r1__read__h610226, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h608035 = - { r1__read__h610368, csrf_software_int_pend_vec_0 } ; + assign mcause_csr__read__h607796 = + { r1__read__h610363, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h607541 = + { r1__read__h610350, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h607141 = + { r1__read__h610186, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h607236 = + { r1__read__h610203, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h607367 = + { r1__read__h610227, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h608036 = + { r1__read__h610369, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28148,40 +28148,40 @@ module mkCore(CLK, !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; assign msip__h75409 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h606992 = { r1__read__h610048, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h607448 = - { r1__read__h610344, csrf_mtvec_mode_low_reg } ; - assign n___1__h195752 = + assign mstatus_csr__read__h606993 = { r1__read__h610049, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h607449 = + { r1__read__h610345, csrf_mtvec_mode_low_reg } ; + assign n___1__h195750 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h194349[63:56], + x__h194347[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h194349[55:48], + x__h194347[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h194349[47:40], + x__h194347[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h194349[39:32], + x__h194347[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h194349[31:24], + x__h194347[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h194349[23:16], + x__h194347[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h194349[15:8], + x__h194347[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h194349[7:0] } ; - assign n__read__h608139 = + x__h194347[7:0] } ; + assign n__read__h608140 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h608330 = + assign n__read__h608331 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -28192,250 +28192,250 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h703199 = + assign n__read__h703197 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h294022 = + assign next_deqP___1__h294020 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h302018 = + assign next_deqP___1__h302016 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h308299 = + assign next_deqP___1__h308297 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h316153 = + assign next_deqP___1__h316151 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h326210 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h329435 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h702542 = + assign next_deqP___1__h326208 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h329433 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h702540 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign out___1_sfd__h479378 = + assign out___1_sfd__h479376 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ; - assign out___1_sfd__h518320 = + assign out___1_sfd__h518318 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ; - assign out___1_sfd__h557521 = + assign out___1_sfd__h557519 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ; - assign out_exp__h351932 = - sfdin__h351407[34] ? - _theResult___exp__h351929 : - _theResult___fst_exp__h351413 ; - assign out_exp__h360514 = - _theResult___snd__h360020[34] ? - _theResult___exp__h360511 : - _theResult___fst_exp__h360069 ; - assign out_exp__h369698 = - sfdin__h369173[34] ? - _theResult___exp__h369695 : - _theResult___fst_exp__h369179 ; - assign out_exp__h378334 = - _theResult___snd__h377810[34] ? - _theResult___exp__h378331 : - _theResult___fst_exp__h377864 ; - assign out_exp__h397622 = - sfdin__h397097[34] ? - _theResult___exp__h397619 : - _theResult___fst_exp__h397103 ; - assign out_exp__h406204 = - _theResult___snd__h405710[34] ? - _theResult___exp__h406201 : - _theResult___fst_exp__h405759 ; - assign out_exp__h415388 = - sfdin__h414863[34] ? - _theResult___exp__h415385 : - _theResult___fst_exp__h414869 ; - assign out_exp__h424024 = - _theResult___snd__h423500[34] ? - _theResult___exp__h424021 : - _theResult___fst_exp__h423554 ; - assign out_exp__h443310 = - sfdin__h442785[34] ? - _theResult___exp__h443307 : - _theResult___fst_exp__h442791 ; - assign out_exp__h451892 = - _theResult___snd__h451398[34] ? - _theResult___exp__h451889 : - _theResult___fst_exp__h451447 ; - assign out_exp__h461076 = - sfdin__h460551[34] ? - _theResult___exp__h461073 : - _theResult___fst_exp__h460557 ; - assign out_exp__h469712 = - _theResult___snd__h469188[34] ? - _theResult___exp__h469709 : - _theResult___fst_exp__h469242 ; - assign out_exp__h499334 = - _theResult___snd__h498627[5] ? - _theResult___exp__h499331 : - _theResult___fst_exp__h498676 ; - assign out_exp__h508985 = - sfdin__h508247[5] ? - _theResult___exp__h508982 : - _theResult___fst_exp__h508253 ; - assign out_exp__h517769 = - _theResult___snd__h517032[5] ? - _theResult___exp__h517766 : - _theResult___fst_exp__h517086 ; - assign out_exp__h538135 = - _theResult___snd__h537428[5] ? - _theResult___exp__h538132 : - _theResult___fst_exp__h537477 ; - assign out_exp__h547786 = - sfdin__h547048[5] ? - _theResult___exp__h547783 : - _theResult___fst_exp__h547054 ; - assign out_exp__h556570 = - _theResult___snd__h555833[5] ? - _theResult___exp__h556567 : - _theResult___fst_exp__h555887 ; - assign out_exp__h577336 = - _theResult___snd__h576629[5] ? - _theResult___exp__h577333 : - _theResult___fst_exp__h576678 ; - assign out_exp__h586987 = - sfdin__h586249[5] ? - _theResult___exp__h586984 : - _theResult___fst_exp__h586255 ; - assign out_exp__h595771 = - _theResult___snd__h595034[5] ? - _theResult___exp__h595768 : - _theResult___fst_exp__h595088 ; - assign out_f_exp__h378710 = - (_theResult___exp__h378433 == 8'd255 && - _theResult___sfd__h378434 != 23'd0 || + assign out_exp__h351930 = + sfdin__h351405[34] ? + _theResult___exp__h351927 : + _theResult___fst_exp__h351411 ; + assign out_exp__h360512 = + _theResult___snd__h360018[34] ? + _theResult___exp__h360509 : + _theResult___fst_exp__h360067 ; + assign out_exp__h369696 = + sfdin__h369171[34] ? + _theResult___exp__h369693 : + _theResult___fst_exp__h369177 ; + assign out_exp__h378332 = + _theResult___snd__h377808[34] ? + _theResult___exp__h378329 : + _theResult___fst_exp__h377862 ; + assign out_exp__h397620 = + sfdin__h397095[34] ? + _theResult___exp__h397617 : + _theResult___fst_exp__h397101 ; + assign out_exp__h406202 = + _theResult___snd__h405708[34] ? + _theResult___exp__h406199 : + _theResult___fst_exp__h405757 ; + assign out_exp__h415386 = + sfdin__h414861[34] ? + _theResult___exp__h415383 : + _theResult___fst_exp__h414867 ; + assign out_exp__h424022 = + _theResult___snd__h423498[34] ? + _theResult___exp__h424019 : + _theResult___fst_exp__h423552 ; + assign out_exp__h443308 = + sfdin__h442783[34] ? + _theResult___exp__h443305 : + _theResult___fst_exp__h442789 ; + assign out_exp__h451890 = + _theResult___snd__h451396[34] ? + _theResult___exp__h451887 : + _theResult___fst_exp__h451445 ; + assign out_exp__h461074 = + sfdin__h460549[34] ? + _theResult___exp__h461071 : + _theResult___fst_exp__h460555 ; + assign out_exp__h469710 = + _theResult___snd__h469186[34] ? + _theResult___exp__h469707 : + _theResult___fst_exp__h469240 ; + assign out_exp__h499332 = + _theResult___snd__h498625[5] ? + _theResult___exp__h499329 : + _theResult___fst_exp__h498674 ; + assign out_exp__h508983 = + sfdin__h508245[5] ? + _theResult___exp__h508980 : + _theResult___fst_exp__h508251 ; + assign out_exp__h517767 = + _theResult___snd__h517030[5] ? + _theResult___exp__h517764 : + _theResult___fst_exp__h517084 ; + assign out_exp__h538133 = + _theResult___snd__h537426[5] ? + _theResult___exp__h538130 : + _theResult___fst_exp__h537475 ; + assign out_exp__h547784 = + sfdin__h547046[5] ? + _theResult___exp__h547781 : + _theResult___fst_exp__h547052 ; + assign out_exp__h556568 = + _theResult___snd__h555831[5] ? + _theResult___exp__h556565 : + _theResult___fst_exp__h555885 ; + assign out_exp__h577334 = + _theResult___snd__h576627[5] ? + _theResult___exp__h577331 : + _theResult___fst_exp__h576676 ; + assign out_exp__h586985 = + sfdin__h586247[5] ? + _theResult___exp__h586982 : + _theResult___fst_exp__h586253 ; + assign out_exp__h595769 = + _theResult___snd__h595032[5] ? + _theResult___exp__h595766 : + _theResult___fst_exp__h595086 ; + assign out_f_exp__h378708 = + (_theResult___exp__h378431 == 8'd255 && + _theResult___sfd__h378432 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378424 ; - assign out_f_exp__h424400 = - (_theResult___exp__h424123 == 8'd255 && - _theResult___sfd__h424124 != 23'd0 || + _theResult___fst_exp__h378422 ; + assign out_f_exp__h424398 = + (_theResult___exp__h424121 == 8'd255 && + _theResult___sfd__h424122 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424114 ; - assign out_f_exp__h470088 = - (_theResult___exp__h469811 == 8'd255 && - _theResult___sfd__h469812 != 23'd0 || + _theResult___fst_exp__h424112 ; + assign out_f_exp__h470086 = + (_theResult___exp__h469809 == 8'd255 && + _theResult___sfd__h469810 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469802 ; - assign out_f_sfd__h378711 = - (_theResult___exp__h378433 == 8'd255 && - _theResult___sfd__h378434 != 23'd0) ? + _theResult___fst_exp__h469800 ; + assign out_f_sfd__h378709 = + (_theResult___exp__h378431 == 8'd255 && + _theResult___sfd__h378432 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h378434 ; - assign out_f_sfd__h424401 = - (_theResult___exp__h424123 == 8'd255 && - _theResult___sfd__h424124 != 23'd0) ? + _theResult___sfd__h378432 ; + assign out_f_sfd__h424399 = + (_theResult___exp__h424121 == 8'd255 && + _theResult___sfd__h424122 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h424124 ; - assign out_f_sfd__h470089 = - (_theResult___exp__h469811 == 8'd255 && - _theResult___sfd__h469812 != 23'd0) ? + _theResult___sfd__h424122 ; + assign out_f_sfd__h470087 = + (_theResult___exp__h469809 == 8'd255 && + _theResult___sfd__h469810 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h469812 ; - assign out_sfd__h351933 = - sfdin__h351407[34] ? - _theResult___sfd__h351930 : - sfdin__h351407[56:34] ; - assign out_sfd__h360515 = - _theResult___snd__h360020[34] ? - _theResult___sfd__h360512 : - _theResult___snd__h360020[56:34] ; - assign out_sfd__h369699 = - sfdin__h369173[34] ? - _theResult___sfd__h369696 : - sfdin__h369173[56:34] ; - assign out_sfd__h378335 = - _theResult___snd__h377810[34] ? - _theResult___sfd__h378332 : - _theResult___snd__h377810[56:34] ; - assign out_sfd__h397623 = - sfdin__h397097[34] ? - _theResult___sfd__h397620 : - sfdin__h397097[56:34] ; - assign out_sfd__h406205 = - _theResult___snd__h405710[34] ? - _theResult___sfd__h406202 : - _theResult___snd__h405710[56:34] ; - assign out_sfd__h415389 = - sfdin__h414863[34] ? - _theResult___sfd__h415386 : - sfdin__h414863[56:34] ; - assign out_sfd__h424025 = - _theResult___snd__h423500[34] ? - _theResult___sfd__h424022 : - _theResult___snd__h423500[56:34] ; - assign out_sfd__h443311 = - sfdin__h442785[34] ? - _theResult___sfd__h443308 : - sfdin__h442785[56:34] ; - assign out_sfd__h451893 = - _theResult___snd__h451398[34] ? - _theResult___sfd__h451890 : - _theResult___snd__h451398[56:34] ; - assign out_sfd__h461077 = - sfdin__h460551[34] ? - _theResult___sfd__h461074 : - sfdin__h460551[56:34] ; - assign out_sfd__h469713 = - _theResult___snd__h469188[34] ? - _theResult___sfd__h469710 : - _theResult___snd__h469188[56:34] ; - assign out_sfd__h499335 = - _theResult___snd__h498627[5] ? - _theResult___sfd__h499332 : - _theResult___snd__h498627[56:5] ; - assign out_sfd__h508986 = - sfdin__h508247[5] ? - _theResult___sfd__h508983 : - sfdin__h508247[56:5] ; - assign out_sfd__h517770 = - _theResult___snd__h517032[5] ? - _theResult___sfd__h517767 : - _theResult___snd__h517032[56:5] ; - assign out_sfd__h538136 = - _theResult___snd__h537428[5] ? - _theResult___sfd__h538133 : - _theResult___snd__h537428[56:5] ; - assign out_sfd__h547787 = - sfdin__h547048[5] ? - _theResult___sfd__h547784 : - sfdin__h547048[56:5] ; - assign out_sfd__h556571 = - _theResult___snd__h555833[5] ? - _theResult___sfd__h556568 : - _theResult___snd__h555833[56:5] ; - assign out_sfd__h577337 = - _theResult___snd__h576629[5] ? - _theResult___sfd__h577334 : - _theResult___snd__h576629[56:5] ; - assign out_sfd__h586988 = - sfdin__h586249[5] ? - _theResult___sfd__h586985 : - sfdin__h586249[56:5] ; - assign out_sfd__h595772 = - _theResult___snd__h595034[5] ? - _theResult___sfd__h595769 : - _theResult___snd__h595034[56:5] ; - assign pend_ints__h645396 = + _theResult___sfd__h469810 ; + assign out_sfd__h351931 = + sfdin__h351405[34] ? + _theResult___sfd__h351928 : + sfdin__h351405[56:34] ; + assign out_sfd__h360513 = + _theResult___snd__h360018[34] ? + _theResult___sfd__h360510 : + _theResult___snd__h360018[56:34] ; + assign out_sfd__h369697 = + sfdin__h369171[34] ? + _theResult___sfd__h369694 : + sfdin__h369171[56:34] ; + assign out_sfd__h378333 = + _theResult___snd__h377808[34] ? + _theResult___sfd__h378330 : + _theResult___snd__h377808[56:34] ; + assign out_sfd__h397621 = + sfdin__h397095[34] ? + _theResult___sfd__h397618 : + sfdin__h397095[56:34] ; + assign out_sfd__h406203 = + _theResult___snd__h405708[34] ? + _theResult___sfd__h406200 : + _theResult___snd__h405708[56:34] ; + assign out_sfd__h415387 = + sfdin__h414861[34] ? + _theResult___sfd__h415384 : + sfdin__h414861[56:34] ; + assign out_sfd__h424023 = + _theResult___snd__h423498[34] ? + _theResult___sfd__h424020 : + _theResult___snd__h423498[56:34] ; + assign out_sfd__h443309 = + sfdin__h442783[34] ? + _theResult___sfd__h443306 : + sfdin__h442783[56:34] ; + assign out_sfd__h451891 = + _theResult___snd__h451396[34] ? + _theResult___sfd__h451888 : + _theResult___snd__h451396[56:34] ; + assign out_sfd__h461075 = + sfdin__h460549[34] ? + _theResult___sfd__h461072 : + sfdin__h460549[56:34] ; + assign out_sfd__h469711 = + _theResult___snd__h469186[34] ? + _theResult___sfd__h469708 : + _theResult___snd__h469186[56:34] ; + assign out_sfd__h499333 = + _theResult___snd__h498625[5] ? + _theResult___sfd__h499330 : + _theResult___snd__h498625[56:5] ; + assign out_sfd__h508984 = + sfdin__h508245[5] ? + _theResult___sfd__h508981 : + sfdin__h508245[56:5] ; + assign out_sfd__h517768 = + _theResult___snd__h517030[5] ? + _theResult___sfd__h517765 : + _theResult___snd__h517030[56:5] ; + assign out_sfd__h538134 = + _theResult___snd__h537426[5] ? + _theResult___sfd__h538131 : + _theResult___snd__h537426[56:5] ; + assign out_sfd__h547785 = + sfdin__h547046[5] ? + _theResult___sfd__h547782 : + sfdin__h547046[56:5] ; + assign out_sfd__h556569 = + _theResult___snd__h555831[5] ? + _theResult___sfd__h556566 : + _theResult___snd__h555831[56:5] ; + assign out_sfd__h577335 = + _theResult___snd__h576627[5] ? + _theResult___sfd__h577332 : + _theResult___snd__h576627[56:5] ; + assign out_sfd__h586986 = + sfdin__h586247[5] ? + _theResult___sfd__h586983 : + sfdin__h586247[56:5] ; + assign out_sfd__h595770 = + _theResult___snd__h595032[5] ? + _theResult___sfd__h595767 : + _theResult___snd__h595032[56:5] ; + assign pend_ints__h645394 = { csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h707142 = csrf_prv_reg ; - assign prv__h707186 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h473080 = + assign prv__h707140 = csrf_prv_reg ; + assign prv__h707184 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h473078 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_12_TO_0___h645918 = + assign r1__read_BITS_12_TO_0___h645916 = { 3'd0, csrf_mideleg_11_reg, 1'b0, @@ -28443,126 +28443,126 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h649322 = csrf_fs_reg ; - assign r1__read_BIT_20___h649950 = csrf_tw_reg ; - assign r1__read__h608837 = { r1__read__h608839, csrf_ie_vec_1 } ; - assign r1__read__h608839 = { r1__read__h608841, 2'b0 } ; - assign r1__read__h608841 = { r1__read__h608843, csrf_prev_ie_vec_0 } ; - assign r1__read__h608843 = { r1__read__h608845, csrf_prev_ie_vec_1 } ; - assign r1__read__h608845 = { r1__read__h608847, 2'b0 } ; - assign r1__read__h608847 = { r1__read__h608849, csrf_spp_reg } ; - assign r1__read__h608849 = { r1__read__h608851, 4'b0 } ; - assign r1__read__h608851 = { r1__read__h608853, csrf_fs_reg } ; - assign r1__read__h608853 = { r1__read__h608855, 2'd0 } ; - assign r1__read__h608855 = { r1__read__h608857, 1'b0 } ; - assign r1__read__h608857 = { r1__read__h608859, csrf_sum_reg } ; - assign r1__read__h608859 = { r1__read__h608861, csrf_mxr_reg } ; - assign r1__read__h608861 = { r1__read__h608863, 12'b0 } ; - assign r1__read__h608863 = { r1__read__h608865, 2'b10 } ; - assign r1__read__h608865 = { r__h608869, 29'b0 } ; - assign r1__read__h609241 = - { r1__read__h609243, csrf_software_int_en_vec_1 } ; - assign r1__read__h609243 = { r1__read__h609245, 2'b0 } ; - assign r1__read__h609245 = { r1__read__h609247, csrf_timer_int_en_vec_0 } ; - assign r1__read__h609247 = { r1__read__h609249, csrf_timer_int_en_vec_1 } ; - assign r1__read__h609249 = { r1__read__h609251, 2'b0 } ; - assign r1__read__h609251 = - { r1__read__h609253, csrf_external_int_en_vec_0 } ; - assign r1__read__h609253 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h609771 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h609776 = { r1__read__h609778, csrf_scounteren_tm_reg } ; - assign r1__read__h609778 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h609789 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h609795 = - { r1__read__h609797, csrf_software_int_pend_vec_1 } ; - assign r1__read__h609797 = { r1__read__h609799, 2'b0 } ; - assign r1__read__h609799 = - { r1__read__h609801, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h609801 = - { r1__read__h609803, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h609803 = { r1__read__h609805, 2'b0 } ; - assign r1__read__h609805 = - { r1__read__h609807, csrf_external_int_pend_vec_0 } ; - assign r1__read__h609807 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610025 = { vm_mode_reg__read__h610031, 16'd0 } ; - assign r1__read__h610048 = { r1__read__h610050, csrf_ie_vec_1 } ; - assign r1__read__h610050 = { r1__read__h610052, 1'b0 } ; - assign r1__read__h610052 = { r1__read__h610054, csrf_ie_vec_3 } ; - assign r1__read__h610054 = { r1__read__h610056, csrf_prev_ie_vec_0 } ; - assign r1__read__h610056 = { r1__read__h610058, csrf_prev_ie_vec_1 } ; - assign r1__read__h610058 = { r1__read__h610060, 1'b0 } ; - assign r1__read__h610060 = { r1__read__h610062, csrf_prev_ie_vec_3 } ; - assign r1__read__h610062 = { r1__read__h610064, csrf_spp_reg } ; - assign r1__read__h610064 = { r1__read__h610066, 2'b0 } ; - assign r1__read__h610066 = { r1__read__h610068, csrf_mpp_reg } ; - assign r1__read__h610068 = { r1__read__h610070, csrf_fs_reg } ; - assign r1__read__h610070 = { r1__read__h610072, 2'd0 } ; - assign r1__read__h610072 = { r1__read__h610074, csrf_mprv_reg } ; - assign r1__read__h610074 = { r1__read__h610076, csrf_sum_reg } ; - assign r1__read__h610076 = { r1__read__h610078, csrf_mxr_reg } ; - assign r1__read__h610078 = { r1__read__h610080, csrf_tvm_reg } ; - assign r1__read__h610080 = { r1__read__h610082, csrf_tw_reg } ; - assign r1__read__h610082 = { r1__read__h610084, csrf_tsr_reg } ; - assign r1__read__h610084 = { r1__read__h610086, 9'b0 } ; - assign r1__read__h610086 = { r1__read__h610088, 2'b10 } ; - assign r1__read__h610088 = { r1__read__h610090, 2'b10 } ; - assign r1__read__h610090 = { r__h608869, 27'b0 } ; - assign r1__read__h610185 = { r1__read__h610187, 1'b0 } ; - assign r1__read__h610187 = { r1__read__h610189, csrf_medeleg_13_11_reg } ; - assign r1__read__h610189 = { r1__read__h610191, 1'b0 } ; - assign r1__read__h610191 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h610202 = { r1__read__h610204, 1'b0 } ; - assign r1__read__h610204 = { r1__read__h610206, csrf_mideleg_5_3_reg } ; - assign r1__read__h610206 = { r1__read__h610208, 1'b0 } ; - assign r1__read__h610208 = { r1__read__h610210, csrf_mideleg_9_7_reg } ; - assign r1__read__h610210 = { r1__read__h610212, 1'b0 } ; - assign r1__read__h610212 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h610226 = - { r1__read__h610228, csrf_software_int_en_vec_1 } ; - assign r1__read__h610228 = { r1__read__h610230, 1'b0 } ; - assign r1__read__h610230 = - { r1__read__h610232, csrf_software_int_en_vec_3 } ; - assign r1__read__h610232 = { r1__read__h610234, csrf_timer_int_en_vec_0 } ; - assign r1__read__h610234 = { r1__read__h610236, csrf_timer_int_en_vec_1 } ; - assign r1__read__h610236 = { r1__read__h610238, 1'b0 } ; - assign r1__read__h610238 = { r1__read__h610240, csrf_timer_int_en_vec_3 } ; - assign r1__read__h610240 = - { r1__read__h610242, csrf_external_int_en_vec_0 } ; - assign r1__read__h610242 = - { r1__read__h610244, csrf_external_int_en_vec_1 } ; - assign r1__read__h610244 = { r1__read__h610246, 1'b0 } ; - assign r1__read__h610246 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h610344 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h610349 = { r1__read__h610351, csrf_mcounteren_tm_reg } ; - assign r1__read__h610351 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h610362 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h610368 = - { r1__read__h610370, csrf_software_int_pend_vec_1 } ; - assign r1__read__h610370 = { r1__read__h610372, 1'b0 } ; - assign r1__read__h610372 = - { r1__read__h610374, csrf_software_int_pend_vec_3 } ; - assign r1__read__h610374 = - { r1__read__h610376, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h610376 = - { r1__read__h610378, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h610378 = { r1__read__h610380, 1'b0 } ; - assign r1__read__h610380 = - { r1__read__h610382, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h610382 = - { r1__read__h610384, csrf_external_int_pend_vec_0 } ; - assign r1__read__h610384 = - { r1__read__h610386, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610386 = { r1__read__h610388, 1'b0 } ; - assign r1__read__h610388 = - { r1__read__h610390, csrf_external_int_pend_vec_3 } ; - assign r1__read__h610390 = { r1__read__h610392, 2'b0 } ; - assign r1__read__h610392 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h478961 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h478962 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h473106 = + assign r1__read_BITS_13_TO_12___h649320 = csrf_fs_reg ; + assign r1__read_BIT_20___h649948 = csrf_tw_reg ; + assign r1__read__h608838 = { r1__read__h608840, csrf_ie_vec_1 } ; + assign r1__read__h608840 = { r1__read__h608842, 2'b0 } ; + assign r1__read__h608842 = { r1__read__h608844, csrf_prev_ie_vec_0 } ; + assign r1__read__h608844 = { r1__read__h608846, csrf_prev_ie_vec_1 } ; + assign r1__read__h608846 = { r1__read__h608848, 2'b0 } ; + assign r1__read__h608848 = { r1__read__h608850, csrf_spp_reg } ; + assign r1__read__h608850 = { r1__read__h608852, 4'b0 } ; + assign r1__read__h608852 = { r1__read__h608854, csrf_fs_reg } ; + assign r1__read__h608854 = { r1__read__h608856, 2'd0 } ; + assign r1__read__h608856 = { r1__read__h608858, 1'b0 } ; + assign r1__read__h608858 = { r1__read__h608860, csrf_sum_reg } ; + assign r1__read__h608860 = { r1__read__h608862, csrf_mxr_reg } ; + assign r1__read__h608862 = { r1__read__h608864, 12'b0 } ; + assign r1__read__h608864 = { r1__read__h608866, 2'b10 } ; + assign r1__read__h608866 = { r__h608870, 29'b0 } ; + assign r1__read__h609242 = + { r1__read__h609244, csrf_software_int_en_vec_1 } ; + assign r1__read__h609244 = { r1__read__h609246, 2'b0 } ; + assign r1__read__h609246 = { r1__read__h609248, csrf_timer_int_en_vec_0 } ; + assign r1__read__h609248 = { r1__read__h609250, csrf_timer_int_en_vec_1 } ; + assign r1__read__h609250 = { r1__read__h609252, 2'b0 } ; + assign r1__read__h609252 = + { r1__read__h609254, csrf_external_int_en_vec_0 } ; + assign r1__read__h609254 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h609772 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h609777 = { r1__read__h609779, csrf_scounteren_tm_reg } ; + assign r1__read__h609779 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h609790 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h609796 = + { r1__read__h609798, csrf_software_int_pend_vec_1 } ; + assign r1__read__h609798 = { r1__read__h609800, 2'b0 } ; + assign r1__read__h609800 = + { r1__read__h609802, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h609802 = + { r1__read__h609804, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h609804 = { r1__read__h609806, 2'b0 } ; + assign r1__read__h609806 = + { r1__read__h609808, csrf_external_int_pend_vec_0 } ; + assign r1__read__h609808 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610026 = { vm_mode_reg__read__h610032, 16'd0 } ; + assign r1__read__h610049 = { r1__read__h610051, csrf_ie_vec_1 } ; + assign r1__read__h610051 = { r1__read__h610053, 1'b0 } ; + assign r1__read__h610053 = { r1__read__h610055, csrf_ie_vec_3 } ; + assign r1__read__h610055 = { r1__read__h610057, csrf_prev_ie_vec_0 } ; + assign r1__read__h610057 = { r1__read__h610059, csrf_prev_ie_vec_1 } ; + assign r1__read__h610059 = { r1__read__h610061, 1'b0 } ; + assign r1__read__h610061 = { r1__read__h610063, csrf_prev_ie_vec_3 } ; + assign r1__read__h610063 = { r1__read__h610065, csrf_spp_reg } ; + assign r1__read__h610065 = { r1__read__h610067, 2'b0 } ; + assign r1__read__h610067 = { r1__read__h610069, csrf_mpp_reg } ; + assign r1__read__h610069 = { r1__read__h610071, csrf_fs_reg } ; + assign r1__read__h610071 = { r1__read__h610073, 2'd0 } ; + assign r1__read__h610073 = { r1__read__h610075, csrf_mprv_reg } ; + assign r1__read__h610075 = { r1__read__h610077, csrf_sum_reg } ; + assign r1__read__h610077 = { r1__read__h610079, csrf_mxr_reg } ; + assign r1__read__h610079 = { r1__read__h610081, csrf_tvm_reg } ; + assign r1__read__h610081 = { r1__read__h610083, csrf_tw_reg } ; + assign r1__read__h610083 = { r1__read__h610085, csrf_tsr_reg } ; + assign r1__read__h610085 = { r1__read__h610087, 9'b0 } ; + assign r1__read__h610087 = { r1__read__h610089, 2'b10 } ; + assign r1__read__h610089 = { r1__read__h610091, 2'b10 } ; + assign r1__read__h610091 = { r__h608870, 27'b0 } ; + assign r1__read__h610186 = { r1__read__h610188, 1'b0 } ; + assign r1__read__h610188 = { r1__read__h610190, csrf_medeleg_13_11_reg } ; + assign r1__read__h610190 = { r1__read__h610192, 1'b0 } ; + assign r1__read__h610192 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h610203 = { r1__read__h610205, 1'b0 } ; + assign r1__read__h610205 = { r1__read__h610207, csrf_mideleg_5_3_reg } ; + assign r1__read__h610207 = { r1__read__h610209, 1'b0 } ; + assign r1__read__h610209 = { r1__read__h610211, csrf_mideleg_9_7_reg } ; + assign r1__read__h610211 = { r1__read__h610213, 1'b0 } ; + assign r1__read__h610213 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h610227 = + { r1__read__h610229, csrf_software_int_en_vec_1 } ; + assign r1__read__h610229 = { r1__read__h610231, 1'b0 } ; + assign r1__read__h610231 = + { r1__read__h610233, csrf_software_int_en_vec_3 } ; + assign r1__read__h610233 = { r1__read__h610235, csrf_timer_int_en_vec_0 } ; + assign r1__read__h610235 = { r1__read__h610237, csrf_timer_int_en_vec_1 } ; + assign r1__read__h610237 = { r1__read__h610239, 1'b0 } ; + assign r1__read__h610239 = { r1__read__h610241, csrf_timer_int_en_vec_3 } ; + assign r1__read__h610241 = + { r1__read__h610243, csrf_external_int_en_vec_0 } ; + assign r1__read__h610243 = + { r1__read__h610245, csrf_external_int_en_vec_1 } ; + assign r1__read__h610245 = { r1__read__h610247, 1'b0 } ; + assign r1__read__h610247 = { 52'd4, csrf_external_int_en_vec_3 } ; + assign r1__read__h610345 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h610350 = { r1__read__h610352, csrf_mcounteren_tm_reg } ; + assign r1__read__h610352 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h610363 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h610369 = + { r1__read__h610371, csrf_software_int_pend_vec_1 } ; + assign r1__read__h610371 = { r1__read__h610373, 1'b0 } ; + assign r1__read__h610373 = + { r1__read__h610375, csrf_software_int_pend_vec_3 } ; + assign r1__read__h610375 = + { r1__read__h610377, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h610377 = + { r1__read__h610379, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h610379 = { r1__read__h610381, 1'b0 } ; + assign r1__read__h610381 = + { r1__read__h610383, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h610383 = + { r1__read__h610385, csrf_external_int_pend_vec_0 } ; + assign r1__read__h610385 = + { r1__read__h610387, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610387 = { r1__read__h610389, 1'b0 } ; + assign r1__read__h610389 = + { r1__read__h610391, csrf_external_int_pend_vec_3 } ; + assign r1__read__h610391 = { r1__read__h610393, 2'b0 } ; + assign r1__read__h610393 = { 49'b0, csrf_debug_int_pend } ; + assign rVal1__h478959 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h478960 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h473104 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h608869 = csrf_fs_reg == 2'b11 ; + assign r__h608870 = csrf_fs_reg == 2'b11 ; assign regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && @@ -28662,12 +28662,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign renaming_spec_bits__h675348 = + assign renaming_spec_bits__h675346 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h672114 : + y_avValue_snd_fst__h672112 : specTagManager$currentSpecBits ; - assign res_data__h335089 = { 32'd0, x__h335101 } ; - assign res_data__h335094 = + assign res_data__h335087 = { 32'd0, x__h335099 } ; + assign res_data__h335092 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28680,8 +28680,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h380784 = { 32'd0, x__h380796 } ; - assign res_data__h380789 = + assign res_data__h380782 = { 32'd0, x__h380794 } ; + assign res_data__h380787 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28694,8 +28694,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h426472 = { 32'd0, x__h426484 } ; - assign res_data__h426477 = + assign res_data__h426470 = { 32'd0, x__h426482 } ; + assign res_data__h426475 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28708,7 +28708,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h335090 = + assign res_fflags__h335088 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -28776,7 +28776,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ; - assign res_fflags__h380785 = + assign res_fflags__h380783 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -28844,7 +28844,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ; - assign res_fflags__h426473 = + assign res_fflags__h426471 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -28912,35 +28912,35 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ; - assign resp_addr__h289193 = + assign resp_addr__h289191 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h361554 = + assign result__h361552 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] | - guard__h361549 } ; - assign result__h407244 = + guard__h361547 } ; + assign result__h407242 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] | - guard__h407239 } ; - assign result__h452932 = + guard__h407237 } ; + assign result__h452930 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] | - guard__h452927 } ; - assign result__h500630 = + guard__h452925 } ; + assign result__h500628 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[0] | - guard__h500625 } ; - assign result__h539431 = + guard__h500623 } ; + assign result__h539429 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[0] | - guard__h539426 } ; - assign result__h578632 = + guard__h539424 } ; + assign result__h578630 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[0] | - guard__h578627 } ; - assign result__h641105 = w__h641100 & y__h641134 ; - assign result__h641156 = ~x__h641155 ; + guard__h578625 } ; + assign result__h641103 = w__h641098 & y__h641132 ; + assign result__h641154 = ~x__h641153 ; assign rob_RDY_enqPort_0_enq__2627_AND_regRenamingTab_ETC___d13095 = rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && @@ -28972,12 +28972,12 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q261 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h649453 = + assign rs1__h649451 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h606849 = { r1__read__h610025, csrf_ppn_reg } ; + assign satp_csr__read__h606850 = { r1__read__h610026, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 && @@ -29003,259 +29003,259 @@ module mkCore(CLK, coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h606647 = - { r1__read__h609789, csrf_scause_code_reg } ; - assign scounteren_csr__read__h606509 = - { r1__read__h609776, csrf_scounteren_cy_reg } ; - assign sfd__h335697 = { value__h343924, 3'd0 } ; - assign sfd__h351505 = + assign scause_csr__read__h606648 = + { r1__read__h609790, csrf_scause_code_reg } ; + assign scounteren_csr__read__h606510 = + { r1__read__h609777, csrf_scounteren_cy_reg } ; + assign sfd__h335695 = { value__h343922, 3'd0 } ; + assign sfd__h351503 = { 1'b0, - _theResult___fst_exp__h351413 != 8'd0, - sfdin__h351407[56:34] } + + _theResult___fst_exp__h351411 != 8'd0, + sfdin__h351405[56:34] } + 25'd1 ; - assign sfd__h360087 = + assign sfd__h360085 = { 1'b0, - _theResult___fst_exp__h360069 != 8'd0, - _theResult___snd__h360020[56:34] } + + _theResult___fst_exp__h360067 != 8'd0, + _theResult___snd__h360018[56:34] } + 25'd1 ; - assign sfd__h369271 = + assign sfd__h369269 = { 1'b0, - _theResult___fst_exp__h369179 != 8'd0, - sfdin__h369173[56:34] } + + _theResult___fst_exp__h369177 != 8'd0, + sfdin__h369171[56:34] } + 25'd1 ; - assign sfd__h377883 = + assign sfd__h377881 = { 1'b0, - _theResult___fst_exp__h377864 != 8'd0, - _theResult___snd__h377810[56:34] } + + _theResult___fst_exp__h377862 != 8'd0, + _theResult___snd__h377808[56:34] } + 25'd1 ; - assign sfd__h381392 = { value__h389614, 3'd0 } ; - assign sfd__h397195 = + assign sfd__h381390 = { value__h389612, 3'd0 } ; + assign sfd__h397193 = { 1'b0, - _theResult___fst_exp__h397103 != 8'd0, - sfdin__h397097[56:34] } + + _theResult___fst_exp__h397101 != 8'd0, + sfdin__h397095[56:34] } + 25'd1 ; - assign sfd__h405777 = + assign sfd__h405775 = { 1'b0, - _theResult___fst_exp__h405759 != 8'd0, - _theResult___snd__h405710[56:34] } + + _theResult___fst_exp__h405757 != 8'd0, + _theResult___snd__h405708[56:34] } + 25'd1 ; - assign sfd__h414961 = + assign sfd__h414959 = { 1'b0, - _theResult___fst_exp__h414869 != 8'd0, - sfdin__h414863[56:34] } + + _theResult___fst_exp__h414867 != 8'd0, + sfdin__h414861[56:34] } + 25'd1 ; - assign sfd__h423573 = + assign sfd__h423571 = { 1'b0, - _theResult___fst_exp__h423554 != 8'd0, - _theResult___snd__h423500[56:34] } + + _theResult___fst_exp__h423552 != 8'd0, + _theResult___snd__h423498[56:34] } + 25'd1 ; - assign sfd__h427080 = { value__h435302, 3'd0 } ; - assign sfd__h442883 = + assign sfd__h427078 = { value__h435300, 3'd0 } ; + assign sfd__h442881 = { 1'b0, - _theResult___fst_exp__h442791 != 8'd0, - sfdin__h442785[56:34] } + + _theResult___fst_exp__h442789 != 8'd0, + sfdin__h442783[56:34] } + 25'd1 ; - assign sfd__h451465 = + assign sfd__h451463 = { 1'b0, - _theResult___fst_exp__h451447 != 8'd0, - _theResult___snd__h451398[56:34] } + + _theResult___fst_exp__h451445 != 8'd0, + _theResult___snd__h451396[56:34] } + 25'd1 ; - assign sfd__h460649 = + assign sfd__h460647 = { 1'b0, - _theResult___fst_exp__h460557 != 8'd0, - sfdin__h460551[56:34] } + + _theResult___fst_exp__h460555 != 8'd0, + sfdin__h460549[56:34] } + 25'd1 ; - assign sfd__h469261 = + assign sfd__h469259 = { 1'b0, - _theResult___fst_exp__h469242 != 8'd0, - _theResult___snd__h469188[56:34] } + + _theResult___fst_exp__h469240 != 8'd0, + _theResult___snd__h469186[56:34] } + 25'd1 ; - assign sfd__h479675 = { value__h484233, 32'd0 } ; - assign sfd__h498694 = + assign sfd__h479673 = { value__h484231, 32'd0 } ; + assign sfd__h498692 = { 1'b0, - _theResult___fst_exp__h498676 != 11'd0, - _theResult___snd__h498627[56:5] } + + _theResult___fst_exp__h498674 != 11'd0, + _theResult___snd__h498625[56:5] } + 54'd1 ; - assign sfd__h508345 = + assign sfd__h508343 = { 1'b0, - _theResult___fst_exp__h508253 != 11'd0, - sfdin__h508247[56:5] } + + _theResult___fst_exp__h508251 != 11'd0, + sfdin__h508245[56:5] } + 54'd1 ; - assign sfd__h517105 = + assign sfd__h517103 = { 1'b0, - _theResult___fst_exp__h517086 != 11'd0, - _theResult___snd__h517032[56:5] } + + _theResult___fst_exp__h517084 != 11'd0, + _theResult___snd__h517030[56:5] } + 54'd1 ; - assign sfd__h518617 = { value__h523034, 32'd0 } ; - assign sfd__h537495 = + assign sfd__h518615 = { value__h523032, 32'd0 } ; + assign sfd__h537493 = { 1'b0, - _theResult___fst_exp__h537477 != 11'd0, - _theResult___snd__h537428[56:5] } + + _theResult___fst_exp__h537475 != 11'd0, + _theResult___snd__h537426[56:5] } + 54'd1 ; - assign sfd__h547146 = + assign sfd__h547144 = { 1'b0, - _theResult___fst_exp__h547054 != 11'd0, - sfdin__h547048[56:5] } + + _theResult___fst_exp__h547052 != 11'd0, + sfdin__h547046[56:5] } + 54'd1 ; - assign sfd__h555906 = + assign sfd__h555904 = { 1'b0, - _theResult___fst_exp__h555887 != 11'd0, - _theResult___snd__h555833[56:5] } + + _theResult___fst_exp__h555885 != 11'd0, + _theResult___snd__h555831[56:5] } + 54'd1 ; - assign sfd__h557818 = { value__h562235, 32'd0 } ; - assign sfd__h576696 = + assign sfd__h557816 = { value__h562233, 32'd0 } ; + assign sfd__h576694 = { 1'b0, - _theResult___fst_exp__h576678 != 11'd0, - _theResult___snd__h576629[56:5] } + + _theResult___fst_exp__h576676 != 11'd0, + _theResult___snd__h576627[56:5] } + 54'd1 ; - assign sfd__h586347 = + assign sfd__h586345 = { 1'b0, - _theResult___fst_exp__h586255 != 11'd0, - sfdin__h586249[56:5] } + + _theResult___fst_exp__h586253 != 11'd0, + sfdin__h586247[56:5] } + 54'd1 ; - assign sfd__h595107 = + assign sfd__h595105 = { 1'b0, - _theResult___fst_exp__h595088 != 11'd0, - _theResult___snd__h595034[56:5] } + + _theResult___fst_exp__h595086 != 11'd0, + _theResult___snd__h595032[56:5] } + 54'd1 ; - assign sfdin__h351407 = - _theResult____h343302[56] ? - _theResult___snd__h351424 : - _theResult___snd__h351435 ; - assign sfdin__h369173 = - _theResult____h360941[56] ? - _theResult___snd__h369190 : - _theResult___snd__h369201 ; - assign sfdin__h397097 = - _theResult____h388994[56] ? - _theResult___snd__h397114 : - _theResult___snd__h397125 ; - assign sfdin__h414863 = - _theResult____h406631[56] ? - _theResult___snd__h414880 : - _theResult___snd__h414891 ; - assign sfdin__h442785 = - _theResult____h434682[56] ? - _theResult___snd__h442802 : - _theResult___snd__h442813 ; - assign sfdin__h460551 = - _theResult____h452319[56] ? - _theResult___snd__h460568 : - _theResult___snd__h460579 ; - assign sfdin__h508247 = - _theResult____h500017[56] ? - _theResult___snd__h508264 : - _theResult___snd__h508275 ; - assign sfdin__h547048 = - _theResult____h538818[56] ? - _theResult___snd__h547065 : - _theResult___snd__h547076 ; - assign sfdin__h586249 = - _theResult____h578019[56] ? - _theResult___snd__h586266 : - _theResult___snd__h586277 ; - assign shiftData__h180516 = - coreFix_memExe_regToExeQ$first[75:12] << x__h180648 ; - assign sie_csr__read__h606413 = - { r1__read__h609241, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h606786 = - { r1__read__h609795, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h678443 = specTagManager$currentSpecBits | y__h678456 ; - assign sstatus_csr__read__h606344 = { r1__read__h608837, csrf_ie_vec_0 } ; - assign stvec_csr__read__h606456 = - { r1__read__h609771, csrf_stvec_mode_low_reg } ; + assign sfdin__h351405 = + _theResult____h343300[56] ? + _theResult___snd__h351422 : + _theResult___snd__h351433 ; + assign sfdin__h369171 = + _theResult____h360939[56] ? + _theResult___snd__h369188 : + _theResult___snd__h369199 ; + assign sfdin__h397095 = + _theResult____h388992[56] ? + _theResult___snd__h397112 : + _theResult___snd__h397123 ; + assign sfdin__h414861 = + _theResult____h406629[56] ? + _theResult___snd__h414878 : + _theResult___snd__h414889 ; + assign sfdin__h442783 = + _theResult____h434680[56] ? + _theResult___snd__h442800 : + _theResult___snd__h442811 ; + assign sfdin__h460549 = + _theResult____h452317[56] ? + _theResult___snd__h460566 : + _theResult___snd__h460577 ; + assign sfdin__h508245 = + _theResult____h500015[56] ? + _theResult___snd__h508262 : + _theResult___snd__h508273 ; + assign sfdin__h547046 = + _theResult____h538816[56] ? + _theResult___snd__h547063 : + _theResult___snd__h547074 ; + assign sfdin__h586247 = + _theResult____h578017[56] ? + _theResult___snd__h586264 : + _theResult___snd__h586275 ; + assign shiftData__h180514 = + coreFix_memExe_regToExeQ$first[75:12] << x__h180646 ; + assign sie_csr__read__h606414 = + { r1__read__h609242, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h606787 = + { r1__read__h609796, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h678441 = specTagManager$currentSpecBits | y__h678454 ; + assign sstatus_csr__read__h606345 = { r1__read__h608838, csrf_ie_vec_0 } ; + assign stvec_csr__read__h606457 = + { r1__read__h609772, csrf_stvec_mode_low_reg } ; assign upd__h3639 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; assign upd__h4956 = n__read__h6134 + 64'd1 ; - assign v__h293163 = + assign v__h293161 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ? - v__h293394 : + v__h293392 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h293394 = + assign v__h293392 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h296508 = + assign v__h296506 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ? - v__h297026 : + v__h297024 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h297026 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h307022 = + assign v__h297024 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h307020 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ? - v__h307253 : + v__h307251 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h307253 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h310898 = + assign v__h307251 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h310896 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ? - v__h311129 : + v__h311127 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h311129 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h325499 = + assign v__h311127 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h325497 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ? - v__h325730 : + v__h325728 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h325730 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h328724 = + assign v__h325728 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h328722 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ? - v__h328955 : + v__h328953 : coreFix_memExe_forwardQ_enqP ; - assign v__h328955 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h600774 = + assign v__h328953 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h600772 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h600784 : + v__h600782 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h600784 = + assign v__h600782 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h601419 = v__h600774 - 2'd1 ; - assign v__h604754 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605660 ; - assign v__h628444 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629197 ; - assign vaddr__h180511 = + assign v__h601417 = v__h600772 - 2'd1 ; + assign v__h604755 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605661 ; + assign v__h628443 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629196 ; + assign vaddr__h180509 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 } ; - assign value__h343924 = + assign value__h343922 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h389614 = + assign value__h389612 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h435302 = + assign value__h435300 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h484233 = + assign value__h484231 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ; - assign value__h523034 = + assign value__h523032 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ; - assign value__h562235 = + assign value__h562233 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ; - assign vm_mode_reg__read__h610031 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h641100 = + assign vm_mode_reg__read__h610032 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h641098 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h641156 : + result__h641154 : 12'd4095 ; assign x__h152884 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? @@ -29298,130 +29298,130 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h180425 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179513 ; - assign x__h180426 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180119 ; - assign x__h180648 = { vaddr__h180511[2:0], 3'b0 } ; - assign x__h190902 = + assign x__h180423 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179511 ; + assign x__h180424 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180117 ; + assign x__h180646 = { vaddr__h180509[2:0], 3'b0 } ; + assign x__h190900 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h190139[63:32] : - curData__h190139[31:0] ; + curData__h190137[63:32] : + curData__h190137[31:0] ; assign x__h20210 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h284501 = + assign x__h284499 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h284513 = + assign x__h284511 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h286367 = + assign x__h286365 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h299373 = + assign x__h299371 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h335101 = - { (_theResult___exp__h378433 != 8'd255 || - _theResult___sfd__h378434 == 23'd0) && + assign x__h335099 = + { (_theResult___exp__h378431 != 8'd255 || + _theResult___sfd__h378432 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - out_f_exp__h378710, - out_f_sfd__h378711 } ; - assign x__h361651 = - sfd__h335697 << (x__h361684[11] ? 12'hAAA : x__h361684) ; - assign x__h361684 = + out_f_exp__h378708, + out_f_sfd__h378709 } ; + assign x__h361649 = + sfd__h335695 << (x__h361682[11] ? 12'hAAA : x__h361682) ; + assign x__h361682 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ; - assign x__h380796 = - { (_theResult___exp__h424123 != 8'd255 || - _theResult___sfd__h424124 == 23'd0) && + assign x__h380794 = + { (_theResult___exp__h424121 != 8'd255 || + _theResult___sfd__h424122 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - out_f_exp__h424400, - out_f_sfd__h424401 } ; - assign x__h407341 = - sfd__h381392 << (x__h407374[11] ? 12'hAAA : x__h407374) ; - assign x__h407374 = + out_f_exp__h424398, + out_f_sfd__h424399 } ; + assign x__h407339 = + sfd__h381390 << (x__h407372[11] ? 12'hAAA : x__h407372) ; + assign x__h407372 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ; - assign x__h426484 = - { (_theResult___exp__h469811 != 8'd255 || - _theResult___sfd__h469812 == 23'd0) && + assign x__h426482 = + { (_theResult___exp__h469809 != 8'd255 || + _theResult___sfd__h469810 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - out_f_exp__h470088, - out_f_sfd__h470089 } ; - assign x__h453029 = - sfd__h427080 << (x__h453062[11] ? 12'hAAA : x__h453062) ; - assign x__h453062 = + out_f_exp__h470086, + out_f_sfd__h470087 } ; + assign x__h453027 = + sfd__h427078 << (x__h453060[11] ? 12'hAAA : x__h453060) ; + assign x__h453060 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ; assign x__h45579 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; + assign x__h478868 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476004 ; + assign x__h478869 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476612 ; assign x__h478870 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476006 ; - assign x__h478871 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476614 ; - assign x__h478872 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477216 ; + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477214 ; assign x__h48115 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h500725 = sfd__h479675 << x__h500758 ; - assign x__h500758 = + assign x__h500723 = sfd__h479673 << x__h500756 ; + assign x__h500756 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; - assign x__h539526 = sfd__h518617 << x__h539559 ; - assign x__h539559 = + assign x__h539524 = sfd__h518615 << x__h539557 ; + assign x__h539557 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; - assign x__h578727 = sfd__h557818 << x__h578760 ; - assign x__h578760 = + assign x__h578725 = sfd__h557816 << x__h578758 ; + assign x__h578758 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; - assign x__h600275 = a__h599839[63] ^ b__h599840[63] ; - assign x__h608822 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h613033 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h605870 : - v__h604754 ; + assign x__h600273 = a__h599837[63] ^ b__h599838[63] ; + assign x__h608823 = { csrf_frm_reg, csrf_fflags_reg } ; assign x__h613034 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610922 ; - assign x__h634256 = + coreFix_aluExe_1_dispToRegQ$first[131] ? + rVal1__h605871 : + v__h604755 ; + assign x__h613035 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610923 ; + assign x__h634254 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h629405 : - v__h628444 ; - assign x__h634257 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632155 ; - assign x__h641104 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h641155 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h688725 = + rVal1__h629404 : + v__h628443 ; + assign x__h634255 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632153 ; + assign x__h641102 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h641153 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h688723 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h694806 = { cause_code__h692189, 2'b0 } ; - assign x__h702602 = { 1'b0, csrf_spp_reg } ; - assign x__h705875 = + assign x__h694804 = { cause_code__h692187, 2'b0 } ; + assign x__h702600 = { 1'b0, csrf_spp_reg } ; + assign x__h705873 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_fst__h705697 : + y_avValue_snd_snd_snd_fst__h705695 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 ; assign x__h75524 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h311296 = + assign x_addr__h311294 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; @@ -29429,29 +29429,29 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h667949 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h682692 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h649137 = csrf_frm_reg ; - assign x_quotient__h472395 = + assign x_data_imm__h667947 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h682690 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h649135 = csrf_frm_reg ; + assign x_quotient__h472393 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h473080 : + q___1__h473078 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h606253 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h472396 = + assign x_reg_ifc__read__h606254 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h472394 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h473106 : + r___1__h473104 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h252026 = + assign y__h252024 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h641134 = ~x__h641104 ; - assign y__h645907 = + assign y__h641132 = ~x__h641102 ; + assign y__h645905 = { 3'd7, ~csrf_mideleg_11_reg, 1'd1, @@ -29460,71 +29460,71 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h678456 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h705650 = + assign y__h678454 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h705648 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_snd_snd__h705703 : + y_avValue_snd_snd_snd_snd_snd__h705701 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 ; - assign y_avValue__h179513 = + assign y_avValue__h179511 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ; - assign y_avValue__h180119 = + assign y_avValue__h180117 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ; - assign y_avValue__h476006 = + assign y_avValue__h476004 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ; - assign y_avValue__h476614 = + assign y_avValue__h476612 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ; - assign y_avValue__h477216 = + assign y_avValue__h477214 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ; - assign y_avValue__h605660 = + assign y_avValue__h605661 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11330 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11708 ; - assign y_avValue__h610922 = + assign y_avValue__h610923 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11358 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11720 ; - assign y_avValue__h629197 = + assign y_avValue__h629196 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12125 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12317 ; - assign y_avValue__h632155 = + assign y_avValue__h632153 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12153 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12329 ; - assign y_avValue__h693067 = + assign y_avValue__h693065 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694791 + { 58'd0, x__h694806 } : - base__h694791 ; - assign y_avValue__h694828 = + base__h694789 + { 58'd0, x__h694804 } : + base__h694789 ; + assign y_avValue__h694826 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694994 + { 58'd0, x__h694806 } : - base__h694994 ; - assign y_avValue_fst__h671840 = + base__h694992 + { 58'd0, x__h694804 } : + base__h694992 ; + assign y_avValue_fst__h671838 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h678443 : + spec_bits__h678441 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672114 = + assign y_avValue_snd_fst__h672112 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207) ? - y_avValue_snd_fst__h672149 : + y_avValue_snd_fst__h672147 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672149 = + assign y_avValue_snd_fst__h672147 = IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 ? - y_avValue_fst__h671840 : + y_avValue_fst__h671838 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h705134 = + assign y_avValue_snd_fst__h705132 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29538,7 +29538,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h705687 = + assign y_avValue_snd_fst__h705685 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29551,11 +29551,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 : - y_avValue_snd_fst__h705716 ; - assign y_avValue_snd_fst__h705716 = + y_avValue_snd_fst__h705714 ; + assign y_avValue_snd_fst__h705714 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_snd_snd_fst__h705144 = + assign y_avValue_snd_snd_snd_fst__h705142 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29569,7 +29569,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h705697 = + assign y_avValue_snd_snd_snd_fst__h705695 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29582,11 +29582,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 : - y_avValue_snd_snd_snd_fst__h705726 ; - assign y_avValue_snd_snd_snd_fst__h705726 = + y_avValue_snd_snd_snd_fst__h705724 ; + assign y_avValue_snd_snd_snd_fst__h705724 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705150 = + assign y_avValue_snd_snd_snd_snd_snd__h705148 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29600,7 +29600,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705703 = + assign y_avValue_snd_snd_snd_snd_snd__h705701 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29613,8 +29613,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 : - y_avValue_snd_snd_snd_snd_snd__h705732 ; - assign y_avValue_snd_snd_snd_snd_snd__h705732 = + y_avValue_snd_snd_snd_snd_snd__h705730 ; + assign y_avValue_snd_snd_snd_snd_snd__h705730 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -29633,28 +29633,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -29670,28 +29670,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -29701,10 +29701,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h287289 = + addr__h287287 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h287289 = + addr__h287287 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -29713,36 +29713,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h693220 = commitStage_commitTrap[132:69]; - default: trap_val__h693220 = + 4'd0, 4'd3: trap_val__h693218 = commitStage_commitTrap[132:69]; + default: trap_val__h693218 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -29757,247 +29757,247 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h288836 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h288836 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h606123 or - frm_csr__read__h606134 or - fcsr_csr__read__h606148 or - sstatus_csr__read__h606344 or - sie_csr__read__h606413 or - stvec_csr__read__h606456 or - scounteren_csr__read__h606509 or + fflags_csr__read__h606124 or + frm_csr__read__h606135 or + fcsr_csr__read__h606149 or + sstatus_csr__read__h606345 or + sie_csr__read__h606414 or + stvec_csr__read__h606457 or + scounteren_csr__read__h606510 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606647 or + scause_csr__read__h606648 or csrf_stval_csr or - sip_csr__read__h606786 or - satp_csr__read__h606849 or - mstatus_csr__read__h606992 or - medeleg_csr__read__h607140 or - mideleg_csr__read__h607235 or - mie_csr__read__h607366 or - mtvec_csr__read__h607448 or - mcounteren_csr__read__h607540 or + sip_csr__read__h606787 or + satp_csr__read__h606850 or + mstatus_csr__read__h606993 or + medeleg_csr__read__h607141 or + mideleg_csr__read__h607236 or + mie_csr__read__h607367 or + mtvec_csr__read__h607449 or + mcounteren_csr__read__h607541 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607795 or + mcause_csr__read__h607796 or csrf_mtval_csr or - mip_csr__read__h608035 or - x_reg_ifc__read__h606253 or - n__read__h608139 or n__read__h608330 or csrf_time_reg) + mip_csr__read__h608036 or + x_reg_ifc__read__h606254 or + n__read__h608140 or n__read__h608331 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h605870 = fflags_csr__read__h606123; - 12'd2: rVal1__h605870 = frm_csr__read__h606134; - 12'd3: rVal1__h605870 = fcsr_csr__read__h606148; - 12'd256: rVal1__h605870 = sstatus_csr__read__h606344; - 12'd260: rVal1__h605870 = sie_csr__read__h606413; - 12'd261: rVal1__h605870 = stvec_csr__read__h606456; - 12'd262: rVal1__h605870 = scounteren_csr__read__h606509; - 12'd320: rVal1__h605870 = csrf_sscratch_csr; - 12'd321: rVal1__h605870 = csrf_sepc_csr; - 12'd322: rVal1__h605870 = scause_csr__read__h606647; - 12'd323: rVal1__h605870 = csrf_stval_csr; - 12'd324: rVal1__h605870 = sip_csr__read__h606786; - 12'd384: rVal1__h605870 = satp_csr__read__h606849; - 12'd768: rVal1__h605870 = mstatus_csr__read__h606992; - 12'd769: rVal1__h605870 = 64'h8000000000141129; - 12'd770: rVal1__h605870 = medeleg_csr__read__h607140; - 12'd771: rVal1__h605870 = mideleg_csr__read__h607235; - 12'd772: rVal1__h605870 = mie_csr__read__h607366; - 12'd773: rVal1__h605870 = mtvec_csr__read__h607448; - 12'd774: rVal1__h605870 = mcounteren_csr__read__h607540; - 12'd832: rVal1__h605870 = csrf_mscratch_csr; - 12'd833: rVal1__h605870 = csrf_mepc_csr; - 12'd834: rVal1__h605870 = mcause_csr__read__h607795; - 12'd835: rVal1__h605870 = csrf_mtval_csr; - 12'd836: rVal1__h605870 = mip_csr__read__h608035; - 12'd2048: rVal1__h605870 = 64'd0; - 12'd2049: rVal1__h605870 = x_reg_ifc__read__h606253; - 12'd2816, 12'd3072: rVal1__h605870 = n__read__h608139; - 12'd2818, 12'd3074: rVal1__h605870 = n__read__h608330; - 12'd3073: rVal1__h605870 = csrf_time_reg; - default: rVal1__h605870 = 64'd0; + 12'd1: rVal1__h605871 = fflags_csr__read__h606124; + 12'd2: rVal1__h605871 = frm_csr__read__h606135; + 12'd3: rVal1__h605871 = fcsr_csr__read__h606149; + 12'd256: rVal1__h605871 = sstatus_csr__read__h606345; + 12'd260: rVal1__h605871 = sie_csr__read__h606414; + 12'd261: rVal1__h605871 = stvec_csr__read__h606457; + 12'd262: rVal1__h605871 = scounteren_csr__read__h606510; + 12'd320: rVal1__h605871 = csrf_sscratch_csr; + 12'd321: rVal1__h605871 = csrf_sepc_csr; + 12'd322: rVal1__h605871 = scause_csr__read__h606648; + 12'd323: rVal1__h605871 = csrf_stval_csr; + 12'd324: rVal1__h605871 = sip_csr__read__h606787; + 12'd384: rVal1__h605871 = satp_csr__read__h606850; + 12'd768: rVal1__h605871 = mstatus_csr__read__h606993; + 12'd769: rVal1__h605871 = 64'h8000000000141129; + 12'd770: rVal1__h605871 = medeleg_csr__read__h607141; + 12'd771: rVal1__h605871 = mideleg_csr__read__h607236; + 12'd772: rVal1__h605871 = mie_csr__read__h607367; + 12'd773: rVal1__h605871 = mtvec_csr__read__h607449; + 12'd774: rVal1__h605871 = mcounteren_csr__read__h607541; + 12'd832: rVal1__h605871 = csrf_mscratch_csr; + 12'd833: rVal1__h605871 = csrf_mepc_csr; + 12'd834: rVal1__h605871 = mcause_csr__read__h607796; + 12'd835: rVal1__h605871 = csrf_mtval_csr; + 12'd836: rVal1__h605871 = mip_csr__read__h608036; + 12'd2048: rVal1__h605871 = 64'd0; + 12'd2049: rVal1__h605871 = x_reg_ifc__read__h606254; + 12'd2816, 12'd3072: rVal1__h605871 = n__read__h608140; + 12'd2818, 12'd3074: rVal1__h605871 = n__read__h608331; + 12'd3073: rVal1__h605871 = csrf_time_reg; + default: rVal1__h605871 = 64'd0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h606123 or - frm_csr__read__h606134 or - fcsr_csr__read__h606148 or - sstatus_csr__read__h606344 or - sie_csr__read__h606413 or - stvec_csr__read__h606456 or - scounteren_csr__read__h606509 or + fflags_csr__read__h606124 or + frm_csr__read__h606135 or + fcsr_csr__read__h606149 or + sstatus_csr__read__h606345 or + sie_csr__read__h606414 or + stvec_csr__read__h606457 or + scounteren_csr__read__h606510 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606647 or + scause_csr__read__h606648 or csrf_stval_csr or - sip_csr__read__h606786 or - satp_csr__read__h606849 or - mstatus_csr__read__h606992 or - medeleg_csr__read__h607140 or - mideleg_csr__read__h607235 or - mie_csr__read__h607366 or - mtvec_csr__read__h607448 or - mcounteren_csr__read__h607540 or + sip_csr__read__h606787 or + satp_csr__read__h606850 or + mstatus_csr__read__h606993 or + medeleg_csr__read__h607141 or + mideleg_csr__read__h607236 or + mie_csr__read__h607367 or + mtvec_csr__read__h607449 or + mcounteren_csr__read__h607541 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607795 or + mcause_csr__read__h607796 or csrf_mtval_csr or - mip_csr__read__h608035 or - x_reg_ifc__read__h606253 or - n__read__h608139 or n__read__h608330 or csrf_time_reg) + mip_csr__read__h608036 or + x_reg_ifc__read__h606254 or + n__read__h608140 or n__read__h608331 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h629405 = fflags_csr__read__h606123; - 12'd2: rVal1__h629405 = frm_csr__read__h606134; - 12'd3: rVal1__h629405 = fcsr_csr__read__h606148; - 12'd256: rVal1__h629405 = sstatus_csr__read__h606344; - 12'd260: rVal1__h629405 = sie_csr__read__h606413; - 12'd261: rVal1__h629405 = stvec_csr__read__h606456; - 12'd262: rVal1__h629405 = scounteren_csr__read__h606509; - 12'd320: rVal1__h629405 = csrf_sscratch_csr; - 12'd321: rVal1__h629405 = csrf_sepc_csr; - 12'd322: rVal1__h629405 = scause_csr__read__h606647; - 12'd323: rVal1__h629405 = csrf_stval_csr; - 12'd324: rVal1__h629405 = sip_csr__read__h606786; - 12'd384: rVal1__h629405 = satp_csr__read__h606849; - 12'd768: rVal1__h629405 = mstatus_csr__read__h606992; - 12'd769: rVal1__h629405 = 64'h8000000000141129; - 12'd770: rVal1__h629405 = medeleg_csr__read__h607140; - 12'd771: rVal1__h629405 = mideleg_csr__read__h607235; - 12'd772: rVal1__h629405 = mie_csr__read__h607366; - 12'd773: rVal1__h629405 = mtvec_csr__read__h607448; - 12'd774: rVal1__h629405 = mcounteren_csr__read__h607540; - 12'd832: rVal1__h629405 = csrf_mscratch_csr; - 12'd833: rVal1__h629405 = csrf_mepc_csr; - 12'd834: rVal1__h629405 = mcause_csr__read__h607795; - 12'd835: rVal1__h629405 = csrf_mtval_csr; - 12'd836: rVal1__h629405 = mip_csr__read__h608035; - 12'd2048: rVal1__h629405 = 64'd0; - 12'd2049: rVal1__h629405 = x_reg_ifc__read__h606253; - 12'd2816, 12'd3072: rVal1__h629405 = n__read__h608139; - 12'd2818, 12'd3074: rVal1__h629405 = n__read__h608330; - 12'd3073: rVal1__h629405 = csrf_time_reg; - default: rVal1__h629405 = 64'd0; + 12'd1: rVal1__h629404 = fflags_csr__read__h606124; + 12'd2: rVal1__h629404 = frm_csr__read__h606135; + 12'd3: rVal1__h629404 = fcsr_csr__read__h606149; + 12'd256: rVal1__h629404 = sstatus_csr__read__h606345; + 12'd260: rVal1__h629404 = sie_csr__read__h606414; + 12'd261: rVal1__h629404 = stvec_csr__read__h606457; + 12'd262: rVal1__h629404 = scounteren_csr__read__h606510; + 12'd320: rVal1__h629404 = csrf_sscratch_csr; + 12'd321: rVal1__h629404 = csrf_sepc_csr; + 12'd322: rVal1__h629404 = scause_csr__read__h606648; + 12'd323: rVal1__h629404 = csrf_stval_csr; + 12'd324: rVal1__h629404 = sip_csr__read__h606787; + 12'd384: rVal1__h629404 = satp_csr__read__h606850; + 12'd768: rVal1__h629404 = mstatus_csr__read__h606993; + 12'd769: rVal1__h629404 = 64'h8000000000141129; + 12'd770: rVal1__h629404 = medeleg_csr__read__h607141; + 12'd771: rVal1__h629404 = mideleg_csr__read__h607236; + 12'd772: rVal1__h629404 = mie_csr__read__h607367; + 12'd773: rVal1__h629404 = mtvec_csr__read__h607449; + 12'd774: rVal1__h629404 = mcounteren_csr__read__h607541; + 12'd832: rVal1__h629404 = csrf_mscratch_csr; + 12'd833: rVal1__h629404 = csrf_mepc_csr; + 12'd834: rVal1__h629404 = mcause_csr__read__h607796; + 12'd835: rVal1__h629404 = csrf_mtval_csr; + 12'd836: rVal1__h629404 = mip_csr__read__h608036; + 12'd2048: rVal1__h629404 = 64'd0; + 12'd2049: rVal1__h629404 = x_reg_ifc__read__h606254; + 12'd2816, 12'd3072: rVal1__h629404 = n__read__h608140; + 12'd2818, 12'd3074: rVal1__h629404 = n__read__h608331; + 12'd3073: rVal1__h629404 = csrf_time_reg; + default: rVal1__h629404 = 64'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h388976 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h388974 = 8'd255; 3'd2: - _theResult___fst_exp__h388976 = + _theResult___fst_exp__h388974 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h388976 = + _theResult___fst_exp__h388974 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h388976 = 8'd254; - default: _theResult___fst_exp__h388976 = 8'd0; + 3'd4: _theResult___fst_exp__h388974 = 8'd254; + default: _theResult___fst_exp__h388974 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h343284 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h343282 = 8'd255; 3'd2: - _theResult___fst_exp__h343284 = + _theResult___fst_exp__h343282 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h343284 = + _theResult___fst_exp__h343282 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h343284 = 8'd254; - default: _theResult___fst_exp__h343284 = 8'd0; + 3'd4: _theResult___fst_exp__h343282 = 8'd254; + default: _theResult___fst_exp__h343282 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h343285 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h343283 = 23'd0; 3'd2: - _theResult___fst_sfd__h343285 = + _theResult___fst_sfd__h343283 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h343285 = + _theResult___fst_sfd__h343283 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h343285 = 23'd8388607; - default: _theResult___fst_sfd__h343285 = 23'd0; + 3'd4: _theResult___fst_sfd__h343283 = 23'd8388607; + default: _theResult___fst_sfd__h343283 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h388977 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h388975 = 23'd0; 3'd2: - _theResult___fst_sfd__h388977 = + _theResult___fst_sfd__h388975 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h388977 = + _theResult___fst_sfd__h388975 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h388977 = 23'd8388607; - default: _theResult___fst_sfd__h388977 = 23'd0; + 3'd4: _theResult___fst_sfd__h388975 = 23'd8388607; + default: _theResult___fst_sfd__h388975 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h434664 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h434662 = 8'd255; 3'd2: - _theResult___fst_exp__h434664 = + _theResult___fst_exp__h434662 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h434664 = + _theResult___fst_exp__h434662 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h434664 = 8'd254; - default: _theResult___fst_exp__h434664 = 8'd0; + 3'd4: _theResult___fst_exp__h434662 = 8'd254; + default: _theResult___fst_exp__h434662 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h434665 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h434663 = 23'd0; 3'd2: - _theResult___fst_sfd__h434665 = + _theResult___fst_sfd__h434663 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h434665 = + _theResult___fst_sfd__h434663 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h434665 = 23'd8388607; - default: _theResult___fst_sfd__h434665 = 23'd0; + 3'd4: _theResult___fst_sfd__h434663 = 23'd8388607; + default: _theResult___fst_sfd__h434663 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -30124,16 +30124,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h692204 = commitStage_commitTrap[3:0]; - default: i__h692204 = 4'd15; + i__h692202 = commitStage_commitTrap[3:0]; + default: i__h692202 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11: - i__h692364 = commitStage_commitTrap[3:0]; - default: i__h692364 = 4'd14; + i__h692362 = commitStage_commitTrap[3:0]; + default: i__h692362 = 4'd14; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -30374,446 +30374,446 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352021 or - _theResult___fst_exp__h360069 or - out_exp__h360514 or _theResult___exp__h360511) + always@(guard__h352019 or + _theResult___fst_exp__h360067 or + out_exp__h360512 or _theResult___exp__h360509) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = - _theResult___fst_exp__h360069; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = + _theResult___fst_exp__h360067; 2'b10: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = - out_exp__h360514; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = + out_exp__h360512; 2'b11: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = - _theResult___exp__h360511; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = + _theResult___exp__h360509; endcase end - always@(guard__h352021 or - _theResult___fst_exp__h360069 or _theResult___exp__h360511) + always@(guard__h352019 or + _theResult___fst_exp__h360067 or _theResult___exp__h360509) begin - case (guard__h352021) + case (guard__h352019) 2'b0: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = - _theResult___fst_exp__h360069; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 = + _theResult___fst_exp__h360067; 2'b01, 2'b10, 2'b11: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = - _theResult___exp__h360511; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 = + _theResult___exp__h360509; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 or - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 or + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 or + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or - _theResult___fst_exp__h360069) + _theResult___fst_exp__h360067) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h360589 = - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24; + _theResult___fst_exp__h360587 = + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24; 3'd1: - _theResult___fst_exp__h360589 = - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25; + _theResult___fst_exp__h360587 = + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25; 3'd2: - _theResult___fst_exp__h360589 = + _theResult___fst_exp__h360587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528; 3'd3: - _theResult___fst_exp__h360589 = + _theResult___fst_exp__h360587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530; - 3'd4: _theResult___fst_exp__h360589 = _theResult___fst_exp__h360069; - default: _theResult___fst_exp__h360589 = 8'd0; + 3'd4: _theResult___fst_exp__h360587 = _theResult___fst_exp__h360067; + default: _theResult___fst_exp__h360587 = 8'd0; endcase end - always@(guard__h343312 or - _theResult___fst_exp__h351413 or - out_exp__h351932 or _theResult___exp__h351929) + always@(guard__h343310 or + _theResult___fst_exp__h351411 or + out_exp__h351930 or _theResult___exp__h351927) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = - _theResult___fst_exp__h351413; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = + _theResult___fst_exp__h351411; 2'b10: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = - out_exp__h351932; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = + out_exp__h351930; 2'b11: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = - _theResult___exp__h351929; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = + _theResult___exp__h351927; endcase end - always@(guard__h343312 or - _theResult___fst_exp__h351413 or _theResult___exp__h351929) + always@(guard__h343310 or + _theResult___fst_exp__h351411 or _theResult___exp__h351927) begin - case (guard__h343312) + case (guard__h343310) 2'b0: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = - _theResult___fst_exp__h351413; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 = + _theResult___fst_exp__h351411; 2'b01, 2'b10, 2'b11: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = - _theResult___exp__h351929; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 = + _theResult___exp__h351927; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 or - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 or + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 or + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or - _theResult___fst_exp__h351413) + _theResult___fst_exp__h351411) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h352007 = - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26; + _theResult___fst_exp__h352005 = + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26; 3'd1: - _theResult___fst_exp__h352007 = - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27; + _theResult___fst_exp__h352005 = + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27; 3'd2: - _theResult___fst_exp__h352007 = + _theResult___fst_exp__h352005 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306; 3'd3: - _theResult___fst_exp__h352007 = + _theResult___fst_exp__h352005 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309; - 3'd4: _theResult___fst_exp__h352007 = _theResult___fst_exp__h351413; - default: _theResult___fst_exp__h352007 = 8'd0; + 3'd4: _theResult___fst_exp__h352005 = _theResult___fst_exp__h351411; + default: _theResult___fst_exp__h352005 = 8'd0; endcase end - always@(guard__h360951 or - _theResult___fst_exp__h369179 or - out_exp__h369698 or _theResult___exp__h369695) + always@(guard__h360949 or + _theResult___fst_exp__h369177 or + out_exp__h369696 or _theResult___exp__h369693) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = - _theResult___fst_exp__h369179; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = + _theResult___fst_exp__h369177; 2'b10: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = - out_exp__h369698; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = + out_exp__h369696; 2'b11: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = - _theResult___exp__h369695; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = + _theResult___exp__h369693; endcase end - always@(guard__h360951 or - _theResult___fst_exp__h369179 or _theResult___exp__h369695) + always@(guard__h360949 or + _theResult___fst_exp__h369177 or _theResult___exp__h369693) begin - case (guard__h360951) + case (guard__h360949) 2'b0: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = - _theResult___fst_exp__h369179; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 = + _theResult___fst_exp__h369177; 2'b01, 2'b10, 2'b11: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = - _theResult___exp__h369695; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 = + _theResult___exp__h369693; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 or - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 or + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 or + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or - _theResult___fst_exp__h369179) + _theResult___fst_exp__h369177) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h369773 = - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32; + _theResult___fst_exp__h369771 = + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32; 3'd1: - _theResult___fst_exp__h369773 = - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33; + _theResult___fst_exp__h369771 = + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33; 3'd2: - _theResult___fst_exp__h369773 = + _theResult___fst_exp__h369771 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853; 3'd3: - _theResult___fst_exp__h369773 = + _theResult___fst_exp__h369771 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855; - 3'd4: _theResult___fst_exp__h369773 = _theResult___fst_exp__h369179; - default: _theResult___fst_exp__h369773 = 8'd0; + 3'd4: _theResult___fst_exp__h369771 = _theResult___fst_exp__h369177; + default: _theResult___fst_exp__h369771 = 8'd0; endcase end - always@(guard__h369787 or - _theResult___fst_exp__h377864 or - out_exp__h378334 or _theResult___exp__h378331) + always@(guard__h369785 or + _theResult___fst_exp__h377862 or + out_exp__h378332 or _theResult___exp__h378329) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = - _theResult___fst_exp__h377864; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = + _theResult___fst_exp__h377862; 2'b10: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = - out_exp__h378334; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = + out_exp__h378332; 2'b11: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = - _theResult___exp__h378331; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = + _theResult___exp__h378329; endcase end - always@(guard__h369787 or - _theResult___fst_exp__h377864 or _theResult___exp__h378331) + always@(guard__h369785 or + _theResult___fst_exp__h377862 or _theResult___exp__h378329) begin - case (guard__h369787) + case (guard__h369785) 2'b0: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = - _theResult___fst_exp__h377864; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 = + _theResult___fst_exp__h377862; 2'b01, 2'b10, 2'b11: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = - _theResult___exp__h378331; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 = + _theResult___exp__h378329; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 or - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 or + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 or + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or - _theResult___fst_exp__h377864) + _theResult___fst_exp__h377862) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h378409 = - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37; + _theResult___fst_exp__h378407 = + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37; 3'd1: - _theResult___fst_exp__h378409 = - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38; + _theResult___fst_exp__h378407 = + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38; 3'd2: - _theResult___fst_exp__h378409 = + _theResult___fst_exp__h378407 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922; 3'd3: - _theResult___fst_exp__h378409 = + _theResult___fst_exp__h378407 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924; - 3'd4: _theResult___fst_exp__h378409 = _theResult___fst_exp__h377864; - default: _theResult___fst_exp__h378409 = 8'd0; + 3'd4: _theResult___fst_exp__h378407 = _theResult___fst_exp__h377862; + default: _theResult___fst_exp__h378407 = 8'd0; endcase end - always@(guard__h352021 or - _theResult___snd__h360020 or - out_sfd__h360515 or _theResult___sfd__h360512) + always@(guard__h352019 or + _theResult___snd__h360018 or + out_sfd__h360513 or _theResult___sfd__h360510) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = - _theResult___snd__h360020[56:34]; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = + _theResult___snd__h360018[56:34]; 2'b10: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = - out_sfd__h360515; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = + out_sfd__h360513; 2'b11: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = - _theResult___sfd__h360512; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = + _theResult___sfd__h360510; endcase end - always@(guard__h352021 or - _theResult___snd__h360020 or _theResult___sfd__h360512) + always@(guard__h352019 or + _theResult___snd__h360018 or _theResult___sfd__h360510) begin - case (guard__h352021) + case (guard__h352019) 2'b0: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = - _theResult___snd__h360020[56:34]; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 = + _theResult___snd__h360018[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = - _theResult___sfd__h360512; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 = + _theResult___sfd__h360510; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 or - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 or + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 or + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or - _theResult___snd__h360020) + _theResult___snd__h360018) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h360590 = - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39; + _theResult___fst_sfd__h360588 = + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39; 3'd1: - _theResult___fst_sfd__h360590 = - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40; + _theResult___fst_sfd__h360588 = + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40; 3'd2: - _theResult___fst_sfd__h360590 = + _theResult___fst_sfd__h360588 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972; 3'd3: - _theResult___fst_sfd__h360590 = + _theResult___fst_sfd__h360588 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974; - 3'd4: _theResult___fst_sfd__h360590 = _theResult___snd__h360020[56:34]; - default: _theResult___fst_sfd__h360590 = 23'd0; + 3'd4: _theResult___fst_sfd__h360588 = _theResult___snd__h360018[56:34]; + default: _theResult___fst_sfd__h360588 = 23'd0; endcase end - always@(guard__h343312 or - sfdin__h351407 or out_sfd__h351933 or _theResult___sfd__h351930) + always@(guard__h343310 or + sfdin__h351405 or out_sfd__h351931 or _theResult___sfd__h351928) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = - sfdin__h351407[56:34]; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = + sfdin__h351405[56:34]; 2'b10: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = - out_sfd__h351933; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = + out_sfd__h351931; 2'b11: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = - _theResult___sfd__h351930; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = + _theResult___sfd__h351928; endcase end - always@(guard__h343312 or sfdin__h351407 or _theResult___sfd__h351930) + always@(guard__h343310 or sfdin__h351405 or _theResult___sfd__h351928) begin - case (guard__h343312) + case (guard__h343310) 2'b0: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = - sfdin__h351407[56:34]; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 = + sfdin__h351405[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h351930; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h351928; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 or - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 or + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 or + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or - sfdin__h351407) + sfdin__h351405) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h352008 = - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41; + _theResult___fst_sfd__h352006 = + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41; 3'd1: - _theResult___fst_sfd__h352008 = - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42; + _theResult___fst_sfd__h352006 = + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42; 3'd2: - _theResult___fst_sfd__h352008 = + _theResult___fst_sfd__h352006 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953; 3'd3: - _theResult___fst_sfd__h352008 = + _theResult___fst_sfd__h352006 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955; - 3'd4: _theResult___fst_sfd__h352008 = sfdin__h351407[56:34]; - default: _theResult___fst_sfd__h352008 = 23'd0; + 3'd4: _theResult___fst_sfd__h352006 = sfdin__h351405[56:34]; + default: _theResult___fst_sfd__h352006 = 23'd0; endcase end - always@(guard__h360951 or - sfdin__h369173 or out_sfd__h369699 or _theResult___sfd__h369696) + always@(guard__h360949 or + sfdin__h369171 or out_sfd__h369697 or _theResult___sfd__h369694) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = - sfdin__h369173[56:34]; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = + sfdin__h369171[56:34]; 2'b10: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = - out_sfd__h369699; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = + out_sfd__h369697; 2'b11: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h369696; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h369694; endcase end - always@(guard__h360951 or sfdin__h369173 or _theResult___sfd__h369696) + always@(guard__h360949 or sfdin__h369171 or _theResult___sfd__h369694) begin - case (guard__h360951) + case (guard__h360949) 2'b0: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = - sfdin__h369173[56:34]; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 = + sfdin__h369171[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h369696; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h369694; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 or - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 or + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 or + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or - sfdin__h369173) + sfdin__h369171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h369774 = - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43; + _theResult___fst_sfd__h369772 = + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43; 3'd1: - _theResult___fst_sfd__h369774 = - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44; + _theResult___fst_sfd__h369772 = + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44; 3'd2: - _theResult___fst_sfd__h369774 = + _theResult___fst_sfd__h369772 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999; 3'd3: - _theResult___fst_sfd__h369774 = + _theResult___fst_sfd__h369772 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001; - 3'd4: _theResult___fst_sfd__h369774 = sfdin__h369173[56:34]; - default: _theResult___fst_sfd__h369774 = 23'd0; + 3'd4: _theResult___fst_sfd__h369772 = sfdin__h369171[56:34]; + default: _theResult___fst_sfd__h369772 = 23'd0; endcase end - always@(guard__h369787 or - _theResult___snd__h377810 or - out_sfd__h378335 or _theResult___sfd__h378332) + always@(guard__h369785 or + _theResult___snd__h377808 or + out_sfd__h378333 or _theResult___sfd__h378330) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = - _theResult___snd__h377810[56:34]; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = + _theResult___snd__h377808[56:34]; 2'b10: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = - out_sfd__h378335; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = + out_sfd__h378333; 2'b11: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = - _theResult___sfd__h378332; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = + _theResult___sfd__h378330; endcase end - always@(guard__h369787 or - _theResult___snd__h377810 or _theResult___sfd__h378332) + always@(guard__h369785 or + _theResult___snd__h377808 or _theResult___sfd__h378330) begin - case (guard__h369787) + case (guard__h369785) 2'b0: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = - _theResult___snd__h377810[56:34]; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 = + _theResult___snd__h377808[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = - _theResult___sfd__h378332; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 = + _theResult___sfd__h378330; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 or - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 or + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 or + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or - _theResult___snd__h377810) + _theResult___snd__h377808) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h378410 = - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45; + _theResult___fst_sfd__h378408 = + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45; 3'd1: - _theResult___fst_sfd__h378410 = - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46; + _theResult___fst_sfd__h378408 = + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46; 3'd2: - _theResult___fst_sfd__h378410 = + _theResult___fst_sfd__h378408 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; 3'd3: - _theResult___fst_sfd__h378410 = + _theResult___fst_sfd__h378408 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; - 3'd4: _theResult___fst_sfd__h378410 = _theResult___snd__h377810[56:34]; - default: _theResult___fst_sfd__h378410 = 23'd0; + 3'd4: _theResult___fst_sfd__h378408 = _theResult___snd__h377808[56:34]; + default: _theResult___fst_sfd__h378408 = 23'd0; endcase end - always@(guard__h343312 or + always@(guard__h343310 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01, 2'b10: - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = - guard__h343312 == 2'b11 && + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + guard__h343310 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or - guard__h343312) + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or + guard__h343310) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - (guard__h343312 == 2'b0) ? + (guard__h343310 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h343312 == 2'b01 || guard__h343312 == 2'b10 || - guard__h343312 == 2'b11) && + (guard__h343310 == 2'b01 || guard__h343310 == 2'b10 || + guard__h343310 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = @@ -30824,34 +30824,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352021 or + always@(guard__h352019 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01, 2'b10: - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h352021 == 2'b11 && + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h352019 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h352021) + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h352019) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - (guard__h352021 == 2'b0) ? + (guard__h352019 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h352021 == 2'b01 || guard__h352021 == 2'b10 || - guard__h352021 == 2'b11) && + (guard__h352019 == 2'b01 || guard__h352019 == 2'b10 || + guard__h352019 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = @@ -30862,34 +30862,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h343312 or + always@(guard__h343310 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01, 2'b10: - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h343312 != 2'b11 || + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h343310 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h343312) + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h343310) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - (guard__h343312 == 2'b0) ? + (guard__h343310 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h343312 != 2'b01 && guard__h343312 != 2'b10 && - guard__h343312 != 2'b11 || + guard__h343310 != 2'b01 && guard__h343310 != 2'b10 && + guard__h343310 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = @@ -30900,34 +30900,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352021 or + always@(guard__h352019 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01, 2'b10: - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = - guard__h352021 != 2'b11 || + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + guard__h352019 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or - guard__h352021) + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or + guard__h352019) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - (guard__h352021 == 2'b0) ? + (guard__h352019 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h352021 != 2'b01 && guard__h352021 != 2'b10 && - guard__h352021 != 2'b11 || + guard__h352019 != 2'b01 && guard__h352019 != 2'b10 && + guard__h352019 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = @@ -30938,34 +30938,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360951 or + always@(guard__h360949 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01, 2'b10: - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = - guard__h360951 == 2'b11 && + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + guard__h360949 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or - guard__h360951) + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or + guard__h360949) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - (guard__h360951 == 2'b0) ? + (guard__h360949 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h360951 == 2'b01 || guard__h360951 == 2'b10 || - guard__h360951 == 2'b11) && + (guard__h360949 == 2'b01 || guard__h360949 == 2'b10 || + guard__h360949 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = @@ -30976,34 +30976,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369787 or + always@(guard__h369785 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01, 2'b10: - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h369787 == 2'b11 && + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h369785 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h369787) + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h369785) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - (guard__h369787 == 2'b0) ? + (guard__h369785 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h369787 == 2'b01 || guard__h369787 == 2'b10 || - guard__h369787 == 2'b11) && + (guard__h369785 == 2'b01 || guard__h369785 == 2'b10 || + guard__h369785 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = @@ -31014,34 +31014,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360951 or + always@(guard__h360949 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01, 2'b10: - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h360951 != 2'b11 || + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h360949 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h360951) + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h360949) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - (guard__h360951 == 2'b0) ? + (guard__h360949 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h360951 != 2'b01 && guard__h360951 != 2'b10 && - guard__h360951 != 2'b11 || + guard__h360949 != 2'b01 && guard__h360949 != 2'b10 && + guard__h360949 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = @@ -31052,34 +31052,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369787 or + always@(guard__h369785 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01, 2'b10: - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = - guard__h369787 != 2'b11 || + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + guard__h369785 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or - guard__h369787) + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or + guard__h369785) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - (guard__h369787 == 2'b0) ? + (guard__h369785 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h369787 != 2'b01 && guard__h369787 != 2'b10 && - guard__h369787 != 2'b11 || + guard__h369785 != 2'b01 && guard__h369785 != 2'b10 && + guard__h369785 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = @@ -31103,446 +31103,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h397711 or - _theResult___fst_exp__h405759 or - out_exp__h406204 or _theResult___exp__h406201) + always@(guard__h397709 or + _theResult___fst_exp__h405757 or + out_exp__h406202 or _theResult___exp__h406199) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = - _theResult___fst_exp__h405759; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = + _theResult___fst_exp__h405757; 2'b10: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = - out_exp__h406204; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = + out_exp__h406202; 2'b11: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = - _theResult___exp__h406201; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = + _theResult___exp__h406199; endcase end - always@(guard__h397711 or - _theResult___fst_exp__h405759 or _theResult___exp__h406201) + always@(guard__h397709 or + _theResult___fst_exp__h405757 or _theResult___exp__h406199) begin - case (guard__h397711) + case (guard__h397709) 2'b0: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = - _theResult___fst_exp__h405759; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 = + _theResult___fst_exp__h405757; 2'b01, 2'b10, 2'b11: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = - _theResult___exp__h406201; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 = + _theResult___exp__h406199; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 or - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 or + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 or + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or - _theResult___fst_exp__h405759) + _theResult___fst_exp__h405757) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h406279 = - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59; + _theResult___fst_exp__h406277 = + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59; 3'd1: - _theResult___fst_exp__h406279 = - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60; + _theResult___fst_exp__h406277 = + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60; 3'd2: - _theResult___fst_exp__h406279 = + _theResult___fst_exp__h406277 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920; 3'd3: - _theResult___fst_exp__h406279 = + _theResult___fst_exp__h406277 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922; - 3'd4: _theResult___fst_exp__h406279 = _theResult___fst_exp__h405759; - default: _theResult___fst_exp__h406279 = 8'd0; + 3'd4: _theResult___fst_exp__h406277 = _theResult___fst_exp__h405757; + default: _theResult___fst_exp__h406277 = 8'd0; endcase end - always@(guard__h389004 or - _theResult___fst_exp__h397103 or - out_exp__h397622 or _theResult___exp__h397619) + always@(guard__h389002 or + _theResult___fst_exp__h397101 or + out_exp__h397620 or _theResult___exp__h397617) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = - _theResult___fst_exp__h397103; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = + _theResult___fst_exp__h397101; 2'b10: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = - out_exp__h397622; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = + out_exp__h397620; 2'b11: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = - _theResult___exp__h397619; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = + _theResult___exp__h397617; endcase end - always@(guard__h389004 or - _theResult___fst_exp__h397103 or _theResult___exp__h397619) + always@(guard__h389002 or + _theResult___fst_exp__h397101 or _theResult___exp__h397617) begin - case (guard__h389004) + case (guard__h389002) 2'b0: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = - _theResult___fst_exp__h397103; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 = + _theResult___fst_exp__h397101; 2'b01, 2'b10, 2'b11: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = - _theResult___exp__h397619; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 = + _theResult___exp__h397617; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 or - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 or + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 or + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or - _theResult___fst_exp__h397103) + _theResult___fst_exp__h397101) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h397697 = - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61; + _theResult___fst_exp__h397695 = + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61; 3'd1: - _theResult___fst_exp__h397697 = - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62; + _theResult___fst_exp__h397695 = + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62; 3'd2: - _theResult___fst_exp__h397697 = + _theResult___fst_exp__h397695 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698; 3'd3: - _theResult___fst_exp__h397697 = + _theResult___fst_exp__h397695 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701; - 3'd4: _theResult___fst_exp__h397697 = _theResult___fst_exp__h397103; - default: _theResult___fst_exp__h397697 = 8'd0; + 3'd4: _theResult___fst_exp__h397695 = _theResult___fst_exp__h397101; + default: _theResult___fst_exp__h397695 = 8'd0; endcase end - always@(guard__h406641 or - _theResult___fst_exp__h414869 or - out_exp__h415388 or _theResult___exp__h415385) + always@(guard__h406639 or + _theResult___fst_exp__h414867 or + out_exp__h415386 or _theResult___exp__h415383) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = - _theResult___fst_exp__h414869; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = + _theResult___fst_exp__h414867; 2'b10: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = - out_exp__h415388; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = + out_exp__h415386; 2'b11: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = - _theResult___exp__h415385; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = + _theResult___exp__h415383; endcase end - always@(guard__h406641 or - _theResult___fst_exp__h414869 or _theResult___exp__h415385) + always@(guard__h406639 or + _theResult___fst_exp__h414867 or _theResult___exp__h415383) begin - case (guard__h406641) + case (guard__h406639) 2'b0: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = - _theResult___fst_exp__h414869; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 = + _theResult___fst_exp__h414867; 2'b01, 2'b10, 2'b11: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = - _theResult___exp__h415385; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 = + _theResult___exp__h415383; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 or - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 or + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 or + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or - _theResult___fst_exp__h414869) + _theResult___fst_exp__h414867) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h415463 = - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67; + _theResult___fst_exp__h415461 = + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67; 3'd1: - _theResult___fst_exp__h415463 = - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68; + _theResult___fst_exp__h415461 = + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68; 3'd2: - _theResult___fst_exp__h415463 = + _theResult___fst_exp__h415461 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245; 3'd3: - _theResult___fst_exp__h415463 = + _theResult___fst_exp__h415461 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247; - 3'd4: _theResult___fst_exp__h415463 = _theResult___fst_exp__h414869; - default: _theResult___fst_exp__h415463 = 8'd0; + 3'd4: _theResult___fst_exp__h415461 = _theResult___fst_exp__h414867; + default: _theResult___fst_exp__h415461 = 8'd0; endcase end - always@(guard__h415477 or - _theResult___fst_exp__h423554 or - out_exp__h424024 or _theResult___exp__h424021) + always@(guard__h415475 or + _theResult___fst_exp__h423552 or + out_exp__h424022 or _theResult___exp__h424019) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = - _theResult___fst_exp__h423554; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = + _theResult___fst_exp__h423552; 2'b10: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = - out_exp__h424024; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = + out_exp__h424022; 2'b11: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = - _theResult___exp__h424021; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = + _theResult___exp__h424019; endcase end - always@(guard__h415477 or - _theResult___fst_exp__h423554 or _theResult___exp__h424021) + always@(guard__h415475 or + _theResult___fst_exp__h423552 or _theResult___exp__h424019) begin - case (guard__h415477) + case (guard__h415475) 2'b0: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = - _theResult___fst_exp__h423554; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 = + _theResult___fst_exp__h423552; 2'b01, 2'b10, 2'b11: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = - _theResult___exp__h424021; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 = + _theResult___exp__h424019; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 or - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 or + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 or + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or - _theResult___fst_exp__h423554) + _theResult___fst_exp__h423552) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h424099 = - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72; + _theResult___fst_exp__h424097 = + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72; 3'd1: - _theResult___fst_exp__h424099 = - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73; + _theResult___fst_exp__h424097 = + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73; 3'd2: - _theResult___fst_exp__h424099 = + _theResult___fst_exp__h424097 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314; 3'd3: - _theResult___fst_exp__h424099 = + _theResult___fst_exp__h424097 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316; - 3'd4: _theResult___fst_exp__h424099 = _theResult___fst_exp__h423554; - default: _theResult___fst_exp__h424099 = 8'd0; + 3'd4: _theResult___fst_exp__h424097 = _theResult___fst_exp__h423552; + default: _theResult___fst_exp__h424097 = 8'd0; endcase end - always@(guard__h397711 or - _theResult___snd__h405710 or - out_sfd__h406205 or _theResult___sfd__h406202) + always@(guard__h397709 or + _theResult___snd__h405708 or + out_sfd__h406203 or _theResult___sfd__h406200) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = - _theResult___snd__h405710[56:34]; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = + _theResult___snd__h405708[56:34]; 2'b10: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = - out_sfd__h406205; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = + out_sfd__h406203; 2'b11: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = - _theResult___sfd__h406202; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = + _theResult___sfd__h406200; endcase end - always@(guard__h397711 or - _theResult___snd__h405710 or _theResult___sfd__h406202) + always@(guard__h397709 or + _theResult___snd__h405708 or _theResult___sfd__h406200) begin - case (guard__h397711) + case (guard__h397709) 2'b0: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = - _theResult___snd__h405710[56:34]; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 = + _theResult___snd__h405708[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = - _theResult___sfd__h406202; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 = + _theResult___sfd__h406200; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 or - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 or + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 or + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or - _theResult___snd__h405710) + _theResult___snd__h405708) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h406280 = - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74; + _theResult___fst_sfd__h406278 = + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74; 3'd1: - _theResult___fst_sfd__h406280 = - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75; + _theResult___fst_sfd__h406278 = + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75; 3'd2: - _theResult___fst_sfd__h406280 = + _theResult___fst_sfd__h406278 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364; 3'd3: - _theResult___fst_sfd__h406280 = + _theResult___fst_sfd__h406278 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366; - 3'd4: _theResult___fst_sfd__h406280 = _theResult___snd__h405710[56:34]; - default: _theResult___fst_sfd__h406280 = 23'd0; + 3'd4: _theResult___fst_sfd__h406278 = _theResult___snd__h405708[56:34]; + default: _theResult___fst_sfd__h406278 = 23'd0; endcase end - always@(guard__h389004 or - sfdin__h397097 or out_sfd__h397623 or _theResult___sfd__h397620) + always@(guard__h389002 or + sfdin__h397095 or out_sfd__h397621 or _theResult___sfd__h397618) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = - sfdin__h397097[56:34]; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = + sfdin__h397095[56:34]; 2'b10: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = - out_sfd__h397623; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = + out_sfd__h397621; 2'b11: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h397620; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = + _theResult___sfd__h397618; endcase end - always@(guard__h389004 or sfdin__h397097 or _theResult___sfd__h397620) + always@(guard__h389002 or sfdin__h397095 or _theResult___sfd__h397618) begin - case (guard__h389004) + case (guard__h389002) 2'b0: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = - sfdin__h397097[56:34]; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 = + sfdin__h397095[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h397620; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h397618; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 or - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 or + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 or + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or - sfdin__h397097) + sfdin__h397095) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h397698 = - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76; + _theResult___fst_sfd__h397696 = + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76; 3'd1: - _theResult___fst_sfd__h397698 = - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h397696 = + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77; 3'd2: - _theResult___fst_sfd__h397698 = + _theResult___fst_sfd__h397696 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; 3'd3: - _theResult___fst_sfd__h397698 = + _theResult___fst_sfd__h397696 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; - 3'd4: _theResult___fst_sfd__h397698 = sfdin__h397097[56:34]; - default: _theResult___fst_sfd__h397698 = 23'd0; + 3'd4: _theResult___fst_sfd__h397696 = sfdin__h397095[56:34]; + default: _theResult___fst_sfd__h397696 = 23'd0; endcase end - always@(guard__h406641 or - sfdin__h414863 or out_sfd__h415389 or _theResult___sfd__h415386) + always@(guard__h406639 or + sfdin__h414861 or out_sfd__h415387 or _theResult___sfd__h415384) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = - sfdin__h414863[56:34]; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = + sfdin__h414861[56:34]; 2'b10: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = - out_sfd__h415389; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = + out_sfd__h415387; 2'b11: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h415386; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h415384; endcase end - always@(guard__h406641 or sfdin__h414863 or _theResult___sfd__h415386) + always@(guard__h406639 or sfdin__h414861 or _theResult___sfd__h415384) begin - case (guard__h406641) + case (guard__h406639) 2'b0: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = - sfdin__h414863[56:34]; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 = + sfdin__h414861[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h415386; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h415384; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 or - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 or + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 or + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or - sfdin__h414863) + sfdin__h414861) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h415464 = - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h415462 = + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78; 3'd1: - _theResult___fst_sfd__h415464 = - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h415462 = + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79; 3'd2: - _theResult___fst_sfd__h415464 = + _theResult___fst_sfd__h415462 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391; 3'd3: - _theResult___fst_sfd__h415464 = + _theResult___fst_sfd__h415462 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393; - 3'd4: _theResult___fst_sfd__h415464 = sfdin__h414863[56:34]; - default: _theResult___fst_sfd__h415464 = 23'd0; + 3'd4: _theResult___fst_sfd__h415462 = sfdin__h414861[56:34]; + default: _theResult___fst_sfd__h415462 = 23'd0; endcase end - always@(guard__h415477 or - _theResult___snd__h423500 or - out_sfd__h424025 or _theResult___sfd__h424022) + always@(guard__h415475 or + _theResult___snd__h423498 or + out_sfd__h424023 or _theResult___sfd__h424020) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = - _theResult___snd__h423500[56:34]; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = + _theResult___snd__h423498[56:34]; 2'b10: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = - out_sfd__h424025; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = + out_sfd__h424023; 2'b11: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = - _theResult___sfd__h424022; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = + _theResult___sfd__h424020; endcase end - always@(guard__h415477 or - _theResult___snd__h423500 or _theResult___sfd__h424022) + always@(guard__h415475 or + _theResult___snd__h423498 or _theResult___sfd__h424020) begin - case (guard__h415477) + case (guard__h415475) 2'b0: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = - _theResult___snd__h423500[56:34]; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 = + _theResult___snd__h423498[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = - _theResult___sfd__h424022; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 = + _theResult___sfd__h424020; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 or - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 or + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 or + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or - _theResult___snd__h423500) + _theResult___snd__h423498) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h424100 = - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80; + _theResult___fst_sfd__h424098 = + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80; 3'd1: - _theResult___fst_sfd__h424100 = - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81; + _theResult___fst_sfd__h424098 = + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81; 3'd2: - _theResult___fst_sfd__h424100 = + _theResult___fst_sfd__h424098 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410; 3'd3: - _theResult___fst_sfd__h424100 = + _theResult___fst_sfd__h424098 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412; - 3'd4: _theResult___fst_sfd__h424100 = _theResult___snd__h423500[56:34]; - default: _theResult___fst_sfd__h424100 = 23'd0; + 3'd4: _theResult___fst_sfd__h424098 = _theResult___snd__h423498[56:34]; + default: _theResult___fst_sfd__h424098 = 23'd0; endcase end - always@(guard__h389004 or + always@(guard__h389002 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01, 2'b10: - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = - guard__h389004 == 2'b11 && + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + guard__h389002 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or - guard__h389004) + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or + guard__h389002) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - (guard__h389004 == 2'b0) ? + (guard__h389002 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h389004 == 2'b01 || guard__h389004 == 2'b10 || - guard__h389004 == 2'b11) && + (guard__h389002 == 2'b01 || guard__h389002 == 2'b10 || + guard__h389002 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = @@ -31553,34 +31553,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h389004 or + always@(guard__h389002 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01, 2'b10: - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = - guard__h389004 != 2'b11 || + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + guard__h389002 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or - guard__h389004) + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or + guard__h389002) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - (guard__h389004 == 2'b0) ? + (guard__h389002 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h389004 != 2'b01 && guard__h389004 != 2'b10 && - guard__h389004 != 2'b11 || + guard__h389002 != 2'b01 && guard__h389002 != 2'b10 && + guard__h389002 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = @@ -31591,34 +31591,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397711 or + always@(guard__h397709 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01, 2'b10: - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = - guard__h397711 == 2'b11 && + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + guard__h397709 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or - guard__h397711) + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or + guard__h397709) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - (guard__h397711 == 2'b0) ? + (guard__h397709 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h397711 == 2'b01 || guard__h397711 == 2'b10 || - guard__h397711 == 2'b11) && + (guard__h397709 == 2'b01 || guard__h397709 == 2'b10 || + guard__h397709 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = @@ -31629,34 +31629,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397711 or + always@(guard__h397709 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01, 2'b10: - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = - guard__h397711 != 2'b11 || + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + guard__h397709 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or - guard__h397711) + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or + guard__h397709) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - (guard__h397711 == 2'b0) ? + (guard__h397709 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h397711 != 2'b01 && guard__h397711 != 2'b10 && - guard__h397711 != 2'b11 || + guard__h397709 != 2'b01 && guard__h397709 != 2'b10 && + guard__h397709 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = @@ -31667,34 +31667,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406641 or + always@(guard__h406639 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01, 2'b10: - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = - guard__h406641 == 2'b11 && + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + guard__h406639 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or - guard__h406641) + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or + guard__h406639) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - (guard__h406641 == 2'b0) ? + (guard__h406639 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h406641 == 2'b01 || guard__h406641 == 2'b10 || - guard__h406641 == 2'b11) && + (guard__h406639 == 2'b01 || guard__h406639 == 2'b10 || + guard__h406639 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = @@ -31705,34 +31705,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406641 or + always@(guard__h406639 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01, 2'b10: - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = - guard__h406641 != 2'b11 || + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + guard__h406639 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or - guard__h406641) + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or + guard__h406639) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - (guard__h406641 == 2'b0) ? + (guard__h406639 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h406641 != 2'b01 && guard__h406641 != 2'b10 && - guard__h406641 != 2'b11 || + guard__h406639 != 2'b01 && guard__h406639 != 2'b10 && + guard__h406639 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = @@ -31743,34 +31743,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415477 or + always@(guard__h415475 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01, 2'b10: - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = - guard__h415477 == 2'b11 && + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + guard__h415475 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or - guard__h415477) + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or + guard__h415475) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - (guard__h415477 == 2'b0) ? + (guard__h415475 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h415477 == 2'b01 || guard__h415477 == 2'b10 || - guard__h415477 == 2'b11) && + (guard__h415475 == 2'b01 || guard__h415475 == 2'b10 || + guard__h415475 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = @@ -31781,34 +31781,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415477 or + always@(guard__h415475 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01, 2'b10: - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = - guard__h415477 != 2'b11 || + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + guard__h415475 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or - guard__h415477) + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or + guard__h415475) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - (guard__h415477 == 2'b0) ? + (guard__h415475 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h415477 != 2'b01 && guard__h415477 != 2'b10 && - guard__h415477 != 2'b11 || + guard__h415475 != 2'b01 && guard__h415475 != 2'b10 && + guard__h415475 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = @@ -31845,446 +31845,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h443399 or - _theResult___fst_exp__h451447 or - out_exp__h451892 or _theResult___exp__h451889) + always@(guard__h443397 or + _theResult___fst_exp__h451445 or + out_exp__h451890 or _theResult___exp__h451887) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = - _theResult___fst_exp__h451447; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = + _theResult___fst_exp__h451445; 2'b10: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = - out_exp__h451892; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = + out_exp__h451890; 2'b11: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = - _theResult___exp__h451889; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = + _theResult___exp__h451887; endcase end - always@(guard__h443399 or - _theResult___fst_exp__h451447 or _theResult___exp__h451889) + always@(guard__h443397 or + _theResult___fst_exp__h451445 or _theResult___exp__h451887) begin - case (guard__h443399) + case (guard__h443397) 2'b0: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = - _theResult___fst_exp__h451447; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 = + _theResult___fst_exp__h451445; 2'b01, 2'b10, 2'b11: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = - _theResult___exp__h451889; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 = + _theResult___exp__h451887; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 or - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 or + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 or + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or - _theResult___fst_exp__h451447) + _theResult___fst_exp__h451445) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h451967 = - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94; + _theResult___fst_exp__h451965 = + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94; 3'd1: - _theResult___fst_exp__h451967 = - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95; + _theResult___fst_exp__h451965 = + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95; 3'd2: - _theResult___fst_exp__h451967 = + _theResult___fst_exp__h451965 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312; 3'd3: - _theResult___fst_exp__h451967 = + _theResult___fst_exp__h451965 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314; - 3'd4: _theResult___fst_exp__h451967 = _theResult___fst_exp__h451447; - default: _theResult___fst_exp__h451967 = 8'd0; + 3'd4: _theResult___fst_exp__h451965 = _theResult___fst_exp__h451445; + default: _theResult___fst_exp__h451965 = 8'd0; endcase end - always@(guard__h434692 or - _theResult___fst_exp__h442791 or - out_exp__h443310 or _theResult___exp__h443307) + always@(guard__h434690 or + _theResult___fst_exp__h442789 or + out_exp__h443308 or _theResult___exp__h443305) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = - _theResult___fst_exp__h442791; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = + _theResult___fst_exp__h442789; 2'b10: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = - out_exp__h443310; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = + out_exp__h443308; 2'b11: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = - _theResult___exp__h443307; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = + _theResult___exp__h443305; endcase end - always@(guard__h434692 or - _theResult___fst_exp__h442791 or _theResult___exp__h443307) + always@(guard__h434690 or + _theResult___fst_exp__h442789 or _theResult___exp__h443305) begin - case (guard__h434692) + case (guard__h434690) 2'b0: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = - _theResult___fst_exp__h442791; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 = + _theResult___fst_exp__h442789; 2'b01, 2'b10, 2'b11: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = - _theResult___exp__h443307; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 = + _theResult___exp__h443305; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 or - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 or + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 or + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or - _theResult___fst_exp__h442791) + _theResult___fst_exp__h442789) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h443385 = - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96; + _theResult___fst_exp__h443383 = + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96; 3'd1: - _theResult___fst_exp__h443385 = - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97; + _theResult___fst_exp__h443383 = + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97; 3'd2: - _theResult___fst_exp__h443385 = + _theResult___fst_exp__h443383 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090; 3'd3: - _theResult___fst_exp__h443385 = + _theResult___fst_exp__h443383 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093; - 3'd4: _theResult___fst_exp__h443385 = _theResult___fst_exp__h442791; - default: _theResult___fst_exp__h443385 = 8'd0; + 3'd4: _theResult___fst_exp__h443383 = _theResult___fst_exp__h442789; + default: _theResult___fst_exp__h443383 = 8'd0; endcase end - always@(guard__h452329 or - _theResult___fst_exp__h460557 or - out_exp__h461076 or _theResult___exp__h461073) + always@(guard__h452327 or + _theResult___fst_exp__h460555 or + out_exp__h461074 or _theResult___exp__h461071) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = - _theResult___fst_exp__h460557; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = + _theResult___fst_exp__h460555; 2'b10: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = - out_exp__h461076; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = + out_exp__h461074; 2'b11: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = - _theResult___exp__h461073; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = + _theResult___exp__h461071; endcase end - always@(guard__h452329 or - _theResult___fst_exp__h460557 or _theResult___exp__h461073) + always@(guard__h452327 or + _theResult___fst_exp__h460555 or _theResult___exp__h461071) begin - case (guard__h452329) + case (guard__h452327) 2'b0: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = - _theResult___fst_exp__h460557; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 = + _theResult___fst_exp__h460555; 2'b01, 2'b10, 2'b11: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = - _theResult___exp__h461073; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 = + _theResult___exp__h461071; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 or - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 or + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 or + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or - _theResult___fst_exp__h460557) + _theResult___fst_exp__h460555) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h461151 = - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102; + _theResult___fst_exp__h461149 = + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102; 3'd1: - _theResult___fst_exp__h461151 = - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103; + _theResult___fst_exp__h461149 = + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103; 3'd2: - _theResult___fst_exp__h461151 = + _theResult___fst_exp__h461149 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637; 3'd3: - _theResult___fst_exp__h461151 = + _theResult___fst_exp__h461149 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639; - 3'd4: _theResult___fst_exp__h461151 = _theResult___fst_exp__h460557; - default: _theResult___fst_exp__h461151 = 8'd0; + 3'd4: _theResult___fst_exp__h461149 = _theResult___fst_exp__h460555; + default: _theResult___fst_exp__h461149 = 8'd0; endcase end - always@(guard__h461165 or - _theResult___fst_exp__h469242 or - out_exp__h469712 or _theResult___exp__h469709) + always@(guard__h461163 or + _theResult___fst_exp__h469240 or + out_exp__h469710 or _theResult___exp__h469707) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = - _theResult___fst_exp__h469242; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = + _theResult___fst_exp__h469240; 2'b10: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = - out_exp__h469712; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = + out_exp__h469710; 2'b11: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = - _theResult___exp__h469709; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = + _theResult___exp__h469707; endcase end - always@(guard__h461165 or - _theResult___fst_exp__h469242 or _theResult___exp__h469709) + always@(guard__h461163 or + _theResult___fst_exp__h469240 or _theResult___exp__h469707) begin - case (guard__h461165) + case (guard__h461163) 2'b0: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = - _theResult___fst_exp__h469242; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 = + _theResult___fst_exp__h469240; 2'b01, 2'b10, 2'b11: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = - _theResult___exp__h469709; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 = + _theResult___exp__h469707; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 or - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 or + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 or + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or - _theResult___fst_exp__h469242) + _theResult___fst_exp__h469240) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h469787 = - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107; + _theResult___fst_exp__h469785 = + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107; 3'd1: - _theResult___fst_exp__h469787 = - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108; + _theResult___fst_exp__h469785 = + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108; 3'd2: - _theResult___fst_exp__h469787 = + _theResult___fst_exp__h469785 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706; 3'd3: - _theResult___fst_exp__h469787 = + _theResult___fst_exp__h469785 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708; - 3'd4: _theResult___fst_exp__h469787 = _theResult___fst_exp__h469242; - default: _theResult___fst_exp__h469787 = 8'd0; + 3'd4: _theResult___fst_exp__h469785 = _theResult___fst_exp__h469240; + default: _theResult___fst_exp__h469785 = 8'd0; endcase end - always@(guard__h443399 or - _theResult___snd__h451398 or - out_sfd__h451893 or _theResult___sfd__h451890) + always@(guard__h443397 or + _theResult___snd__h451396 or + out_sfd__h451891 or _theResult___sfd__h451888) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = - _theResult___snd__h451398[56:34]; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = + _theResult___snd__h451396[56:34]; 2'b10: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = - out_sfd__h451893; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = + out_sfd__h451891; 2'b11: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = - _theResult___sfd__h451890; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = + _theResult___sfd__h451888; endcase end - always@(guard__h443399 or - _theResult___snd__h451398 or _theResult___sfd__h451890) + always@(guard__h443397 or + _theResult___snd__h451396 or _theResult___sfd__h451888) begin - case (guard__h443399) + case (guard__h443397) 2'b0: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = - _theResult___snd__h451398[56:34]; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 = + _theResult___snd__h451396[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = - _theResult___sfd__h451890; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 = + _theResult___sfd__h451888; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 or - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 or + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 or + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or - _theResult___snd__h451398) + _theResult___snd__h451396) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h451968 = - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109; + _theResult___fst_sfd__h451966 = + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109; 3'd1: - _theResult___fst_sfd__h451968 = - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110; + _theResult___fst_sfd__h451966 = + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110; 3'd2: - _theResult___fst_sfd__h451968 = + _theResult___fst_sfd__h451966 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756; 3'd3: - _theResult___fst_sfd__h451968 = + _theResult___fst_sfd__h451966 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758; - 3'd4: _theResult___fst_sfd__h451968 = _theResult___snd__h451398[56:34]; - default: _theResult___fst_sfd__h451968 = 23'd0; + 3'd4: _theResult___fst_sfd__h451966 = _theResult___snd__h451396[56:34]; + default: _theResult___fst_sfd__h451966 = 23'd0; endcase end - always@(guard__h434692 or - sfdin__h442785 or out_sfd__h443311 or _theResult___sfd__h443308) + always@(guard__h434690 or + sfdin__h442783 or out_sfd__h443309 or _theResult___sfd__h443306) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = - sfdin__h442785[56:34]; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = + sfdin__h442783[56:34]; 2'b10: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = - out_sfd__h443311; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = + out_sfd__h443309; 2'b11: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = - _theResult___sfd__h443308; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = + _theResult___sfd__h443306; endcase end - always@(guard__h434692 or sfdin__h442785 or _theResult___sfd__h443308) + always@(guard__h434690 or sfdin__h442783 or _theResult___sfd__h443306) begin - case (guard__h434692) + case (guard__h434690) 2'b0: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = - sfdin__h442785[56:34]; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 = + sfdin__h442783[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h443308; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h443306; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 or - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 or + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 or + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or - sfdin__h442785) + sfdin__h442783) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h443386 = - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111; + _theResult___fst_sfd__h443384 = + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111; 3'd1: - _theResult___fst_sfd__h443386 = - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h443384 = + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112; 3'd2: - _theResult___fst_sfd__h443386 = + _theResult___fst_sfd__h443384 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737; 3'd3: - _theResult___fst_sfd__h443386 = + _theResult___fst_sfd__h443384 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739; - 3'd4: _theResult___fst_sfd__h443386 = sfdin__h442785[56:34]; - default: _theResult___fst_sfd__h443386 = 23'd0; + 3'd4: _theResult___fst_sfd__h443384 = sfdin__h442783[56:34]; + default: _theResult___fst_sfd__h443384 = 23'd0; endcase end - always@(guard__h452329 or - sfdin__h460551 or out_sfd__h461077 or _theResult___sfd__h461074) + always@(guard__h452327 or + sfdin__h460549 or out_sfd__h461075 or _theResult___sfd__h461072) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = - sfdin__h460551[56:34]; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = + sfdin__h460549[56:34]; 2'b10: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = - out_sfd__h461077; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = + out_sfd__h461075; 2'b11: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h461074; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h461072; endcase end - always@(guard__h452329 or sfdin__h460551 or _theResult___sfd__h461074) + always@(guard__h452327 or sfdin__h460549 or _theResult___sfd__h461072) begin - case (guard__h452329) + case (guard__h452327) 2'b0: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = - sfdin__h460551[56:34]; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 = + sfdin__h460549[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h461074; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h461072; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 or - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 or + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 or + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or - sfdin__h460551) + sfdin__h460549) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h461152 = - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h461150 = + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113; 3'd1: - _theResult___fst_sfd__h461152 = - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h461150 = + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114; 3'd2: - _theResult___fst_sfd__h461152 = + _theResult___fst_sfd__h461150 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783; 3'd3: - _theResult___fst_sfd__h461152 = + _theResult___fst_sfd__h461150 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785; - 3'd4: _theResult___fst_sfd__h461152 = sfdin__h460551[56:34]; - default: _theResult___fst_sfd__h461152 = 23'd0; + 3'd4: _theResult___fst_sfd__h461150 = sfdin__h460549[56:34]; + default: _theResult___fst_sfd__h461150 = 23'd0; endcase end - always@(guard__h461165 or - _theResult___snd__h469188 or - out_sfd__h469713 or _theResult___sfd__h469710) + always@(guard__h461163 or + _theResult___snd__h469186 or + out_sfd__h469711 or _theResult___sfd__h469708) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = - _theResult___snd__h469188[56:34]; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = + _theResult___snd__h469186[56:34]; 2'b10: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = - out_sfd__h469713; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = + out_sfd__h469711; 2'b11: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = - _theResult___sfd__h469710; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = + _theResult___sfd__h469708; endcase end - always@(guard__h461165 or - _theResult___snd__h469188 or _theResult___sfd__h469710) + always@(guard__h461163 or + _theResult___snd__h469186 or _theResult___sfd__h469708) begin - case (guard__h461165) + case (guard__h461163) 2'b0: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = - _theResult___snd__h469188[56:34]; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 = + _theResult___snd__h469186[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = - _theResult___sfd__h469710; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 = + _theResult___sfd__h469708; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 or - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 or + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 or + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or - _theResult___snd__h469188) + _theResult___snd__h469186) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h469788 = - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115; + _theResult___fst_sfd__h469786 = + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115; 3'd1: - _theResult___fst_sfd__h469788 = - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116; + _theResult___fst_sfd__h469786 = + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116; 3'd2: - _theResult___fst_sfd__h469788 = + _theResult___fst_sfd__h469786 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802; 3'd3: - _theResult___fst_sfd__h469788 = + _theResult___fst_sfd__h469786 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804; - 3'd4: _theResult___fst_sfd__h469788 = _theResult___snd__h469188[56:34]; - default: _theResult___fst_sfd__h469788 = 23'd0; + 3'd4: _theResult___fst_sfd__h469786 = _theResult___snd__h469186[56:34]; + default: _theResult___fst_sfd__h469786 = 23'd0; endcase end - always@(guard__h434692 or + always@(guard__h434690 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01, 2'b10: - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = - guard__h434692 == 2'b11 && + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + guard__h434690 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or - guard__h434692) + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or + guard__h434690) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - (guard__h434692 == 2'b0) ? + (guard__h434690 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h434692 == 2'b01 || guard__h434692 == 2'b10 || - guard__h434692 == 2'b11) && + (guard__h434690 == 2'b01 || guard__h434690 == 2'b10 || + guard__h434690 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = @@ -32295,34 +32295,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h434692 or + always@(guard__h434690 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01, 2'b10: - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = - guard__h434692 != 2'b11 || + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + guard__h434690 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or - guard__h434692) + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or + guard__h434690) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - (guard__h434692 == 2'b0) ? + (guard__h434690 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h434692 != 2'b01 && guard__h434692 != 2'b10 && - guard__h434692 != 2'b11 || + guard__h434690 != 2'b01 && guard__h434690 != 2'b10 && + guard__h434690 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = @@ -32333,34 +32333,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443399 or + always@(guard__h443397 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01, 2'b10: - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = - guard__h443399 == 2'b11 && + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h443397 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or - guard__h443399) + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h443397) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - (guard__h443399 == 2'b0) ? + (guard__h443397 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h443399 == 2'b01 || guard__h443399 == 2'b10 || - guard__h443399 == 2'b11) && + (guard__h443397 == 2'b01 || guard__h443397 == 2'b10 || + guard__h443397 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = @@ -32371,34 +32371,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443399 or + always@(guard__h443397 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01, 2'b10: - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h443399 != 2'b11 || + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h443397 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h443399) + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h443397) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - (guard__h443399 == 2'b0) ? + (guard__h443397 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h443399 != 2'b01 && guard__h443399 != 2'b10 && - guard__h443399 != 2'b11 || + guard__h443397 != 2'b01 && guard__h443397 != 2'b10 && + guard__h443397 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = @@ -32409,34 +32409,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452329 or + always@(guard__h452327 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01, 2'b10: - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = - guard__h452329 == 2'b11 && + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + guard__h452327 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or - guard__h452329) + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or + guard__h452327) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - (guard__h452329 == 2'b0) ? + (guard__h452327 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h452329 == 2'b01 || guard__h452329 == 2'b10 || - guard__h452329 == 2'b11) && + (guard__h452327 == 2'b01 || guard__h452327 == 2'b10 || + guard__h452327 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = @@ -32447,34 +32447,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452329 or + always@(guard__h452327 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01, 2'b10: - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = - guard__h452329 != 2'b11 || + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + guard__h452327 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or - guard__h452329) + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or + guard__h452327) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - (guard__h452329 == 2'b0) ? + (guard__h452327 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h452329 != 2'b01 && guard__h452329 != 2'b10 && - guard__h452329 != 2'b11 || + guard__h452327 != 2'b01 && guard__h452327 != 2'b10 && + guard__h452327 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = @@ -32485,34 +32485,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461165 or + always@(guard__h461163 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01, 2'b10: - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h461165 == 2'b11 && + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + guard__h461163 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h461165) + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or + guard__h461163) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - (guard__h461165 == 2'b0) ? + (guard__h461163 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h461165 == 2'b01 || guard__h461165 == 2'b10 || - guard__h461165 == 2'b11) && + (guard__h461163 == 2'b01 || guard__h461163 == 2'b10 || + guard__h461163 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = @@ -32523,34 +32523,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461165 or + always@(guard__h461163 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01, 2'b10: - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = - guard__h461165 != 2'b11 || + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + guard__h461163 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or - guard__h461165) + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or + guard__h461163) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - (guard__h461165 == 2'b0) ? + (guard__h461163 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h461165 != 2'b01 && guard__h461165 != 2'b10 && - guard__h461165 != 2'b11 || + guard__h461163 != 2'b01 && guard__h461163 != 2'b10 && + guard__h461163 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = @@ -32607,28 +32607,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h490715 or - _theResult___fst_exp__h498676 or _theResult___exp__h499331) + always@(guard__h490713 or + _theResult___fst_exp__h498674 or _theResult___exp__h499329) begin - case (guard__h490715) + case (guard__h490713) 2'b0: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = - _theResult___fst_exp__h498676; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135 = + _theResult___fst_exp__h498674; 2'b01, 2'b10, 2'b11: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = - _theResult___exp__h499331; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135 = + _theResult___exp__h499329; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h498676 or + _theResult___fst_exp__h498674 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 or - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135) + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - _theResult___fst_exp__h498676; + _theResult___fst_exp__h498674; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007; @@ -32637,40 +32637,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = 11'd0; endcase end - always@(guard__h490715 or - _theResult___fst_exp__h498676 or - out_exp__h499334 or _theResult___exp__h499331) + always@(guard__h490713 or + _theResult___fst_exp__h498674 or + out_exp__h499332 or _theResult___exp__h499329) begin - case (guard__h490715) + case (guard__h490713) 2'b0, 2'b01: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = - _theResult___fst_exp__h498676; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = + _theResult___fst_exp__h498674; 2'b10: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = - out_exp__h499334; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = + out_exp__h499332; 2'b11: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = - _theResult___exp__h499331; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = + _theResult___exp__h499329; endcase end - always@(guard__h490715 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h490713 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h490715) + case (guard__h490713) 2'b0, 2'b01, 2'b10: - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h490715 == 2'b11 && + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h490713 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490715) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490713) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32678,29 +32678,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h490715 == 2'b0) ? + (guard__h490713 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h490715 == 2'b01 || guard__h490715 == 2'b10 || - guard__h490715 == 2'b11) && + (guard__h490713 == 2'b01 || guard__h490713 == 2'b10 || + guard__h490713 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h500027 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h500025 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h500027) + case (guard__h500025) 2'b0, 2'b01, 2'b10: - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h500027 == 2'b11 && + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h500025 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500027) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500025) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32708,29 +32708,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h500027 == 2'b0) ? + (guard__h500025 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h500027 == 2'b01 || guard__h500027 == 2'b10 || - guard__h500027 == 2'b11) && + (guard__h500025 == 2'b01 || guard__h500025 == 2'b10 || + guard__h500025 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h509096 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h509094 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h509096) + case (guard__h509094) 2'b0, 2'b01, 2'b10: - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h509096 == 2'b11 && + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h509094 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509096) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509094) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32738,38 +32738,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h509096 == 2'b0) ? + (guard__h509094 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h509096 == 2'b01 || guard__h509096 == 2'b10 || - guard__h509096 == 2'b11) && + (guard__h509094 == 2'b01 || guard__h509094 == 2'b10 || + guard__h509094 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h568717 or - _theResult___fst_exp__h576678 or _theResult___exp__h577333) + always@(guard__h568715 or + _theResult___fst_exp__h576676 or _theResult___exp__h577331) begin - case (guard__h568717) + case (guard__h568715) 2'b0: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = - _theResult___fst_exp__h576678; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152 = + _theResult___fst_exp__h576676; 2'b01, 2'b10, 2'b11: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = - _theResult___exp__h577333; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152 = + _theResult___exp__h577331; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h576678 or + _theResult___fst_exp__h576676 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 or - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152) + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - _theResult___fst_exp__h576678; + _theResult___fst_exp__h576676; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717; @@ -32778,40 +32778,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = 11'd0; endcase end - always@(guard__h568717 or - _theResult___fst_exp__h576678 or - out_exp__h577336 or _theResult___exp__h577333) + always@(guard__h568715 or + _theResult___fst_exp__h576676 or + out_exp__h577334 or _theResult___exp__h577331) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = - _theResult___fst_exp__h576678; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = + _theResult___fst_exp__h576676; 2'b10: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = - out_exp__h577336; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = + out_exp__h577334; 2'b11: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = - _theResult___exp__h577333; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = + _theResult___exp__h577331; endcase end - always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568715 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01, 2'b10: - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h568717 == 2'b11 && + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h568715 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568715) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32819,29 +32819,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h568717 == 2'b0) ? + (guard__h568715 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h568717 == 2'b01 || guard__h568717 == 2'b10 || - guard__h568717 == 2'b11) && + (guard__h568715 == 2'b01 || guard__h568715 == 2'b10 || + guard__h568715 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578027 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01, 2'b10: - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h578029 == 2'b11 && + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h578027 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578027) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32849,29 +32849,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h578029 == 2'b0) ? + (guard__h578027 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h578029 == 2'b01 || guard__h578029 == 2'b10 || - guard__h578029 == 2'b11) && + (guard__h578027 == 2'b01 || guard__h578027 == 2'b10 || + guard__h578027 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587096 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01, 2'b10: - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h587098 == 2'b11 && + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h587096 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587096) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32879,29 +32879,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h587098 == 2'b0) ? + (guard__h587096 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h587098 == 2'b01 || guard__h587098 == 2'b10 || - guard__h587098 == 2'b11) && + (guard__h587096 == 2'b01 || guard__h587096 == 2'b10 || + guard__h587096 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578027 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01, 2'b10: - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h578029 != 2'b11 || + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h578027 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578027) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32909,29 +32909,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h578029 == 2'b0) ? + (guard__h578027 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h578029 != 2'b01 && guard__h578029 != 2'b10 && - guard__h578029 != 2'b11 || + guard__h578027 != 2'b01 && guard__h578027 != 2'b10 && + guard__h578027 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587096 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01, 2'b10: - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h587098 != 2'b11 || + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h587096 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587096) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32939,29 +32939,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h587098 == 2'b0) ? + (guard__h587096 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h587098 != 2'b01 && guard__h587098 != 2'b10 && - guard__h587098 != 2'b11 || + guard__h587096 != 2'b01 && guard__h587096 != 2'b10 && + guard__h587096 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568715 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01, 2'b10: - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h568717 != 2'b11 || + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h568715 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568715) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32969,38 +32969,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h568717 == 2'b0) ? + (guard__h568715 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h568717 != 2'b01 && guard__h568717 != 2'b10 && - guard__h568717 != 2'b11 || + guard__h568715 != 2'b01 && guard__h568715 != 2'b10 && + guard__h568715 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h529516 or - _theResult___fst_exp__h537477 or _theResult___exp__h538132) + always@(guard__h529514 or + _theResult___fst_exp__h537475 or _theResult___exp__h538130) begin - case (guard__h529516) + case (guard__h529514) 2'b0: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = - _theResult___fst_exp__h537477; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175 = + _theResult___fst_exp__h537475; 2'b01, 2'b10, 2'b11: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = - _theResult___exp__h538132; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175 = + _theResult___exp__h538130; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h537477 or + _theResult___fst_exp__h537475 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 or - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175) + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - _theResult___fst_exp__h537477; + _theResult___fst_exp__h537475; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480; @@ -33009,49 +33009,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = 11'd0; endcase end - always@(guard__h529516 or - _theResult___fst_exp__h537477 or - out_exp__h538135 or _theResult___exp__h538132) + always@(guard__h529514 or + _theResult___fst_exp__h537475 or + out_exp__h538133 or _theResult___exp__h538130) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = - _theResult___fst_exp__h537477; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = + _theResult___fst_exp__h537475; 2'b10: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = - out_exp__h538135; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = + out_exp__h538133; 2'b11: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = - _theResult___exp__h538132; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = + _theResult___exp__h538130; endcase end - always@(guard__h538828 or - _theResult___fst_exp__h547054 or _theResult___exp__h547783) + always@(guard__h538826 or + _theResult___fst_exp__h547052 or _theResult___exp__h547781) begin - case (guard__h538828) + case (guard__h538826) 2'b0: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = - _theResult___fst_exp__h547054; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177 = + _theResult___fst_exp__h547052; 2'b01, 2'b10, 2'b11: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = - _theResult___exp__h547783; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177 = + _theResult___exp__h547781; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h547054 or + _theResult___fst_exp__h547052 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 or - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177) + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - _theResult___fst_exp__h547054; + _theResult___fst_exp__h547052; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518; @@ -33060,49 +33060,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = 11'd0; endcase end - always@(guard__h538828 or - _theResult___fst_exp__h547054 or - out_exp__h547786 or _theResult___exp__h547783) + always@(guard__h538826 or + _theResult___fst_exp__h547052 or + out_exp__h547784 or _theResult___exp__h547781) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = - _theResult___fst_exp__h547054; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = + _theResult___fst_exp__h547052; 2'b10: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = - out_exp__h547786; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = + out_exp__h547784; 2'b11: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = - _theResult___exp__h547783; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = + _theResult___exp__h547781; endcase end - always@(guard__h547897 or - _theResult___fst_exp__h555887 or _theResult___exp__h556567) + always@(guard__h547895 or + _theResult___fst_exp__h555885 or _theResult___exp__h556565) begin - case (guard__h547897) + case (guard__h547895) 2'b0: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = - _theResult___fst_exp__h555887; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179 = + _theResult___fst_exp__h555885; 2'b01, 2'b10, 2'b11: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = - _theResult___exp__h556567; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179 = + _theResult___exp__h556565; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h555887 or + _theResult___fst_exp__h555885 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 or - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179) + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - _theResult___fst_exp__h555887; + _theResult___fst_exp__h555885; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549; @@ -33111,49 +33111,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = 11'd0; endcase end - always@(guard__h547897 or - _theResult___fst_exp__h555887 or - out_exp__h556570 or _theResult___exp__h556567) + always@(guard__h547895 or + _theResult___fst_exp__h555885 or + out_exp__h556568 or _theResult___exp__h556565) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = - _theResult___fst_exp__h555887; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = + _theResult___fst_exp__h555885; 2'b10: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = - out_exp__h556570; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = + out_exp__h556568; 2'b11: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = - _theResult___exp__h556567; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = + _theResult___exp__h556565; endcase end - always@(guard__h587098 or - _theResult___fst_exp__h595088 or _theResult___exp__h595768) + always@(guard__h587096 or + _theResult___fst_exp__h595086 or _theResult___exp__h595766) begin - case (guard__h587098) + case (guard__h587096) 2'b0: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = - _theResult___fst_exp__h595088; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181 = + _theResult___fst_exp__h595086; 2'b01, 2'b10, 2'b11: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = - _theResult___exp__h595768; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181 = + _theResult___exp__h595766; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h595088 or + _theResult___fst_exp__h595086 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 or - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181) + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - _theResult___fst_exp__h595088; + _theResult___fst_exp__h595086; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786; @@ -33162,49 +33162,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = 11'd0; endcase end - always@(guard__h587098 or - _theResult___fst_exp__h595088 or - out_exp__h595771 or _theResult___exp__h595768) + always@(guard__h587096 or + _theResult___fst_exp__h595086 or + out_exp__h595769 or _theResult___exp__h595766) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = - _theResult___fst_exp__h595088; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = + _theResult___fst_exp__h595086; 2'b10: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = - out_exp__h595771; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = + out_exp__h595769; 2'b11: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = - _theResult___exp__h595768; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = + _theResult___exp__h595766; endcase end - always@(guard__h578029 or - _theResult___fst_exp__h586255 or _theResult___exp__h586984) + always@(guard__h578027 or + _theResult___fst_exp__h586253 or _theResult___exp__h586982) begin - case (guard__h578029) + case (guard__h578027) 2'b0: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = - _theResult___fst_exp__h586255; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183 = + _theResult___fst_exp__h586253; 2'b01, 2'b10, 2'b11: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = - _theResult___exp__h586984; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183 = + _theResult___exp__h586982; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h586255 or + _theResult___fst_exp__h586253 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 or - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183) + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - _theResult___fst_exp__h586255; + _theResult___fst_exp__h586253; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755; @@ -33213,40 +33213,40 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = 11'd0; endcase end - always@(guard__h578029 or - _theResult___fst_exp__h586255 or - out_exp__h586987 or _theResult___exp__h586984) + always@(guard__h578027 or + _theResult___fst_exp__h586253 or + out_exp__h586985 or _theResult___exp__h586982) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = - _theResult___fst_exp__h586255; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = + _theResult___fst_exp__h586253; 2'b10: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = - out_exp__h586987; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = + out_exp__h586985; 2'b11: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = - _theResult___exp__h586984; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = + _theResult___exp__h586982; endcase end - always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529514 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01, 2'b10: - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h529516 == 2'b11 && + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h529514 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529514) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33254,29 +33254,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h529516 == 2'b0) ? + (guard__h529514 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h529516 == 2'b01 || guard__h529516 == 2'b10 || - guard__h529516 == 2'b11) && + (guard__h529514 == 2'b01 || guard__h529514 == 2'b10 || + guard__h529514 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538826 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01, 2'b10: - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h538828 == 2'b11 && + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h538826 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538826) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33284,29 +33284,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h538828 == 2'b0) ? + (guard__h538826 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h538828 == 2'b01 || guard__h538828 == 2'b10 || - guard__h538828 == 2'b11) && + (guard__h538826 == 2'b01 || guard__h538826 == 2'b10 || + guard__h538826 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547895 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01, 2'b10: - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h547897 == 2'b11 && + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h547895 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547895) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33314,29 +33314,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h547897 == 2'b0) ? + (guard__h547895 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h547897 == 2'b01 || guard__h547897 == 2'b10 || - guard__h547897 == 2'b11) && + (guard__h547895 == 2'b01 || guard__h547895 == 2'b10 || + guard__h547895 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538826 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01, 2'b10: - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h538828 != 2'b11 || + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h538826 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538826) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33344,29 +33344,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h538828 == 2'b0) ? + (guard__h538826 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h538828 != 2'b01 && guard__h538828 != 2'b10 && - guard__h538828 != 2'b11 || + guard__h538826 != 2'b01 && guard__h538826 != 2'b10 && + guard__h538826 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547895 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01, 2'b10: - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h547897 != 2'b11 || + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h547895 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547895) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33374,29 +33374,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h547897 == 2'b0) ? + (guard__h547895 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h547897 != 2'b01 && guard__h547897 != 2'b10 && - guard__h547897 != 2'b11 || + guard__h547895 != 2'b01 && guard__h547895 != 2'b10 && + guard__h547895 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529514 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01, 2'b10: - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h529516 != 2'b11 || + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h529514 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529514) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33404,38 +33404,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h529516 == 2'b0) ? + (guard__h529514 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h529516 != 2'b01 && guard__h529516 != 2'b10 && - guard__h529516 != 2'b11 || + guard__h529514 != 2'b01 && guard__h529514 != 2'b10 && + guard__h529514 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529516 or - _theResult___snd__h537428 or _theResult___sfd__h538133) + always@(guard__h529514 or + _theResult___snd__h537426 or _theResult___sfd__h538131) begin - case (guard__h529516) + case (guard__h529514) 2'b0: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = - _theResult___snd__h537428[56:5]; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197 = + _theResult___snd__h537426[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = - _theResult___sfd__h538133; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197 = + _theResult___sfd__h538131; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h537428 or + _theResult___snd__h537426 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 or - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197) + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - _theResult___snd__h537428[56:5]; + _theResult___snd__h537426[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575; @@ -33444,48 +33444,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = 52'd0; endcase end - always@(guard__h529516 or - _theResult___snd__h537428 or - out_sfd__h538136 or _theResult___sfd__h538133) + always@(guard__h529514 or + _theResult___snd__h537426 or + out_sfd__h538134 or _theResult___sfd__h538131) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = - _theResult___snd__h537428[56:5]; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = + _theResult___snd__h537426[56:5]; 2'b10: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = - out_sfd__h538136; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = + out_sfd__h538134; 2'b11: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = - _theResult___sfd__h538133; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = + _theResult___sfd__h538131; endcase end - always@(guard__h538828 or sfdin__h547048 or _theResult___sfd__h547784) + always@(guard__h538826 or sfdin__h547046 or _theResult___sfd__h547782) begin - case (guard__h538828) + case (guard__h538826) 2'b0: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h547048[56:5]; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199 = + sfdin__h547046[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h547784; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199 = + _theResult___sfd__h547782; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h547048 or + sfdin__h547046 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 or - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199) + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - sfdin__h547048[56:5]; + sfdin__h547046[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601; @@ -33494,48 +33494,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = 52'd0; endcase end - always@(guard__h538828 or - sfdin__h547048 or out_sfd__h547787 or _theResult___sfd__h547784) + always@(guard__h538826 or + sfdin__h547046 or out_sfd__h547785 or _theResult___sfd__h547782) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h547048[56:5]; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = + sfdin__h547046[56:5]; 2'b10: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h547787; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = + out_sfd__h547785; 2'b11: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h547784; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = + _theResult___sfd__h547782; endcase end - always@(guard__h547897 or - _theResult___snd__h555833 or _theResult___sfd__h556568) + always@(guard__h547895 or + _theResult___snd__h555831 or _theResult___sfd__h556566) begin - case (guard__h547897) + case (guard__h547895) 2'b0: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = - _theResult___snd__h555833[56:5]; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201 = + _theResult___snd__h555831[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = - _theResult___sfd__h556568; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201 = + _theResult___sfd__h556566; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h555833 or + _theResult___snd__h555831 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 or - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201) + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - _theResult___snd__h555833[56:5]; + _theResult___snd__h555831[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620; @@ -33544,49 +33544,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = 52'd0; endcase end - always@(guard__h547897 or - _theResult___snd__h555833 or - out_sfd__h556571 or _theResult___sfd__h556568) + always@(guard__h547895 or + _theResult___snd__h555831 or + out_sfd__h556569 or _theResult___sfd__h556566) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = - _theResult___snd__h555833[56:5]; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = + _theResult___snd__h555831[56:5]; 2'b10: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = - out_sfd__h556571; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = + out_sfd__h556569; 2'b11: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = - _theResult___sfd__h556568; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = + _theResult___sfd__h556566; endcase end - always@(guard__h500027 or - _theResult___fst_exp__h508253 or _theResult___exp__h508982) + always@(guard__h500025 or + _theResult___fst_exp__h508251 or _theResult___exp__h508980) begin - case (guard__h500027) + case (guard__h500025) 2'b0: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = - _theResult___fst_exp__h508253; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203 = + _theResult___fst_exp__h508251; 2'b01, 2'b10, 2'b11: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = - _theResult___exp__h508982; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203 = + _theResult___exp__h508980; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h508253 or + _theResult___fst_exp__h508251 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 or - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203) + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - _theResult___fst_exp__h508253; + _theResult___fst_exp__h508251; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050; @@ -33595,49 +33595,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = 11'd0; endcase end - always@(guard__h500027 or - _theResult___fst_exp__h508253 or - out_exp__h508985 or _theResult___exp__h508982) + always@(guard__h500025 or + _theResult___fst_exp__h508251 or + out_exp__h508983 or _theResult___exp__h508980) begin - case (guard__h500027) + case (guard__h500025) 2'b0, 2'b01: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = - _theResult___fst_exp__h508253; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = + _theResult___fst_exp__h508251; 2'b10: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = - out_exp__h508985; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = + out_exp__h508983; 2'b11: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = - _theResult___exp__h508982; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = + _theResult___exp__h508980; endcase end - always@(guard__h509096 or - _theResult___fst_exp__h517086 or _theResult___exp__h517766) + always@(guard__h509094 or + _theResult___fst_exp__h517084 or _theResult___exp__h517764) begin - case (guard__h509096) + case (guard__h509094) 2'b0: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = - _theResult___fst_exp__h517086; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205 = + _theResult___fst_exp__h517084; 2'b01, 2'b10, 2'b11: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = - _theResult___exp__h517766; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205 = + _theResult___exp__h517764; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h517086 or + _theResult___fst_exp__h517084 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 or - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205) + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - _theResult___fst_exp__h517086; + _theResult___fst_exp__h517084; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081; @@ -33646,49 +33646,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = 11'd0; endcase end - always@(guard__h509096 or - _theResult___fst_exp__h517086 or - out_exp__h517769 or _theResult___exp__h517766) + always@(guard__h509094 or + _theResult___fst_exp__h517084 or + out_exp__h517767 or _theResult___exp__h517764) begin - case (guard__h509096) + case (guard__h509094) 2'b0, 2'b01: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = - _theResult___fst_exp__h517086; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = + _theResult___fst_exp__h517084; 2'b10: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = - out_exp__h517769; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = + out_exp__h517767; 2'b11: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = - _theResult___exp__h517766; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = + _theResult___exp__h517764; endcase end - always@(guard__h490715 or - _theResult___snd__h498627 or _theResult___sfd__h499332) + always@(guard__h490713 or + _theResult___snd__h498625 or _theResult___sfd__h499330) begin - case (guard__h490715) + case (guard__h490713) 2'b0: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = - _theResult___snd__h498627[56:5]; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207 = + _theResult___snd__h498625[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = - _theResult___sfd__h499332; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207 = + _theResult___sfd__h499330; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h498627 or + _theResult___snd__h498625 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 or - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207) + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - _theResult___snd__h498627[56:5]; + _theResult___snd__h498625[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107; @@ -33697,49 +33697,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = 52'd0; endcase end - always@(guard__h490715 or - _theResult___snd__h498627 or - out_sfd__h499335 or _theResult___sfd__h499332) + always@(guard__h490713 or + _theResult___snd__h498625 or + out_sfd__h499333 or _theResult___sfd__h499330) begin - case (guard__h490715) + case (guard__h490713) 2'b0, 2'b01: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = - _theResult___snd__h498627[56:5]; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = + _theResult___snd__h498625[56:5]; 2'b10: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = - out_sfd__h499335; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = + out_sfd__h499333; 2'b11: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = - _theResult___sfd__h499332; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = + _theResult___sfd__h499330; endcase end - always@(guard__h509096 or - _theResult___snd__h517032 or _theResult___sfd__h517767) + always@(guard__h509094 or + _theResult___snd__h517030 or _theResult___sfd__h517765) begin - case (guard__h509096) + case (guard__h509094) 2'b0: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = - _theResult___snd__h517032[56:5]; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209 = + _theResult___snd__h517030[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = - _theResult___sfd__h517767; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209 = + _theResult___sfd__h517765; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h517032 or + _theResult___snd__h517030 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 or - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209) + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - _theResult___snd__h517032[56:5]; + _theResult___snd__h517030[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153; @@ -33748,48 +33748,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = 52'd0; endcase end - always@(guard__h509096 or - _theResult___snd__h517032 or - out_sfd__h517770 or _theResult___sfd__h517767) + always@(guard__h509094 or + _theResult___snd__h517030 or + out_sfd__h517768 or _theResult___sfd__h517765) begin - case (guard__h509096) + case (guard__h509094) 2'b0, 2'b01: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = - _theResult___snd__h517032[56:5]; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = + _theResult___snd__h517030[56:5]; 2'b10: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = - out_sfd__h517770; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = + out_sfd__h517768; 2'b11: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = - _theResult___sfd__h517767; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = + _theResult___sfd__h517765; endcase end - always@(guard__h500027 or sfdin__h508247 or _theResult___sfd__h508983) + always@(guard__h500025 or sfdin__h508245 or _theResult___sfd__h508981) begin - case (guard__h500027) + case (guard__h500025) 2'b0: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = - sfdin__h508247[56:5]; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211 = + sfdin__h508245[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = - _theResult___sfd__h508983; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211 = + _theResult___sfd__h508981; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h508247 or + sfdin__h508245 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 or - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211) + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - sfdin__h508247[56:5]; + sfdin__h508245[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134; @@ -33798,48 +33798,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = 52'd0; endcase end - always@(guard__h500027 or - sfdin__h508247 or out_sfd__h508986 or _theResult___sfd__h508983) + always@(guard__h500025 or + sfdin__h508245 or out_sfd__h508984 or _theResult___sfd__h508981) begin - case (guard__h500027) + case (guard__h500025) 2'b0, 2'b01: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = - sfdin__h508247[56:5]; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = + sfdin__h508245[56:5]; 2'b10: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = - out_sfd__h508986; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = + out_sfd__h508984; 2'b11: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = - _theResult___sfd__h508983; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = + _theResult___sfd__h508981; endcase end - always@(guard__h568717 or - _theResult___snd__h576629 or _theResult___sfd__h577334) + always@(guard__h568715 or + _theResult___snd__h576627 or _theResult___sfd__h577332) begin - case (guard__h568717) + case (guard__h568715) 2'b0: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = - _theResult___snd__h576629[56:5]; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213 = + _theResult___snd__h576627[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = - _theResult___sfd__h577334; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213 = + _theResult___sfd__h577332; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h576629 or + _theResult___snd__h576627 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 or - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213) + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - _theResult___snd__h576629[56:5]; + _theResult___snd__h576627[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812; @@ -33848,48 +33848,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = 52'd0; endcase end - always@(guard__h568717 or - _theResult___snd__h576629 or - out_sfd__h577337 or _theResult___sfd__h577334) + always@(guard__h568715 or + _theResult___snd__h576627 or + out_sfd__h577335 or _theResult___sfd__h577332) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = - _theResult___snd__h576629[56:5]; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = + _theResult___snd__h576627[56:5]; 2'b10: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = - out_sfd__h577337; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = + out_sfd__h577335; 2'b11: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = - _theResult___sfd__h577334; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = + _theResult___sfd__h577332; endcase end - always@(guard__h578029 or sfdin__h586249 or _theResult___sfd__h586985) + always@(guard__h578027 or sfdin__h586247 or _theResult___sfd__h586983) begin - case (guard__h578029) + case (guard__h578027) 2'b0: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h586249[56:5]; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h586247[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h586985; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h586983; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h586249 or + sfdin__h586247 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 or - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215) + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - sfdin__h586249[56:5]; + sfdin__h586247[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838; @@ -33898,24 +33898,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = 52'd0; endcase end - always@(guard__h578029 or - sfdin__h586249 or out_sfd__h586988 or _theResult___sfd__h586985) + always@(guard__h578027 or + sfdin__h586247 or out_sfd__h586986 or _theResult___sfd__h586983) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h586249[56:5]; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h586247[56:5]; 2'b10: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h586988; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h586986; 2'b11: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h586985; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h586983; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -33950,28 +33950,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830; endcase end - always@(guard__h587098 or - _theResult___snd__h595034 or _theResult___sfd__h595769) + always@(guard__h587096 or + _theResult___snd__h595032 or _theResult___sfd__h595767) begin - case (guard__h587098) + case (guard__h587096) 2'b0: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = - _theResult___snd__h595034[56:5]; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217 = + _theResult___snd__h595032[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = - _theResult___sfd__h595769; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217 = + _theResult___sfd__h595767; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h595034 or + _theResult___snd__h595032 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 or - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217) + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - _theResult___snd__h595034[56:5]; + _theResult___snd__h595032[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857; @@ -33980,25 +33980,25 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = 52'd0; endcase end - always@(guard__h587098 or - _theResult___snd__h595034 or - out_sfd__h595772 or _theResult___sfd__h595769) + always@(guard__h587096 or + _theResult___snd__h595032 or + out_sfd__h595770 or _theResult___sfd__h595767) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = - _theResult___snd__h595034[56:5]; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = + _theResult___snd__h595032[56:5]; 2'b10: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = - out_sfd__h595772; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = + out_sfd__h595770; 2'b11: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = - _theResult___sfd__h595769; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = + _theResult___sfd__h595767; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34311,10 +34311,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h661045 or + always@(k__h661043 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661045) + case (k__h661043) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 = coreFix_aluExe_0_rsAlu$canEnq; @@ -34353,10 +34353,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(k__h661045 or + always@(k__h661043 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661045) + case (k__h661043) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -34498,14 +34498,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h675479 or + always@(idx__h675477 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13509 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675479) + case (idx__h675477) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 = fetchStage$pipelines_0_canDeq && @@ -34641,15 +34641,15 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494; endcase end - always@(k__h661045 or + always@(k__h661043 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h661045) + case (k__h661043) 1'd0: - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -34752,14 +34752,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(idx__h675479 or + always@(idx__h675477 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13731 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13738 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675479) + case (idx__h675477) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 = (!fetchStage$pipelines_0_canDeq || @@ -37751,7 +37751,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h600774 == 2'd0) + v__h600772 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index 8a98286..88a0737 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v index 1a41e81..681bff9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v index 5c00da0..87a58eb 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_CSR_Tap.v b/src_SSITH_P3/Verilog_RTL/mkDM_CSR_Tap.v index a3bcf6f..029d85d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_CSR_Tap.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_CSR_Tap.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_GPR_Tap.v b/src_SSITH_P3/Verilog_RTL/mkDM_GPR_Tap.v index be8b221..1e9a074 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_GPR_Tap.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_GPR_Tap.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v b/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v index 9996cf1..3e9ea1b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Mem_Tap.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v index 935f2d7..62280a6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v index 2f1561d..2b68dc4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v index f6ead5f..659476b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v index 2843207..16f6afa 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v index 9f748f7..b30df25 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v index 32b8295..0d6421c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v index 1a3ba20..7eb91a4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v index 8f7dfb4..d7ed640 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v index 5e92dd3..053bf66 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v index 5d2e0d5..a75a034 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v index 8b1becd..22b5f44 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v index 9d6c366..7242060 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v index e6946a8..ccb122d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v index 25e8f29..31207ea 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v +++ b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v index 6f1d821..d9cea29 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -786,8 +786,8 @@ module mkFetchStage(CLK, out_fifo_enqueueElement_1_dummy_1_0$wget, out_fifo_enqueueFifo_lat_0$whas, out_fifo_enqueueFifo_lat_1$whas, - pc_reg_lat_0$whas, - pc_reg_lat_1$whas; + pc_reg_dummy_1_0$whas, + pc_reg_lat_0$whas; // register decode_epoch reg decode_epoch; @@ -4818,7 +4818,7 @@ module mkFetchStage(CLK, // inlined wires assign pc_reg_lat_0$whas = EN_start || WILL_FIRE_RL_doFetch1 ; - assign pc_reg_lat_1$whas = + assign pc_reg_dummy_1_0$whas = WILL_FIRE_RL_doDecode && SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5447 ; @@ -9130,7 +9130,7 @@ module mkFetchStage(CLK, // submodule pc_reg_dummy2_1 assign pc_reg_dummy2_1$D_IN = 1'd1 ; - assign pc_reg_dummy2_1$EN = pc_reg_lat_1$whas ; + assign pc_reg_dummy2_1$EN = pc_reg_dummy_1_0$whas ; // submodule pc_reg_dummy2_2 assign pc_reg_dummy2_2$D_IN = 1'd1 ; @@ -11527,7 +11527,7 @@ module mkFetchStage(CLK, assign IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337 = x__h115849 + 64'd4 ; assign IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d9 = - pc_reg_lat_1$whas ? + pc_reg_dummy_1_0$whas ? upd__h1659 : (pc_reg_lat_0$whas ? upd__h1686 : pc_reg_rl) ; assign IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986 = diff --git a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v index 9bec235..19077ae 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v index 3999df6..1ac4e8b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v index 2a255b9..15d044c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v index 5c24b1f..582c46c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v index a94e505..a99ba17 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v index b420b9a..8f2496d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v index f9897e7..633084f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v index ab96233..fb6650c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v index 87e4954..0f647fc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkICoCache.v b/src_SSITH_P3/Verilog_RTL/mkICoCache.v index 434f48e..a18b0ec 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkICoCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v index ba18f4f..5290f98 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v index cc3465d..3234ef8 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkITlb.v b/src_SSITH_P3/Verilog_RTL/mkITlb.v index c5a0864..8337f28 100644 --- a/src_SSITH_P3/Verilog_RTL/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkITlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v index 805dcc5..6cbc0b2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkLLCache.v b/src_SSITH_P3/Verilog_RTL/mkLLCache.v index 41a36dc..b2795ea 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v index f15ec88..b9ad56d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v index b4fa4a6..4b0453f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v index 63a9d74..68735ad 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v index 08033b6..b0ef48d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v index b7a1045..b257c36 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v index 0848cfa..2eea032 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v index 3e2332b..7254a62 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v index 8ce1ce4..62600d8 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v index 086d61c..7ef963e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v index a7de61e..a186981 100644 --- a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index e4d4458..382f1e2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -1347,9 +1347,9 @@ module mkP3_Core(CLK, .axi_out_tlast(tv_xactor$axi_out_tlast)); // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = + assign CAN_FIRE_RL_rl_once = WILL_FIRE_RL_rl_once ; + assign WILL_FIRE_RL_rl_once = corew$RDY_cpu_reset_server_request_put && !rg_once ; - assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; // rule RL_rl_reset_response assign CAN_FIRE_RL_rl_reset_response = @@ -1637,7 +1637,7 @@ module mkP3_Core(CLK, assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; + assign corew$EN_cpu_reset_server_request_put = WILL_FIRE_RL_rl_once ; assign corew$EN_cpu_reset_server_response_get = corew$RDY_cpu_reset_server_response_get ; assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; diff --git a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v index 7dfaf3e..7490ccc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index d10f5a0..969e53c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v index 955c79f..a181d0f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkRas.v b/src_SSITH_P3/Verilog_RTL/mkRas.v index 0399a9b..9192168 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL/mkRas.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v index 473ebaa..7b123fe 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v index 3e76786..bc0bb5b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v index c07ff78..a7070c3 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v index 35e774f..b21ff7c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v index 7350806..62c6ac0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v index 2725b41..5153b0f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v index 6bc3736..46f17d4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v index e1af2db..6c29b38 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v index 2aafd79..4071131 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v index f161a85..689b342 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v index cc2c578..ea8ce28 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v index fd3654a..4437b39 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v index 1762326..a0aef54 100644 --- a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v index e064e0f..e492bcf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v b/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v index 5c7edaa..00ef896 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTV_Encode.v b/src_SSITH_P3/Verilog_RTL/mkTV_Encode.v index ef33452..5348886 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTV_Encode.v +++ b/src_SSITH_P3/Verilog_RTL/mkTV_Encode.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v b/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v index d07abc0..4ce5fb1 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v +++ b/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v index d7059a8..a049da6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPred.v b/src_SSITH_P3/Verilog_RTL/mkTourPred.v index f4f9439..6cef5a7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v index 417af0c..7ab9bb7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v index faa8cb7..6614f96 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v index 4053473..279d862 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v index 7bdbe69..e610c1f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v index 9e9d6fe..dc53756 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v index 14f72ed..65ad672 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v index c39d9cd..544866c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v index 318d1f5..0d705fd 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v index 7421709..0114038 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v index 128468d..85ac1bf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_alu.v b/src_SSITH_P3/Verilog_RTL/module_alu.v index a3dc704..3ca27d9 100644 --- a/src_SSITH_P3/Verilog_RTL/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL/module_alu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_aluBr.v b/src_SSITH_P3/Verilog_RTL/module_aluBr.v index b602264..9ec85ca 100644 --- a/src_SSITH_P3/Verilog_RTL/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL/module_aluBr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_amoExec.v b/src_SSITH_P3/Verilog_RTL/module_amoExec.v index b530943..fe0dcca 100644 --- a/src_SSITH_P3/Verilog_RTL/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_amoExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_basicExec.v b/src_SSITH_P3/Verilog_RTL/module_basicExec.v index 062a838..c47f51b 100644 --- a/src_SSITH_P3/Verilog_RTL/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_basicExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v index fcd8244..2ffba0b 100644 --- a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_checkForException.v b/src_SSITH_P3/Verilog_RTL/module_checkForException.v index e98a4f4..b645a07 100644 --- a/src_SSITH_P3/Verilog_RTL/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL/module_checkForException.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_decode.v b/src_SSITH_P3/Verilog_RTL/module_decode.v index 1e08888..8d04782 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL/module_decode.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v index b9f2cd4..76da3ab 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v index 1c8195c..edefcc7 100644 --- a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v b/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v index da452c1..9e73d6c 100644 --- a/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v +++ b/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v index 71be41e..7aac7c0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v index b9fa4af..580b173 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v index e1e9a5b..a4c7e30 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v index d689f0a..bbc0dff 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index c6c37b4..2e619cf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -4060,33 +4060,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - addr__h287289, - curData__h190139, - rVal1__h605870, - rVal1__h629405, - trap_val__h693220, - x__h194349; + addr__h287287, + curData__h190137, + rVal1__h605871, + rVal1__h629404, + trap_val__h693218, + x__h194347; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211, - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212, - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209, - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210, - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197, - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198, - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199, - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200, - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201, - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202, - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213, - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214, - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215, - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216, - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217, - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218, - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207, - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208, + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211, + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212, + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209, + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210, + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197, + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198, + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199, + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200, + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201, + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202, + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213, + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214, + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215, + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216, + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217, + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218, + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207, + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624, @@ -4098,45 +4098,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78, - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79, - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80, - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81, - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111, - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112, - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41, - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42, - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109, - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110, - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39, - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40, - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113, - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114, - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43, - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44, - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115, - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116, - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45, - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46, - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76, - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77, - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74, - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75, - _theResult___fst_sfd__h343285, - _theResult___fst_sfd__h352008, - _theResult___fst_sfd__h360590, - _theResult___fst_sfd__h369774, - _theResult___fst_sfd__h378410, - _theResult___fst_sfd__h388977, - _theResult___fst_sfd__h397698, - _theResult___fst_sfd__h406280, - _theResult___fst_sfd__h415464, - _theResult___fst_sfd__h424100, - _theResult___fst_sfd__h434665, - _theResult___fst_sfd__h443386, - _theResult___fst_sfd__h451968, - _theResult___fst_sfd__h461152, - _theResult___fst_sfd__h469788; + reg [22 : 0] CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78, + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79, + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80, + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81, + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111, + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112, + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41, + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42, + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109, + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110, + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39, + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40, + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113, + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114, + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43, + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44, + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115, + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116, + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45, + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46, + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76, + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77, + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74, + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75, + _theResult___fst_sfd__h343283, + _theResult___fst_sfd__h352006, + _theResult___fst_sfd__h360588, + _theResult___fst_sfd__h369772, + _theResult___fst_sfd__h378408, + _theResult___fst_sfd__h388975, + _theResult___fst_sfd__h397696, + _theResult___fst_sfd__h406278, + _theResult___fst_sfd__h415462, + _theResult___fst_sfd__h424098, + _theResult___fst_sfd__h434663, + _theResult___fst_sfd__h443384, + _theResult___fst_sfd__h451966, + _theResult___fst_sfd__h461150, + _theResult___fst_sfd__h469786; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4160,24 +4160,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203, - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204, - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205, - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206, - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175, - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176, - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177, - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178, - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179, - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180, - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152, - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153, - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183, - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184, - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181, - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182, - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135, - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136, + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203, + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204, + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205, + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206, + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175, + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176, + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177, + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178, + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179, + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180, + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152, + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153, + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183, + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184, + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181, + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182, + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135, + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553, @@ -4187,47 +4187,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790; - reg [7 : 0] CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67, - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68, - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72, - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73, - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96, - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97, - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26, - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27, - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94, - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95, - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24, - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25, - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102, - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103, - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32, - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33, - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107, - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108, - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37, - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38, - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61, - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62, - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59, - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60, + reg [7 : 0] CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67, + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68, + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72, + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73, + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96, + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97, + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26, + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27, + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94, + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95, + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24, + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25, + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102, + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103, + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32, + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33, + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107, + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108, + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37, + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38, + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61, + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62, + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59, + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h343284, - _theResult___fst_exp__h352007, - _theResult___fst_exp__h360589, - _theResult___fst_exp__h369773, - _theResult___fst_exp__h378409, - _theResult___fst_exp__h388976, - _theResult___fst_exp__h397697, - _theResult___fst_exp__h406279, - _theResult___fst_exp__h415463, - _theResult___fst_exp__h424099, - _theResult___fst_exp__h434664, - _theResult___fst_exp__h443385, - _theResult___fst_exp__h451967, - _theResult___fst_exp__h461151, - _theResult___fst_exp__h469787; + _theResult___fst_exp__h343282, + _theResult___fst_exp__h352005, + _theResult___fst_exp__h360587, + _theResult___fst_exp__h369771, + _theResult___fst_exp__h378407, + _theResult___fst_exp__h388974, + _theResult___fst_exp__h397695, + _theResult___fst_exp__h406277, + _theResult___fst_exp__h415461, + _theResult___fst_exp__h424097, + _theResult___fst_exp__h434662, + _theResult___fst_exp__h443383, + _theResult___fst_exp__h451965, + _theResult___fst_exp__h461149, + _theResult___fst_exp__h469785; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262, @@ -4245,8 +4245,8 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995, - i__h692204, - i__h692364; + i__h692202, + i__h692362; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266, @@ -4260,8 +4260,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695, - x__h283068, - x__h288838; + x__h283066, + x__h288836; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, @@ -4292,46 +4292,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, @@ -4448,152 +4448,152 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663, - _theResult___fst__h600261, - _theResult___snd__h600262, - a___1__h599980, - a___1__h600266, - a__h599839, + _theResult___fst__h600259, + _theResult___snd__h600260, + a___1__h599978, + a___1__h600264, + a__h599837, amoExec___d880, - b___1__h599981, - b___1__h600311, - b__h599840, - base__h694791, - base__h694994, - data___1__h472207, - data___1__h473015, - data__h472481, - fcsr_csr__read__h606148, - fflags_csr__read__h606123, - frm_csr__read__h606134, - mcause_csr__read__h607795, - mcounteren_csr__read__h607540, - medeleg_csr__read__h607140, - mideleg_csr__read__h607235, - mie_csr__read__h607366, - mip_csr__read__h608035, - mstatus_csr__read__h606992, - mtvec_csr__read__h607448, - n___1__h195752, - n__h191677, - n__read__h608139, - n__read__h608330, + b___1__h599979, + b___1__h600309, + b__h599838, + base__h694789, + base__h694992, + data___1__h472205, + data___1__h473013, + data__h472479, + fcsr_csr__read__h606149, + fflags_csr__read__h606124, + frm_csr__read__h606135, + mcause_csr__read__h607796, + mcounteren_csr__read__h607541, + medeleg_csr__read__h607141, + mideleg_csr__read__h607236, + mie_csr__read__h607367, + mip_csr__read__h608036, + mstatus_csr__read__h606993, + mtvec_csr__read__h607449, + n___1__h195750, + n__h191675, + n__read__h608140, + n__read__h608331, n__read__h6134, - n__read__h703199, - next_pc__h702542, - q___1__h473080, - rVal1__h478961, - rVal2__h478962, - r___1__h473106, - res_data__h335089, - res_data__h335094, - res_data__h380784, - res_data__h380789, - res_data__h426472, - res_data__h426477, - resp_addr__h289193, + n__read__h703197, + next_pc__h702540, + q___1__h473078, + rVal1__h478959, + rVal2__h478960, + r___1__h473104, + res_data__h335087, + res_data__h335092, + res_data__h380782, + res_data__h380787, + res_data__h426470, + res_data__h426475, + resp_addr__h289191, robdeqPort_0_deq_data_BITS_95_TO_32__q261, - satp_csr__read__h606849, - scause_csr__read__h606647, - scounteren_csr__read__h606509, - shiftData__h180516, - sie_csr__read__h606413, - sip_csr__read__h606786, - sstatus_csr__read__h606344, - stvec_csr__read__h606456, + satp_csr__read__h606850, + scause_csr__read__h606648, + scounteren_csr__read__h606510, + shiftData__h180514, + sie_csr__read__h606414, + sip_csr__read__h606787, + sstatus_csr__read__h606345, + stvec_csr__read__h606457, upd__h3639, upd__h4956, - v__h604754, - v__h628444, - vaddr__h180511, + v__h604755, + v__h628443, + vaddr__h180509, x__h152890, x__h156437, x__h159251, x__h161099, x__h17672, - x__h180425, - x__h180426, + x__h180423, + x__h180424, x__h20210, - x__h284513, - x__h286367, + x__h284511, + x__h286365, x__h45579, + x__h478868, + x__h478869, x__h478870, - x__h478871, - x__h478872, x__h48115, - x__h613033, x__h613034, - x__h634256, - x__h634257, - x__h688725, - x_addr__h311296, - x_quotient__h472395, - x_reg_ifc__read__h606253, - x_remainder__h472396, - y__h705650, - y_avValue__h179513, - y_avValue__h180119, - y_avValue__h476006, - y_avValue__h476614, - y_avValue__h477216, - y_avValue__h605660, - y_avValue__h610922, - y_avValue__h629197, - y_avValue__h632155, - y_avValue__h693067, - y_avValue__h694828, - y_avValue_snd_snd_snd_snd_snd__h705150, - y_avValue_snd_snd_snd_snd_snd__h705703, - y_avValue_snd_snd_snd_snd_snd__h705732; + x__h613035, + x__h634254, + x__h634255, + x__h688723, + x_addr__h311294, + x_quotient__h472393, + x_reg_ifc__read__h606254, + x_remainder__h472394, + y__h705648, + y_avValue__h179511, + y_avValue__h180117, + y_avValue__h476004, + y_avValue__h476612, + y_avValue__h477214, + y_avValue__h605661, + y_avValue__h610923, + y_avValue__h629196, + y_avValue__h632153, + y_avValue__h693065, + y_avValue__h694826, + y_avValue_snd_snd_snd_snd_snd__h705148, + y_avValue_snd_snd_snd_snd_snd__h705701, + y_avValue_snd_snd_snd_snd_snd__h705730; wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869, - r1__read__h608837, - r1__read__h609241, - r1__read__h609771, - r1__read__h609776, - r1__read__h609795, - r1__read__h610048, - r1__read__h610226, - r1__read__h610344, - r1__read__h610349, - r1__read__h610368; - wire [61 : 0] r1__read__h608839, - r1__read__h609243, - r1__read__h609778, - r1__read__h609797, - r1__read__h610050, - r1__read__h610202, - r1__read__h610228, - r1__read__h610351, - r1__read__h610370; - wire [60 : 0] r1__read__h610052, - r1__read__h610204, - r1__read__h610230, - r1__read__h610372; - wire [59 : 0] r1__read__h608841, - r1__read__h609245, - r1__read__h609789, - r1__read__h609799, - r1__read__h610054, - r1__read__h610232, - r1__read__h610362, - r1__read__h610374; - wire [58 : 0] r1__read__h608843, - r1__read__h609247, - r1__read__h609801, - r1__read__h610056, - r1__read__h610234, - r1__read__h610376; + r1__read__h608838, + r1__read__h609242, + r1__read__h609772, + r1__read__h609777, + r1__read__h609796, + r1__read__h610049, + r1__read__h610227, + r1__read__h610345, + r1__read__h610350, + r1__read__h610369; + wire [61 : 0] r1__read__h608840, + r1__read__h609244, + r1__read__h609779, + r1__read__h609798, + r1__read__h610051, + r1__read__h610203, + r1__read__h610229, + r1__read__h610352, + r1__read__h610371; + wire [60 : 0] r1__read__h610053, + r1__read__h610205, + r1__read__h610231, + r1__read__h610373; + wire [59 : 0] r1__read__h608842, + r1__read__h609246, + r1__read__h609790, + r1__read__h609800, + r1__read__h610055, + r1__read__h610233, + r1__read__h610363, + r1__read__h610375; + wire [58 : 0] r1__read__h608844, + r1__read__h609248, + r1__read__h609802, + r1__read__h610057, + r1__read__h610235, + r1__read__h610377; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - r1__read__h608845, - r1__read__h609249, - r1__read__h609803, - r1__read__h610058, - r1__read__h610206, - r1__read__h610236, - r1__read__h610378, - y__h252026; + r1__read__h608846, + r1__read__h609250, + r1__read__h609804, + r1__read__h610059, + r1__read__h610207, + r1__read__h610237, + r1__read__h610379, + y__h252024; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90, @@ -4621,187 +4621,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355, - _theResult____h343302, - _theResult____h360941, - _theResult____h388994, - _theResult____h406631, - _theResult____h434682, - _theResult____h452319, - _theResult____h500017, - _theResult____h538818, - _theResult____h578019, - _theResult___snd__h351424, + _theResult____h343300, + _theResult____h360939, + _theResult____h388992, + _theResult____h406629, + _theResult____h434680, + _theResult____h452317, + _theResult____h500015, + _theResult____h538816, + _theResult____h578017, + _theResult___snd__h351422, + _theResult___snd__h351433, _theResult___snd__h351435, - _theResult___snd__h351437, - _theResult___snd__h351447, - _theResult___snd__h351453, - _theResult___snd__h351476, + _theResult___snd__h351445, + _theResult___snd__h351451, + _theResult___snd__h351474, + _theResult___snd__h360018, _theResult___snd__h360020, - _theResult___snd__h360022, - _theResult___snd__h360029, - _theResult___snd__h360035, - _theResult___snd__h360058, - _theResult___snd__h369190, + _theResult___snd__h360027, + _theResult___snd__h360033, + _theResult___snd__h360056, + _theResult___snd__h369188, + _theResult___snd__h369199, _theResult___snd__h369201, - _theResult___snd__h369203, - _theResult___snd__h369213, - _theResult___snd__h369219, - _theResult___snd__h369242, - _theResult___snd__h377810, - _theResult___snd__h377824, - _theResult___snd__h377830, - _theResult___snd__h377848, - _theResult___snd__h397114, + _theResult___snd__h369211, + _theResult___snd__h369217, + _theResult___snd__h369240, + _theResult___snd__h377808, + _theResult___snd__h377822, + _theResult___snd__h377828, + _theResult___snd__h377846, + _theResult___snd__h397112, + _theResult___snd__h397123, _theResult___snd__h397125, - _theResult___snd__h397127, - _theResult___snd__h397137, - _theResult___snd__h397143, - _theResult___snd__h397166, + _theResult___snd__h397135, + _theResult___snd__h397141, + _theResult___snd__h397164, + _theResult___snd__h405708, _theResult___snd__h405710, - _theResult___snd__h405712, - _theResult___snd__h405719, - _theResult___snd__h405725, - _theResult___snd__h405748, - _theResult___snd__h414880, + _theResult___snd__h405717, + _theResult___snd__h405723, + _theResult___snd__h405746, + _theResult___snd__h414878, + _theResult___snd__h414889, _theResult___snd__h414891, - _theResult___snd__h414893, - _theResult___snd__h414903, - _theResult___snd__h414909, - _theResult___snd__h414932, - _theResult___snd__h423500, - _theResult___snd__h423514, - _theResult___snd__h423520, - _theResult___snd__h423538, - _theResult___snd__h442802, + _theResult___snd__h414901, + _theResult___snd__h414907, + _theResult___snd__h414930, + _theResult___snd__h423498, + _theResult___snd__h423512, + _theResult___snd__h423518, + _theResult___snd__h423536, + _theResult___snd__h442800, + _theResult___snd__h442811, _theResult___snd__h442813, - _theResult___snd__h442815, - _theResult___snd__h442825, - _theResult___snd__h442831, - _theResult___snd__h442854, + _theResult___snd__h442823, + _theResult___snd__h442829, + _theResult___snd__h442852, + _theResult___snd__h451396, _theResult___snd__h451398, - _theResult___snd__h451400, - _theResult___snd__h451407, - _theResult___snd__h451413, - _theResult___snd__h451436, - _theResult___snd__h460568, + _theResult___snd__h451405, + _theResult___snd__h451411, + _theResult___snd__h451434, + _theResult___snd__h460566, + _theResult___snd__h460577, _theResult___snd__h460579, - _theResult___snd__h460581, - _theResult___snd__h460591, - _theResult___snd__h460597, - _theResult___snd__h460620, - _theResult___snd__h469188, - _theResult___snd__h469202, - _theResult___snd__h469208, - _theResult___snd__h469226, + _theResult___snd__h460589, + _theResult___snd__h460595, + _theResult___snd__h460618, + _theResult___snd__h469186, + _theResult___snd__h469200, + _theResult___snd__h469206, + _theResult___snd__h469224, + _theResult___snd__h498625, _theResult___snd__h498627, - _theResult___snd__h498629, - _theResult___snd__h498636, - _theResult___snd__h498642, - _theResult___snd__h498665, - _theResult___snd__h508264, + _theResult___snd__h498634, + _theResult___snd__h498640, + _theResult___snd__h498663, + _theResult___snd__h508262, + _theResult___snd__h508273, _theResult___snd__h508275, - _theResult___snd__h508277, - _theResult___snd__h508287, - _theResult___snd__h508293, - _theResult___snd__h508316, - _theResult___snd__h517032, - _theResult___snd__h517046, - _theResult___snd__h517052, - _theResult___snd__h517070, + _theResult___snd__h508285, + _theResult___snd__h508291, + _theResult___snd__h508314, + _theResult___snd__h517030, + _theResult___snd__h517044, + _theResult___snd__h517050, + _theResult___snd__h517068, + _theResult___snd__h537426, _theResult___snd__h537428, - _theResult___snd__h537430, - _theResult___snd__h537437, - _theResult___snd__h537443, - _theResult___snd__h537466, - _theResult___snd__h547065, + _theResult___snd__h537435, + _theResult___snd__h537441, + _theResult___snd__h537464, + _theResult___snd__h547063, + _theResult___snd__h547074, _theResult___snd__h547076, - _theResult___snd__h547078, - _theResult___snd__h547088, - _theResult___snd__h547094, - _theResult___snd__h547117, - _theResult___snd__h555833, - _theResult___snd__h555847, - _theResult___snd__h555853, - _theResult___snd__h555871, + _theResult___snd__h547086, + _theResult___snd__h547092, + _theResult___snd__h547115, + _theResult___snd__h555831, + _theResult___snd__h555845, + _theResult___snd__h555851, + _theResult___snd__h555869, + _theResult___snd__h576627, _theResult___snd__h576629, - _theResult___snd__h576631, - _theResult___snd__h576638, - _theResult___snd__h576644, - _theResult___snd__h576667, - _theResult___snd__h586266, + _theResult___snd__h576636, + _theResult___snd__h576642, + _theResult___snd__h576665, + _theResult___snd__h586264, + _theResult___snd__h586275, _theResult___snd__h586277, - _theResult___snd__h586279, - _theResult___snd__h586289, - _theResult___snd__h586295, - _theResult___snd__h586318, - _theResult___snd__h595034, - _theResult___snd__h595048, - _theResult___snd__h595054, - _theResult___snd__h595072, - r1__read__h610060, - r1__read__h610208, - r1__read__h610238, - r1__read__h610380, - result__h361554, - result__h407244, - result__h452932, - result__h500630, - result__h539431, - result__h578632, - sfd__h335697, - sfd__h381392, - sfd__h427080, - sfd__h479675, - sfd__h518617, - sfd__h557818, - sfdin__h351407, - sfdin__h369173, - sfdin__h397097, - sfdin__h414863, - sfdin__h442785, - sfdin__h460551, - sfdin__h508247, - sfdin__h547048, - sfdin__h586249, - x__h361651, - x__h407341, - x__h453029, - x__h500725, - x__h539526, - x__h578727; - wire [55 : 0] r1__read__h608847, - r1__read__h609251, - r1__read__h609805, - r1__read__h610062, - r1__read__h610240, - r1__read__h610382; - wire [54 : 0] r1__read__h608849, - r1__read__h609253, - r1__read__h609807, - r1__read__h610064, - r1__read__h610242, - r1__read__h610384; - wire [53 : 0] r1__read__h610185, - r1__read__h610210, - r1__read__h610244, - r1__read__h610386, - sfd__h498694, - sfd__h508345, - sfd__h517105, - sfd__h537495, - sfd__h547146, - sfd__h555906, - sfd__h576696, - sfd__h586347, - sfd__h595107, - value__h343924, - value__h389614, - value__h435302; - wire [52 : 0] r1__read__h610066, - r1__read__h610187, - r1__read__h610212, - r1__read__h610246, - r1__read__h610388; + _theResult___snd__h586287, + _theResult___snd__h586293, + _theResult___snd__h586316, + _theResult___snd__h595032, + _theResult___snd__h595046, + _theResult___snd__h595052, + _theResult___snd__h595070, + r1__read__h610061, + r1__read__h610209, + r1__read__h610239, + r1__read__h610381, + result__h361552, + result__h407242, + result__h452930, + result__h500628, + result__h539429, + result__h578630, + sfd__h335695, + sfd__h381390, + sfd__h427078, + sfd__h479673, + sfd__h518615, + sfd__h557816, + sfdin__h351405, + sfdin__h369171, + sfdin__h397095, + sfdin__h414861, + sfdin__h442783, + sfdin__h460549, + sfdin__h508245, + sfdin__h547046, + sfdin__h586247, + x__h361649, + x__h407339, + x__h453027, + x__h500723, + x__h539524, + x__h578725; + wire [55 : 0] r1__read__h608848, + r1__read__h609252, + r1__read__h609806, + r1__read__h610063, + r1__read__h610241, + r1__read__h610383; + wire [54 : 0] r1__read__h608850, + r1__read__h609254, + r1__read__h609808, + r1__read__h610065, + r1__read__h610243, + r1__read__h610385; + wire [53 : 0] r1__read__h610186, + r1__read__h610211, + r1__read__h610245, + r1__read__h610387, + sfd__h498692, + sfd__h508343, + sfd__h517103, + sfd__h537493, + sfd__h547144, + sfd__h555904, + sfd__h576694, + sfd__h586345, + sfd__h595105, + value__h343922, + value__h389612, + value__h435300; + wire [52 : 0] r1__read__h610067, + r1__read__h610188, + r1__read__h610213, + r1__read__h610247, + r1__read__h610389; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132, @@ -4820,110 +4820,110 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857, - _theResult___fst_sfd__h483604, - _theResult___fst_sfd__h499432, - _theResult___fst_sfd__h499435, - _theResult___fst_sfd__h509083, - _theResult___fst_sfd__h509086, - _theResult___fst_sfd__h517867, - _theResult___fst_sfd__h517870, - _theResult___fst_sfd__h517879, - _theResult___fst_sfd__h517885, - _theResult___fst_sfd__h522405, - _theResult___fst_sfd__h538233, - _theResult___fst_sfd__h538236, - _theResult___fst_sfd__h547884, - _theResult___fst_sfd__h547887, - _theResult___fst_sfd__h556668, - _theResult___fst_sfd__h556671, - _theResult___fst_sfd__h556680, - _theResult___fst_sfd__h556686, - _theResult___fst_sfd__h561606, - _theResult___fst_sfd__h577434, - _theResult___fst_sfd__h577437, - _theResult___fst_sfd__h587085, - _theResult___fst_sfd__h587088, - _theResult___fst_sfd__h595869, - _theResult___fst_sfd__h595872, - _theResult___fst_sfd__h595881, - _theResult___fst_sfd__h595887, - _theResult___sfd__h499332, - _theResult___sfd__h508983, - _theResult___sfd__h517767, - _theResult___sfd__h538133, - _theResult___sfd__h547784, - _theResult___sfd__h556568, - _theResult___sfd__h577334, - _theResult___sfd__h586985, - _theResult___sfd__h595769, - _theResult___snd_fst_sfd__h479629, - _theResult___snd_fst_sfd__h499438, - _theResult___snd_fst_sfd__h517873, - _theResult___snd_fst_sfd__h518571, - _theResult___snd_fst_sfd__h538239, - _theResult___snd_fst_sfd__h556674, - _theResult___snd_fst_sfd__h557772, - _theResult___snd_fst_sfd__h577440, - _theResult___snd_fst_sfd__h595875, - out___1_sfd__h479378, - out___1_sfd__h518320, - out___1_sfd__h557521, - out_sfd__h499335, - out_sfd__h508986, - out_sfd__h517770, - out_sfd__h538136, - out_sfd__h547787, - out_sfd__h556571, - out_sfd__h577337, - out_sfd__h586988, - out_sfd__h595772, - r1__read__h610390; - wire [50 : 0] r1__read__h608851, r1__read__h610068; - wire [49 : 0] r1__read__h610189, r1__read__h610392; - wire [48 : 0] r1__read__h608853, r1__read__h610070, r1__read__h610191; - wire [46 : 0] r1__read__h608855, r1__read__h610072; - wire [45 : 0] r1__read__h608857, r1__read__h610074; - wire [44 : 0] r1__read__h608859, r1__read__h610076; - wire [43 : 0] r1__read__h608861, r1__read__h610078; - wire [42 : 0] r1__read__h610080; - wire [41 : 0] r1__read__h610082; - wire [40 : 0] r1__read__h610084; + _theResult___fst_sfd__h483602, + _theResult___fst_sfd__h499430, + _theResult___fst_sfd__h499433, + _theResult___fst_sfd__h509081, + _theResult___fst_sfd__h509084, + _theResult___fst_sfd__h517865, + _theResult___fst_sfd__h517868, + _theResult___fst_sfd__h517877, + _theResult___fst_sfd__h517883, + _theResult___fst_sfd__h522403, + _theResult___fst_sfd__h538231, + _theResult___fst_sfd__h538234, + _theResult___fst_sfd__h547882, + _theResult___fst_sfd__h547885, + _theResult___fst_sfd__h556666, + _theResult___fst_sfd__h556669, + _theResult___fst_sfd__h556678, + _theResult___fst_sfd__h556684, + _theResult___fst_sfd__h561604, + _theResult___fst_sfd__h577432, + _theResult___fst_sfd__h577435, + _theResult___fst_sfd__h587083, + _theResult___fst_sfd__h587086, + _theResult___fst_sfd__h595867, + _theResult___fst_sfd__h595870, + _theResult___fst_sfd__h595879, + _theResult___fst_sfd__h595885, + _theResult___sfd__h499330, + _theResult___sfd__h508981, + _theResult___sfd__h517765, + _theResult___sfd__h538131, + _theResult___sfd__h547782, + _theResult___sfd__h556566, + _theResult___sfd__h577332, + _theResult___sfd__h586983, + _theResult___sfd__h595767, + _theResult___snd_fst_sfd__h479627, + _theResult___snd_fst_sfd__h499436, + _theResult___snd_fst_sfd__h517871, + _theResult___snd_fst_sfd__h518569, + _theResult___snd_fst_sfd__h538237, + _theResult___snd_fst_sfd__h556672, + _theResult___snd_fst_sfd__h557770, + _theResult___snd_fst_sfd__h577438, + _theResult___snd_fst_sfd__h595873, + out___1_sfd__h479376, + out___1_sfd__h518318, + out___1_sfd__h557519, + out_sfd__h499333, + out_sfd__h508984, + out_sfd__h517768, + out_sfd__h538134, + out_sfd__h547785, + out_sfd__h556569, + out_sfd__h577335, + out_sfd__h586986, + out_sfd__h595770, + r1__read__h610391; + wire [50 : 0] r1__read__h608852, r1__read__h610069; + wire [49 : 0] r1__read__h610190, r1__read__h610393; + wire [48 : 0] r1__read__h608854, r1__read__h610071, r1__read__h610192; + wire [46 : 0] r1__read__h608856, r1__read__h610073; + wire [45 : 0] r1__read__h608858, r1__read__h610075; + wire [44 : 0] r1__read__h608860, r1__read__h610077; + wire [43 : 0] r1__read__h608862, r1__read__h610079; + wire [42 : 0] r1__read__h610081; + wire [41 : 0] r1__read__h610083; + wire [40 : 0] r1__read__h610085; wire [37 : 0] IF_fetchStage_pipelines_0_first__2605_BIT_160__ETC___d13871, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4, - data72481_BITS_31_TO_0__q5, - imm__h649454, - r1__read__h608863, - r1__read__h610086, - x__h190902, - x__h335101, - x__h380796, - x__h426484, + data72479_BITS_31_TO_0__q5, + imm__h649452, + r1__read__h608864, + r1__read__h610087, + x__h190900, + x__h335099, + x__h380794, + x__h426482, x__h75524, x_data__h65373, - x_data_imm__h667949, - x_data_imm__h682692; - wire [29 : 0] r1__read__h608865, r1__read__h610088; - wire [27 : 0] r1__read__h610090; + x_data_imm__h667947, + x_data_imm__h682690; + wire [29 : 0] r1__read__h608866, r1__read__h610089; + wire [27 : 0] r1__read__h610091; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13903, - sfd__h351505, - sfd__h360087, - sfd__h369271, - sfd__h377883, - sfd__h397195, - sfd__h405777, - sfd__h414961, - sfd__h423573, - sfd__h442883, - sfd__h451465, - sfd__h460649, - sfd__h469261, - value__h484233, - value__h523034, - value__h562235; + sfd__h351503, + sfd__h360085, + sfd__h369269, + sfd__h377881, + sfd__h397193, + sfd__h405775, + sfd__h414959, + sfd__h423571, + sfd__h442881, + sfd__h451463, + sfd__h460647, + sfd__h469259, + value__h484231, + value__h523032, + value__h562233; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345, @@ -4948,72 +4948,72 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804, - _theResult___fst_sfd__h352011, - _theResult___fst_sfd__h360593, - _theResult___fst_sfd__h369777, - _theResult___fst_sfd__h378413, - _theResult___fst_sfd__h378422, - _theResult___fst_sfd__h378428, - _theResult___fst_sfd__h397701, - _theResult___fst_sfd__h406283, - _theResult___fst_sfd__h415467, - _theResult___fst_sfd__h424103, - _theResult___fst_sfd__h424112, - _theResult___fst_sfd__h424118, - _theResult___fst_sfd__h443389, - _theResult___fst_sfd__h451971, - _theResult___fst_sfd__h461155, - _theResult___fst_sfd__h469791, - _theResult___fst_sfd__h469800, - _theResult___fst_sfd__h469806, - _theResult___sfd__h351930, - _theResult___sfd__h360512, - _theResult___sfd__h369696, - _theResult___sfd__h378332, - _theResult___sfd__h378434, - _theResult___sfd__h397620, - _theResult___sfd__h406202, - _theResult___sfd__h415386, - _theResult___sfd__h424022, - _theResult___sfd__h424124, - _theResult___sfd__h443308, - _theResult___sfd__h451890, - _theResult___sfd__h461074, - _theResult___sfd__h469710, - _theResult___sfd__h469812, - _theResult___snd_fst_sfd__h335647, - _theResult___snd_fst_sfd__h360596, - _theResult___snd_fst_sfd__h378416, - _theResult___snd_fst_sfd__h381342, - _theResult___snd_fst_sfd__h406286, - _theResult___snd_fst_sfd__h424106, - _theResult___snd_fst_sfd__h427030, - _theResult___snd_fst_sfd__h451974, - _theResult___snd_fst_sfd__h469794, - out_f_sfd__h378711, - out_f_sfd__h424401, - out_f_sfd__h470089, - out_sfd__h351933, - out_sfd__h360515, - out_sfd__h369699, - out_sfd__h378335, - out_sfd__h397623, - out_sfd__h406205, - out_sfd__h415389, - out_sfd__h424025, - out_sfd__h443311, - out_sfd__h451893, - out_sfd__h461077, - out_sfd__h469713; - wire [19 : 0] r1__read__h610025; + _theResult___fst_sfd__h352009, + _theResult___fst_sfd__h360591, + _theResult___fst_sfd__h369775, + _theResult___fst_sfd__h378411, + _theResult___fst_sfd__h378420, + _theResult___fst_sfd__h378426, + _theResult___fst_sfd__h397699, + _theResult___fst_sfd__h406281, + _theResult___fst_sfd__h415465, + _theResult___fst_sfd__h424101, + _theResult___fst_sfd__h424110, + _theResult___fst_sfd__h424116, + _theResult___fst_sfd__h443387, + _theResult___fst_sfd__h451969, + _theResult___fst_sfd__h461153, + _theResult___fst_sfd__h469789, + _theResult___fst_sfd__h469798, + _theResult___fst_sfd__h469804, + _theResult___sfd__h351928, + _theResult___sfd__h360510, + _theResult___sfd__h369694, + _theResult___sfd__h378330, + _theResult___sfd__h378432, + _theResult___sfd__h397618, + _theResult___sfd__h406200, + _theResult___sfd__h415384, + _theResult___sfd__h424020, + _theResult___sfd__h424122, + _theResult___sfd__h443306, + _theResult___sfd__h451888, + _theResult___sfd__h461072, + _theResult___sfd__h469708, + _theResult___sfd__h469810, + _theResult___snd_fst_sfd__h335645, + _theResult___snd_fst_sfd__h360594, + _theResult___snd_fst_sfd__h378414, + _theResult___snd_fst_sfd__h381340, + _theResult___snd_fst_sfd__h406284, + _theResult___snd_fst_sfd__h424104, + _theResult___snd_fst_sfd__h427028, + _theResult___snd_fst_sfd__h451972, + _theResult___snd_fst_sfd__h469792, + out_f_sfd__h378709, + out_f_sfd__h424399, + out_f_sfd__h470087, + out_sfd__h351931, + out_sfd__h360513, + out_sfd__h369697, + out_sfd__h378333, + out_sfd__h397621, + out_sfd__h406203, + out_sfd__h415387, + out_sfd__h424023, + out_sfd__h443309, + out_sfd__h451891, + out_sfd__h461075, + out_sfd__h469711; + wire [19 : 0] r1__read__h610026; wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674, - _theResult____h645398, - enabled_ints___1__h645895, - enabled_ints__h645942, - pend_ints__h645396, - y__h645907; + _theResult____h645396, + enabled_ints___1__h645893, + enabled_ints__h645940, + pend_ints__h645394, + y__h645905; wire [12 : 0] fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - r1__read_BITS_12_TO_0___h645918; + r1__read_BITS_12_TO_0___h645916; wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648, @@ -5043,24 +5043,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334, - renaming_spec_bits__h675348, - result__h641105, - result__h641156, - spec_bits__h678443, - w__h641100, - x__h361684, - x__h407374, - x__h453062, - x__h500758, - x__h539559, - x__h578760, - x__h641104, - x__h641155, - y__h641134, - y__h678456, - y_avValue_fst__h671840, - y_avValue_snd_fst__h672114, - y_avValue_snd_fst__h672149; + renaming_spec_bits__h675346, + result__h641103, + result__h641154, + spec_bits__h678441, + w__h641098, + x__h361682, + x__h407372, + x__h453060, + x__h500756, + x__h539557, + x__h578758, + x__h641102, + x__h641153, + y__h641132, + y__h678454, + y_avValue_fst__h671838, + y_avValue_snd_fst__h672112, + y_avValue_snd_fst__h672147; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048, @@ -5082,103 +5082,103 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172, - _theResult___exp__h499331, - _theResult___exp__h508982, - _theResult___exp__h517766, - _theResult___exp__h538132, - _theResult___exp__h547783, - _theResult___exp__h556567, - _theResult___exp__h577333, - _theResult___exp__h586984, - _theResult___exp__h595768, - _theResult___fst_exp__h483603, - _theResult___fst_exp__h498667, - _theResult___fst_exp__h498673, - _theResult___fst_exp__h498676, - _theResult___fst_exp__h499431, - _theResult___fst_exp__h499434, - _theResult___fst_exp__h508253, - _theResult___fst_exp__h508318, - _theResult___fst_exp__h508324, - _theResult___fst_exp__h508327, - _theResult___fst_exp__h509082, - _theResult___fst_exp__h509085, - _theResult___fst_exp__h517038, - _theResult___fst_exp__h517077, - _theResult___fst_exp__h517083, - _theResult___fst_exp__h517086, - _theResult___fst_exp__h517866, - _theResult___fst_exp__h517869, - _theResult___fst_exp__h517878, - _theResult___fst_exp__h517881, - _theResult___fst_exp__h522404, - _theResult___fst_exp__h537468, - _theResult___fst_exp__h537474, - _theResult___fst_exp__h537477, - _theResult___fst_exp__h538232, - _theResult___fst_exp__h538235, - _theResult___fst_exp__h547054, - _theResult___fst_exp__h547119, - _theResult___fst_exp__h547125, - _theResult___fst_exp__h547128, - _theResult___fst_exp__h547883, - _theResult___fst_exp__h547886, - _theResult___fst_exp__h555839, - _theResult___fst_exp__h555878, - _theResult___fst_exp__h555884, - _theResult___fst_exp__h555887, - _theResult___fst_exp__h556667, - _theResult___fst_exp__h556670, - _theResult___fst_exp__h556679, - _theResult___fst_exp__h556682, - _theResult___fst_exp__h561605, - _theResult___fst_exp__h576669, - _theResult___fst_exp__h576675, - _theResult___fst_exp__h576678, - _theResult___fst_exp__h577433, - _theResult___fst_exp__h577436, - _theResult___fst_exp__h586255, - _theResult___fst_exp__h586320, - _theResult___fst_exp__h586326, - _theResult___fst_exp__h586329, - _theResult___fst_exp__h587084, - _theResult___fst_exp__h587087, - _theResult___fst_exp__h595040, - _theResult___fst_exp__h595079, - _theResult___fst_exp__h595085, - _theResult___fst_exp__h595088, - _theResult___fst_exp__h595868, - _theResult___fst_exp__h595871, - _theResult___fst_exp__h595880, - _theResult___fst_exp__h595883, - _theResult___snd_fst_exp__h499437, - _theResult___snd_fst_exp__h517872, - _theResult___snd_fst_exp__h538238, - _theResult___snd_fst_exp__h556673, - _theResult___snd_fst_exp__h577439, - _theResult___snd_fst_exp__h595874, + _theResult___exp__h499329, + _theResult___exp__h508980, + _theResult___exp__h517764, + _theResult___exp__h538130, + _theResult___exp__h547781, + _theResult___exp__h556565, + _theResult___exp__h577331, + _theResult___exp__h586982, + _theResult___exp__h595766, + _theResult___fst_exp__h483601, + _theResult___fst_exp__h498665, + _theResult___fst_exp__h498671, + _theResult___fst_exp__h498674, + _theResult___fst_exp__h499429, + _theResult___fst_exp__h499432, + _theResult___fst_exp__h508251, + _theResult___fst_exp__h508316, + _theResult___fst_exp__h508322, + _theResult___fst_exp__h508325, + _theResult___fst_exp__h509080, + _theResult___fst_exp__h509083, + _theResult___fst_exp__h517036, + _theResult___fst_exp__h517075, + _theResult___fst_exp__h517081, + _theResult___fst_exp__h517084, + _theResult___fst_exp__h517864, + _theResult___fst_exp__h517867, + _theResult___fst_exp__h517876, + _theResult___fst_exp__h517879, + _theResult___fst_exp__h522402, + _theResult___fst_exp__h537466, + _theResult___fst_exp__h537472, + _theResult___fst_exp__h537475, + _theResult___fst_exp__h538230, + _theResult___fst_exp__h538233, + _theResult___fst_exp__h547052, + _theResult___fst_exp__h547117, + _theResult___fst_exp__h547123, + _theResult___fst_exp__h547126, + _theResult___fst_exp__h547881, + _theResult___fst_exp__h547884, + _theResult___fst_exp__h555837, + _theResult___fst_exp__h555876, + _theResult___fst_exp__h555882, + _theResult___fst_exp__h555885, + _theResult___fst_exp__h556665, + _theResult___fst_exp__h556668, + _theResult___fst_exp__h556677, + _theResult___fst_exp__h556680, + _theResult___fst_exp__h561603, + _theResult___fst_exp__h576667, + _theResult___fst_exp__h576673, + _theResult___fst_exp__h576676, + _theResult___fst_exp__h577431, + _theResult___fst_exp__h577434, + _theResult___fst_exp__h586253, + _theResult___fst_exp__h586318, + _theResult___fst_exp__h586324, + _theResult___fst_exp__h586327, + _theResult___fst_exp__h587082, + _theResult___fst_exp__h587085, + _theResult___fst_exp__h595038, + _theResult___fst_exp__h595077, + _theResult___fst_exp__h595083, + _theResult___fst_exp__h595086, + _theResult___fst_exp__h595866, + _theResult___fst_exp__h595869, + _theResult___fst_exp__h595878, + _theResult___fst_exp__h595881, + _theResult___snd_fst_exp__h499435, + _theResult___snd_fst_exp__h517870, + _theResult___snd_fst_exp__h538236, + _theResult___snd_fst_exp__h556671, + _theResult___snd_fst_exp__h577437, + _theResult___snd_fst_exp__h595872, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98, csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, - din_inc___2_exp__h517926, - din_inc___2_exp__h517961, - din_inc___2_exp__h517987, - din_inc___2_exp__h556727, - din_inc___2_exp__h556762, - din_inc___2_exp__h556788, - din_inc___2_exp__h595928, - din_inc___2_exp__h595963, - din_inc___2_exp__h595989, - out_exp__h499334, - out_exp__h508985, - out_exp__h517769, - out_exp__h538135, - out_exp__h547786, - out_exp__h556570, - out_exp__h577336, - out_exp__h586987, - out_exp__h595771; + din_inc___2_exp__h517924, + din_inc___2_exp__h517959, + din_inc___2_exp__h517985, + din_inc___2_exp__h556725, + din_inc___2_exp__h556760, + din_inc___2_exp__h556786, + din_inc___2_exp__h595926, + din_inc___2_exp__h595961, + din_inc___2_exp__h595987, + out_exp__h499332, + out_exp__h508983, + out_exp__h517767, + out_exp__h538133, + out_exp__h547784, + out_exp__h556568, + out_exp__h577334, + out_exp__h586985, + out_exp__h595769; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652; @@ -5209,121 +5209,121 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104, - _theResult___exp__h351929, - _theResult___exp__h360511, - _theResult___exp__h369695, - _theResult___exp__h378331, - _theResult___exp__h378433, - _theResult___exp__h397619, - _theResult___exp__h406201, - _theResult___exp__h415385, - _theResult___exp__h424021, - _theResult___exp__h424123, - _theResult___exp__h443307, - _theResult___exp__h451889, - _theResult___exp__h461073, - _theResult___exp__h469709, - _theResult___exp__h469811, - _theResult___fst_exp__h351413, - _theResult___fst_exp__h351478, - _theResult___fst_exp__h351484, - _theResult___fst_exp__h351487, - _theResult___fst_exp__h352010, - _theResult___fst_exp__h360060, - _theResult___fst_exp__h360066, - _theResult___fst_exp__h360069, - _theResult___fst_exp__h360592, - _theResult___fst_exp__h369179, - _theResult___fst_exp__h369244, - _theResult___fst_exp__h369250, - _theResult___fst_exp__h369253, - _theResult___fst_exp__h369776, - _theResult___fst_exp__h377816, - _theResult___fst_exp__h377855, - _theResult___fst_exp__h377861, - _theResult___fst_exp__h377864, - _theResult___fst_exp__h378412, - _theResult___fst_exp__h378421, - _theResult___fst_exp__h378424, - _theResult___fst_exp__h397103, - _theResult___fst_exp__h397168, - _theResult___fst_exp__h397174, - _theResult___fst_exp__h397177, - _theResult___fst_exp__h397700, - _theResult___fst_exp__h405750, - _theResult___fst_exp__h405756, - _theResult___fst_exp__h405759, - _theResult___fst_exp__h406282, - _theResult___fst_exp__h414869, - _theResult___fst_exp__h414934, - _theResult___fst_exp__h414940, - _theResult___fst_exp__h414943, - _theResult___fst_exp__h415466, - _theResult___fst_exp__h423506, - _theResult___fst_exp__h423545, - _theResult___fst_exp__h423551, - _theResult___fst_exp__h423554, - _theResult___fst_exp__h424102, - _theResult___fst_exp__h424111, - _theResult___fst_exp__h424114, - _theResult___fst_exp__h442791, - _theResult___fst_exp__h442856, - _theResult___fst_exp__h442862, - _theResult___fst_exp__h442865, - _theResult___fst_exp__h443388, - _theResult___fst_exp__h451438, - _theResult___fst_exp__h451444, - _theResult___fst_exp__h451447, - _theResult___fst_exp__h451970, - _theResult___fst_exp__h460557, - _theResult___fst_exp__h460622, - _theResult___fst_exp__h460628, - _theResult___fst_exp__h460631, - _theResult___fst_exp__h461154, - _theResult___fst_exp__h469194, - _theResult___fst_exp__h469233, - _theResult___fst_exp__h469239, - _theResult___fst_exp__h469242, - _theResult___fst_exp__h469790, - _theResult___fst_exp__h469799, - _theResult___fst_exp__h469802, - _theResult___snd_fst_exp__h360595, - _theResult___snd_fst_exp__h378415, - _theResult___snd_fst_exp__h406285, - _theResult___snd_fst_exp__h424105, - _theResult___snd_fst_exp__h451973, - _theResult___snd_fst_exp__h469793, + _theResult___exp__h351927, + _theResult___exp__h360509, + _theResult___exp__h369693, + _theResult___exp__h378329, + _theResult___exp__h378431, + _theResult___exp__h397617, + _theResult___exp__h406199, + _theResult___exp__h415383, + _theResult___exp__h424019, + _theResult___exp__h424121, + _theResult___exp__h443305, + _theResult___exp__h451887, + _theResult___exp__h461071, + _theResult___exp__h469707, + _theResult___exp__h469809, + _theResult___fst_exp__h351411, + _theResult___fst_exp__h351476, + _theResult___fst_exp__h351482, + _theResult___fst_exp__h351485, + _theResult___fst_exp__h352008, + _theResult___fst_exp__h360058, + _theResult___fst_exp__h360064, + _theResult___fst_exp__h360067, + _theResult___fst_exp__h360590, + _theResult___fst_exp__h369177, + _theResult___fst_exp__h369242, + _theResult___fst_exp__h369248, + _theResult___fst_exp__h369251, + _theResult___fst_exp__h369774, + _theResult___fst_exp__h377814, + _theResult___fst_exp__h377853, + _theResult___fst_exp__h377859, + _theResult___fst_exp__h377862, + _theResult___fst_exp__h378410, + _theResult___fst_exp__h378419, + _theResult___fst_exp__h378422, + _theResult___fst_exp__h397101, + _theResult___fst_exp__h397166, + _theResult___fst_exp__h397172, + _theResult___fst_exp__h397175, + _theResult___fst_exp__h397698, + _theResult___fst_exp__h405748, + _theResult___fst_exp__h405754, + _theResult___fst_exp__h405757, + _theResult___fst_exp__h406280, + _theResult___fst_exp__h414867, + _theResult___fst_exp__h414932, + _theResult___fst_exp__h414938, + _theResult___fst_exp__h414941, + _theResult___fst_exp__h415464, + _theResult___fst_exp__h423504, + _theResult___fst_exp__h423543, + _theResult___fst_exp__h423549, + _theResult___fst_exp__h423552, + _theResult___fst_exp__h424100, + _theResult___fst_exp__h424109, + _theResult___fst_exp__h424112, + _theResult___fst_exp__h442789, + _theResult___fst_exp__h442854, + _theResult___fst_exp__h442860, + _theResult___fst_exp__h442863, + _theResult___fst_exp__h443386, + _theResult___fst_exp__h451436, + _theResult___fst_exp__h451442, + _theResult___fst_exp__h451445, + _theResult___fst_exp__h451968, + _theResult___fst_exp__h460555, + _theResult___fst_exp__h460620, + _theResult___fst_exp__h460626, + _theResult___fst_exp__h460629, + _theResult___fst_exp__h461152, + _theResult___fst_exp__h469192, + _theResult___fst_exp__h469231, + _theResult___fst_exp__h469237, + _theResult___fst_exp__h469240, + _theResult___fst_exp__h469788, + _theResult___fst_exp__h469797, + _theResult___fst_exp__h469800, + _theResult___snd_fst_exp__h360593, + _theResult___snd_fst_exp__h378413, + _theResult___snd_fst_exp__h406283, + _theResult___snd_fst_exp__h424103, + _theResult___snd_fst_exp__h451971, + _theResult___snd_fst_exp__h469791, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145, - din_inc___2_exp__h378446, - din_inc___2_exp__h378470, - din_inc___2_exp__h378500, - din_inc___2_exp__h378524, - din_inc___2_exp__h424136, - din_inc___2_exp__h424160, - din_inc___2_exp__h424190, - din_inc___2_exp__h424214, - din_inc___2_exp__h469824, - din_inc___2_exp__h469848, - din_inc___2_exp__h469878, - din_inc___2_exp__h469902, - out_exp__h351932, - out_exp__h360514, - out_exp__h369698, - out_exp__h378334, - out_exp__h397622, - out_exp__h406204, - out_exp__h415388, - out_exp__h424024, - out_exp__h443310, - out_exp__h451892, - out_exp__h461076, - out_exp__h469712, - out_f_exp__h378710, - out_f_exp__h424400, - out_f_exp__h470088, - x__h608822; + din_inc___2_exp__h378444, + din_inc___2_exp__h378468, + din_inc___2_exp__h378498, + din_inc___2_exp__h378522, + din_inc___2_exp__h424134, + din_inc___2_exp__h424158, + din_inc___2_exp__h424188, + din_inc___2_exp__h424212, + din_inc___2_exp__h469822, + din_inc___2_exp__h469846, + din_inc___2_exp__h469876, + din_inc___2_exp__h469900, + out_exp__h351930, + out_exp__h360512, + out_exp__h369696, + out_exp__h378332, + out_exp__h397620, + out_exp__h406202, + out_exp__h415386, + out_exp__h424022, + out_exp__h443308, + out_exp__h451890, + out_exp__h461074, + out_exp__h469710, + out_f_exp__h378708, + out_f_exp__h424398, + out_f_exp__h470086, + x__h608823; wire [6 : 0] csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12642; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635, @@ -5345,8 +5345,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890, - x__h180648, - x__h694806; + x__h180646, + x__h694804; wire [4 : 0] IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165, @@ -5366,18 +5366,18 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804, checkForException___d12839, checkForException___d13458, - fflags__h705627, - res_fflags__h335090, - res_fflags__h380785, - res_fflags__h426473, - rs1__h649453, + fflags__h705625, + res_fflags__h335088, + res_fflags__h380783, + res_fflags__h426471, + rs1__h649451, x__h152884, x__h156431, x__h159247, - x__h284501, - y_avValue_snd_fst__h705134, - y_avValue_snd_fst__h705687, - y_avValue_snd_fst__h705716; + x__h284499, + y_avValue_snd_fst__h705132, + y_avValue_snd_fst__h705685, + y_avValue_snd_fst__h705714; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851, @@ -5404,74 +5404,74 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d13074, - cause_code__h692189, - vm_mode_reg__read__h610031; + cause_code__h692187, + vm_mode_reg__read__h610032; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h293743, - next_deqP___1__h294022, - v__h293163, - v__h293394, - x__h299373, - x_decodeInfo_frm__h649137; + _theResult_____2__h293741, + next_deqP___1__h294020, + v__h293161, + v__h293392, + x__h299371, + x_decodeInfo_frm__h649135; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771, - IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66, - IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91, - IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21, - IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101, - IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31, - IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148, - IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58, - IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71, - IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93, - IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23, - IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106, - IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36, - IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127, - guard__h343312, - guard__h352021, - guard__h360951, - guard__h369787, - guard__h389004, - guard__h397711, - guard__h406641, - guard__h415477, - guard__h434692, - guard__h443399, - guard__h452329, - guard__h461165, - guard__h490715, - guard__h500027, - guard__h509096, - guard__h529516, - guard__h538828, - guard__h547897, - guard__h568717, - guard__h578029, - guard__h587098, - prv__h707142, - prv__h707186, - r1__read_BITS_13_TO_12___h649322, + IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66, + IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91, + IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21, + IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101, + IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31, + IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148, + IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56, + IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58, + IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71, + IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93, + IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23, + IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106, + IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36, + IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127, + guard__h343310, + guard__h352019, + guard__h360949, + guard__h369785, + guard__h389002, + guard__h397709, + guard__h406639, + guard__h415475, + guard__h434690, + guard__h443397, + guard__h452327, + guard__h461163, + guard__h490713, + guard__h500025, + guard__h509094, + guard__h529514, + guard__h538826, + guard__h547895, + guard__h568715, + guard__h578027, + guard__h587096, + prv__h707140, + prv__h707184, + r1__read_BITS_13_TO_12___h649320, sbIdx__h156310, - v__h600774, - v__h600784, - v__h601419, - x__h702602, - x__h705875, - y_avValue_snd_snd_snd_fst__h705144, - y_avValue_snd_snd_snd_fst__h705697, - y_avValue_snd_snd_snd_fst__h705726; + v__h600772, + v__h600782, + v__h601417, + x__h702600, + x__h705873, + y_avValue_snd_snd_snd_fst__h705142, + y_avValue_snd_snd_snd_fst__h705695, + y_avValue_snd_snd_snd_fst__h705724; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457, @@ -5872,7 +5872,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo26, + _dfoo28, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -5898,11 +5898,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h301739, - _theResult_____2__h307733, - _theResult_____2__h315587, - _theResult_____2__h325931, - _theResult_____2__h329156, + _theResult_____2__h301737, + _theResult_____2__h307731, + _theResult_____2__h315585, + _theResult_____2__h325929, + _theResult_____2__h329154, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140, coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114, @@ -6036,14 +6036,14 @@ module mkCore(CLK, fetchStage_pipelines_1_first__2614_BITS_194_TO_ETC___d13720, fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555, fetchStage_pipelines_1_first__2614_BIT_68_3335_ETC___d13724, - guard__h361549, - guard__h407239, - guard__h452927, - guard__h500625, - guard__h539426, - guard__h578627, - idx__h675479, - k__h661045, + guard__h361547, + guard__h407237, + guard__h452925, + guard__h500623, + guard__h539424, + guard__h578625, + idx__h675477, + k__h661043, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6055,13 +6055,13 @@ module mkCore(CLK, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h75409, - next_deqP___1__h302018, - next_deqP___1__h308299, - next_deqP___1__h316153, - next_deqP___1__h326210, - next_deqP___1__h329435, - r1__read_BIT_20___h649950, - r__h608869, + next_deqP___1__h302016, + next_deqP___1__h308297, + next_deqP___1__h316151, + next_deqP___1__h326208, + next_deqP___1__h329433, + r1__read_BIT_20___h649948, + r__h608870, regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688, regRenamingTable_RDY_rename_1_getRename__3744__ETC___d13762, regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258, @@ -6082,17 +6082,17 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631, - v__h296508, - v__h297026, - v__h307022, - v__h307253, - v__h310898, - v__h311129, - v__h325499, - v__h325730, - v__h328724, - v__h328955, - x__h600275; + v__h296506, + v__h297024, + v__h307020, + v__h307251, + v__h310896, + v__h311127, + v__h325497, + v__h325728, + v__h328722, + v__h328953, + x__h600273; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -10783,7 +10783,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -10795,7 +10795,7 @@ module mkCore(CLK, assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = @@ -10803,7 +10803,7 @@ module mkCore(CLK, (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -10860,7 +10860,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h688725, + x__h688723, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259 : @@ -10868,9 +10868,9 @@ module mkCore(CLK, assign MUX_commitStage_rg_instret$write_1__VAL_1 = commitStage_rg_instret + 64'd1 ; assign MUX_commitStage_rg_instret$write_1__VAL_2 = - commitStage_rg_instret + y__h705650 ; + commitStage_rg_instret + y__h705648 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h661045 == 1'd0 && + (k__h661043 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -10891,7 +10891,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -10994,7 +10994,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, @@ -11008,10 +11008,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h283068 } ; + x__h283066 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h284513, + x__h284511, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11019,7 +11019,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h287289, + addr__h287287, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11061,7 +11061,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h289193, + resp_addr__h289191, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11141,7 +11141,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h194349 } ; + x__h194347 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11176,8 +11176,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h190139 : - { {32{x__h190902[31]}}, x__h190902 } } ; + curData__h190137 : + { {32{x__h190900[31]}}, x__h190900 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[325:321], @@ -11206,7 +11206,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h705627 ; + csrf_fflags_reg | fflags__h705625 ; always@(IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 or robdeqPort_0_deq_data_BITS_95_TO_32__q261) begin @@ -11232,9 +11232,9 @@ module mkCore(CLK, csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h703199 + 64'd1 ; + n__read__h703197 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h703199 + { 62'd0, x__h705875 } ; + n__read__h703197 + { 62'd0, x__h705873 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == @@ -11242,7 +11242,7 @@ module mkCore(CLK, MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h693220 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h693218 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || @@ -11258,7 +11258,7 @@ module mkCore(CLK, MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h702602 : + x__h702600 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? @@ -11278,15 +11278,15 @@ module mkCore(CLK, MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? - y_avValue__h693067 : - y_avValue__h694828 ; + y_avValue__h693065 : + y_avValue__h694826 ; always@(rob$deqPort_0_deq_data or - next_pc__h702542 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h702540 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702542; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702540; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11321,23 +11321,23 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h473015 : - data__h472481 ; + data___1__h473013 : + data__h472479 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h335094 : - res_data__h335089 ; + res_data__h335092 : + res_data__h335087 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h380789 : - res_data__h380784 ; + res_data__h380787 : + res_data__h380782 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h426477 : - res_data__h426472 ; + res_data__h426475 : + res_data__h426470 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h472207 : + data___1__h472205 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? @@ -11416,15 +11416,15 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h335090 ; + res_fflags__h335088 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h380785 ; + res_fflags__h380783 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h426473 ; + res_fflags__h426471 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -11739,8 +11739,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h601419 : - v__h600774 ; + v__h601417 : + v__h600772 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -11847,7 +11847,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h293743 ; + _theResult_____2__h293741 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -11869,7 +11869,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h293163 ; + v__h293161 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -11915,7 +11915,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - _theResult_____2__h301739 ; + _theResult_____2__h301737 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -11933,7 +11933,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - v__h296508 ; + v__h296506 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12033,7 +12033,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - _theResult_____2__h307733 ; + _theResult_____2__h307731 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12051,7 +12051,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - v__h307022 ; + v__h307020 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12072,7 +12072,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h311296, + { x_addr__h311294, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12102,7 +12102,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - _theResult_____2__h315587 ; + _theResult_____2__h315585 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12120,7 +12120,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - v__h310898 ; + v__h310896 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12197,7 +12197,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - _theResult_____2__h329156 ; + _theResult_____2__h329154 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12215,7 +12215,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - v__h328724 ; + v__h328722 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12258,7 +12258,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - _theResult_____2__h325931 ; + _theResult_____2__h325929 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12276,7 +12276,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - v__h325499 ; + v__h325497 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12554,7 +12554,7 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__SEL_1 && MUX_csrf_ie_vec_1$write_1__VAL_1 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12570,7 +12570,7 @@ module mkCore(CLK, // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = MUX_csrf_ie_vec_3$write_1__SEL_2 ? - cause_code__h692189 : + cause_code__h692187 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12787,7 +12787,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : csrf_ie_vec_1 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12815,7 +12815,7 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = MUX_csrf_ie_vec_1$write_1__SEL_2 ? - cause_code__h692189 : + cause_code__h692187 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12933,7 +12933,7 @@ module mkCore(CLK, MUX_csrf_spp_reg$write_1__VAL_1 : csrf_prv_reg[0] ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -13472,8 +13472,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h634256, - x__h634257, + x__h634254, + x__h634255, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -13762,8 +13762,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h613033, x__h613034, + x__h613035, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -13805,7 +13805,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h661045 == 1'd1 && + (k__h661043 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -13826,7 +13826,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -13924,7 +13924,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h661045 == 1'd1 && + (k__h661043 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd1 && @@ -14310,19 +14310,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h600261 : - a__h599839 ; + _theResult___fst__h600259 : + a__h599837 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h599840 == 64'd0, - a__h599839, + { b__h599838 == 64'd0, + a__h599837, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h600275, - a__h599839[63], + x__h600273, + a__h599837[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h600262 : - b__h599840 ; + _theResult___snd__h600260 : + b__h599838 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14383,20 +14383,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599839 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599840 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599837 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599838 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h599839 ; + a__h599837 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h599840 ; + b__h599838 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h599839 ; + a__h599837 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h599840 ; + b__h599838 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -14425,9 +14425,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], + x__h478868, + x__h478869, x__h478870, - x__h478871, - x__h478872, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -14479,7 +14479,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14633,8 +14633,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h284501, - x__h284513, + { x__h284499, + x__h284511, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, @@ -14645,13 +14645,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - x__h286367, + x__h286365, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h283068 ; + x__h283066 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -15288,13 +15288,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h180511[2:0], - vaddr__h180511, + coreFix_memExe_lsq$getOrigBE << vaddr__h180509[2:0], + vaddr__h180509, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h180511[2:0] != 3'd0 : + vaddr__h180509[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h180511[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180511[0]), + vaddr__h180509[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180509[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15324,8 +15324,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h707186, - prv__h707186 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h707184, + prv__h707184 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15450,7 +15450,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675348 ; + renaming_spec_bits__h675346 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? @@ -15470,7 +15470,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675348 ; + renaming_spec_bits__h675346 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15550,7 +15550,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h180516 ; + shiftData__h180514 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -15650,8 +15650,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h180425, - x__h180426, + x__h180423, + x__h180424, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15915,7 +15915,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675348, + renaming_spec_bits__h675346, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16624,7 +16624,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h675348 ; + renaming_spec_bits__h675346 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -16883,7 +16883,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, 7'd32, - renaming_spec_bits__h675348 } ; + renaming_spec_bits__h675346 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17385,10 +17385,10 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h190139), + .amoExec_current_data(curData__h190137), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h191677)); + .amoExec(n__h191675)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, @@ -17425,7 +17425,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 }, fetchStage$pipelines_0_first[160], - x_data_imm__h667949 } }), + x_data_imm__h667947 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17434,12 +17434,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649137, - r1__read_BITS_13_TO_12___h649322 != + .checkForException_csrState({ x_decodeInfo_frm__h649135, + r1__read_BITS_13_TO_12___h649320 != 2'd0, - { prv__h707142, + { prv__h707140, csrf_tvm_reg, - { r1__read_BIT_20___h649950, + { r1__read_BIT_20___h649948, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17455,7 +17455,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, { fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, fetchStage$pipelines_1_first[160], - x_data_imm__h682692 } }), + x_data_imm__h682690 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17464,12 +17464,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649137, - r1__read_BITS_13_TO_12___h649322 != + .checkForException_csrState({ x_decodeInfo_frm__h649135, + r1__read_BITS_13_TO_12___h649320 != 2'd0, - { prv__h707142, + { prv__h707140, csrf_tvm_reg, - { r1__read_BIT_20___h649950, + { r1__read_BIT_20___h649948, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17484,139 +17484,139 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h478961), - .execFpuSimple_rVal2(rVal2__h478962), + .execFpuSimple_rVal1(rVal1__h478959), + .execFpuSimple_rVal2(rVal2__h478960), .execFpuSimple(execFpuSimple___d11034)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ? - _theResult___snd__h351476 : - _theResult____h343302 ; + _theResult___snd__h351474 : + _theResult____h343300 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ? - _theResult___snd__h397166 : - _theResult____h388994 ; + _theResult___snd__h397164 : + _theResult____h388992 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ? - _theResult___snd__h442854 : - _theResult____h434682 ; + _theResult___snd__h442852 : + _theResult____h434680 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 ? - _theResult___snd__h508316 : - _theResult____h500017 ; + _theResult___snd__h508314 : + _theResult____h500015 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599 ? - _theResult___snd__h586318 : - _theResult____h578019 ; + _theResult___snd__h586316 : + _theResult____h578017 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 ? - _theResult___snd__h547117 : - _theResult____h538818 ; + _theResult___snd__h547115 : + _theResult____h538816 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ? - _theResult___snd__h460620 : - _theResult____h452319 ; + _theResult___snd__h460618 : + _theResult____h452317 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ? - _theResult___snd__h369242 : - _theResult____h360941 ; + _theResult___snd__h369240 : + _theResult____h360939 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ? - _theResult___snd__h414932 : - _theResult____h406631 ; + _theResult___snd__h414930 : + _theResult____h406629 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ? - _theResult___snd__h451436 : - _theResult___snd__h469226 ; + _theResult___snd__h451434 : + _theResult___snd__h469224 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ? - _theResult___snd__h360058 : + _theResult___snd__h360056 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ? - _theResult___snd__h360058 : - _theResult___snd__h377848 ; + _theResult___snd__h360056 : + _theResult___snd__h377846 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ? - _theResult___snd__h405748 : + _theResult___snd__h405746 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ? - _theResult___snd__h405748 : - _theResult___snd__h423538 ; + _theResult___snd__h405746 : + _theResult___snd__h423536 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ? - _theResult___snd__h451436 : + _theResult___snd__h451434 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 ? - _theResult___snd__h498665 : + _theResult___snd__h498663 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939 ? - _theResult___snd__h498665 : - _theResult___snd__h517070 ; + _theResult___snd__h498663 : + _theResult___snd__h517068 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302 ? - _theResult___snd__h576667 : + _theResult___snd__h576665 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649 ? - _theResult___snd__h576667 : - _theResult___snd__h595072 ; + _theResult___snd__h576665 : + _theResult___snd__h595070 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 ? - _theResult___snd__h537466 : + _theResult___snd__h537464 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412 ? - _theResult___snd__h537466 : - _theResult___snd__h555871 ; + _theResult___snd__h537464 : + _theResult___snd__h555869 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351413 == 8'd255) ? + ((_theResult___fst_exp__h351411 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) : - ((_theResult___fst_exp__h360069 == 8'd255) ? + ((_theResult___fst_exp__h360067 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351413 == 8'd255) ? + ((_theResult___fst_exp__h351411 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) : - ((_theResult___fst_exp__h360069 == 8'd255) ? + ((_theResult___fst_exp__h360067 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397103 == 8'd255) ? + ((_theResult___fst_exp__h397101 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) : - ((_theResult___fst_exp__h405759 == 8'd255) ? + ((_theResult___fst_exp__h405757 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397103 == 8'd255) ? + ((_theResult___fst_exp__h397101 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) : - ((_theResult___fst_exp__h405759 == 8'd255) ? + ((_theResult___fst_exp__h405757 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442791 == 8'd255) ? + ((_theResult___fst_exp__h442789 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) : - ((_theResult___fst_exp__h451447 == 8'd255) ? + ((_theResult___fst_exp__h451445 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442791 == 8'd255) ? + ((_theResult___fst_exp__h442789 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) : - ((_theResult___fst_exp__h451447 == 8'd255) ? + ((_theResult___fst_exp__h451445 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ; assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10657 = @@ -17632,1571 +17632,1571 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892) : !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 = - (_theResult____h343302[56] ? + (_theResult____h343300[56] ? 6'd0 : - (_theResult____h343302[55] ? + (_theResult____h343300[55] ? 6'd1 : - (_theResult____h343302[54] ? + (_theResult____h343300[54] ? 6'd2 : - (_theResult____h343302[53] ? + (_theResult____h343300[53] ? 6'd3 : - (_theResult____h343302[52] ? + (_theResult____h343300[52] ? 6'd4 : - (_theResult____h343302[51] ? + (_theResult____h343300[51] ? 6'd5 : - (_theResult____h343302[50] ? + (_theResult____h343300[50] ? 6'd6 : - (_theResult____h343302[49] ? + (_theResult____h343300[49] ? 6'd7 : - (_theResult____h343302[48] ? + (_theResult____h343300[48] ? 6'd8 : - (_theResult____h343302[47] ? + (_theResult____h343300[47] ? 6'd9 : - (_theResult____h343302[46] ? + (_theResult____h343300[46] ? 6'd10 : - (_theResult____h343302[45] ? + (_theResult____h343300[45] ? 6'd11 : - (_theResult____h343302[44] ? + (_theResult____h343300[44] ? 6'd12 : - (_theResult____h343302[43] ? + (_theResult____h343300[43] ? 6'd13 : - (_theResult____h343302[42] ? + (_theResult____h343300[42] ? 6'd14 : - (_theResult____h343302[41] ? + (_theResult____h343300[41] ? 6'd15 : - (_theResult____h343302[40] ? + (_theResult____h343300[40] ? 6'd16 : - (_theResult____h343302[39] ? + (_theResult____h343300[39] ? 6'd17 : - (_theResult____h343302[38] ? + (_theResult____h343300[38] ? 6'd18 : - (_theResult____h343302[37] ? + (_theResult____h343300[37] ? 6'd19 : - (_theResult____h343302[36] ? + (_theResult____h343300[36] ? 6'd20 : - (_theResult____h343302[35] ? + (_theResult____h343300[35] ? 6'd21 : - (_theResult____h343302[34] ? + (_theResult____h343300[34] ? 6'd22 : - (_theResult____h343302[33] ? + (_theResult____h343300[33] ? 6'd23 : - (_theResult____h343302[32] ? + (_theResult____h343300[32] ? 6'd24 : - (_theResult____h343302[31] ? + (_theResult____h343300[31] ? 6'd25 : - (_theResult____h343302[30] ? + (_theResult____h343300[30] ? 6'd26 : - (_theResult____h343302[29] ? + (_theResult____h343300[29] ? 6'd27 : - (_theResult____h343302[28] ? + (_theResult____h343300[28] ? 6'd28 : - (_theResult____h343302[27] ? + (_theResult____h343300[27] ? 6'd29 : - (_theResult____h343302[26] ? + (_theResult____h343300[26] ? 6'd30 : - (_theResult____h343302[25] ? + (_theResult____h343300[25] ? 6'd31 : - (_theResult____h343302[24] ? + (_theResult____h343300[24] ? 6'd32 : - (_theResult____h343302[23] ? + (_theResult____h343300[23] ? 6'd33 : - (_theResult____h343302[22] ? + (_theResult____h343300[22] ? 6'd34 : - (_theResult____h343302[21] ? + (_theResult____h343300[21] ? 6'd35 : - (_theResult____h343302[20] ? + (_theResult____h343300[20] ? 6'd36 : - (_theResult____h343302[19] ? + (_theResult____h343300[19] ? 6'd37 : - (_theResult____h343302[18] ? + (_theResult____h343300[18] ? 6'd38 : - (_theResult____h343302[17] ? + (_theResult____h343300[17] ? 6'd39 : - (_theResult____h343302[16] ? + (_theResult____h343300[16] ? 6'd40 : - (_theResult____h343302[15] ? + (_theResult____h343300[15] ? 6'd41 : - (_theResult____h343302[14] ? + (_theResult____h343300[14] ? 6'd42 : - (_theResult____h343302[13] ? + (_theResult____h343300[13] ? 6'd43 : - (_theResult____h343302[12] ? + (_theResult____h343300[12] ? 6'd44 : - (_theResult____h343302[11] ? + (_theResult____h343300[11] ? 6'd45 : - (_theResult____h343302[10] ? + (_theResult____h343300[10] ? 6'd46 : - (_theResult____h343302[9] ? + (_theResult____h343300[9] ? 6'd47 : - (_theResult____h343302[8] ? + (_theResult____h343300[8] ? 6'd48 : - (_theResult____h343302[7] ? + (_theResult____h343300[7] ? 6'd49 : - (_theResult____h343302[6] ? + (_theResult____h343300[6] ? 6'd50 : - (_theResult____h343302[5] ? + (_theResult____h343300[5] ? 6'd51 : - (_theResult____h343302[4] ? + (_theResult____h343300[4] ? 6'd52 : - (_theResult____h343302[3] ? + (_theResult____h343300[3] ? 6'd53 : - (_theResult____h343302[2] ? + (_theResult____h343300[2] ? 6'd54 : - (_theResult____h343302[1] ? + (_theResult____h343300[1] ? 6'd55 : - (_theResult____h343302[0] ? + (_theResult____h343300[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 = - (_theResult____h388994[56] ? + (_theResult____h388992[56] ? 6'd0 : - (_theResult____h388994[55] ? + (_theResult____h388992[55] ? 6'd1 : - (_theResult____h388994[54] ? + (_theResult____h388992[54] ? 6'd2 : - (_theResult____h388994[53] ? + (_theResult____h388992[53] ? 6'd3 : - (_theResult____h388994[52] ? + (_theResult____h388992[52] ? 6'd4 : - (_theResult____h388994[51] ? + (_theResult____h388992[51] ? 6'd5 : - (_theResult____h388994[50] ? + (_theResult____h388992[50] ? 6'd6 : - (_theResult____h388994[49] ? + (_theResult____h388992[49] ? 6'd7 : - (_theResult____h388994[48] ? + (_theResult____h388992[48] ? 6'd8 : - (_theResult____h388994[47] ? + (_theResult____h388992[47] ? 6'd9 : - (_theResult____h388994[46] ? + (_theResult____h388992[46] ? 6'd10 : - (_theResult____h388994[45] ? + (_theResult____h388992[45] ? 6'd11 : - (_theResult____h388994[44] ? + (_theResult____h388992[44] ? 6'd12 : - (_theResult____h388994[43] ? + (_theResult____h388992[43] ? 6'd13 : - (_theResult____h388994[42] ? + (_theResult____h388992[42] ? 6'd14 : - (_theResult____h388994[41] ? + (_theResult____h388992[41] ? 6'd15 : - (_theResult____h388994[40] ? + (_theResult____h388992[40] ? 6'd16 : - (_theResult____h388994[39] ? + (_theResult____h388992[39] ? 6'd17 : - (_theResult____h388994[38] ? + (_theResult____h388992[38] ? 6'd18 : - (_theResult____h388994[37] ? + (_theResult____h388992[37] ? 6'd19 : - (_theResult____h388994[36] ? + (_theResult____h388992[36] ? 6'd20 : - (_theResult____h388994[35] ? + (_theResult____h388992[35] ? 6'd21 : - (_theResult____h388994[34] ? + (_theResult____h388992[34] ? 6'd22 : - (_theResult____h388994[33] ? + (_theResult____h388992[33] ? 6'd23 : - (_theResult____h388994[32] ? + (_theResult____h388992[32] ? 6'd24 : - (_theResult____h388994[31] ? + (_theResult____h388992[31] ? 6'd25 : - (_theResult____h388994[30] ? + (_theResult____h388992[30] ? 6'd26 : - (_theResult____h388994[29] ? + (_theResult____h388992[29] ? 6'd27 : - (_theResult____h388994[28] ? + (_theResult____h388992[28] ? 6'd28 : - (_theResult____h388994[27] ? + (_theResult____h388992[27] ? 6'd29 : - (_theResult____h388994[26] ? + (_theResult____h388992[26] ? 6'd30 : - (_theResult____h388994[25] ? + (_theResult____h388992[25] ? 6'd31 : - (_theResult____h388994[24] ? + (_theResult____h388992[24] ? 6'd32 : - (_theResult____h388994[23] ? + (_theResult____h388992[23] ? 6'd33 : - (_theResult____h388994[22] ? + (_theResult____h388992[22] ? 6'd34 : - (_theResult____h388994[21] ? + (_theResult____h388992[21] ? 6'd35 : - (_theResult____h388994[20] ? + (_theResult____h388992[20] ? 6'd36 : - (_theResult____h388994[19] ? + (_theResult____h388992[19] ? 6'd37 : - (_theResult____h388994[18] ? + (_theResult____h388992[18] ? 6'd38 : - (_theResult____h388994[17] ? + (_theResult____h388992[17] ? 6'd39 : - (_theResult____h388994[16] ? + (_theResult____h388992[16] ? 6'd40 : - (_theResult____h388994[15] ? + (_theResult____h388992[15] ? 6'd41 : - (_theResult____h388994[14] ? + (_theResult____h388992[14] ? 6'd42 : - (_theResult____h388994[13] ? + (_theResult____h388992[13] ? 6'd43 : - (_theResult____h388994[12] ? + (_theResult____h388992[12] ? 6'd44 : - (_theResult____h388994[11] ? + (_theResult____h388992[11] ? 6'd45 : - (_theResult____h388994[10] ? + (_theResult____h388992[10] ? 6'd46 : - (_theResult____h388994[9] ? + (_theResult____h388992[9] ? 6'd47 : - (_theResult____h388994[8] ? + (_theResult____h388992[8] ? 6'd48 : - (_theResult____h388994[7] ? + (_theResult____h388992[7] ? 6'd49 : - (_theResult____h388994[6] ? + (_theResult____h388992[6] ? 6'd50 : - (_theResult____h388994[5] ? + (_theResult____h388992[5] ? 6'd51 : - (_theResult____h388994[4] ? + (_theResult____h388992[4] ? 6'd52 : - (_theResult____h388994[3] ? + (_theResult____h388992[3] ? 6'd53 : - (_theResult____h388994[2] ? + (_theResult____h388992[2] ? 6'd54 : - (_theResult____h388994[1] ? + (_theResult____h388992[1] ? 6'd55 : - (_theResult____h388994[0] ? + (_theResult____h388992[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 = - (_theResult____h434682[56] ? + (_theResult____h434680[56] ? 6'd0 : - (_theResult____h434682[55] ? + (_theResult____h434680[55] ? 6'd1 : - (_theResult____h434682[54] ? + (_theResult____h434680[54] ? 6'd2 : - (_theResult____h434682[53] ? + (_theResult____h434680[53] ? 6'd3 : - (_theResult____h434682[52] ? + (_theResult____h434680[52] ? 6'd4 : - (_theResult____h434682[51] ? + (_theResult____h434680[51] ? 6'd5 : - (_theResult____h434682[50] ? + (_theResult____h434680[50] ? 6'd6 : - (_theResult____h434682[49] ? + (_theResult____h434680[49] ? 6'd7 : - (_theResult____h434682[48] ? + (_theResult____h434680[48] ? 6'd8 : - (_theResult____h434682[47] ? + (_theResult____h434680[47] ? 6'd9 : - (_theResult____h434682[46] ? + (_theResult____h434680[46] ? 6'd10 : - (_theResult____h434682[45] ? + (_theResult____h434680[45] ? 6'd11 : - (_theResult____h434682[44] ? + (_theResult____h434680[44] ? 6'd12 : - (_theResult____h434682[43] ? + (_theResult____h434680[43] ? 6'd13 : - (_theResult____h434682[42] ? + (_theResult____h434680[42] ? 6'd14 : - (_theResult____h434682[41] ? + (_theResult____h434680[41] ? 6'd15 : - (_theResult____h434682[40] ? + (_theResult____h434680[40] ? 6'd16 : - (_theResult____h434682[39] ? + (_theResult____h434680[39] ? 6'd17 : - (_theResult____h434682[38] ? + (_theResult____h434680[38] ? 6'd18 : - (_theResult____h434682[37] ? + (_theResult____h434680[37] ? 6'd19 : - (_theResult____h434682[36] ? + (_theResult____h434680[36] ? 6'd20 : - (_theResult____h434682[35] ? + (_theResult____h434680[35] ? 6'd21 : - (_theResult____h434682[34] ? + (_theResult____h434680[34] ? 6'd22 : - (_theResult____h434682[33] ? + (_theResult____h434680[33] ? 6'd23 : - (_theResult____h434682[32] ? + (_theResult____h434680[32] ? 6'd24 : - (_theResult____h434682[31] ? + (_theResult____h434680[31] ? 6'd25 : - (_theResult____h434682[30] ? + (_theResult____h434680[30] ? 6'd26 : - (_theResult____h434682[29] ? + (_theResult____h434680[29] ? 6'd27 : - (_theResult____h434682[28] ? + (_theResult____h434680[28] ? 6'd28 : - (_theResult____h434682[27] ? + (_theResult____h434680[27] ? 6'd29 : - (_theResult____h434682[26] ? + (_theResult____h434680[26] ? 6'd30 : - (_theResult____h434682[25] ? + (_theResult____h434680[25] ? 6'd31 : - (_theResult____h434682[24] ? + (_theResult____h434680[24] ? 6'd32 : - (_theResult____h434682[23] ? + (_theResult____h434680[23] ? 6'd33 : - (_theResult____h434682[22] ? + (_theResult____h434680[22] ? 6'd34 : - (_theResult____h434682[21] ? + (_theResult____h434680[21] ? 6'd35 : - (_theResult____h434682[20] ? + (_theResult____h434680[20] ? 6'd36 : - (_theResult____h434682[19] ? + (_theResult____h434680[19] ? 6'd37 : - (_theResult____h434682[18] ? + (_theResult____h434680[18] ? 6'd38 : - (_theResult____h434682[17] ? + (_theResult____h434680[17] ? 6'd39 : - (_theResult____h434682[16] ? + (_theResult____h434680[16] ? 6'd40 : - (_theResult____h434682[15] ? + (_theResult____h434680[15] ? 6'd41 : - (_theResult____h434682[14] ? + (_theResult____h434680[14] ? 6'd42 : - (_theResult____h434682[13] ? + (_theResult____h434680[13] ? 6'd43 : - (_theResult____h434682[12] ? + (_theResult____h434680[12] ? 6'd44 : - (_theResult____h434682[11] ? + (_theResult____h434680[11] ? 6'd45 : - (_theResult____h434682[10] ? + (_theResult____h434680[10] ? 6'd46 : - (_theResult____h434682[9] ? + (_theResult____h434680[9] ? 6'd47 : - (_theResult____h434682[8] ? + (_theResult____h434680[8] ? 6'd48 : - (_theResult____h434682[7] ? + (_theResult____h434680[7] ? 6'd49 : - (_theResult____h434682[6] ? + (_theResult____h434680[6] ? 6'd50 : - (_theResult____h434682[5] ? + (_theResult____h434680[5] ? 6'd51 : - (_theResult____h434682[4] ? + (_theResult____h434680[4] ? 6'd52 : - (_theResult____h434682[3] ? + (_theResult____h434680[3] ? 6'd53 : - (_theResult____h434682[2] ? + (_theResult____h434680[2] ? 6'd54 : - (_theResult____h434682[1] ? + (_theResult____h434680[1] ? 6'd55 : - (_theResult____h434682[0] ? + (_theResult____h434680[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 = - (_theResult____h538818[56] ? + (_theResult____h538816[56] ? 6'd0 : - (_theResult____h538818[55] ? + (_theResult____h538816[55] ? 6'd1 : - (_theResult____h538818[54] ? + (_theResult____h538816[54] ? 6'd2 : - (_theResult____h538818[53] ? + (_theResult____h538816[53] ? 6'd3 : - (_theResult____h538818[52] ? + (_theResult____h538816[52] ? 6'd4 : - (_theResult____h538818[51] ? + (_theResult____h538816[51] ? 6'd5 : - (_theResult____h538818[50] ? + (_theResult____h538816[50] ? 6'd6 : - (_theResult____h538818[49] ? + (_theResult____h538816[49] ? 6'd7 : - (_theResult____h538818[48] ? + (_theResult____h538816[48] ? 6'd8 : - (_theResult____h538818[47] ? + (_theResult____h538816[47] ? 6'd9 : - (_theResult____h538818[46] ? + (_theResult____h538816[46] ? 6'd10 : - (_theResult____h538818[45] ? + (_theResult____h538816[45] ? 6'd11 : - (_theResult____h538818[44] ? + (_theResult____h538816[44] ? 6'd12 : - (_theResult____h538818[43] ? + (_theResult____h538816[43] ? 6'd13 : - (_theResult____h538818[42] ? + (_theResult____h538816[42] ? 6'd14 : - (_theResult____h538818[41] ? + (_theResult____h538816[41] ? 6'd15 : - (_theResult____h538818[40] ? + (_theResult____h538816[40] ? 6'd16 : - (_theResult____h538818[39] ? + (_theResult____h538816[39] ? 6'd17 : - (_theResult____h538818[38] ? + (_theResult____h538816[38] ? 6'd18 : - (_theResult____h538818[37] ? + (_theResult____h538816[37] ? 6'd19 : - (_theResult____h538818[36] ? + (_theResult____h538816[36] ? 6'd20 : - (_theResult____h538818[35] ? + (_theResult____h538816[35] ? 6'd21 : - (_theResult____h538818[34] ? + (_theResult____h538816[34] ? 6'd22 : - (_theResult____h538818[33] ? + (_theResult____h538816[33] ? 6'd23 : - (_theResult____h538818[32] ? + (_theResult____h538816[32] ? 6'd24 : - (_theResult____h538818[31] ? + (_theResult____h538816[31] ? 6'd25 : - (_theResult____h538818[30] ? + (_theResult____h538816[30] ? 6'd26 : - (_theResult____h538818[29] ? + (_theResult____h538816[29] ? 6'd27 : - (_theResult____h538818[28] ? + (_theResult____h538816[28] ? 6'd28 : - (_theResult____h538818[27] ? + (_theResult____h538816[27] ? 6'd29 : - (_theResult____h538818[26] ? + (_theResult____h538816[26] ? 6'd30 : - (_theResult____h538818[25] ? + (_theResult____h538816[25] ? 6'd31 : - (_theResult____h538818[24] ? + (_theResult____h538816[24] ? 6'd32 : - (_theResult____h538818[23] ? + (_theResult____h538816[23] ? 6'd33 : - (_theResult____h538818[22] ? + (_theResult____h538816[22] ? 6'd34 : - (_theResult____h538818[21] ? + (_theResult____h538816[21] ? 6'd35 : - (_theResult____h538818[20] ? + (_theResult____h538816[20] ? 6'd36 : - (_theResult____h538818[19] ? + (_theResult____h538816[19] ? 6'd37 : - (_theResult____h538818[18] ? + (_theResult____h538816[18] ? 6'd38 : - (_theResult____h538818[17] ? + (_theResult____h538816[17] ? 6'd39 : - (_theResult____h538818[16] ? + (_theResult____h538816[16] ? 6'd40 : - (_theResult____h538818[15] ? + (_theResult____h538816[15] ? 6'd41 : - (_theResult____h538818[14] ? + (_theResult____h538816[14] ? 6'd42 : - (_theResult____h538818[13] ? + (_theResult____h538816[13] ? 6'd43 : - (_theResult____h538818[12] ? + (_theResult____h538816[12] ? 6'd44 : - (_theResult____h538818[11] ? + (_theResult____h538816[11] ? 6'd45 : - (_theResult____h538818[10] ? + (_theResult____h538816[10] ? 6'd46 : - (_theResult____h538818[9] ? + (_theResult____h538816[9] ? 6'd47 : - (_theResult____h538818[8] ? + (_theResult____h538816[8] ? 6'd48 : - (_theResult____h538818[7] ? + (_theResult____h538816[7] ? 6'd49 : - (_theResult____h538818[6] ? + (_theResult____h538816[6] ? 6'd50 : - (_theResult____h538818[5] ? + (_theResult____h538816[5] ? 6'd51 : - (_theResult____h538818[4] ? + (_theResult____h538816[4] ? 6'd52 : - (_theResult____h538818[3] ? + (_theResult____h538816[3] ? 6'd53 : - (_theResult____h538818[2] ? + (_theResult____h538816[2] ? 6'd54 : - (_theResult____h538818[1] ? + (_theResult____h538816[1] ? 6'd55 : - (_theResult____h538818[0] ? + (_theResult____h538816[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 = - (_theResult____h500017[56] ? + (_theResult____h500015[56] ? 6'd0 : - (_theResult____h500017[55] ? + (_theResult____h500015[55] ? 6'd1 : - (_theResult____h500017[54] ? + (_theResult____h500015[54] ? 6'd2 : - (_theResult____h500017[53] ? + (_theResult____h500015[53] ? 6'd3 : - (_theResult____h500017[52] ? + (_theResult____h500015[52] ? 6'd4 : - (_theResult____h500017[51] ? + (_theResult____h500015[51] ? 6'd5 : - (_theResult____h500017[50] ? + (_theResult____h500015[50] ? 6'd6 : - (_theResult____h500017[49] ? + (_theResult____h500015[49] ? 6'd7 : - (_theResult____h500017[48] ? + (_theResult____h500015[48] ? 6'd8 : - (_theResult____h500017[47] ? + (_theResult____h500015[47] ? 6'd9 : - (_theResult____h500017[46] ? + (_theResult____h500015[46] ? 6'd10 : - (_theResult____h500017[45] ? + (_theResult____h500015[45] ? 6'd11 : - (_theResult____h500017[44] ? + (_theResult____h500015[44] ? 6'd12 : - (_theResult____h500017[43] ? + (_theResult____h500015[43] ? 6'd13 : - (_theResult____h500017[42] ? + (_theResult____h500015[42] ? 6'd14 : - (_theResult____h500017[41] ? + (_theResult____h500015[41] ? 6'd15 : - (_theResult____h500017[40] ? + (_theResult____h500015[40] ? 6'd16 : - (_theResult____h500017[39] ? + (_theResult____h500015[39] ? 6'd17 : - (_theResult____h500017[38] ? + (_theResult____h500015[38] ? 6'd18 : - (_theResult____h500017[37] ? + (_theResult____h500015[37] ? 6'd19 : - (_theResult____h500017[36] ? + (_theResult____h500015[36] ? 6'd20 : - (_theResult____h500017[35] ? + (_theResult____h500015[35] ? 6'd21 : - (_theResult____h500017[34] ? + (_theResult____h500015[34] ? 6'd22 : - (_theResult____h500017[33] ? + (_theResult____h500015[33] ? 6'd23 : - (_theResult____h500017[32] ? + (_theResult____h500015[32] ? 6'd24 : - (_theResult____h500017[31] ? + (_theResult____h500015[31] ? 6'd25 : - (_theResult____h500017[30] ? + (_theResult____h500015[30] ? 6'd26 : - (_theResult____h500017[29] ? + (_theResult____h500015[29] ? 6'd27 : - (_theResult____h500017[28] ? + (_theResult____h500015[28] ? 6'd28 : - (_theResult____h500017[27] ? + (_theResult____h500015[27] ? 6'd29 : - (_theResult____h500017[26] ? + (_theResult____h500015[26] ? 6'd30 : - (_theResult____h500017[25] ? + (_theResult____h500015[25] ? 6'd31 : - (_theResult____h500017[24] ? + (_theResult____h500015[24] ? 6'd32 : - (_theResult____h500017[23] ? + (_theResult____h500015[23] ? 6'd33 : - (_theResult____h500017[22] ? + (_theResult____h500015[22] ? 6'd34 : - (_theResult____h500017[21] ? + (_theResult____h500015[21] ? 6'd35 : - (_theResult____h500017[20] ? + (_theResult____h500015[20] ? 6'd36 : - (_theResult____h500017[19] ? + (_theResult____h500015[19] ? 6'd37 : - (_theResult____h500017[18] ? + (_theResult____h500015[18] ? 6'd38 : - (_theResult____h500017[17] ? + (_theResult____h500015[17] ? 6'd39 : - (_theResult____h500017[16] ? + (_theResult____h500015[16] ? 6'd40 : - (_theResult____h500017[15] ? + (_theResult____h500015[15] ? 6'd41 : - (_theResult____h500017[14] ? + (_theResult____h500015[14] ? 6'd42 : - (_theResult____h500017[13] ? + (_theResult____h500015[13] ? 6'd43 : - (_theResult____h500017[12] ? + (_theResult____h500015[12] ? 6'd44 : - (_theResult____h500017[11] ? + (_theResult____h500015[11] ? 6'd45 : - (_theResult____h500017[10] ? + (_theResult____h500015[10] ? 6'd46 : - (_theResult____h500017[9] ? + (_theResult____h500015[9] ? 6'd47 : - (_theResult____h500017[8] ? + (_theResult____h500015[8] ? 6'd48 : - (_theResult____h500017[7] ? + (_theResult____h500015[7] ? 6'd49 : - (_theResult____h500017[6] ? + (_theResult____h500015[6] ? 6'd50 : - (_theResult____h500017[5] ? + (_theResult____h500015[5] ? 6'd51 : - (_theResult____h500017[4] ? + (_theResult____h500015[4] ? 6'd52 : - (_theResult____h500017[3] ? + (_theResult____h500015[3] ? 6'd53 : - (_theResult____h500017[2] ? + (_theResult____h500015[2] ? 6'd54 : - (_theResult____h500017[1] ? + (_theResult____h500015[1] ? 6'd55 : - (_theResult____h500017[0] ? + (_theResult____h500015[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 = - (_theResult____h578019[56] ? + (_theResult____h578017[56] ? 6'd0 : - (_theResult____h578019[55] ? + (_theResult____h578017[55] ? 6'd1 : - (_theResult____h578019[54] ? + (_theResult____h578017[54] ? 6'd2 : - (_theResult____h578019[53] ? + (_theResult____h578017[53] ? 6'd3 : - (_theResult____h578019[52] ? + (_theResult____h578017[52] ? 6'd4 : - (_theResult____h578019[51] ? + (_theResult____h578017[51] ? 6'd5 : - (_theResult____h578019[50] ? + (_theResult____h578017[50] ? 6'd6 : - (_theResult____h578019[49] ? + (_theResult____h578017[49] ? 6'd7 : - (_theResult____h578019[48] ? + (_theResult____h578017[48] ? 6'd8 : - (_theResult____h578019[47] ? + (_theResult____h578017[47] ? 6'd9 : - (_theResult____h578019[46] ? + (_theResult____h578017[46] ? 6'd10 : - (_theResult____h578019[45] ? + (_theResult____h578017[45] ? 6'd11 : - (_theResult____h578019[44] ? + (_theResult____h578017[44] ? 6'd12 : - (_theResult____h578019[43] ? + (_theResult____h578017[43] ? 6'd13 : - (_theResult____h578019[42] ? + (_theResult____h578017[42] ? 6'd14 : - (_theResult____h578019[41] ? + (_theResult____h578017[41] ? 6'd15 : - (_theResult____h578019[40] ? + (_theResult____h578017[40] ? 6'd16 : - (_theResult____h578019[39] ? + (_theResult____h578017[39] ? 6'd17 : - (_theResult____h578019[38] ? + (_theResult____h578017[38] ? 6'd18 : - (_theResult____h578019[37] ? + (_theResult____h578017[37] ? 6'd19 : - (_theResult____h578019[36] ? + (_theResult____h578017[36] ? 6'd20 : - (_theResult____h578019[35] ? + (_theResult____h578017[35] ? 6'd21 : - (_theResult____h578019[34] ? + (_theResult____h578017[34] ? 6'd22 : - (_theResult____h578019[33] ? + (_theResult____h578017[33] ? 6'd23 : - (_theResult____h578019[32] ? + (_theResult____h578017[32] ? 6'd24 : - (_theResult____h578019[31] ? + (_theResult____h578017[31] ? 6'd25 : - (_theResult____h578019[30] ? + (_theResult____h578017[30] ? 6'd26 : - (_theResult____h578019[29] ? + (_theResult____h578017[29] ? 6'd27 : - (_theResult____h578019[28] ? + (_theResult____h578017[28] ? 6'd28 : - (_theResult____h578019[27] ? + (_theResult____h578017[27] ? 6'd29 : - (_theResult____h578019[26] ? + (_theResult____h578017[26] ? 6'd30 : - (_theResult____h578019[25] ? + (_theResult____h578017[25] ? 6'd31 : - (_theResult____h578019[24] ? + (_theResult____h578017[24] ? 6'd32 : - (_theResult____h578019[23] ? + (_theResult____h578017[23] ? 6'd33 : - (_theResult____h578019[22] ? + (_theResult____h578017[22] ? 6'd34 : - (_theResult____h578019[21] ? + (_theResult____h578017[21] ? 6'd35 : - (_theResult____h578019[20] ? + (_theResult____h578017[20] ? 6'd36 : - (_theResult____h578019[19] ? + (_theResult____h578017[19] ? 6'd37 : - (_theResult____h578019[18] ? + (_theResult____h578017[18] ? 6'd38 : - (_theResult____h578019[17] ? + (_theResult____h578017[17] ? 6'd39 : - (_theResult____h578019[16] ? + (_theResult____h578017[16] ? 6'd40 : - (_theResult____h578019[15] ? + (_theResult____h578017[15] ? 6'd41 : - (_theResult____h578019[14] ? + (_theResult____h578017[14] ? 6'd42 : - (_theResult____h578019[13] ? + (_theResult____h578017[13] ? 6'd43 : - (_theResult____h578019[12] ? + (_theResult____h578017[12] ? 6'd44 : - (_theResult____h578019[11] ? + (_theResult____h578017[11] ? 6'd45 : - (_theResult____h578019[10] ? + (_theResult____h578017[10] ? 6'd46 : - (_theResult____h578019[9] ? + (_theResult____h578017[9] ? 6'd47 : - (_theResult____h578019[8] ? + (_theResult____h578017[8] ? 6'd48 : - (_theResult____h578019[7] ? + (_theResult____h578017[7] ? 6'd49 : - (_theResult____h578019[6] ? + (_theResult____h578017[6] ? 6'd50 : - (_theResult____h578019[5] ? + (_theResult____h578017[5] ? 6'd51 : - (_theResult____h578019[4] ? + (_theResult____h578017[4] ? 6'd52 : - (_theResult____h578019[3] ? + (_theResult____h578017[3] ? 6'd53 : - (_theResult____h578019[2] ? + (_theResult____h578017[2] ? 6'd54 : - (_theResult____h578019[1] ? + (_theResult____h578017[1] ? 6'd55 : - (_theResult____h578019[0] ? + (_theResult____h578017[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 = - (_theResult____h360941[56] ? + (_theResult____h360939[56] ? 6'd0 : - (_theResult____h360941[55] ? + (_theResult____h360939[55] ? 6'd1 : - (_theResult____h360941[54] ? + (_theResult____h360939[54] ? 6'd2 : - (_theResult____h360941[53] ? + (_theResult____h360939[53] ? 6'd3 : - (_theResult____h360941[52] ? + (_theResult____h360939[52] ? 6'd4 : - (_theResult____h360941[51] ? + (_theResult____h360939[51] ? 6'd5 : - (_theResult____h360941[50] ? + (_theResult____h360939[50] ? 6'd6 : - (_theResult____h360941[49] ? + (_theResult____h360939[49] ? 6'd7 : - (_theResult____h360941[48] ? + (_theResult____h360939[48] ? 6'd8 : - (_theResult____h360941[47] ? + (_theResult____h360939[47] ? 6'd9 : - (_theResult____h360941[46] ? + (_theResult____h360939[46] ? 6'd10 : - (_theResult____h360941[45] ? + (_theResult____h360939[45] ? 6'd11 : - (_theResult____h360941[44] ? + (_theResult____h360939[44] ? 6'd12 : - (_theResult____h360941[43] ? + (_theResult____h360939[43] ? 6'd13 : - (_theResult____h360941[42] ? + (_theResult____h360939[42] ? 6'd14 : - (_theResult____h360941[41] ? + (_theResult____h360939[41] ? 6'd15 : - (_theResult____h360941[40] ? + (_theResult____h360939[40] ? 6'd16 : - (_theResult____h360941[39] ? + (_theResult____h360939[39] ? 6'd17 : - (_theResult____h360941[38] ? + (_theResult____h360939[38] ? 6'd18 : - (_theResult____h360941[37] ? + (_theResult____h360939[37] ? 6'd19 : - (_theResult____h360941[36] ? + (_theResult____h360939[36] ? 6'd20 : - (_theResult____h360941[35] ? + (_theResult____h360939[35] ? 6'd21 : - (_theResult____h360941[34] ? + (_theResult____h360939[34] ? 6'd22 : - (_theResult____h360941[33] ? + (_theResult____h360939[33] ? 6'd23 : - (_theResult____h360941[32] ? + (_theResult____h360939[32] ? 6'd24 : - (_theResult____h360941[31] ? + (_theResult____h360939[31] ? 6'd25 : - (_theResult____h360941[30] ? + (_theResult____h360939[30] ? 6'd26 : - (_theResult____h360941[29] ? + (_theResult____h360939[29] ? 6'd27 : - (_theResult____h360941[28] ? + (_theResult____h360939[28] ? 6'd28 : - (_theResult____h360941[27] ? + (_theResult____h360939[27] ? 6'd29 : - (_theResult____h360941[26] ? + (_theResult____h360939[26] ? 6'd30 : - (_theResult____h360941[25] ? + (_theResult____h360939[25] ? 6'd31 : - (_theResult____h360941[24] ? + (_theResult____h360939[24] ? 6'd32 : - (_theResult____h360941[23] ? + (_theResult____h360939[23] ? 6'd33 : - (_theResult____h360941[22] ? + (_theResult____h360939[22] ? 6'd34 : - (_theResult____h360941[21] ? + (_theResult____h360939[21] ? 6'd35 : - (_theResult____h360941[20] ? + (_theResult____h360939[20] ? 6'd36 : - (_theResult____h360941[19] ? + (_theResult____h360939[19] ? 6'd37 : - (_theResult____h360941[18] ? + (_theResult____h360939[18] ? 6'd38 : - (_theResult____h360941[17] ? + (_theResult____h360939[17] ? 6'd39 : - (_theResult____h360941[16] ? + (_theResult____h360939[16] ? 6'd40 : - (_theResult____h360941[15] ? + (_theResult____h360939[15] ? 6'd41 : - (_theResult____h360941[14] ? + (_theResult____h360939[14] ? 6'd42 : - (_theResult____h360941[13] ? + (_theResult____h360939[13] ? 6'd43 : - (_theResult____h360941[12] ? + (_theResult____h360939[12] ? 6'd44 : - (_theResult____h360941[11] ? + (_theResult____h360939[11] ? 6'd45 : - (_theResult____h360941[10] ? + (_theResult____h360939[10] ? 6'd46 : - (_theResult____h360941[9] ? + (_theResult____h360939[9] ? 6'd47 : - (_theResult____h360941[8] ? + (_theResult____h360939[8] ? 6'd48 : - (_theResult____h360941[7] ? + (_theResult____h360939[7] ? 6'd49 : - (_theResult____h360941[6] ? + (_theResult____h360939[6] ? 6'd50 : - (_theResult____h360941[5] ? + (_theResult____h360939[5] ? 6'd51 : - (_theResult____h360941[4] ? + (_theResult____h360939[4] ? 6'd52 : - (_theResult____h360941[3] ? + (_theResult____h360939[3] ? 6'd53 : - (_theResult____h360941[2] ? + (_theResult____h360939[2] ? 6'd54 : - (_theResult____h360941[1] ? + (_theResult____h360939[1] ? 6'd55 : - (_theResult____h360941[0] ? + (_theResult____h360939[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 = - (_theResult____h406631[56] ? + (_theResult____h406629[56] ? 6'd0 : - (_theResult____h406631[55] ? + (_theResult____h406629[55] ? 6'd1 : - (_theResult____h406631[54] ? + (_theResult____h406629[54] ? 6'd2 : - (_theResult____h406631[53] ? + (_theResult____h406629[53] ? 6'd3 : - (_theResult____h406631[52] ? + (_theResult____h406629[52] ? 6'd4 : - (_theResult____h406631[51] ? + (_theResult____h406629[51] ? 6'd5 : - (_theResult____h406631[50] ? + (_theResult____h406629[50] ? 6'd6 : - (_theResult____h406631[49] ? + (_theResult____h406629[49] ? 6'd7 : - (_theResult____h406631[48] ? + (_theResult____h406629[48] ? 6'd8 : - (_theResult____h406631[47] ? + (_theResult____h406629[47] ? 6'd9 : - (_theResult____h406631[46] ? + (_theResult____h406629[46] ? 6'd10 : - (_theResult____h406631[45] ? + (_theResult____h406629[45] ? 6'd11 : - (_theResult____h406631[44] ? + (_theResult____h406629[44] ? 6'd12 : - (_theResult____h406631[43] ? + (_theResult____h406629[43] ? 6'd13 : - (_theResult____h406631[42] ? + (_theResult____h406629[42] ? 6'd14 : - (_theResult____h406631[41] ? + (_theResult____h406629[41] ? 6'd15 : - (_theResult____h406631[40] ? + (_theResult____h406629[40] ? 6'd16 : - (_theResult____h406631[39] ? + (_theResult____h406629[39] ? 6'd17 : - (_theResult____h406631[38] ? + (_theResult____h406629[38] ? 6'd18 : - (_theResult____h406631[37] ? + (_theResult____h406629[37] ? 6'd19 : - (_theResult____h406631[36] ? + (_theResult____h406629[36] ? 6'd20 : - (_theResult____h406631[35] ? + (_theResult____h406629[35] ? 6'd21 : - (_theResult____h406631[34] ? + (_theResult____h406629[34] ? 6'd22 : - (_theResult____h406631[33] ? + (_theResult____h406629[33] ? 6'd23 : - (_theResult____h406631[32] ? + (_theResult____h406629[32] ? 6'd24 : - (_theResult____h406631[31] ? + (_theResult____h406629[31] ? 6'd25 : - (_theResult____h406631[30] ? + (_theResult____h406629[30] ? 6'd26 : - (_theResult____h406631[29] ? + (_theResult____h406629[29] ? 6'd27 : - (_theResult____h406631[28] ? + (_theResult____h406629[28] ? 6'd28 : - (_theResult____h406631[27] ? + (_theResult____h406629[27] ? 6'd29 : - (_theResult____h406631[26] ? + (_theResult____h406629[26] ? 6'd30 : - (_theResult____h406631[25] ? + (_theResult____h406629[25] ? 6'd31 : - (_theResult____h406631[24] ? + (_theResult____h406629[24] ? 6'd32 : - (_theResult____h406631[23] ? + (_theResult____h406629[23] ? 6'd33 : - (_theResult____h406631[22] ? + (_theResult____h406629[22] ? 6'd34 : - (_theResult____h406631[21] ? + (_theResult____h406629[21] ? 6'd35 : - (_theResult____h406631[20] ? + (_theResult____h406629[20] ? 6'd36 : - (_theResult____h406631[19] ? + (_theResult____h406629[19] ? 6'd37 : - (_theResult____h406631[18] ? + (_theResult____h406629[18] ? 6'd38 : - (_theResult____h406631[17] ? + (_theResult____h406629[17] ? 6'd39 : - (_theResult____h406631[16] ? + (_theResult____h406629[16] ? 6'd40 : - (_theResult____h406631[15] ? + (_theResult____h406629[15] ? 6'd41 : - (_theResult____h406631[14] ? + (_theResult____h406629[14] ? 6'd42 : - (_theResult____h406631[13] ? + (_theResult____h406629[13] ? 6'd43 : - (_theResult____h406631[12] ? + (_theResult____h406629[12] ? 6'd44 : - (_theResult____h406631[11] ? + (_theResult____h406629[11] ? 6'd45 : - (_theResult____h406631[10] ? + (_theResult____h406629[10] ? 6'd46 : - (_theResult____h406631[9] ? + (_theResult____h406629[9] ? 6'd47 : - (_theResult____h406631[8] ? + (_theResult____h406629[8] ? 6'd48 : - (_theResult____h406631[7] ? + (_theResult____h406629[7] ? 6'd49 : - (_theResult____h406631[6] ? + (_theResult____h406629[6] ? 6'd50 : - (_theResult____h406631[5] ? + (_theResult____h406629[5] ? 6'd51 : - (_theResult____h406631[4] ? + (_theResult____h406629[4] ? 6'd52 : - (_theResult____h406631[3] ? + (_theResult____h406629[3] ? 6'd53 : - (_theResult____h406631[2] ? + (_theResult____h406629[2] ? 6'd54 : - (_theResult____h406631[1] ? + (_theResult____h406629[1] ? 6'd55 : - (_theResult____h406631[0] ? + (_theResult____h406629[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 = - (_theResult____h452319[56] ? + (_theResult____h452317[56] ? 6'd0 : - (_theResult____h452319[55] ? + (_theResult____h452317[55] ? 6'd1 : - (_theResult____h452319[54] ? + (_theResult____h452317[54] ? 6'd2 : - (_theResult____h452319[53] ? + (_theResult____h452317[53] ? 6'd3 : - (_theResult____h452319[52] ? + (_theResult____h452317[52] ? 6'd4 : - (_theResult____h452319[51] ? + (_theResult____h452317[51] ? 6'd5 : - (_theResult____h452319[50] ? + (_theResult____h452317[50] ? 6'd6 : - (_theResult____h452319[49] ? + (_theResult____h452317[49] ? 6'd7 : - (_theResult____h452319[48] ? + (_theResult____h452317[48] ? 6'd8 : - (_theResult____h452319[47] ? + (_theResult____h452317[47] ? 6'd9 : - (_theResult____h452319[46] ? + (_theResult____h452317[46] ? 6'd10 : - (_theResult____h452319[45] ? + (_theResult____h452317[45] ? 6'd11 : - (_theResult____h452319[44] ? + (_theResult____h452317[44] ? 6'd12 : - (_theResult____h452319[43] ? + (_theResult____h452317[43] ? 6'd13 : - (_theResult____h452319[42] ? + (_theResult____h452317[42] ? 6'd14 : - (_theResult____h452319[41] ? + (_theResult____h452317[41] ? 6'd15 : - (_theResult____h452319[40] ? + (_theResult____h452317[40] ? 6'd16 : - (_theResult____h452319[39] ? + (_theResult____h452317[39] ? 6'd17 : - (_theResult____h452319[38] ? + (_theResult____h452317[38] ? 6'd18 : - (_theResult____h452319[37] ? + (_theResult____h452317[37] ? 6'd19 : - (_theResult____h452319[36] ? + (_theResult____h452317[36] ? 6'd20 : - (_theResult____h452319[35] ? + (_theResult____h452317[35] ? 6'd21 : - (_theResult____h452319[34] ? + (_theResult____h452317[34] ? 6'd22 : - (_theResult____h452319[33] ? + (_theResult____h452317[33] ? 6'd23 : - (_theResult____h452319[32] ? + (_theResult____h452317[32] ? 6'd24 : - (_theResult____h452319[31] ? + (_theResult____h452317[31] ? 6'd25 : - (_theResult____h452319[30] ? + (_theResult____h452317[30] ? 6'd26 : - (_theResult____h452319[29] ? + (_theResult____h452317[29] ? 6'd27 : - (_theResult____h452319[28] ? + (_theResult____h452317[28] ? 6'd28 : - (_theResult____h452319[27] ? + (_theResult____h452317[27] ? 6'd29 : - (_theResult____h452319[26] ? + (_theResult____h452317[26] ? 6'd30 : - (_theResult____h452319[25] ? + (_theResult____h452317[25] ? 6'd31 : - (_theResult____h452319[24] ? + (_theResult____h452317[24] ? 6'd32 : - (_theResult____h452319[23] ? + (_theResult____h452317[23] ? 6'd33 : - (_theResult____h452319[22] ? + (_theResult____h452317[22] ? 6'd34 : - (_theResult____h452319[21] ? + (_theResult____h452317[21] ? 6'd35 : - (_theResult____h452319[20] ? + (_theResult____h452317[20] ? 6'd36 : - (_theResult____h452319[19] ? + (_theResult____h452317[19] ? 6'd37 : - (_theResult____h452319[18] ? + (_theResult____h452317[18] ? 6'd38 : - (_theResult____h452319[17] ? + (_theResult____h452317[17] ? 6'd39 : - (_theResult____h452319[16] ? + (_theResult____h452317[16] ? 6'd40 : - (_theResult____h452319[15] ? + (_theResult____h452317[15] ? 6'd41 : - (_theResult____h452319[14] ? + (_theResult____h452317[14] ? 6'd42 : - (_theResult____h452319[13] ? + (_theResult____h452317[13] ? 6'd43 : - (_theResult____h452319[12] ? + (_theResult____h452317[12] ? 6'd44 : - (_theResult____h452319[11] ? + (_theResult____h452317[11] ? 6'd45 : - (_theResult____h452319[10] ? + (_theResult____h452317[10] ? 6'd46 : - (_theResult____h452319[9] ? + (_theResult____h452317[9] ? 6'd47 : - (_theResult____h452319[8] ? + (_theResult____h452317[8] ? 6'd48 : - (_theResult____h452319[7] ? + (_theResult____h452317[7] ? 6'd49 : - (_theResult____h452319[6] ? + (_theResult____h452317[6] ? 6'd50 : - (_theResult____h452319[5] ? + (_theResult____h452317[5] ? 6'd51 : - (_theResult____h452319[4] ? + (_theResult____h452317[4] ? 6'd52 : - (_theResult____h452319[3] ? + (_theResult____h452317[3] ? 6'd53 : - (_theResult____h452319[2] ? + (_theResult____h452317[2] ? 6'd54 : - (_theResult____h452319[1] ? + (_theResult____h452317[1] ? 6'd55 : - (_theResult____h452319[0] ? + (_theResult____h452317[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10404 = - (_theResult___fst_exp__h547054 == 11'd2047) ? + (_theResult___fst_exp__h547052 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10669 = - (_theResult___fst_exp__h547054 == 11'd2047) ? + (_theResult___fst_exp__h547052 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8931 = - (_theResult___fst_exp__h508253 == 11'd2047) ? + (_theResult___fst_exp__h508251 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9641 = - (_theResult___fst_exp__h586255 == 11'd2047) ? + (_theResult___fst_exp__h586253 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9907 = - (_theResult___fst_exp__h586255 == 11'd2047) ? + (_theResult___fst_exp__h586253 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 = - (guard__h343312 == 2'b0 || + (guard__h343310 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h351413 : - _theResult___exp__h351929 ; + _theResult___fst_exp__h351411 : + _theResult___exp__h351927 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 = - (guard__h343312 == 2'b0) ? - _theResult___fst_exp__h351413 : + (guard__h343310 == 2'b0) ? + _theResult___fst_exp__h351411 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h351929 : - _theResult___fst_exp__h351413) ; + _theResult___exp__h351927 : + _theResult___fst_exp__h351411) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 = - (guard__h343312 == 2'b0 || + (guard__h343310 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h351407[56:34] : - _theResult___sfd__h351930 ; + sfdin__h351405[56:34] : + _theResult___sfd__h351928 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 = - (guard__h343312 == 2'b0) ? - sfdin__h351407[56:34] : + (guard__h343310 == 2'b0) ? + sfdin__h351405[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h351930 : - sfdin__h351407[56:34]) ; + _theResult___sfd__h351928 : + sfdin__h351405[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 = - (guard__h389004 == 2'b0 || + (guard__h389002 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h397103 : - _theResult___exp__h397619 ; + _theResult___fst_exp__h397101 : + _theResult___exp__h397617 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 = - (guard__h389004 == 2'b0) ? - _theResult___fst_exp__h397103 : + (guard__h389002 == 2'b0) ? + _theResult___fst_exp__h397101 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h397619 : - _theResult___fst_exp__h397103) ; + _theResult___exp__h397617 : + _theResult___fst_exp__h397101) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 = - (guard__h389004 == 2'b0 || + (guard__h389002 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h397097[56:34] : - _theResult___sfd__h397620 ; + sfdin__h397095[56:34] : + _theResult___sfd__h397618 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 = - (guard__h389004 == 2'b0) ? - sfdin__h397097[56:34] : + (guard__h389002 == 2'b0) ? + sfdin__h397095[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h397620 : - sfdin__h397097[56:34]) ; + _theResult___sfd__h397618 : + sfdin__h397095[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 = - (guard__h434692 == 2'b0 || + (guard__h434690 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h442791 : - _theResult___exp__h443307 ; + _theResult___fst_exp__h442789 : + _theResult___exp__h443305 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 = - (guard__h434692 == 2'b0) ? - _theResult___fst_exp__h442791 : + (guard__h434690 == 2'b0) ? + _theResult___fst_exp__h442789 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h443307 : - _theResult___fst_exp__h442791) ; + _theResult___exp__h443305 : + _theResult___fst_exp__h442789) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 = - (guard__h434692 == 2'b0 || + (guard__h434690 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h442785[56:34] : - _theResult___sfd__h443308 ; + sfdin__h442783[56:34] : + _theResult___sfd__h443306 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 = - (guard__h434692 == 2'b0) ? - sfdin__h442785[56:34] : + (guard__h434690 == 2'b0) ? + sfdin__h442783[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h443308 : - sfdin__h442785[56:34]) ; + _theResult___sfd__h443306 : + sfdin__h442783[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 = - (guard__h538828 == 2'b0 || + (guard__h538826 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h547054 : - _theResult___exp__h547783 ; + _theResult___fst_exp__h547052 : + _theResult___exp__h547781 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 = - (guard__h538828 == 2'b0) ? - _theResult___fst_exp__h547054 : + (guard__h538826 == 2'b0) ? + _theResult___fst_exp__h547052 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h547783 : - _theResult___fst_exp__h547054) ; + _theResult___exp__h547781 : + _theResult___fst_exp__h547052) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 = - (guard__h538828 == 2'b0 || + (guard__h538826 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h547048[56:5] : - _theResult___sfd__h547784 ; + sfdin__h547046[56:5] : + _theResult___sfd__h547782 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 = - (guard__h538828 == 2'b0) ? - sfdin__h547048[56:5] : + (guard__h538826 == 2'b0) ? + sfdin__h547046[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h547784 : - sfdin__h547048[56:5]) ; + _theResult___sfd__h547782 : + sfdin__h547046[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 = - (guard__h500027 == 2'b0 || + (guard__h500025 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h508253 : - _theResult___exp__h508982 ; + _theResult___fst_exp__h508251 : + _theResult___exp__h508980 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 = - (guard__h500027 == 2'b0) ? - _theResult___fst_exp__h508253 : + (guard__h500025 == 2'b0) ? + _theResult___fst_exp__h508251 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h508982 : - _theResult___fst_exp__h508253) ; + _theResult___exp__h508980 : + _theResult___fst_exp__h508251) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 = - (guard__h500027 == 2'b0 || + (guard__h500025 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h508247[56:5] : - _theResult___sfd__h508983 ; + sfdin__h508245[56:5] : + _theResult___sfd__h508981 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 = - (guard__h500027 == 2'b0) ? - sfdin__h508247[56:5] : + (guard__h500025 == 2'b0) ? + sfdin__h508245[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h508983 : - sfdin__h508247[56:5]) ; + _theResult___sfd__h508981 : + sfdin__h508245[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 = - (guard__h578029 == 2'b0 || + (guard__h578027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h586255 : - _theResult___exp__h586984 ; + _theResult___fst_exp__h586253 : + _theResult___exp__h586982 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 = - (guard__h578029 == 2'b0) ? - _theResult___fst_exp__h586255 : + (guard__h578027 == 2'b0) ? + _theResult___fst_exp__h586253 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h586984 : - _theResult___fst_exp__h586255) ; + _theResult___exp__h586982 : + _theResult___fst_exp__h586253) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 = - (guard__h578029 == 2'b0 || + (guard__h578027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h586249[56:5] : - _theResult___sfd__h586985 ; + sfdin__h586247[56:5] : + _theResult___sfd__h586983 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 = - (guard__h578029 == 2'b0) ? - sfdin__h586249[56:5] : + (guard__h578027 == 2'b0) ? + sfdin__h586247[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h586985 : - sfdin__h586249[56:5]) ; + _theResult___sfd__h586983 : + sfdin__h586247[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 = - (guard__h360951 == 2'b0 || + (guard__h360949 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h369179 : - _theResult___exp__h369695 ; + _theResult___fst_exp__h369177 : + _theResult___exp__h369693 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 = - (guard__h360951 == 2'b0) ? - _theResult___fst_exp__h369179 : + (guard__h360949 == 2'b0) ? + _theResult___fst_exp__h369177 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h369695 : - _theResult___fst_exp__h369179) ; + _theResult___exp__h369693 : + _theResult___fst_exp__h369177) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 = - (guard__h360951 == 2'b0 || + (guard__h360949 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h369173[56:34] : - _theResult___sfd__h369696 ; + sfdin__h369171[56:34] : + _theResult___sfd__h369694 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 = - (guard__h360951 == 2'b0) ? - sfdin__h369173[56:34] : + (guard__h360949 == 2'b0) ? + sfdin__h369171[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h369696 : - sfdin__h369173[56:34]) ; + _theResult___sfd__h369694 : + sfdin__h369171[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 = - (guard__h406641 == 2'b0 || + (guard__h406639 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h414869 : - _theResult___exp__h415385 ; + _theResult___fst_exp__h414867 : + _theResult___exp__h415383 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 = - (guard__h406641 == 2'b0) ? - _theResult___fst_exp__h414869 : + (guard__h406639 == 2'b0) ? + _theResult___fst_exp__h414867 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h415385 : - _theResult___fst_exp__h414869) ; + _theResult___exp__h415383 : + _theResult___fst_exp__h414867) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 = - (guard__h406641 == 2'b0 || + (guard__h406639 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h414863[56:34] : - _theResult___sfd__h415386 ; + sfdin__h414861[56:34] : + _theResult___sfd__h415384 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 = - (guard__h406641 == 2'b0) ? - sfdin__h414863[56:34] : + (guard__h406639 == 2'b0) ? + sfdin__h414861[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h415386 : - sfdin__h414863[56:34]) ; + _theResult___sfd__h415384 : + sfdin__h414861[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 = - (guard__h452329 == 2'b0 || + (guard__h452327 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h460557 : - _theResult___exp__h461073 ; + _theResult___fst_exp__h460555 : + _theResult___exp__h461071 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 = - (guard__h452329 == 2'b0) ? - _theResult___fst_exp__h460557 : + (guard__h452327 == 2'b0) ? + _theResult___fst_exp__h460555 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h461073 : - _theResult___fst_exp__h460557) ; + _theResult___exp__h461071 : + _theResult___fst_exp__h460555) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 = - (guard__h452329 == 2'b0 || + (guard__h452327 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h460551[56:34] : - _theResult___sfd__h461074 ; + sfdin__h460549[56:34] : + _theResult___sfd__h461072 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 = - (guard__h452329 == 2'b0) ? - sfdin__h460551[56:34] : + (guard__h452327 == 2'b0) ? + sfdin__h460549[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h461074 : - sfdin__h460551[56:34]) ; + _theResult___sfd__h461072 : + sfdin__h460549[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 = - (guard__h352021 == 2'b0 || + (guard__h352019 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h360069 : - _theResult___exp__h360511 ; + _theResult___fst_exp__h360067 : + _theResult___exp__h360509 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 = - (guard__h352021 == 2'b0) ? - _theResult___fst_exp__h360069 : + (guard__h352019 == 2'b0) ? + _theResult___fst_exp__h360067 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h360511 : - _theResult___fst_exp__h360069) ; + _theResult___exp__h360509 : + _theResult___fst_exp__h360067) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 = - (guard__h369787 == 2'b0 || + (guard__h369785 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h377864 : - _theResult___exp__h378331 ; + _theResult___fst_exp__h377862 : + _theResult___exp__h378329 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 = - (guard__h369787 == 2'b0) ? - _theResult___fst_exp__h377864 : + (guard__h369785 == 2'b0) ? + _theResult___fst_exp__h377862 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h378331 : - _theResult___fst_exp__h377864) ; + _theResult___exp__h378329 : + _theResult___fst_exp__h377862) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 = - (guard__h352021 == 2'b0 || + (guard__h352019 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h360020[56:34] : - _theResult___sfd__h360512 ; + _theResult___snd__h360018[56:34] : + _theResult___sfd__h360510 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 = - (guard__h352021 == 2'b0) ? - _theResult___snd__h360020[56:34] : + (guard__h352019 == 2'b0) ? + _theResult___snd__h360018[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h360512 : - _theResult___snd__h360020[56:34]) ; + _theResult___sfd__h360510 : + _theResult___snd__h360018[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 = - (guard__h369787 == 2'b0 || + (guard__h369785 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h377810[56:34] : - _theResult___sfd__h378332 ; + _theResult___snd__h377808[56:34] : + _theResult___sfd__h378330 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 = - (guard__h369787 == 2'b0) ? - _theResult___snd__h377810[56:34] : + (guard__h369785 == 2'b0) ? + _theResult___snd__h377808[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h378332 : - _theResult___snd__h377810[56:34]) ; + _theResult___sfd__h378330 : + _theResult___snd__h377808[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 = - (guard__h397711 == 2'b0 || + (guard__h397709 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h405759 : - _theResult___exp__h406201 ; + _theResult___fst_exp__h405757 : + _theResult___exp__h406199 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 = - (guard__h397711 == 2'b0) ? - _theResult___fst_exp__h405759 : + (guard__h397709 == 2'b0) ? + _theResult___fst_exp__h405757 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h406201 : - _theResult___fst_exp__h405759) ; + _theResult___exp__h406199 : + _theResult___fst_exp__h405757) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 = - (guard__h415477 == 2'b0 || + (guard__h415475 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h423554 : - _theResult___exp__h424021 ; + _theResult___fst_exp__h423552 : + _theResult___exp__h424019 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 = - (guard__h415477 == 2'b0) ? - _theResult___fst_exp__h423554 : + (guard__h415475 == 2'b0) ? + _theResult___fst_exp__h423552 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h424021 : - _theResult___fst_exp__h423554) ; + _theResult___exp__h424019 : + _theResult___fst_exp__h423552) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 = - (guard__h397711 == 2'b0 || + (guard__h397709 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h405710[56:34] : - _theResult___sfd__h406202 ; + _theResult___snd__h405708[56:34] : + _theResult___sfd__h406200 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 = - (guard__h397711 == 2'b0) ? - _theResult___snd__h405710[56:34] : + (guard__h397709 == 2'b0) ? + _theResult___snd__h405708[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h406202 : - _theResult___snd__h405710[56:34]) ; + _theResult___sfd__h406200 : + _theResult___snd__h405708[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 = - (guard__h415477 == 2'b0 || + (guard__h415475 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h423500[56:34] : - _theResult___sfd__h424022 ; + _theResult___snd__h423498[56:34] : + _theResult___sfd__h424020 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 = - (guard__h415477 == 2'b0) ? - _theResult___snd__h423500[56:34] : + (guard__h415475 == 2'b0) ? + _theResult___snd__h423498[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h424022 : - _theResult___snd__h423500[56:34]) ; + _theResult___sfd__h424020 : + _theResult___snd__h423498[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 = - (guard__h443399 == 2'b0 || + (guard__h443397 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h451447 : - _theResult___exp__h451889 ; + _theResult___fst_exp__h451445 : + _theResult___exp__h451887 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 = - (guard__h443399 == 2'b0) ? - _theResult___fst_exp__h451447 : + (guard__h443397 == 2'b0) ? + _theResult___fst_exp__h451445 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h451889 : - _theResult___fst_exp__h451447) ; + _theResult___exp__h451887 : + _theResult___fst_exp__h451445) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 = - (guard__h461165 == 2'b0 || + (guard__h461163 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h469242 : - _theResult___exp__h469709 ; + _theResult___fst_exp__h469240 : + _theResult___exp__h469707 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 = - (guard__h461165 == 2'b0) ? - _theResult___fst_exp__h469242 : + (guard__h461163 == 2'b0) ? + _theResult___fst_exp__h469240 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h469709 : - _theResult___fst_exp__h469242) ; + _theResult___exp__h469707 : + _theResult___fst_exp__h469240) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 = - (guard__h443399 == 2'b0 || + (guard__h443397 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h451398[56:34] : - _theResult___sfd__h451890 ; + _theResult___snd__h451396[56:34] : + _theResult___sfd__h451888 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 = - (guard__h443399 == 2'b0) ? - _theResult___snd__h451398[56:34] : + (guard__h443397 == 2'b0) ? + _theResult___snd__h451396[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h451890 : - _theResult___snd__h451398[56:34]) ; + _theResult___sfd__h451888 : + _theResult___snd__h451396[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 = - (guard__h461165 == 2'b0 || + (guard__h461163 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h469188[56:34] : - _theResult___sfd__h469710 ; + _theResult___snd__h469186[56:34] : + _theResult___sfd__h469708 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 = - (guard__h461165 == 2'b0) ? - _theResult___snd__h469188[56:34] : + (guard__h461163 == 2'b0) ? + _theResult___snd__h469186[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h469710 : - _theResult___snd__h469188[56:34]) ; + _theResult___sfd__h469708 : + _theResult___snd__h469186[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 = - (guard__h529516 == 2'b0 || + (guard__h529514 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h537477 : - _theResult___exp__h538132 ; + _theResult___fst_exp__h537475 : + _theResult___exp__h538130 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 = - (guard__h529516 == 2'b0) ? - _theResult___fst_exp__h537477 : + (guard__h529514 == 2'b0) ? + _theResult___fst_exp__h537475 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h538132 : - _theResult___fst_exp__h537477) ; + _theResult___exp__h538130 : + _theResult___fst_exp__h537475) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 = - (guard__h547897 == 2'b0 || + (guard__h547895 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h555887 : - _theResult___exp__h556567 ; + _theResult___fst_exp__h555885 : + _theResult___exp__h556565 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 = - (guard__h547897 == 2'b0) ? - _theResult___fst_exp__h555887 : + (guard__h547895 == 2'b0) ? + _theResult___fst_exp__h555885 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h556567 : - _theResult___fst_exp__h555887) ; + _theResult___exp__h556565 : + _theResult___fst_exp__h555885) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 = - (guard__h529516 == 2'b0 || + (guard__h529514 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h537428[56:5] : - _theResult___sfd__h538133 ; + _theResult___snd__h537426[56:5] : + _theResult___sfd__h538131 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 = - (guard__h529516 == 2'b0) ? - _theResult___snd__h537428[56:5] : + (guard__h529514 == 2'b0) ? + _theResult___snd__h537426[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h538133 : - _theResult___snd__h537428[56:5]) ; + _theResult___sfd__h538131 : + _theResult___snd__h537426[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 = - (guard__h547897 == 2'b0 || + (guard__h547895 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h555833[56:5] : - _theResult___sfd__h556568 ; + _theResult___snd__h555831[56:5] : + _theResult___sfd__h556566 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 = - (guard__h547897 == 2'b0) ? - _theResult___snd__h555833[56:5] : + (guard__h547895 == 2'b0) ? + _theResult___snd__h555831[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h556568 : - _theResult___snd__h555833[56:5]) ; + _theResult___sfd__h556566 : + _theResult___snd__h555831[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 = - (guard__h490715 == 2'b0 || + (guard__h490713 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h498676 : - _theResult___exp__h499331 ; + _theResult___fst_exp__h498674 : + _theResult___exp__h499329 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 = - (guard__h490715 == 2'b0) ? - _theResult___fst_exp__h498676 : + (guard__h490713 == 2'b0) ? + _theResult___fst_exp__h498674 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h499331 : - _theResult___fst_exp__h498676) ; + _theResult___exp__h499329 : + _theResult___fst_exp__h498674) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 = - (guard__h509096 == 2'b0 || + (guard__h509094 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h517086 : - _theResult___exp__h517766 ; + _theResult___fst_exp__h517084 : + _theResult___exp__h517764 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 = - (guard__h509096 == 2'b0) ? - _theResult___fst_exp__h517086 : + (guard__h509094 == 2'b0) ? + _theResult___fst_exp__h517084 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h517766 : - _theResult___fst_exp__h517086) ; + _theResult___exp__h517764 : + _theResult___fst_exp__h517084) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 = - (guard__h490715 == 2'b0 || + (guard__h490713 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h498627[56:5] : - _theResult___sfd__h499332 ; + _theResult___snd__h498625[56:5] : + _theResult___sfd__h499330 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 = - (guard__h490715 == 2'b0) ? - _theResult___snd__h498627[56:5] : + (guard__h490713 == 2'b0) ? + _theResult___snd__h498625[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h499332 : - _theResult___snd__h498627[56:5]) ; + _theResult___sfd__h499330 : + _theResult___snd__h498625[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 = - (guard__h509096 == 2'b0 || + (guard__h509094 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h517032[56:5] : - _theResult___sfd__h517767 ; + _theResult___snd__h517030[56:5] : + _theResult___sfd__h517765 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 = - (guard__h509096 == 2'b0) ? - _theResult___snd__h517032[56:5] : + (guard__h509094 == 2'b0) ? + _theResult___snd__h517030[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h517767 : - _theResult___snd__h517032[56:5]) ; + _theResult___sfd__h517765 : + _theResult___snd__h517030[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 = - (guard__h568717 == 2'b0 || + (guard__h568715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h576678 : - _theResult___exp__h577333 ; + _theResult___fst_exp__h576676 : + _theResult___exp__h577331 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 = - (guard__h568717 == 2'b0) ? - _theResult___fst_exp__h576678 : + (guard__h568715 == 2'b0) ? + _theResult___fst_exp__h576676 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h577333 : - _theResult___fst_exp__h576678) ; + _theResult___exp__h577331 : + _theResult___fst_exp__h576676) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 = - (guard__h587098 == 2'b0 || + (guard__h587096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h595088 : - _theResult___exp__h595768 ; + _theResult___fst_exp__h595086 : + _theResult___exp__h595766 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 = - (guard__h587098 == 2'b0) ? - _theResult___fst_exp__h595088 : + (guard__h587096 == 2'b0) ? + _theResult___fst_exp__h595086 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h595768 : - _theResult___fst_exp__h595088) ; + _theResult___exp__h595766 : + _theResult___fst_exp__h595086) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 = - (guard__h568717 == 2'b0 || + (guard__h568715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h576629[56:5] : - _theResult___sfd__h577334 ; + _theResult___snd__h576627[56:5] : + _theResult___sfd__h577332 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 = - (guard__h568717 == 2'b0) ? - _theResult___snd__h576629[56:5] : + (guard__h568715 == 2'b0) ? + _theResult___snd__h576627[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h577334 : - _theResult___snd__h576629[56:5]) ; + _theResult___sfd__h577332 : + _theResult___snd__h576627[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 = - (guard__h587098 == 2'b0 || + (guard__h587096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h595034[56:5] : - _theResult___sfd__h595769 ; + _theResult___snd__h595032[56:5] : + _theResult___sfd__h595767 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 = - (guard__h587098 == 2'b0) ? - _theResult___snd__h595034[56:5] : + (guard__h587096 == 2'b0) ? + _theResult___snd__h595032[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h595769 : - _theResult___snd__h595034[56:5]) ; + _theResult___sfd__h595767 : + _theResult___snd__h595032[56:5]) ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674 = - (_theResult____h645398 == 15'd0 && + (_theResult____h645396 == 15'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h645942 : - _theResult____h645398 ; + enabled_ints__h645940 : + _theResult____h645396 ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12881 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || @@ -19255,67 +19255,67 @@ module mkCore(CLK, checkForException___d13458[4] || csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13547 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10450 = - (_theResult___fst_exp__h555887 == 11'd2047) ? + (_theResult___fst_exp__h555885 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10654 = - (_theResult___fst_exp__h537477 == 11'd2047) ? + (_theResult___fst_exp__h537475 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10681 = - (_theResult___fst_exp__h555887 == 11'd2047) ? + (_theResult___fst_exp__h555885 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8977 = - (_theResult___fst_exp__h517086 == 11'd2047) ? + (_theResult___fst_exp__h517084 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9687 = - (_theResult___fst_exp__h595088 == 11'd2047) ? + (_theResult___fst_exp__h595086 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892 = - (_theResult___fst_exp__h576678 == 11'd2047) ? + (_theResult___fst_exp__h576676 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9919 = - (_theResult___fst_exp__h595088 == 11'd2047) ? + (_theResult___fst_exp__h595086 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 = IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ? @@ -19521,35 +19521,35 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10109 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 || - _theResult___fst_exp__h537477 == 11'd2047) ? + _theResult___fst_exp__h537475 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8636 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 || - _theResult___fst_exp__h498676 == 11'd2047) ? + _theResult___fst_exp__h498674 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9346 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 || - _theResult___fst_exp__h576678 == 11'd2047) ? + _theResult___fst_exp__h576676 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] ? @@ -19987,35 +19987,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369179 == 8'd255) ? + ((_theResult___fst_exp__h369177 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) : - ((_theResult___fst_exp__h377864 == 8'd255) ? + ((_theResult___fst_exp__h377862 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369179 == 8'd255) ? + ((_theResult___fst_exp__h369177 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) : - ((_theResult___fst_exp__h377864 == 8'd255) ? + ((_theResult___fst_exp__h377862 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] : - _theResult___fst_exp__h378412 == 8'd255 && - _theResult___fst_sfd__h378413 == 23'd0 ; + _theResult___fst_exp__h378410 == 8'd255 && + _theResult___fst_sfd__h378411 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] : - _theResult___fst_exp__h377864 == 8'd0 && - guard__h369787 != 2'b0 ; + _theResult___fst_exp__h377862 == 8'd0 && + guard__h369785 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] : - _theResult___fst_exp__h377864 != 8'd255 && - guard__h369787 != 2'b0 ; + _theResult___fst_exp__h377862 != 8'd255 && + guard__h369785 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? @@ -20025,35 +20025,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414869 == 8'd255) ? + ((_theResult___fst_exp__h414867 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) : - ((_theResult___fst_exp__h423554 == 8'd255) ? + ((_theResult___fst_exp__h423552 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414869 == 8'd255) ? + ((_theResult___fst_exp__h414867 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) : - ((_theResult___fst_exp__h423554 == 8'd255) ? + ((_theResult___fst_exp__h423552 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] : - _theResult___fst_exp__h424102 == 8'd255 && - _theResult___fst_sfd__h424103 == 23'd0 ; + _theResult___fst_exp__h424100 == 8'd255 && + _theResult___fst_sfd__h424101 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] : - _theResult___fst_exp__h423554 == 8'd0 && - guard__h415477 != 2'b0 ; + _theResult___fst_exp__h423552 == 8'd0 && + guard__h415475 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] : - _theResult___fst_exp__h423554 != 8'd255 && - guard__h415477 != 2'b0 ; + _theResult___fst_exp__h423552 != 8'd255 && + guard__h415475 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? @@ -20063,35 +20063,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460557 == 8'd255) ? + ((_theResult___fst_exp__h460555 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) : - ((_theResult___fst_exp__h469242 == 8'd255) ? + ((_theResult___fst_exp__h469240 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460557 == 8'd255) ? + ((_theResult___fst_exp__h460555 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) : - ((_theResult___fst_exp__h469242 == 8'd255) ? + ((_theResult___fst_exp__h469240 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] : - _theResult___fst_exp__h469790 == 8'd255 && - _theResult___fst_sfd__h469791 == 23'd0 ; + _theResult___fst_exp__h469788 == 8'd255 && + _theResult___fst_sfd__h469789 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] : - _theResult___fst_exp__h469242 == 8'd0 && - guard__h461165 != 2'b0 ; + _theResult___fst_exp__h469240 == 8'd0 && + guard__h461163 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] : - _theResult___fst_exp__h469242 != 8'd255 && - guard__h461165 != 2'b0 ; + _theResult___fst_exp__h469240 != 8'd255 && + guard__h461163 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? @@ -20114,48 +20114,48 @@ module mkCore(CLK, assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10878 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[2] : - _theResult___fst_exp__h517869 == 11'd2047 && - _theResult___fst_sfd__h517870 == 52'd0 ; + _theResult___fst_exp__h517867 == 11'd2047 && + _theResult___fst_sfd__h517868 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10892 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[2] : - _theResult___fst_exp__h556670 == 11'd2047 && - _theResult___fst_sfd__h556671 == 52'd0 ; + _theResult___fst_exp__h556668 == 11'd2047 && + _theResult___fst_sfd__h556669 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10907 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[2] : - _theResult___fst_exp__h595871 == 11'd2047 && - _theResult___fst_sfd__h595872 == 52'd0 ; + _theResult___fst_exp__h595869 == 11'd2047 && + _theResult___fst_sfd__h595870 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10924 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[1] : - _theResult___fst_exp__h517086 == 11'd0 && - guard__h509096 != 2'b0 ; + _theResult___fst_exp__h517084 == 11'd0 && + guard__h509094 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10936 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[1] : - _theResult___fst_exp__h555887 == 11'd0 && - guard__h547897 != 2'b0 ; + _theResult___fst_exp__h555885 == 11'd0 && + guard__h547895 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10949 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[1] : - _theResult___fst_exp__h595088 == 11'd0 && - guard__h587098 != 2'b0 ; + _theResult___fst_exp__h595086 == 11'd0 && + guard__h587096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10966 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[0] : - _theResult___fst_exp__h517086 != 11'd2047 && - guard__h509096 != 2'b0 ; + _theResult___fst_exp__h517084 != 11'd2047 && + guard__h509094 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10978 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[0] : - _theResult___fst_exp__h555887 != 11'd2047 && - guard__h547897 != 2'b0 ; + _theResult___fst_exp__h555885 != 11'd2047 && + guard__h547895 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10991 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[0] : - _theResult___fst_exp__h595088 != 11'd2047 && - guard__h587098 != 2'b0 ; + _theResult___fst_exp__h595086 != 11'd2047 && + guard__h587096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? @@ -20877,11 +20877,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h556682, + _theResult___fst_exp__h556680, (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ? - _theResult___snd_fst_sfd__h518571 : - _theResult___fst_sfd__h556686 } ; + _theResult___snd_fst_sfd__h518569 : + _theResult___fst_sfd__h556684 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] : @@ -21079,11 +21079,11 @@ module mkCore(CLK, { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8981, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h517881, + _theResult___fst_exp__h517879, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ? - _theResult___snd_fst_sfd__h479629 : - _theResult___fst_sfd__h517885 } ; + _theResult___snd_fst_sfd__h479627 : + _theResult___fst_sfd__h517883 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] : @@ -21152,11 +21152,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h595883, + _theResult___fst_exp__h595881, (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ? - _theResult___snd_fst_sfd__h557772 : - _theResult___fst_sfd__h595887 } ; + _theResult___snd_fst_sfd__h557770 : + _theResult___fst_sfd__h595885 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] : @@ -21180,8 +21180,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h641105 : - w__h641100 ; + result__h641103 : + w__h641098 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -21203,39 +21203,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h195752 : + n___1__h195750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21288,7 +21288,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h194349 : + x__h194347 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? 64'd0 : 64'd1) ; @@ -21300,7 +21300,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 = - _theResult_____2__h293743 == v__h293163 ; + _theResult_____2__h293741 == v__h293161 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21309,7 +21309,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 = - _theResult_____2__h301739 == v__h296508 ; + _theResult_____2__h301737 == v__h296506 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21338,7 +21338,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h299373 } ; + x__h299371 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -21436,35 +21436,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h191677 : + n__h191675 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -21492,7 +21492,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 = - _theResult_____2__h307733 == v__h307022 ; + _theResult_____2__h307731 == v__h307020 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21501,7 +21501,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 = - _theResult_____2__h315587 == v__h310898 ; + _theResult_____2__h315585 == v__h310896 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21653,7 +21653,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 = - _theResult_____2__h329156 == v__h328724 ; + _theResult_____2__h329154 == v__h328722 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -21702,7 +21702,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 = - _theResult_____2__h325931 == v__h325499 ; + _theResult_____2__h325929 == v__h325497 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -21849,60 +21849,60 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h705150 : + y_avValue_snd_snd_snd_snd_snd__h705148 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705134 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705132 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h705144 : + y_avValue_snd_snd_snd_fst__h705142 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 = rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__4562_BIT_25_456_ETC___d14762 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h508247[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66 = - sfdin__h414863[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91 = - sfdin__h442785[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h547048[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21 = - sfdin__h351407[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101 = - sfdin__h460551[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31 = - sfdin__h369173[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h586249[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56 = - sfdin__h397097[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58 = - _theResult___snd__h405710[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h517032[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71 = - _theResult___snd__h423500[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h537428[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93 = - _theResult___snd__h451398[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h555833[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23 = - _theResult___snd__h360020[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106 = - _theResult___snd__h469188[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h576629[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36 = - _theResult___snd__h377810[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h595034[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h498627[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h508245[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66 = + sfdin__h414861[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91 = + sfdin__h442783[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h547046[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21 = + sfdin__h351405[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101 = + sfdin__h460549[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31 = + sfdin__h369171[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h586247[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56 = + sfdin__h397095[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58 = + _theResult___snd__h405708[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h517030[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71 = + _theResult___snd__h423498[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h537426[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93 = + _theResult___snd__h451396[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h555831[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23 = + _theResult___snd__h360018[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106 = + _theResult___snd__h469186[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h576627[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36 = + _theResult___snd__h377808[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h595032[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h498625[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? @@ -21991,10 +21991,10 @@ module mkCore(CLK, !checkForException___d13458[4] && NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13483 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4555_4556_OR__ETC___d14768 = - (fflags__h705627 & csrf_fflags_reg) != fflags__h705627 || - !r__h608869 && + (fflags__h705625 & csrf_fflags_reg) != fflags__h705625 || + !r__h608870 && (IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 || - fflags__h705627 != 5'd0) ; + fflags__h705625 != 5'd0) ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13263 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -22806,8 +22806,8 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13117 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h649453 == 5'd0 && - imm__h649454 == 32'd0 || + rs1__h649451 == 5'd0 && + imm__h649452 == 32'd0 || IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 = @@ -23142,7 +23142,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - x__h288838 } ; + x__h288836 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -23275,15 +23275,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 = { 3'd0, - _theResult___fst_exp__h351413 == 8'd0 && - (sfdin__h351407[56:34] == 23'd0 || guard__h343312 != 2'b0), + _theResult___fst_exp__h351411 == 8'd0 && + (sfdin__h351405[56:34] == 23'd0 || guard__h343310 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h352010 == 8'd255 && - _theResult___fst_sfd__h352011 == 23'd0, + _theResult___fst_exp__h352008 == 8'd255 && + _theResult___fst_sfd__h352009 == 23'd0, 1'd0, - _theResult___fst_exp__h351413 != 8'd255 && - guard__h343312 != 2'b0 } ; + _theResult___fst_exp__h351411 != 8'd255 && + guard__h343310 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^ @@ -23291,15 +23291,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 = { 3'd0, - _theResult___fst_exp__h397103 == 8'd0 && - (sfdin__h397097[56:34] == 23'd0 || guard__h389004 != 2'b0), + _theResult___fst_exp__h397101 == 8'd0 && + (sfdin__h397095[56:34] == 23'd0 || guard__h389002 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h397700 == 8'd255 && - _theResult___fst_sfd__h397701 == 23'd0, + _theResult___fst_exp__h397698 == 8'd255 && + _theResult___fst_sfd__h397699 == 23'd0, 1'd0, - _theResult___fst_exp__h397103 != 8'd255 && - guard__h389004 != 2'b0 } ; + _theResult___fst_exp__h397101 != 8'd255 && + guard__h389002 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^ @@ -23307,15 +23307,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 = { 3'd0, - _theResult___fst_exp__h442791 == 8'd0 && - (sfdin__h442785[56:34] == 23'd0 || guard__h434692 != 2'b0), + _theResult___fst_exp__h442789 == 8'd0 && + (sfdin__h442783[56:34] == 23'd0 || guard__h434690 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h443388 == 8'd255 && - _theResult___fst_sfd__h443389 == 23'd0, + _theResult___fst_exp__h443386 == 8'd255 && + _theResult___fst_sfd__h443387 == 23'd0, 1'd0, - _theResult___fst_exp__h442791 != 8'd255 && - guard__h434692 != 2'b0 } ; + _theResult___fst_exp__h442789 != 8'd255 && + guard__h434690 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ^ @@ -23323,37 +23323,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736 = { 3'd0, - _theResult___fst_exp__h508253 == 11'd0 && - (sfdin__h508247[56:5] == 52'd0 || guard__h500027 != 2'b0), + _theResult___fst_exp__h508251 == 11'd0 && + (sfdin__h508245[56:5] == 52'd0 || guard__h500025 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h509085 == 11'd2047 && - _theResult___fst_sfd__h509086 == 52'd0, + _theResult___fst_exp__h509083 == 11'd2047 && + _theResult___fst_sfd__h509084 == 52'd0, 1'd0, - _theResult___fst_exp__h508253 != 11'd2047 && - guard__h500027 != 2'b0 } ; + _theResult___fst_exp__h508251 != 11'd2047 && + guard__h500025 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777 = { 3'd0, - _theResult___fst_exp__h547054 == 11'd0 && - (sfdin__h547048[56:5] == 52'd0 || guard__h538828 != 2'b0), + _theResult___fst_exp__h547052 == 11'd0 && + (sfdin__h547046[56:5] == 52'd0 || guard__h538826 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h547886 == 11'd2047 && - _theResult___fst_sfd__h547887 == 52'd0, + _theResult___fst_exp__h547884 == 11'd2047 && + _theResult___fst_sfd__h547885 == 52'd0, 1'd0, - _theResult___fst_exp__h547054 != 11'd2047 && - guard__h538828 != 2'b0 } ; + _theResult___fst_exp__h547052 != 11'd2047 && + guard__h538826 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821 = { 3'd0, - _theResult___fst_exp__h586255 == 11'd0 && - (sfdin__h586249[56:5] == 52'd0 || guard__h578029 != 2'b0), + _theResult___fst_exp__h586253 == 11'd0 && + (sfdin__h586247[56:5] == 52'd0 || guard__h578027 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h587087 == 11'd2047 && - _theResult___fst_sfd__h587088 == 52'd0, + _theResult___fst_exp__h587085 == 11'd2047 && + _theResult___fst_sfd__h587086 == 52'd0, 1'd0, - _theResult___fst_exp__h586255 != 11'd2047 && - guard__h578029 != 2'b0 } ; + _theResult___fst_exp__h586253 != 11'd2047 && + guard__h578027 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ^ @@ -23371,15 +23371,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 = { 3'd0, - _theResult___fst_exp__h369179 == 8'd0 && - (sfdin__h369173[56:34] == 23'd0 || guard__h360951 != 2'b0), + _theResult___fst_exp__h369177 == 8'd0 && + (sfdin__h369171[56:34] == 23'd0 || guard__h360949 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h369776 == 8'd255 && - _theResult___fst_sfd__h369777 == 23'd0, + _theResult___fst_exp__h369774 == 8'd255 && + _theResult___fst_sfd__h369775 == 23'd0, 1'd0, - _theResult___fst_exp__h369179 != 8'd255 && - guard__h360951 != 2'b0 } ; + _theResult___fst_exp__h369177 != 8'd255 && + guard__h360949 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^ @@ -23387,15 +23387,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 = { 3'd0, - _theResult___fst_exp__h414869 == 8'd0 && - (sfdin__h414863[56:34] == 23'd0 || guard__h406641 != 2'b0), + _theResult___fst_exp__h414867 == 8'd0 && + (sfdin__h414861[56:34] == 23'd0 || guard__h406639 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h415466 == 8'd255 && - _theResult___fst_sfd__h415467 == 23'd0, + _theResult___fst_exp__h415464 == 8'd255 && + _theResult___fst_sfd__h415465 == 23'd0, 1'd0, - _theResult___fst_exp__h414869 != 8'd255 && - guard__h406641 != 2'b0 } ; + _theResult___fst_exp__h414867 != 8'd255 && + guard__h406639 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^ @@ -23403,15 +23403,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 = { 3'd0, - _theResult___fst_exp__h460557 == 8'd0 && - (sfdin__h460551[56:34] == 23'd0 || guard__h452329 != 2'b0), + _theResult___fst_exp__h460555 == 8'd0 && + (sfdin__h460549[56:34] == 23'd0 || guard__h452327 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h461154 == 8'd255 && - _theResult___fst_sfd__h461155 == 23'd0, + _theResult___fst_exp__h461152 == 8'd255 && + _theResult___fst_sfd__h461153 == 23'd0, 1'd0, - _theResult___fst_exp__h460557 != 8'd255 && - guard__h452329 != 2'b0 } ; + _theResult___fst_exp__h460555 != 8'd255 && + guard__h452327 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^ @@ -23425,15 +23425,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 = { 3'd0, - _theResult___fst_exp__h360069 == 8'd0 && - guard__h352021 != 2'b0, + _theResult___fst_exp__h360067 == 8'd0 && + guard__h352019 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h360592 == 8'd255 && - _theResult___fst_sfd__h360593 == 23'd0, + _theResult___fst_exp__h360590 == 8'd255 && + _theResult___fst_sfd__h360591 == 23'd0, 1'd0, - _theResult___fst_exp__h360069 != 8'd255 && - guard__h352021 != 2'b0 } ; + _theResult___fst_exp__h360067 != 8'd255 && + guard__h352019 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ @@ -23447,15 +23447,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 = { 3'd0, - _theResult___fst_exp__h405759 == 8'd0 && - guard__h397711 != 2'b0, + _theResult___fst_exp__h405757 == 8'd0 && + guard__h397709 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h406282 == 8'd255 && - _theResult___fst_sfd__h406283 == 23'd0, + _theResult___fst_exp__h406280 == 8'd255 && + _theResult___fst_sfd__h406281 == 23'd0, 1'd0, - _theResult___fst_exp__h405759 != 8'd255 && - guard__h397711 != 2'b0 } ; + _theResult___fst_exp__h405757 != 8'd255 && + guard__h397709 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ @@ -23469,15 +23469,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 = { 3'd0, - _theResult___fst_exp__h451447 == 8'd0 && - guard__h443399 != 2'b0, + _theResult___fst_exp__h451445 == 8'd0 && + guard__h443397 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h451970 == 8'd255 && - _theResult___fst_sfd__h451971 == 23'd0, + _theResult___fst_exp__h451968 == 8'd255 && + _theResult___fst_sfd__h451969 == 23'd0, 1'd0, - _theResult___fst_exp__h451447 != 8'd255 && - guard__h443399 != 2'b0 } ; + _theResult___fst_exp__h451445 != 8'd255 && + guard__h443397 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ^ @@ -23491,37 +23491,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719 = { 3'd0, - _theResult___fst_exp__h498676 == 11'd0 && - guard__h490715 != 2'b0, + _theResult___fst_exp__h498674 == 11'd0 && + guard__h490713 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h499434 == 11'd2047 && - _theResult___fst_sfd__h499435 == 52'd0, + _theResult___fst_exp__h499432 == 11'd2047 && + _theResult___fst_sfd__h499433 == 52'd0, 1'd0, - _theResult___fst_exp__h498676 != 11'd2047 && - guard__h490715 != 2'b0 } ; + _theResult___fst_exp__h498674 != 11'd2047 && + guard__h490713 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760 = { 3'd0, - _theResult___fst_exp__h537477 == 11'd0 && - guard__h529516 != 2'b0, + _theResult___fst_exp__h537475 == 11'd0 && + guard__h529514 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h538235 == 11'd2047 && - _theResult___fst_sfd__h538236 == 52'd0, + _theResult___fst_exp__h538233 == 11'd2047 && + _theResult___fst_sfd__h538234 == 52'd0, 1'd0, - _theResult___fst_exp__h537477 != 11'd2047 && - guard__h529516 != 2'b0 } ; + _theResult___fst_exp__h537475 != 11'd2047 && + guard__h529514 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804 = { 3'd0, - _theResult___fst_exp__h576678 == 11'd0 && - guard__h568717 != 2'b0, + _theResult___fst_exp__h576676 == 11'd0 && + guard__h568715 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h577436 == 11'd2047 && - _theResult___fst_sfd__h577437 == 52'd0, + _theResult___fst_exp__h577434 == 11'd2047 && + _theResult___fst_sfd__h577435 == 52'd0, 1'd0, - _theResult___fst_exp__h576678 != 11'd2047 && - guard__h568717 != 2'b0 } ; + _theResult___fst_exp__h576676 != 11'd2047 && + guard__h568715 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ^ @@ -23547,7 +23547,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2605_BI_ETC___d13675 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2614_BI_ETC___d13760 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -23559,33 +23559,33 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 = - sfd__h335697 >> + sfd__h335695 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 = - sfd__h381392 >> + sfd__h381390 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 = - sfd__h427080 >> + sfd__h427078 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118 = - sfd__h518617 >> + sfd__h518615 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645 = - sfd__h479675 >> + sfd__h479673 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355 = - sfd__h557818 >> + sfd__h557816 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1598_1599_ETC___d14227 = - medeleg_csr__read__h607140[i__h692204] ; + medeleg_csr__read__h607141[i__h692202] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1606_1607_ETC___d14209 = - mideleg_csr__read__h607235[i__h692364] ; + mideleg_csr__read__h607236[i__h692362] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 = 12'd3074 - { 6'd0, @@ -24180,7 +24180,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h661045 == 1'd0 && + k__h661043 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd0 && @@ -24199,7 +24199,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo26 = + assign _dfoo28 = rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd8 || @@ -24287,1430 +24287,1430 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h293743 = + assign _theResult_____2__h293741 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ? - next_deqP___1__h294022 : + next_deqP___1__h294020 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h301739 = + assign _theResult_____2__h301737 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ? - next_deqP___1__h302018 : + next_deqP___1__h302016 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h307733 = + assign _theResult_____2__h307731 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ? - next_deqP___1__h308299 : + next_deqP___1__h308297 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h315587 = + assign _theResult_____2__h315585 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ? - next_deqP___1__h316153 : + next_deqP___1__h316151 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h325931 = + assign _theResult_____2__h325929 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ? - next_deqP___1__h326210 : + next_deqP___1__h326208 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h329156 = + assign _theResult_____2__h329154 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ? - next_deqP___1__h329435 : + next_deqP___1__h329433 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h343302 = - (value__h343924 == 54'd0) ? sfd__h335697 : 57'd1 ; - assign _theResult____h360941 = + assign _theResult____h343300 = + (value__h343922 == 54'd0) ? sfd__h335695 : 57'd1 ; + assign _theResult____h360939 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^ 12'h800) < 12'd2105) ? - result__h361554 : - _theResult____h343302 ; - assign _theResult____h388994 = - (value__h389614 == 54'd0) ? sfd__h381392 : 57'd1 ; - assign _theResult____h406631 = + result__h361552 : + _theResult____h343300 ; + assign _theResult____h388992 = + (value__h389612 == 54'd0) ? sfd__h381390 : 57'd1 ; + assign _theResult____h406629 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^ 12'h800) < 12'd2105) ? - result__h407244 : - _theResult____h388994 ; - assign _theResult____h434682 = - (value__h435302 == 54'd0) ? sfd__h427080 : 57'd1 ; - assign _theResult____h452319 = + result__h407242 : + _theResult____h388992 ; + assign _theResult____h434680 = + (value__h435300 == 54'd0) ? sfd__h427078 : 57'd1 ; + assign _theResult____h452317 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^ 12'h800) < 12'd2105) ? - result__h452932 : - _theResult____h434682 ; - assign _theResult____h500017 = + result__h452930 : + _theResult____h434680 ; + assign _theResult____h500015 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ^ 12'h800) < 12'd2105) ? - result__h500630 : - ((value__h484233 == 25'd0) ? sfd__h479675 : 57'd1) ; - assign _theResult____h538818 = + result__h500628 : + ((value__h484231 == 25'd0) ? sfd__h479673 : 57'd1) ; + assign _theResult____h538816 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ^ 12'h800) < 12'd2105) ? - result__h539431 : - ((value__h523034 == 25'd0) ? sfd__h518617 : 57'd1) ; - assign _theResult____h578019 = + result__h539429 : + ((value__h523032 == 25'd0) ? sfd__h518615 : 57'd1) ; + assign _theResult____h578017 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ^ 12'h800) < 12'd2105) ? - result__h578632 : - ((value__h562235 == 25'd0) ? sfd__h557818 : 57'd1) ; - assign _theResult____h645398 = + result__h578630 : + ((value__h562233 == 25'd0) ? sfd__h557816 : 57'd1) ; + assign _theResult____h645396 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h645895 : + enabled_ints___1__h645893 : 15'd0 ; - assign _theResult___exp__h351929 = - sfd__h351505[24] ? - ((_theResult___fst_exp__h351413 == 8'd254) ? + assign _theResult___exp__h351927 = + sfd__h351503[24] ? + ((_theResult___fst_exp__h351411 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378446) : - ((_theResult___fst_exp__h351413 == 8'd0 && - sfd__h351505[24:23] == 2'b01) ? + din_inc___2_exp__h378444) : + ((_theResult___fst_exp__h351411 == 8'd0 && + sfd__h351503[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h351413) ; - assign _theResult___exp__h360511 = - sfd__h360087[24] ? - ((_theResult___fst_exp__h360069 == 8'd254) ? + _theResult___fst_exp__h351411) ; + assign _theResult___exp__h360509 = + sfd__h360085[24] ? + ((_theResult___fst_exp__h360067 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378470) : - ((_theResult___fst_exp__h360069 == 8'd0 && - sfd__h360087[24:23] == 2'b01) ? + din_inc___2_exp__h378468) : + ((_theResult___fst_exp__h360067 == 8'd0 && + sfd__h360085[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h360069) ; - assign _theResult___exp__h369695 = - sfd__h369271[24] ? - ((_theResult___fst_exp__h369179 == 8'd254) ? + _theResult___fst_exp__h360067) ; + assign _theResult___exp__h369693 = + sfd__h369269[24] ? + ((_theResult___fst_exp__h369177 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378500) : - ((_theResult___fst_exp__h369179 == 8'd0 && - sfd__h369271[24:23] == 2'b01) ? + din_inc___2_exp__h378498) : + ((_theResult___fst_exp__h369177 == 8'd0 && + sfd__h369269[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h369179) ; - assign _theResult___exp__h378331 = - sfd__h377883[24] ? - ((_theResult___fst_exp__h377864 == 8'd254) ? + _theResult___fst_exp__h369177) ; + assign _theResult___exp__h378329 = + sfd__h377881[24] ? + ((_theResult___fst_exp__h377862 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378524) : - ((_theResult___fst_exp__h377864 == 8'd0 && - sfd__h377883[24:23] == 2'b01) ? + din_inc___2_exp__h378522) : + ((_theResult___fst_exp__h377862 == 8'd0 && + sfd__h377881[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h377864) ; - assign _theResult___exp__h378433 = + _theResult___fst_exp__h377862) ; + assign _theResult___exp__h378431 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378424 ; - assign _theResult___exp__h397619 = - sfd__h397195[24] ? - ((_theResult___fst_exp__h397103 == 8'd254) ? + _theResult___fst_exp__h378422 ; + assign _theResult___exp__h397617 = + sfd__h397193[24] ? + ((_theResult___fst_exp__h397101 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424136) : - ((_theResult___fst_exp__h397103 == 8'd0 && - sfd__h397195[24:23] == 2'b01) ? + din_inc___2_exp__h424134) : + ((_theResult___fst_exp__h397101 == 8'd0 && + sfd__h397193[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h397103) ; - assign _theResult___exp__h406201 = - sfd__h405777[24] ? - ((_theResult___fst_exp__h405759 == 8'd254) ? + _theResult___fst_exp__h397101) ; + assign _theResult___exp__h406199 = + sfd__h405775[24] ? + ((_theResult___fst_exp__h405757 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424160) : - ((_theResult___fst_exp__h405759 == 8'd0 && - sfd__h405777[24:23] == 2'b01) ? + din_inc___2_exp__h424158) : + ((_theResult___fst_exp__h405757 == 8'd0 && + sfd__h405775[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h405759) ; - assign _theResult___exp__h415385 = - sfd__h414961[24] ? - ((_theResult___fst_exp__h414869 == 8'd254) ? + _theResult___fst_exp__h405757) ; + assign _theResult___exp__h415383 = + sfd__h414959[24] ? + ((_theResult___fst_exp__h414867 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424190) : - ((_theResult___fst_exp__h414869 == 8'd0 && - sfd__h414961[24:23] == 2'b01) ? + din_inc___2_exp__h424188) : + ((_theResult___fst_exp__h414867 == 8'd0 && + sfd__h414959[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h414869) ; - assign _theResult___exp__h424021 = - sfd__h423573[24] ? - ((_theResult___fst_exp__h423554 == 8'd254) ? + _theResult___fst_exp__h414867) ; + assign _theResult___exp__h424019 = + sfd__h423571[24] ? + ((_theResult___fst_exp__h423552 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424214) : - ((_theResult___fst_exp__h423554 == 8'd0 && - sfd__h423573[24:23] == 2'b01) ? + din_inc___2_exp__h424212) : + ((_theResult___fst_exp__h423552 == 8'd0 && + sfd__h423571[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h423554) ; - assign _theResult___exp__h424123 = + _theResult___fst_exp__h423552) ; + assign _theResult___exp__h424121 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424114 ; - assign _theResult___exp__h443307 = - sfd__h442883[24] ? - ((_theResult___fst_exp__h442791 == 8'd254) ? + _theResult___fst_exp__h424112 ; + assign _theResult___exp__h443305 = + sfd__h442881[24] ? + ((_theResult___fst_exp__h442789 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469824) : - ((_theResult___fst_exp__h442791 == 8'd0 && - sfd__h442883[24:23] == 2'b01) ? + din_inc___2_exp__h469822) : + ((_theResult___fst_exp__h442789 == 8'd0 && + sfd__h442881[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h442791) ; - assign _theResult___exp__h451889 = - sfd__h451465[24] ? - ((_theResult___fst_exp__h451447 == 8'd254) ? + _theResult___fst_exp__h442789) ; + assign _theResult___exp__h451887 = + sfd__h451463[24] ? + ((_theResult___fst_exp__h451445 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469848) : - ((_theResult___fst_exp__h451447 == 8'd0 && - sfd__h451465[24:23] == 2'b01) ? + din_inc___2_exp__h469846) : + ((_theResult___fst_exp__h451445 == 8'd0 && + sfd__h451463[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h451447) ; - assign _theResult___exp__h461073 = - sfd__h460649[24] ? - ((_theResult___fst_exp__h460557 == 8'd254) ? + _theResult___fst_exp__h451445) ; + assign _theResult___exp__h461071 = + sfd__h460647[24] ? + ((_theResult___fst_exp__h460555 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469878) : - ((_theResult___fst_exp__h460557 == 8'd0 && - sfd__h460649[24:23] == 2'b01) ? + din_inc___2_exp__h469876) : + ((_theResult___fst_exp__h460555 == 8'd0 && + sfd__h460647[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h460557) ; - assign _theResult___exp__h469709 = - sfd__h469261[24] ? - ((_theResult___fst_exp__h469242 == 8'd254) ? + _theResult___fst_exp__h460555) ; + assign _theResult___exp__h469707 = + sfd__h469259[24] ? + ((_theResult___fst_exp__h469240 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469902) : - ((_theResult___fst_exp__h469242 == 8'd0 && - sfd__h469261[24:23] == 2'b01) ? + din_inc___2_exp__h469900) : + ((_theResult___fst_exp__h469240 == 8'd0 && + sfd__h469259[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h469242) ; - assign _theResult___exp__h469811 = + _theResult___fst_exp__h469240) ; + assign _theResult___exp__h469809 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469802 ; - assign _theResult___exp__h499331 = - sfd__h498694[53] ? - ((_theResult___fst_exp__h498676 == 11'd2046) ? + _theResult___fst_exp__h469800 ; + assign _theResult___exp__h499329 = + sfd__h498692[53] ? + ((_theResult___fst_exp__h498674 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517926) : - ((_theResult___fst_exp__h498676 == 11'd0 && - sfd__h498694[53:52] == 2'b01) ? + din_inc___2_exp__h517924) : + ((_theResult___fst_exp__h498674 == 11'd0 && + sfd__h498692[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h498676) ; - assign _theResult___exp__h508982 = - sfd__h508345[53] ? - ((_theResult___fst_exp__h508253 == 11'd2046) ? + _theResult___fst_exp__h498674) ; + assign _theResult___exp__h508980 = + sfd__h508343[53] ? + ((_theResult___fst_exp__h508251 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517961) : - ((_theResult___fst_exp__h508253 == 11'd0 && - sfd__h508345[53:52] == 2'b01) ? + din_inc___2_exp__h517959) : + ((_theResult___fst_exp__h508251 == 11'd0 && + sfd__h508343[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h508253) ; - assign _theResult___exp__h517766 = - sfd__h517105[53] ? - ((_theResult___fst_exp__h517086 == 11'd2046) ? + _theResult___fst_exp__h508251) ; + assign _theResult___exp__h517764 = + sfd__h517103[53] ? + ((_theResult___fst_exp__h517084 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517987) : - ((_theResult___fst_exp__h517086 == 11'd0 && - sfd__h517105[53:52] == 2'b01) ? + din_inc___2_exp__h517985) : + ((_theResult___fst_exp__h517084 == 11'd0 && + sfd__h517103[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h517086) ; - assign _theResult___exp__h538132 = - sfd__h537495[53] ? - ((_theResult___fst_exp__h537477 == 11'd2046) ? + _theResult___fst_exp__h517084) ; + assign _theResult___exp__h538130 = + sfd__h537493[53] ? + ((_theResult___fst_exp__h537475 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556727) : - ((_theResult___fst_exp__h537477 == 11'd0 && - sfd__h537495[53:52] == 2'b01) ? + din_inc___2_exp__h556725) : + ((_theResult___fst_exp__h537475 == 11'd0 && + sfd__h537493[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h537477) ; - assign _theResult___exp__h547783 = - sfd__h547146[53] ? - ((_theResult___fst_exp__h547054 == 11'd2046) ? + _theResult___fst_exp__h537475) ; + assign _theResult___exp__h547781 = + sfd__h547144[53] ? + ((_theResult___fst_exp__h547052 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556762) : - ((_theResult___fst_exp__h547054 == 11'd0 && - sfd__h547146[53:52] == 2'b01) ? + din_inc___2_exp__h556760) : + ((_theResult___fst_exp__h547052 == 11'd0 && + sfd__h547144[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h547054) ; - assign _theResult___exp__h556567 = - sfd__h555906[53] ? - ((_theResult___fst_exp__h555887 == 11'd2046) ? + _theResult___fst_exp__h547052) ; + assign _theResult___exp__h556565 = + sfd__h555904[53] ? + ((_theResult___fst_exp__h555885 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556788) : - ((_theResult___fst_exp__h555887 == 11'd0 && - sfd__h555906[53:52] == 2'b01) ? + din_inc___2_exp__h556786) : + ((_theResult___fst_exp__h555885 == 11'd0 && + sfd__h555904[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h555887) ; - assign _theResult___exp__h577333 = - sfd__h576696[53] ? - ((_theResult___fst_exp__h576678 == 11'd2046) ? + _theResult___fst_exp__h555885) ; + assign _theResult___exp__h577331 = + sfd__h576694[53] ? + ((_theResult___fst_exp__h576676 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595928) : - ((_theResult___fst_exp__h576678 == 11'd0 && - sfd__h576696[53:52] == 2'b01) ? + din_inc___2_exp__h595926) : + ((_theResult___fst_exp__h576676 == 11'd0 && + sfd__h576694[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h576678) ; - assign _theResult___exp__h586984 = - sfd__h586347[53] ? - ((_theResult___fst_exp__h586255 == 11'd2046) ? + _theResult___fst_exp__h576676) ; + assign _theResult___exp__h586982 = + sfd__h586345[53] ? + ((_theResult___fst_exp__h586253 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595963) : - ((_theResult___fst_exp__h586255 == 11'd0 && - sfd__h586347[53:52] == 2'b01) ? + din_inc___2_exp__h595961) : + ((_theResult___fst_exp__h586253 == 11'd0 && + sfd__h586345[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h586255) ; - assign _theResult___exp__h595768 = - sfd__h595107[53] ? - ((_theResult___fst_exp__h595088 == 11'd2046) ? + _theResult___fst_exp__h586253) ; + assign _theResult___exp__h595766 = + sfd__h595105[53] ? + ((_theResult___fst_exp__h595086 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595989) : - ((_theResult___fst_exp__h595088 == 11'd0 && - sfd__h595107[53:52] == 2'b01) ? + din_inc___2_exp__h595987) : + ((_theResult___fst_exp__h595086 == 11'd0 && + sfd__h595105[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h595088) ; - assign _theResult___fst__h600261 = - a__h599839[63] ? a___1__h600266 : a__h599839 ; - assign _theResult___fst_exp__h351413 = - _theResult____h343302[56] ? + _theResult___fst_exp__h595086) ; + assign _theResult___fst__h600259 = + a__h599837[63] ? a___1__h600264 : a__h599837 ; + assign _theResult___fst_exp__h351411 = + _theResult____h343300[56] ? 8'd2 : - _theResult___fst_exp__h351487 ; - assign _theResult___fst_exp__h351478 = + _theResult___fst_exp__h351485 ; + assign _theResult___fst_exp__h351476 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ; - assign _theResult___fst_exp__h351484 = - (!_theResult____h343302[56] && !_theResult____h343302[55] && - !_theResult____h343302[54] && - !_theResult____h343302[53] && - !_theResult____h343302[52] && - !_theResult____h343302[51] && - !_theResult____h343302[50] && - !_theResult____h343302[49] && - !_theResult____h343302[48] && - !_theResult____h343302[47] && - !_theResult____h343302[46] && - !_theResult____h343302[45] && - !_theResult____h343302[44] && - !_theResult____h343302[43] && - !_theResult____h343302[42] && - !_theResult____h343302[41] && - !_theResult____h343302[40] && - !_theResult____h343302[39] && - !_theResult____h343302[38] && - !_theResult____h343302[37] && - !_theResult____h343302[36] && - !_theResult____h343302[35] && - !_theResult____h343302[34] && - !_theResult____h343302[33] && - !_theResult____h343302[32] && - !_theResult____h343302[31] && - !_theResult____h343302[30] && - !_theResult____h343302[29] && - !_theResult____h343302[28] && - !_theResult____h343302[27] && - !_theResult____h343302[26] && - !_theResult____h343302[25] && - !_theResult____h343302[24] && - !_theResult____h343302[23] && - !_theResult____h343302[22] && - !_theResult____h343302[21] && - !_theResult____h343302[20] && - !_theResult____h343302[19] && - !_theResult____h343302[18] && - !_theResult____h343302[17] && - !_theResult____h343302[16] && - !_theResult____h343302[15] && - !_theResult____h343302[14] && - !_theResult____h343302[13] && - !_theResult____h343302[12] && - !_theResult____h343302[11] && - !_theResult____h343302[10] && - !_theResult____h343302[9] && - !_theResult____h343302[8] && - !_theResult____h343302[7] && - !_theResult____h343302[6] && - !_theResult____h343302[5] && - !_theResult____h343302[4] && - !_theResult____h343302[3] && - !_theResult____h343302[2] && - !_theResult____h343302[1] && - !_theResult____h343302[0] || + assign _theResult___fst_exp__h351482 = + (!_theResult____h343300[56] && !_theResult____h343300[55] && + !_theResult____h343300[54] && + !_theResult____h343300[53] && + !_theResult____h343300[52] && + !_theResult____h343300[51] && + !_theResult____h343300[50] && + !_theResult____h343300[49] && + !_theResult____h343300[48] && + !_theResult____h343300[47] && + !_theResult____h343300[46] && + !_theResult____h343300[45] && + !_theResult____h343300[44] && + !_theResult____h343300[43] && + !_theResult____h343300[42] && + !_theResult____h343300[41] && + !_theResult____h343300[40] && + !_theResult____h343300[39] && + !_theResult____h343300[38] && + !_theResult____h343300[37] && + !_theResult____h343300[36] && + !_theResult____h343300[35] && + !_theResult____h343300[34] && + !_theResult____h343300[33] && + !_theResult____h343300[32] && + !_theResult____h343300[31] && + !_theResult____h343300[30] && + !_theResult____h343300[29] && + !_theResult____h343300[28] && + !_theResult____h343300[27] && + !_theResult____h343300[26] && + !_theResult____h343300[25] && + !_theResult____h343300[24] && + !_theResult____h343300[23] && + !_theResult____h343300[22] && + !_theResult____h343300[21] && + !_theResult____h343300[20] && + !_theResult____h343300[19] && + !_theResult____h343300[18] && + !_theResult____h343300[17] && + !_theResult____h343300[16] && + !_theResult____h343300[15] && + !_theResult____h343300[14] && + !_theResult____h343300[13] && + !_theResult____h343300[12] && + !_theResult____h343300[11] && + !_theResult____h343300[10] && + !_theResult____h343300[9] && + !_theResult____h343300[8] && + !_theResult____h343300[7] && + !_theResult____h343300[6] && + !_theResult____h343300[5] && + !_theResult____h343300[4] && + !_theResult____h343300[3] && + !_theResult____h343300[2] && + !_theResult____h343300[1] && + !_theResult____h343300[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ? 8'd0 : - _theResult___fst_exp__h351478 ; - assign _theResult___fst_exp__h351487 = - (!_theResult____h343302[56] && _theResult____h343302[55]) ? + _theResult___fst_exp__h351476 ; + assign _theResult___fst_exp__h351485 = + (!_theResult____h343300[56] && _theResult____h343300[55]) ? 8'd1 : - _theResult___fst_exp__h351484 ; - assign _theResult___fst_exp__h352010 = - (_theResult___fst_exp__h351413 == 8'd255) ? - _theResult___fst_exp__h351413 : - _theResult___fst_exp__h352007 ; - assign _theResult___fst_exp__h360060 = + _theResult___fst_exp__h351482 ; + assign _theResult___fst_exp__h352008 = + (_theResult___fst_exp__h351411 == 8'd255) ? + _theResult___fst_exp__h351411 : + _theResult___fst_exp__h352005 ; + assign _theResult___fst_exp__h360058 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h360066 = + assign _theResult___fst_exp__h360064 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ? 8'd0 : - _theResult___fst_exp__h360060 ; - assign _theResult___fst_exp__h360069 = + _theResult___fst_exp__h360058 ; + assign _theResult___fst_exp__h360067 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h360066 : + _theResult___fst_exp__h360064 : 8'd129 ; - assign _theResult___fst_exp__h360592 = - (_theResult___fst_exp__h360069 == 8'd255) ? - _theResult___fst_exp__h360069 : - _theResult___fst_exp__h360589 ; - assign _theResult___fst_exp__h369179 = - _theResult____h360941[56] ? + assign _theResult___fst_exp__h360590 = + (_theResult___fst_exp__h360067 == 8'd255) ? + _theResult___fst_exp__h360067 : + _theResult___fst_exp__h360587 ; + assign _theResult___fst_exp__h369177 = + _theResult____h360939[56] ? 8'd2 : - _theResult___fst_exp__h369253 ; - assign _theResult___fst_exp__h369244 = + _theResult___fst_exp__h369251 ; + assign _theResult___fst_exp__h369242 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ; - assign _theResult___fst_exp__h369250 = - (!_theResult____h360941[56] && !_theResult____h360941[55] && - !_theResult____h360941[54] && - !_theResult____h360941[53] && - !_theResult____h360941[52] && - !_theResult____h360941[51] && - !_theResult____h360941[50] && - !_theResult____h360941[49] && - !_theResult____h360941[48] && - !_theResult____h360941[47] && - !_theResult____h360941[46] && - !_theResult____h360941[45] && - !_theResult____h360941[44] && - !_theResult____h360941[43] && - !_theResult____h360941[42] && - !_theResult____h360941[41] && - !_theResult____h360941[40] && - !_theResult____h360941[39] && - !_theResult____h360941[38] && - !_theResult____h360941[37] && - !_theResult____h360941[36] && - !_theResult____h360941[35] && - !_theResult____h360941[34] && - !_theResult____h360941[33] && - !_theResult____h360941[32] && - !_theResult____h360941[31] && - !_theResult____h360941[30] && - !_theResult____h360941[29] && - !_theResult____h360941[28] && - !_theResult____h360941[27] && - !_theResult____h360941[26] && - !_theResult____h360941[25] && - !_theResult____h360941[24] && - !_theResult____h360941[23] && - !_theResult____h360941[22] && - !_theResult____h360941[21] && - !_theResult____h360941[20] && - !_theResult____h360941[19] && - !_theResult____h360941[18] && - !_theResult____h360941[17] && - !_theResult____h360941[16] && - !_theResult____h360941[15] && - !_theResult____h360941[14] && - !_theResult____h360941[13] && - !_theResult____h360941[12] && - !_theResult____h360941[11] && - !_theResult____h360941[10] && - !_theResult____h360941[9] && - !_theResult____h360941[8] && - !_theResult____h360941[7] && - !_theResult____h360941[6] && - !_theResult____h360941[5] && - !_theResult____h360941[4] && - !_theResult____h360941[3] && - !_theResult____h360941[2] && - !_theResult____h360941[1] && - !_theResult____h360941[0] || + assign _theResult___fst_exp__h369248 = + (!_theResult____h360939[56] && !_theResult____h360939[55] && + !_theResult____h360939[54] && + !_theResult____h360939[53] && + !_theResult____h360939[52] && + !_theResult____h360939[51] && + !_theResult____h360939[50] && + !_theResult____h360939[49] && + !_theResult____h360939[48] && + !_theResult____h360939[47] && + !_theResult____h360939[46] && + !_theResult____h360939[45] && + !_theResult____h360939[44] && + !_theResult____h360939[43] && + !_theResult____h360939[42] && + !_theResult____h360939[41] && + !_theResult____h360939[40] && + !_theResult____h360939[39] && + !_theResult____h360939[38] && + !_theResult____h360939[37] && + !_theResult____h360939[36] && + !_theResult____h360939[35] && + !_theResult____h360939[34] && + !_theResult____h360939[33] && + !_theResult____h360939[32] && + !_theResult____h360939[31] && + !_theResult____h360939[30] && + !_theResult____h360939[29] && + !_theResult____h360939[28] && + !_theResult____h360939[27] && + !_theResult____h360939[26] && + !_theResult____h360939[25] && + !_theResult____h360939[24] && + !_theResult____h360939[23] && + !_theResult____h360939[22] && + !_theResult____h360939[21] && + !_theResult____h360939[20] && + !_theResult____h360939[19] && + !_theResult____h360939[18] && + !_theResult____h360939[17] && + !_theResult____h360939[16] && + !_theResult____h360939[15] && + !_theResult____h360939[14] && + !_theResult____h360939[13] && + !_theResult____h360939[12] && + !_theResult____h360939[11] && + !_theResult____h360939[10] && + !_theResult____h360939[9] && + !_theResult____h360939[8] && + !_theResult____h360939[7] && + !_theResult____h360939[6] && + !_theResult____h360939[5] && + !_theResult____h360939[4] && + !_theResult____h360939[3] && + !_theResult____h360939[2] && + !_theResult____h360939[1] && + !_theResult____h360939[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ? 8'd0 : - _theResult___fst_exp__h369244 ; - assign _theResult___fst_exp__h369253 = - (!_theResult____h360941[56] && _theResult____h360941[55]) ? + _theResult___fst_exp__h369242 ; + assign _theResult___fst_exp__h369251 = + (!_theResult____h360939[56] && _theResult____h360939[55]) ? 8'd1 : - _theResult___fst_exp__h369250 ; - assign _theResult___fst_exp__h369776 = - (_theResult___fst_exp__h369179 == 8'd255) ? - _theResult___fst_exp__h369179 : - _theResult___fst_exp__h369773 ; - assign _theResult___fst_exp__h377816 = + _theResult___fst_exp__h369248 ; + assign _theResult___fst_exp__h369774 = + (_theResult___fst_exp__h369177 == 8'd255) ? + _theResult___fst_exp__h369177 : + _theResult___fst_exp__h369771 ; + assign _theResult___fst_exp__h377814 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ; - assign _theResult___fst_exp__h377855 = + assign _theResult___fst_exp__h377853 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h377861 = + assign _theResult___fst_exp__h377859 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ? 8'd0 : - _theResult___fst_exp__h377855 ; - assign _theResult___fst_exp__h377864 = + _theResult___fst_exp__h377853 ; + assign _theResult___fst_exp__h377862 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h377861 : - _theResult___fst_exp__h377816 ; - assign _theResult___fst_exp__h378412 = - (_theResult___fst_exp__h377864 == 8'd255) ? - _theResult___fst_exp__h377864 : - _theResult___fst_exp__h378409 ; - assign _theResult___fst_exp__h378421 = + _theResult___fst_exp__h377859 : + _theResult___fst_exp__h377814 ; + assign _theResult___fst_exp__h378410 = + (_theResult___fst_exp__h377862 == 8'd255) ? + _theResult___fst_exp__h377862 : + _theResult___fst_exp__h378407 ; + assign _theResult___fst_exp__h378419 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_exp__h360595 : - _theResult___fst_exp__h343284) : + _theResult___snd_fst_exp__h360593 : + _theResult___fst_exp__h343282) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_exp__h378415 : - _theResult___fst_exp__h343284) ; - assign _theResult___fst_exp__h378424 = + _theResult___snd_fst_exp__h378413 : + _theResult___fst_exp__h343282) ; + assign _theResult___fst_exp__h378422 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h378421 ; - assign _theResult___fst_exp__h397103 = - _theResult____h388994[56] ? + _theResult___fst_exp__h378419 ; + assign _theResult___fst_exp__h397101 = + _theResult____h388992[56] ? 8'd2 : - _theResult___fst_exp__h397177 ; - assign _theResult___fst_exp__h397168 = + _theResult___fst_exp__h397175 ; + assign _theResult___fst_exp__h397166 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ; - assign _theResult___fst_exp__h397174 = - (!_theResult____h388994[56] && !_theResult____h388994[55] && - !_theResult____h388994[54] && - !_theResult____h388994[53] && - !_theResult____h388994[52] && - !_theResult____h388994[51] && - !_theResult____h388994[50] && - !_theResult____h388994[49] && - !_theResult____h388994[48] && - !_theResult____h388994[47] && - !_theResult____h388994[46] && - !_theResult____h388994[45] && - !_theResult____h388994[44] && - !_theResult____h388994[43] && - !_theResult____h388994[42] && - !_theResult____h388994[41] && - !_theResult____h388994[40] && - !_theResult____h388994[39] && - !_theResult____h388994[38] && - !_theResult____h388994[37] && - !_theResult____h388994[36] && - !_theResult____h388994[35] && - !_theResult____h388994[34] && - !_theResult____h388994[33] && - !_theResult____h388994[32] && - !_theResult____h388994[31] && - !_theResult____h388994[30] && - !_theResult____h388994[29] && - !_theResult____h388994[28] && - !_theResult____h388994[27] && - !_theResult____h388994[26] && - !_theResult____h388994[25] && - !_theResult____h388994[24] && - !_theResult____h388994[23] && - !_theResult____h388994[22] && - !_theResult____h388994[21] && - !_theResult____h388994[20] && - !_theResult____h388994[19] && - !_theResult____h388994[18] && - !_theResult____h388994[17] && - !_theResult____h388994[16] && - !_theResult____h388994[15] && - !_theResult____h388994[14] && - !_theResult____h388994[13] && - !_theResult____h388994[12] && - !_theResult____h388994[11] && - !_theResult____h388994[10] && - !_theResult____h388994[9] && - !_theResult____h388994[8] && - !_theResult____h388994[7] && - !_theResult____h388994[6] && - !_theResult____h388994[5] && - !_theResult____h388994[4] && - !_theResult____h388994[3] && - !_theResult____h388994[2] && - !_theResult____h388994[1] && - !_theResult____h388994[0] || + assign _theResult___fst_exp__h397172 = + (!_theResult____h388992[56] && !_theResult____h388992[55] && + !_theResult____h388992[54] && + !_theResult____h388992[53] && + !_theResult____h388992[52] && + !_theResult____h388992[51] && + !_theResult____h388992[50] && + !_theResult____h388992[49] && + !_theResult____h388992[48] && + !_theResult____h388992[47] && + !_theResult____h388992[46] && + !_theResult____h388992[45] && + !_theResult____h388992[44] && + !_theResult____h388992[43] && + !_theResult____h388992[42] && + !_theResult____h388992[41] && + !_theResult____h388992[40] && + !_theResult____h388992[39] && + !_theResult____h388992[38] && + !_theResult____h388992[37] && + !_theResult____h388992[36] && + !_theResult____h388992[35] && + !_theResult____h388992[34] && + !_theResult____h388992[33] && + !_theResult____h388992[32] && + !_theResult____h388992[31] && + !_theResult____h388992[30] && + !_theResult____h388992[29] && + !_theResult____h388992[28] && + !_theResult____h388992[27] && + !_theResult____h388992[26] && + !_theResult____h388992[25] && + !_theResult____h388992[24] && + !_theResult____h388992[23] && + !_theResult____h388992[22] && + !_theResult____h388992[21] && + !_theResult____h388992[20] && + !_theResult____h388992[19] && + !_theResult____h388992[18] && + !_theResult____h388992[17] && + !_theResult____h388992[16] && + !_theResult____h388992[15] && + !_theResult____h388992[14] && + !_theResult____h388992[13] && + !_theResult____h388992[12] && + !_theResult____h388992[11] && + !_theResult____h388992[10] && + !_theResult____h388992[9] && + !_theResult____h388992[8] && + !_theResult____h388992[7] && + !_theResult____h388992[6] && + !_theResult____h388992[5] && + !_theResult____h388992[4] && + !_theResult____h388992[3] && + !_theResult____h388992[2] && + !_theResult____h388992[1] && + !_theResult____h388992[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ? 8'd0 : - _theResult___fst_exp__h397168 ; - assign _theResult___fst_exp__h397177 = - (!_theResult____h388994[56] && _theResult____h388994[55]) ? + _theResult___fst_exp__h397166 ; + assign _theResult___fst_exp__h397175 = + (!_theResult____h388992[56] && _theResult____h388992[55]) ? 8'd1 : - _theResult___fst_exp__h397174 ; - assign _theResult___fst_exp__h397700 = - (_theResult___fst_exp__h397103 == 8'd255) ? - _theResult___fst_exp__h397103 : - _theResult___fst_exp__h397697 ; - assign _theResult___fst_exp__h405750 = + _theResult___fst_exp__h397172 ; + assign _theResult___fst_exp__h397698 = + (_theResult___fst_exp__h397101 == 8'd255) ? + _theResult___fst_exp__h397101 : + _theResult___fst_exp__h397695 ; + assign _theResult___fst_exp__h405748 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h405756 = + assign _theResult___fst_exp__h405754 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ? 8'd0 : - _theResult___fst_exp__h405750 ; - assign _theResult___fst_exp__h405759 = + _theResult___fst_exp__h405748 ; + assign _theResult___fst_exp__h405757 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h405756 : + _theResult___fst_exp__h405754 : 8'd129 ; - assign _theResult___fst_exp__h406282 = - (_theResult___fst_exp__h405759 == 8'd255) ? - _theResult___fst_exp__h405759 : - _theResult___fst_exp__h406279 ; - assign _theResult___fst_exp__h414869 = - _theResult____h406631[56] ? + assign _theResult___fst_exp__h406280 = + (_theResult___fst_exp__h405757 == 8'd255) ? + _theResult___fst_exp__h405757 : + _theResult___fst_exp__h406277 ; + assign _theResult___fst_exp__h414867 = + _theResult____h406629[56] ? 8'd2 : - _theResult___fst_exp__h414943 ; - assign _theResult___fst_exp__h414934 = + _theResult___fst_exp__h414941 ; + assign _theResult___fst_exp__h414932 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ; - assign _theResult___fst_exp__h414940 = - (!_theResult____h406631[56] && !_theResult____h406631[55] && - !_theResult____h406631[54] && - !_theResult____h406631[53] && - !_theResult____h406631[52] && - !_theResult____h406631[51] && - !_theResult____h406631[50] && - !_theResult____h406631[49] && - !_theResult____h406631[48] && - !_theResult____h406631[47] && - !_theResult____h406631[46] && - !_theResult____h406631[45] && - !_theResult____h406631[44] && - !_theResult____h406631[43] && - !_theResult____h406631[42] && - !_theResult____h406631[41] && - !_theResult____h406631[40] && - !_theResult____h406631[39] && - !_theResult____h406631[38] && - !_theResult____h406631[37] && - !_theResult____h406631[36] && - !_theResult____h406631[35] && - !_theResult____h406631[34] && - !_theResult____h406631[33] && - !_theResult____h406631[32] && - !_theResult____h406631[31] && - !_theResult____h406631[30] && - !_theResult____h406631[29] && - !_theResult____h406631[28] && - !_theResult____h406631[27] && - !_theResult____h406631[26] && - !_theResult____h406631[25] && - !_theResult____h406631[24] && - !_theResult____h406631[23] && - !_theResult____h406631[22] && - !_theResult____h406631[21] && - !_theResult____h406631[20] && - !_theResult____h406631[19] && - !_theResult____h406631[18] && - !_theResult____h406631[17] && - !_theResult____h406631[16] && - !_theResult____h406631[15] && - !_theResult____h406631[14] && - !_theResult____h406631[13] && - !_theResult____h406631[12] && - !_theResult____h406631[11] && - !_theResult____h406631[10] && - !_theResult____h406631[9] && - !_theResult____h406631[8] && - !_theResult____h406631[7] && - !_theResult____h406631[6] && - !_theResult____h406631[5] && - !_theResult____h406631[4] && - !_theResult____h406631[3] && - !_theResult____h406631[2] && - !_theResult____h406631[1] && - !_theResult____h406631[0] || + assign _theResult___fst_exp__h414938 = + (!_theResult____h406629[56] && !_theResult____h406629[55] && + !_theResult____h406629[54] && + !_theResult____h406629[53] && + !_theResult____h406629[52] && + !_theResult____h406629[51] && + !_theResult____h406629[50] && + !_theResult____h406629[49] && + !_theResult____h406629[48] && + !_theResult____h406629[47] && + !_theResult____h406629[46] && + !_theResult____h406629[45] && + !_theResult____h406629[44] && + !_theResult____h406629[43] && + !_theResult____h406629[42] && + !_theResult____h406629[41] && + !_theResult____h406629[40] && + !_theResult____h406629[39] && + !_theResult____h406629[38] && + !_theResult____h406629[37] && + !_theResult____h406629[36] && + !_theResult____h406629[35] && + !_theResult____h406629[34] && + !_theResult____h406629[33] && + !_theResult____h406629[32] && + !_theResult____h406629[31] && + !_theResult____h406629[30] && + !_theResult____h406629[29] && + !_theResult____h406629[28] && + !_theResult____h406629[27] && + !_theResult____h406629[26] && + !_theResult____h406629[25] && + !_theResult____h406629[24] && + !_theResult____h406629[23] && + !_theResult____h406629[22] && + !_theResult____h406629[21] && + !_theResult____h406629[20] && + !_theResult____h406629[19] && + !_theResult____h406629[18] && + !_theResult____h406629[17] && + !_theResult____h406629[16] && + !_theResult____h406629[15] && + !_theResult____h406629[14] && + !_theResult____h406629[13] && + !_theResult____h406629[12] && + !_theResult____h406629[11] && + !_theResult____h406629[10] && + !_theResult____h406629[9] && + !_theResult____h406629[8] && + !_theResult____h406629[7] && + !_theResult____h406629[6] && + !_theResult____h406629[5] && + !_theResult____h406629[4] && + !_theResult____h406629[3] && + !_theResult____h406629[2] && + !_theResult____h406629[1] && + !_theResult____h406629[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ? 8'd0 : - _theResult___fst_exp__h414934 ; - assign _theResult___fst_exp__h414943 = - (!_theResult____h406631[56] && _theResult____h406631[55]) ? + _theResult___fst_exp__h414932 ; + assign _theResult___fst_exp__h414941 = + (!_theResult____h406629[56] && _theResult____h406629[55]) ? 8'd1 : - _theResult___fst_exp__h414940 ; - assign _theResult___fst_exp__h415466 = - (_theResult___fst_exp__h414869 == 8'd255) ? - _theResult___fst_exp__h414869 : - _theResult___fst_exp__h415463 ; - assign _theResult___fst_exp__h423506 = + _theResult___fst_exp__h414938 ; + assign _theResult___fst_exp__h415464 = + (_theResult___fst_exp__h414867 == 8'd255) ? + _theResult___fst_exp__h414867 : + _theResult___fst_exp__h415461 ; + assign _theResult___fst_exp__h423504 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ; - assign _theResult___fst_exp__h423545 = + assign _theResult___fst_exp__h423543 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h423551 = + assign _theResult___fst_exp__h423549 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ? 8'd0 : - _theResult___fst_exp__h423545 ; - assign _theResult___fst_exp__h423554 = + _theResult___fst_exp__h423543 ; + assign _theResult___fst_exp__h423552 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h423551 : - _theResult___fst_exp__h423506 ; - assign _theResult___fst_exp__h424102 = - (_theResult___fst_exp__h423554 == 8'd255) ? - _theResult___fst_exp__h423554 : - _theResult___fst_exp__h424099 ; - assign _theResult___fst_exp__h424111 = + _theResult___fst_exp__h423549 : + _theResult___fst_exp__h423504 ; + assign _theResult___fst_exp__h424100 = + (_theResult___fst_exp__h423552 == 8'd255) ? + _theResult___fst_exp__h423552 : + _theResult___fst_exp__h424097 ; + assign _theResult___fst_exp__h424109 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_exp__h406285 : - _theResult___fst_exp__h388976) : + _theResult___snd_fst_exp__h406283 : + _theResult___fst_exp__h388974) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_exp__h424105 : - _theResult___fst_exp__h388976) ; - assign _theResult___fst_exp__h424114 = + _theResult___snd_fst_exp__h424103 : + _theResult___fst_exp__h388974) ; + assign _theResult___fst_exp__h424112 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h424111 ; - assign _theResult___fst_exp__h442791 = - _theResult____h434682[56] ? + _theResult___fst_exp__h424109 ; + assign _theResult___fst_exp__h442789 = + _theResult____h434680[56] ? 8'd2 : - _theResult___fst_exp__h442865 ; - assign _theResult___fst_exp__h442856 = + _theResult___fst_exp__h442863 ; + assign _theResult___fst_exp__h442854 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ; - assign _theResult___fst_exp__h442862 = - (!_theResult____h434682[56] && !_theResult____h434682[55] && - !_theResult____h434682[54] && - !_theResult____h434682[53] && - !_theResult____h434682[52] && - !_theResult____h434682[51] && - !_theResult____h434682[50] && - !_theResult____h434682[49] && - !_theResult____h434682[48] && - !_theResult____h434682[47] && - !_theResult____h434682[46] && - !_theResult____h434682[45] && - !_theResult____h434682[44] && - !_theResult____h434682[43] && - !_theResult____h434682[42] && - !_theResult____h434682[41] && - !_theResult____h434682[40] && - !_theResult____h434682[39] && - !_theResult____h434682[38] && - !_theResult____h434682[37] && - !_theResult____h434682[36] && - !_theResult____h434682[35] && - !_theResult____h434682[34] && - !_theResult____h434682[33] && - !_theResult____h434682[32] && - !_theResult____h434682[31] && - !_theResult____h434682[30] && - !_theResult____h434682[29] && - !_theResult____h434682[28] && - !_theResult____h434682[27] && - !_theResult____h434682[26] && - !_theResult____h434682[25] && - !_theResult____h434682[24] && - !_theResult____h434682[23] && - !_theResult____h434682[22] && - !_theResult____h434682[21] && - !_theResult____h434682[20] && - !_theResult____h434682[19] && - !_theResult____h434682[18] && - !_theResult____h434682[17] && - !_theResult____h434682[16] && - !_theResult____h434682[15] && - !_theResult____h434682[14] && - !_theResult____h434682[13] && - !_theResult____h434682[12] && - !_theResult____h434682[11] && - !_theResult____h434682[10] && - !_theResult____h434682[9] && - !_theResult____h434682[8] && - !_theResult____h434682[7] && - !_theResult____h434682[6] && - !_theResult____h434682[5] && - !_theResult____h434682[4] && - !_theResult____h434682[3] && - !_theResult____h434682[2] && - !_theResult____h434682[1] && - !_theResult____h434682[0] || + assign _theResult___fst_exp__h442860 = + (!_theResult____h434680[56] && !_theResult____h434680[55] && + !_theResult____h434680[54] && + !_theResult____h434680[53] && + !_theResult____h434680[52] && + !_theResult____h434680[51] && + !_theResult____h434680[50] && + !_theResult____h434680[49] && + !_theResult____h434680[48] && + !_theResult____h434680[47] && + !_theResult____h434680[46] && + !_theResult____h434680[45] && + !_theResult____h434680[44] && + !_theResult____h434680[43] && + !_theResult____h434680[42] && + !_theResult____h434680[41] && + !_theResult____h434680[40] && + !_theResult____h434680[39] && + !_theResult____h434680[38] && + !_theResult____h434680[37] && + !_theResult____h434680[36] && + !_theResult____h434680[35] && + !_theResult____h434680[34] && + !_theResult____h434680[33] && + !_theResult____h434680[32] && + !_theResult____h434680[31] && + !_theResult____h434680[30] && + !_theResult____h434680[29] && + !_theResult____h434680[28] && + !_theResult____h434680[27] && + !_theResult____h434680[26] && + !_theResult____h434680[25] && + !_theResult____h434680[24] && + !_theResult____h434680[23] && + !_theResult____h434680[22] && + !_theResult____h434680[21] && + !_theResult____h434680[20] && + !_theResult____h434680[19] && + !_theResult____h434680[18] && + !_theResult____h434680[17] && + !_theResult____h434680[16] && + !_theResult____h434680[15] && + !_theResult____h434680[14] && + !_theResult____h434680[13] && + !_theResult____h434680[12] && + !_theResult____h434680[11] && + !_theResult____h434680[10] && + !_theResult____h434680[9] && + !_theResult____h434680[8] && + !_theResult____h434680[7] && + !_theResult____h434680[6] && + !_theResult____h434680[5] && + !_theResult____h434680[4] && + !_theResult____h434680[3] && + !_theResult____h434680[2] && + !_theResult____h434680[1] && + !_theResult____h434680[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ? 8'd0 : - _theResult___fst_exp__h442856 ; - assign _theResult___fst_exp__h442865 = - (!_theResult____h434682[56] && _theResult____h434682[55]) ? + _theResult___fst_exp__h442854 ; + assign _theResult___fst_exp__h442863 = + (!_theResult____h434680[56] && _theResult____h434680[55]) ? 8'd1 : - _theResult___fst_exp__h442862 ; - assign _theResult___fst_exp__h443388 = - (_theResult___fst_exp__h442791 == 8'd255) ? - _theResult___fst_exp__h442791 : - _theResult___fst_exp__h443385 ; - assign _theResult___fst_exp__h451438 = + _theResult___fst_exp__h442860 ; + assign _theResult___fst_exp__h443386 = + (_theResult___fst_exp__h442789 == 8'd255) ? + _theResult___fst_exp__h442789 : + _theResult___fst_exp__h443383 ; + assign _theResult___fst_exp__h451436 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h451444 = + assign _theResult___fst_exp__h451442 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ? 8'd0 : - _theResult___fst_exp__h451438 ; - assign _theResult___fst_exp__h451447 = + _theResult___fst_exp__h451436 ; + assign _theResult___fst_exp__h451445 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h451444 : + _theResult___fst_exp__h451442 : 8'd129 ; - assign _theResult___fst_exp__h451970 = - (_theResult___fst_exp__h451447 == 8'd255) ? - _theResult___fst_exp__h451447 : - _theResult___fst_exp__h451967 ; - assign _theResult___fst_exp__h460557 = - _theResult____h452319[56] ? + assign _theResult___fst_exp__h451968 = + (_theResult___fst_exp__h451445 == 8'd255) ? + _theResult___fst_exp__h451445 : + _theResult___fst_exp__h451965 ; + assign _theResult___fst_exp__h460555 = + _theResult____h452317[56] ? 8'd2 : - _theResult___fst_exp__h460631 ; - assign _theResult___fst_exp__h460622 = + _theResult___fst_exp__h460629 ; + assign _theResult___fst_exp__h460620 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ; - assign _theResult___fst_exp__h460628 = - (!_theResult____h452319[56] && !_theResult____h452319[55] && - !_theResult____h452319[54] && - !_theResult____h452319[53] && - !_theResult____h452319[52] && - !_theResult____h452319[51] && - !_theResult____h452319[50] && - !_theResult____h452319[49] && - !_theResult____h452319[48] && - !_theResult____h452319[47] && - !_theResult____h452319[46] && - !_theResult____h452319[45] && - !_theResult____h452319[44] && - !_theResult____h452319[43] && - !_theResult____h452319[42] && - !_theResult____h452319[41] && - !_theResult____h452319[40] && - !_theResult____h452319[39] && - !_theResult____h452319[38] && - !_theResult____h452319[37] && - !_theResult____h452319[36] && - !_theResult____h452319[35] && - !_theResult____h452319[34] && - !_theResult____h452319[33] && - !_theResult____h452319[32] && - !_theResult____h452319[31] && - !_theResult____h452319[30] && - !_theResult____h452319[29] && - !_theResult____h452319[28] && - !_theResult____h452319[27] && - !_theResult____h452319[26] && - !_theResult____h452319[25] && - !_theResult____h452319[24] && - !_theResult____h452319[23] && - !_theResult____h452319[22] && - !_theResult____h452319[21] && - !_theResult____h452319[20] && - !_theResult____h452319[19] && - !_theResult____h452319[18] && - !_theResult____h452319[17] && - !_theResult____h452319[16] && - !_theResult____h452319[15] && - !_theResult____h452319[14] && - !_theResult____h452319[13] && - !_theResult____h452319[12] && - !_theResult____h452319[11] && - !_theResult____h452319[10] && - !_theResult____h452319[9] && - !_theResult____h452319[8] && - !_theResult____h452319[7] && - !_theResult____h452319[6] && - !_theResult____h452319[5] && - !_theResult____h452319[4] && - !_theResult____h452319[3] && - !_theResult____h452319[2] && - !_theResult____h452319[1] && - !_theResult____h452319[0] || + assign _theResult___fst_exp__h460626 = + (!_theResult____h452317[56] && !_theResult____h452317[55] && + !_theResult____h452317[54] && + !_theResult____h452317[53] && + !_theResult____h452317[52] && + !_theResult____h452317[51] && + !_theResult____h452317[50] && + !_theResult____h452317[49] && + !_theResult____h452317[48] && + !_theResult____h452317[47] && + !_theResult____h452317[46] && + !_theResult____h452317[45] && + !_theResult____h452317[44] && + !_theResult____h452317[43] && + !_theResult____h452317[42] && + !_theResult____h452317[41] && + !_theResult____h452317[40] && + !_theResult____h452317[39] && + !_theResult____h452317[38] && + !_theResult____h452317[37] && + !_theResult____h452317[36] && + !_theResult____h452317[35] && + !_theResult____h452317[34] && + !_theResult____h452317[33] && + !_theResult____h452317[32] && + !_theResult____h452317[31] && + !_theResult____h452317[30] && + !_theResult____h452317[29] && + !_theResult____h452317[28] && + !_theResult____h452317[27] && + !_theResult____h452317[26] && + !_theResult____h452317[25] && + !_theResult____h452317[24] && + !_theResult____h452317[23] && + !_theResult____h452317[22] && + !_theResult____h452317[21] && + !_theResult____h452317[20] && + !_theResult____h452317[19] && + !_theResult____h452317[18] && + !_theResult____h452317[17] && + !_theResult____h452317[16] && + !_theResult____h452317[15] && + !_theResult____h452317[14] && + !_theResult____h452317[13] && + !_theResult____h452317[12] && + !_theResult____h452317[11] && + !_theResult____h452317[10] && + !_theResult____h452317[9] && + !_theResult____h452317[8] && + !_theResult____h452317[7] && + !_theResult____h452317[6] && + !_theResult____h452317[5] && + !_theResult____h452317[4] && + !_theResult____h452317[3] && + !_theResult____h452317[2] && + !_theResult____h452317[1] && + !_theResult____h452317[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ? 8'd0 : - _theResult___fst_exp__h460622 ; - assign _theResult___fst_exp__h460631 = - (!_theResult____h452319[56] && _theResult____h452319[55]) ? + _theResult___fst_exp__h460620 ; + assign _theResult___fst_exp__h460629 = + (!_theResult____h452317[56] && _theResult____h452317[55]) ? 8'd1 : - _theResult___fst_exp__h460628 ; - assign _theResult___fst_exp__h461154 = - (_theResult___fst_exp__h460557 == 8'd255) ? - _theResult___fst_exp__h460557 : - _theResult___fst_exp__h461151 ; - assign _theResult___fst_exp__h469194 = + _theResult___fst_exp__h460626 ; + assign _theResult___fst_exp__h461152 = + (_theResult___fst_exp__h460555 == 8'd255) ? + _theResult___fst_exp__h460555 : + _theResult___fst_exp__h461149 ; + assign _theResult___fst_exp__h469192 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ; - assign _theResult___fst_exp__h469233 = + assign _theResult___fst_exp__h469231 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h469239 = + assign _theResult___fst_exp__h469237 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ? 8'd0 : - _theResult___fst_exp__h469233 ; - assign _theResult___fst_exp__h469242 = + _theResult___fst_exp__h469231 ; + assign _theResult___fst_exp__h469240 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h469239 : - _theResult___fst_exp__h469194 ; - assign _theResult___fst_exp__h469790 = - (_theResult___fst_exp__h469242 == 8'd255) ? - _theResult___fst_exp__h469242 : - _theResult___fst_exp__h469787 ; - assign _theResult___fst_exp__h469799 = + _theResult___fst_exp__h469237 : + _theResult___fst_exp__h469192 ; + assign _theResult___fst_exp__h469788 = + (_theResult___fst_exp__h469240 == 8'd255) ? + _theResult___fst_exp__h469240 : + _theResult___fst_exp__h469785 ; + assign _theResult___fst_exp__h469797 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_exp__h451973 : - _theResult___fst_exp__h434664) : + _theResult___snd_fst_exp__h451971 : + _theResult___fst_exp__h434662) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_exp__h469793 : - _theResult___fst_exp__h434664) ; - assign _theResult___fst_exp__h469802 = + _theResult___snd_fst_exp__h469791 : + _theResult___fst_exp__h434662) ; + assign _theResult___fst_exp__h469800 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h469799 ; - assign _theResult___fst_exp__h483603 = + _theResult___fst_exp__h469797 ; + assign _theResult___fst_exp__h483601 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ; - assign _theResult___fst_exp__h498667 = + assign _theResult___fst_exp__h498665 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h498673 = + assign _theResult___fst_exp__h498671 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577) ? 11'd0 : - _theResult___fst_exp__h498667 ; - assign _theResult___fst_exp__h498676 = + _theResult___fst_exp__h498665 ; + assign _theResult___fst_exp__h498674 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h498673 : + _theResult___fst_exp__h498671 : 11'd897 ; - assign _theResult___fst_exp__h499431 = + assign _theResult___fst_exp__h499429 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 : + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 ; - assign _theResult___fst_exp__h499434 = - (_theResult___fst_exp__h498676 == 11'd2047) ? - _theResult___fst_exp__h498676 : - _theResult___fst_exp__h499431 ; - assign _theResult___fst_exp__h508253 = - _theResult____h500017[56] ? + assign _theResult___fst_exp__h499432 = + (_theResult___fst_exp__h498674 == 11'd2047) ? + _theResult___fst_exp__h498674 : + _theResult___fst_exp__h499429 ; + assign _theResult___fst_exp__h508251 = + _theResult____h500015[56] ? 11'd2 : - _theResult___fst_exp__h508327 ; - assign _theResult___fst_exp__h508318 = + _theResult___fst_exp__h508325 ; + assign _theResult___fst_exp__h508316 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ; - assign _theResult___fst_exp__h508324 = - (!_theResult____h500017[56] && !_theResult____h500017[55] && - !_theResult____h500017[54] && - !_theResult____h500017[53] && - !_theResult____h500017[52] && - !_theResult____h500017[51] && - !_theResult____h500017[50] && - !_theResult____h500017[49] && - !_theResult____h500017[48] && - !_theResult____h500017[47] && - !_theResult____h500017[46] && - !_theResult____h500017[45] && - !_theResult____h500017[44] && - !_theResult____h500017[43] && - !_theResult____h500017[42] && - !_theResult____h500017[41] && - !_theResult____h500017[40] && - !_theResult____h500017[39] && - !_theResult____h500017[38] && - !_theResult____h500017[37] && - !_theResult____h500017[36] && - !_theResult____h500017[35] && - !_theResult____h500017[34] && - !_theResult____h500017[33] && - !_theResult____h500017[32] && - !_theResult____h500017[31] && - !_theResult____h500017[30] && - !_theResult____h500017[29] && - !_theResult____h500017[28] && - !_theResult____h500017[27] && - !_theResult____h500017[26] && - !_theResult____h500017[25] && - !_theResult____h500017[24] && - !_theResult____h500017[23] && - !_theResult____h500017[22] && - !_theResult____h500017[21] && - !_theResult____h500017[20] && - !_theResult____h500017[19] && - !_theResult____h500017[18] && - !_theResult____h500017[17] && - !_theResult____h500017[16] && - !_theResult____h500017[15] && - !_theResult____h500017[14] && - !_theResult____h500017[13] && - !_theResult____h500017[12] && - !_theResult____h500017[11] && - !_theResult____h500017[10] && - !_theResult____h500017[9] && - !_theResult____h500017[8] && - !_theResult____h500017[7] && - !_theResult____h500017[6] && - !_theResult____h500017[5] && - !_theResult____h500017[4] && - !_theResult____h500017[3] && - !_theResult____h500017[2] && - !_theResult____h500017[1] && - !_theResult____h500017[0] || + assign _theResult___fst_exp__h508322 = + (!_theResult____h500015[56] && !_theResult____h500015[55] && + !_theResult____h500015[54] && + !_theResult____h500015[53] && + !_theResult____h500015[52] && + !_theResult____h500015[51] && + !_theResult____h500015[50] && + !_theResult____h500015[49] && + !_theResult____h500015[48] && + !_theResult____h500015[47] && + !_theResult____h500015[46] && + !_theResult____h500015[45] && + !_theResult____h500015[44] && + !_theResult____h500015[43] && + !_theResult____h500015[42] && + !_theResult____h500015[41] && + !_theResult____h500015[40] && + !_theResult____h500015[39] && + !_theResult____h500015[38] && + !_theResult____h500015[37] && + !_theResult____h500015[36] && + !_theResult____h500015[35] && + !_theResult____h500015[34] && + !_theResult____h500015[33] && + !_theResult____h500015[32] && + !_theResult____h500015[31] && + !_theResult____h500015[30] && + !_theResult____h500015[29] && + !_theResult____h500015[28] && + !_theResult____h500015[27] && + !_theResult____h500015[26] && + !_theResult____h500015[25] && + !_theResult____h500015[24] && + !_theResult____h500015[23] && + !_theResult____h500015[22] && + !_theResult____h500015[21] && + !_theResult____h500015[20] && + !_theResult____h500015[19] && + !_theResult____h500015[18] && + !_theResult____h500015[17] && + !_theResult____h500015[16] && + !_theResult____h500015[15] && + !_theResult____h500015[14] && + !_theResult____h500015[13] && + !_theResult____h500015[12] && + !_theResult____h500015[11] && + !_theResult____h500015[10] && + !_theResult____h500015[9] && + !_theResult____h500015[8] && + !_theResult____h500015[7] && + !_theResult____h500015[6] && + !_theResult____h500015[5] && + !_theResult____h500015[4] && + !_theResult____h500015[3] && + !_theResult____h500015[2] && + !_theResult____h500015[1] && + !_theResult____h500015[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889) ? 11'd0 : - _theResult___fst_exp__h508318 ; - assign _theResult___fst_exp__h508327 = - (!_theResult____h500017[56] && _theResult____h500017[55]) ? + _theResult___fst_exp__h508316 ; + assign _theResult___fst_exp__h508325 = + (!_theResult____h500015[56] && _theResult____h500015[55]) ? 11'd1 : - _theResult___fst_exp__h508324 ; - assign _theResult___fst_exp__h509082 = + _theResult___fst_exp__h508322 ; + assign _theResult___fst_exp__h509080 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 : + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 ; - assign _theResult___fst_exp__h509085 = - (_theResult___fst_exp__h508253 == 11'd2047) ? - _theResult___fst_exp__h508253 : - _theResult___fst_exp__h509082 ; - assign _theResult___fst_exp__h517038 = + assign _theResult___fst_exp__h509083 = + (_theResult___fst_exp__h508251 == 11'd2047) ? + _theResult___fst_exp__h508251 : + _theResult___fst_exp__h509080 ; + assign _theResult___fst_exp__h517036 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ; - assign _theResult___fst_exp__h517077 = + assign _theResult___fst_exp__h517075 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h517083 = + assign _theResult___fst_exp__h517081 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939) ? 11'd0 : - _theResult___fst_exp__h517077 ; - assign _theResult___fst_exp__h517086 = + _theResult___fst_exp__h517075 ; + assign _theResult___fst_exp__h517084 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h517083 : - _theResult___fst_exp__h517038 ; - assign _theResult___fst_exp__h517866 = + _theResult___fst_exp__h517081 : + _theResult___fst_exp__h517036 ; + assign _theResult___fst_exp__h517864 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 : + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 ; - assign _theResult___fst_exp__h517869 = - (_theResult___fst_exp__h517086 == 11'd2047) ? - _theResult___fst_exp__h517086 : - _theResult___fst_exp__h517866 ; - assign _theResult___fst_exp__h517878 = + assign _theResult___fst_exp__h517867 = + (_theResult___fst_exp__h517084 == 11'd2047) ? + _theResult___fst_exp__h517084 : + _theResult___fst_exp__h517864 ; + assign _theResult___fst_exp__h517876 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_exp__h499437 : - _theResult___fst_exp__h483603) : + _theResult___snd_fst_exp__h499435 : + _theResult___fst_exp__h483601) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_exp__h517872 : - _theResult___fst_exp__h483603) ; - assign _theResult___fst_exp__h517881 = + _theResult___snd_fst_exp__h517870 : + _theResult___fst_exp__h483601) ; + assign _theResult___fst_exp__h517879 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h517878 ; - assign _theResult___fst_exp__h522404 = + _theResult___fst_exp__h517876 ; + assign _theResult___fst_exp__h522402 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_exp__h537468 = + assign _theResult___fst_exp__h537466 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h537474 = + assign _theResult___fst_exp__h537472 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065) ? 11'd0 : - _theResult___fst_exp__h537468 ; - assign _theResult___fst_exp__h537477 = + _theResult___fst_exp__h537466 ; + assign _theResult___fst_exp__h537475 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h537474 : + _theResult___fst_exp__h537472 : 11'd897 ; - assign _theResult___fst_exp__h538232 = + assign _theResult___fst_exp__h538230 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 : + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 ; - assign _theResult___fst_exp__h538235 = - (_theResult___fst_exp__h537477 == 11'd2047) ? - _theResult___fst_exp__h537477 : - _theResult___fst_exp__h538232 ; - assign _theResult___fst_exp__h547054 = - _theResult____h538818[56] ? + assign _theResult___fst_exp__h538233 = + (_theResult___fst_exp__h537475 == 11'd2047) ? + _theResult___fst_exp__h537475 : + _theResult___fst_exp__h538230 ; + assign _theResult___fst_exp__h547052 = + _theResult____h538816[56] ? 11'd2 : - _theResult___fst_exp__h547128 ; - assign _theResult___fst_exp__h547119 = + _theResult___fst_exp__h547126 ; + assign _theResult___fst_exp__h547117 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ; - assign _theResult___fst_exp__h547125 = - (!_theResult____h538818[56] && !_theResult____h538818[55] && - !_theResult____h538818[54] && - !_theResult____h538818[53] && - !_theResult____h538818[52] && - !_theResult____h538818[51] && - !_theResult____h538818[50] && - !_theResult____h538818[49] && - !_theResult____h538818[48] && - !_theResult____h538818[47] && - !_theResult____h538818[46] && - !_theResult____h538818[45] && - !_theResult____h538818[44] && - !_theResult____h538818[43] && - !_theResult____h538818[42] && - !_theResult____h538818[41] && - !_theResult____h538818[40] && - !_theResult____h538818[39] && - !_theResult____h538818[38] && - !_theResult____h538818[37] && - !_theResult____h538818[36] && - !_theResult____h538818[35] && - !_theResult____h538818[34] && - !_theResult____h538818[33] && - !_theResult____h538818[32] && - !_theResult____h538818[31] && - !_theResult____h538818[30] && - !_theResult____h538818[29] && - !_theResult____h538818[28] && - !_theResult____h538818[27] && - !_theResult____h538818[26] && - !_theResult____h538818[25] && - !_theResult____h538818[24] && - !_theResult____h538818[23] && - !_theResult____h538818[22] && - !_theResult____h538818[21] && - !_theResult____h538818[20] && - !_theResult____h538818[19] && - !_theResult____h538818[18] && - !_theResult____h538818[17] && - !_theResult____h538818[16] && - !_theResult____h538818[15] && - !_theResult____h538818[14] && - !_theResult____h538818[13] && - !_theResult____h538818[12] && - !_theResult____h538818[11] && - !_theResult____h538818[10] && - !_theResult____h538818[9] && - !_theResult____h538818[8] && - !_theResult____h538818[7] && - !_theResult____h538818[6] && - !_theResult____h538818[5] && - !_theResult____h538818[4] && - !_theResult____h538818[3] && - !_theResult____h538818[2] && - !_theResult____h538818[1] && - !_theResult____h538818[0] || + assign _theResult___fst_exp__h547123 = + (!_theResult____h538816[56] && !_theResult____h538816[55] && + !_theResult____h538816[54] && + !_theResult____h538816[53] && + !_theResult____h538816[52] && + !_theResult____h538816[51] && + !_theResult____h538816[50] && + !_theResult____h538816[49] && + !_theResult____h538816[48] && + !_theResult____h538816[47] && + !_theResult____h538816[46] && + !_theResult____h538816[45] && + !_theResult____h538816[44] && + !_theResult____h538816[43] && + !_theResult____h538816[42] && + !_theResult____h538816[41] && + !_theResult____h538816[40] && + !_theResult____h538816[39] && + !_theResult____h538816[38] && + !_theResult____h538816[37] && + !_theResult____h538816[36] && + !_theResult____h538816[35] && + !_theResult____h538816[34] && + !_theResult____h538816[33] && + !_theResult____h538816[32] && + !_theResult____h538816[31] && + !_theResult____h538816[30] && + !_theResult____h538816[29] && + !_theResult____h538816[28] && + !_theResult____h538816[27] && + !_theResult____h538816[26] && + !_theResult____h538816[25] && + !_theResult____h538816[24] && + !_theResult____h538816[23] && + !_theResult____h538816[22] && + !_theResult____h538816[21] && + !_theResult____h538816[20] && + !_theResult____h538816[19] && + !_theResult____h538816[18] && + !_theResult____h538816[17] && + !_theResult____h538816[16] && + !_theResult____h538816[15] && + !_theResult____h538816[14] && + !_theResult____h538816[13] && + !_theResult____h538816[12] && + !_theResult____h538816[11] && + !_theResult____h538816[10] && + !_theResult____h538816[9] && + !_theResult____h538816[8] && + !_theResult____h538816[7] && + !_theResult____h538816[6] && + !_theResult____h538816[5] && + !_theResult____h538816[4] && + !_theResult____h538816[3] && + !_theResult____h538816[2] && + !_theResult____h538816[1] && + !_theResult____h538816[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362) ? 11'd0 : - _theResult___fst_exp__h547119 ; - assign _theResult___fst_exp__h547128 = - (!_theResult____h538818[56] && _theResult____h538818[55]) ? + _theResult___fst_exp__h547117 ; + assign _theResult___fst_exp__h547126 = + (!_theResult____h538816[56] && _theResult____h538816[55]) ? 11'd1 : - _theResult___fst_exp__h547125 ; - assign _theResult___fst_exp__h547883 = + _theResult___fst_exp__h547123 ; + assign _theResult___fst_exp__h547881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 : + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 ; - assign _theResult___fst_exp__h547886 = - (_theResult___fst_exp__h547054 == 11'd2047) ? - _theResult___fst_exp__h547054 : - _theResult___fst_exp__h547883 ; - assign _theResult___fst_exp__h555839 = + assign _theResult___fst_exp__h547884 = + (_theResult___fst_exp__h547052 == 11'd2047) ? + _theResult___fst_exp__h547052 : + _theResult___fst_exp__h547881 ; + assign _theResult___fst_exp__h555837 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ; - assign _theResult___fst_exp__h555878 = + assign _theResult___fst_exp__h555876 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h555884 = + assign _theResult___fst_exp__h555882 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412) ? 11'd0 : - _theResult___fst_exp__h555878 ; - assign _theResult___fst_exp__h555887 = + _theResult___fst_exp__h555876 ; + assign _theResult___fst_exp__h555885 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h555884 : - _theResult___fst_exp__h555839 ; - assign _theResult___fst_exp__h556667 = + _theResult___fst_exp__h555882 : + _theResult___fst_exp__h555837 ; + assign _theResult___fst_exp__h556665 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 : + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 ; - assign _theResult___fst_exp__h556670 = - (_theResult___fst_exp__h555887 == 11'd2047) ? - _theResult___fst_exp__h555887 : - _theResult___fst_exp__h556667 ; - assign _theResult___fst_exp__h556679 = + assign _theResult___fst_exp__h556668 = + (_theResult___fst_exp__h555885 == 11'd2047) ? + _theResult___fst_exp__h555885 : + _theResult___fst_exp__h556665 ; + assign _theResult___fst_exp__h556677 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_exp__h538238 : - _theResult___fst_exp__h522404) : + _theResult___snd_fst_exp__h538236 : + _theResult___fst_exp__h522402) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_exp__h556673 : - _theResult___fst_exp__h522404) ; - assign _theResult___fst_exp__h556682 = + _theResult___snd_fst_exp__h556671 : + _theResult___fst_exp__h522402) ; + assign _theResult___fst_exp__h556680 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h556679 ; - assign _theResult___fst_exp__h561605 = + _theResult___fst_exp__h556677 ; + assign _theResult___fst_exp__h561603 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_exp__h576669 = + assign _theResult___fst_exp__h576667 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h576675 = + assign _theResult___fst_exp__h576673 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302) ? 11'd0 : - _theResult___fst_exp__h576669 ; - assign _theResult___fst_exp__h576678 = + _theResult___fst_exp__h576667 ; + assign _theResult___fst_exp__h576676 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h576675 : + _theResult___fst_exp__h576673 : 11'd897 ; - assign _theResult___fst_exp__h577433 = + assign _theResult___fst_exp__h577431 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 : + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 ; - assign _theResult___fst_exp__h577436 = - (_theResult___fst_exp__h576678 == 11'd2047) ? - _theResult___fst_exp__h576678 : - _theResult___fst_exp__h577433 ; - assign _theResult___fst_exp__h586255 = - _theResult____h578019[56] ? + assign _theResult___fst_exp__h577434 = + (_theResult___fst_exp__h576676 == 11'd2047) ? + _theResult___fst_exp__h576676 : + _theResult___fst_exp__h577431 ; + assign _theResult___fst_exp__h586253 = + _theResult____h578017[56] ? 11'd2 : - _theResult___fst_exp__h586329 ; - assign _theResult___fst_exp__h586320 = + _theResult___fst_exp__h586327 ; + assign _theResult___fst_exp__h586318 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 } ; - assign _theResult___fst_exp__h586326 = - (!_theResult____h578019[56] && !_theResult____h578019[55] && - !_theResult____h578019[54] && - !_theResult____h578019[53] && - !_theResult____h578019[52] && - !_theResult____h578019[51] && - !_theResult____h578019[50] && - !_theResult____h578019[49] && - !_theResult____h578019[48] && - !_theResult____h578019[47] && - !_theResult____h578019[46] && - !_theResult____h578019[45] && - !_theResult____h578019[44] && - !_theResult____h578019[43] && - !_theResult____h578019[42] && - !_theResult____h578019[41] && - !_theResult____h578019[40] && - !_theResult____h578019[39] && - !_theResult____h578019[38] && - !_theResult____h578019[37] && - !_theResult____h578019[36] && - !_theResult____h578019[35] && - !_theResult____h578019[34] && - !_theResult____h578019[33] && - !_theResult____h578019[32] && - !_theResult____h578019[31] && - !_theResult____h578019[30] && - !_theResult____h578019[29] && - !_theResult____h578019[28] && - !_theResult____h578019[27] && - !_theResult____h578019[26] && - !_theResult____h578019[25] && - !_theResult____h578019[24] && - !_theResult____h578019[23] && - !_theResult____h578019[22] && - !_theResult____h578019[21] && - !_theResult____h578019[20] && - !_theResult____h578019[19] && - !_theResult____h578019[18] && - !_theResult____h578019[17] && - !_theResult____h578019[16] && - !_theResult____h578019[15] && - !_theResult____h578019[14] && - !_theResult____h578019[13] && - !_theResult____h578019[12] && - !_theResult____h578019[11] && - !_theResult____h578019[10] && - !_theResult____h578019[9] && - !_theResult____h578019[8] && - !_theResult____h578019[7] && - !_theResult____h578019[6] && - !_theResult____h578019[5] && - !_theResult____h578019[4] && - !_theResult____h578019[3] && - !_theResult____h578019[2] && - !_theResult____h578019[1] && - !_theResult____h578019[0] || + assign _theResult___fst_exp__h586324 = + (!_theResult____h578017[56] && !_theResult____h578017[55] && + !_theResult____h578017[54] && + !_theResult____h578017[53] && + !_theResult____h578017[52] && + !_theResult____h578017[51] && + !_theResult____h578017[50] && + !_theResult____h578017[49] && + !_theResult____h578017[48] && + !_theResult____h578017[47] && + !_theResult____h578017[46] && + !_theResult____h578017[45] && + !_theResult____h578017[44] && + !_theResult____h578017[43] && + !_theResult____h578017[42] && + !_theResult____h578017[41] && + !_theResult____h578017[40] && + !_theResult____h578017[39] && + !_theResult____h578017[38] && + !_theResult____h578017[37] && + !_theResult____h578017[36] && + !_theResult____h578017[35] && + !_theResult____h578017[34] && + !_theResult____h578017[33] && + !_theResult____h578017[32] && + !_theResult____h578017[31] && + !_theResult____h578017[30] && + !_theResult____h578017[29] && + !_theResult____h578017[28] && + !_theResult____h578017[27] && + !_theResult____h578017[26] && + !_theResult____h578017[25] && + !_theResult____h578017[24] && + !_theResult____h578017[23] && + !_theResult____h578017[22] && + !_theResult____h578017[21] && + !_theResult____h578017[20] && + !_theResult____h578017[19] && + !_theResult____h578017[18] && + !_theResult____h578017[17] && + !_theResult____h578017[16] && + !_theResult____h578017[15] && + !_theResult____h578017[14] && + !_theResult____h578017[13] && + !_theResult____h578017[12] && + !_theResult____h578017[11] && + !_theResult____h578017[10] && + !_theResult____h578017[9] && + !_theResult____h578017[8] && + !_theResult____h578017[7] && + !_theResult____h578017[6] && + !_theResult____h578017[5] && + !_theResult____h578017[4] && + !_theResult____h578017[3] && + !_theResult____h578017[2] && + !_theResult____h578017[1] && + !_theResult____h578017[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599) ? 11'd0 : - _theResult___fst_exp__h586320 ; - assign _theResult___fst_exp__h586329 = - (!_theResult____h578019[56] && _theResult____h578019[55]) ? + _theResult___fst_exp__h586318 ; + assign _theResult___fst_exp__h586327 = + (!_theResult____h578017[56] && _theResult____h578017[55]) ? 11'd1 : - _theResult___fst_exp__h586326 ; - assign _theResult___fst_exp__h587084 = + _theResult___fst_exp__h586324 ; + assign _theResult___fst_exp__h587082 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 : + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 ; - assign _theResult___fst_exp__h587087 = - (_theResult___fst_exp__h586255 == 11'd2047) ? - _theResult___fst_exp__h586255 : - _theResult___fst_exp__h587084 ; - assign _theResult___fst_exp__h595040 = + assign _theResult___fst_exp__h587085 = + (_theResult___fst_exp__h586253 == 11'd2047) ? + _theResult___fst_exp__h586253 : + _theResult___fst_exp__h587082 ; + assign _theResult___fst_exp__h595038 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ; - assign _theResult___fst_exp__h595079 = + assign _theResult___fst_exp__h595077 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h595085 = + assign _theResult___fst_exp__h595083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649) ? 11'd0 : - _theResult___fst_exp__h595079 ; - assign _theResult___fst_exp__h595088 = + _theResult___fst_exp__h595077 ; + assign _theResult___fst_exp__h595086 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h595085 : - _theResult___fst_exp__h595040 ; - assign _theResult___fst_exp__h595868 = + _theResult___fst_exp__h595083 : + _theResult___fst_exp__h595038 ; + assign _theResult___fst_exp__h595866 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 : + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 ; - assign _theResult___fst_exp__h595871 = - (_theResult___fst_exp__h595088 == 11'd2047) ? - _theResult___fst_exp__h595088 : - _theResult___fst_exp__h595868 ; - assign _theResult___fst_exp__h595880 = + assign _theResult___fst_exp__h595869 = + (_theResult___fst_exp__h595086 == 11'd2047) ? + _theResult___fst_exp__h595086 : + _theResult___fst_exp__h595866 ; + assign _theResult___fst_exp__h595878 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_exp__h577439 : - _theResult___fst_exp__h561605) : + _theResult___snd_fst_exp__h577437 : + _theResult___fst_exp__h561603) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_exp__h595874 : - _theResult___fst_exp__h561605) ; - assign _theResult___fst_exp__h595883 = + _theResult___snd_fst_exp__h595872 : + _theResult___fst_exp__h561603) ; + assign _theResult___fst_exp__h595881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h595880 ; - assign _theResult___fst_sfd__h352011 = - (_theResult___fst_exp__h351413 == 8'd255) ? - sfdin__h351407[56:34] : - _theResult___fst_sfd__h352008 ; - assign _theResult___fst_sfd__h360593 = - (_theResult___fst_exp__h360069 == 8'd255) ? - _theResult___snd__h360020[56:34] : - _theResult___fst_sfd__h360590 ; - assign _theResult___fst_sfd__h369777 = - (_theResult___fst_exp__h369179 == 8'd255) ? - sfdin__h369173[56:34] : - _theResult___fst_sfd__h369774 ; - assign _theResult___fst_sfd__h378413 = - (_theResult___fst_exp__h377864 == 8'd255) ? - _theResult___snd__h377810[56:34] : - _theResult___fst_sfd__h378410 ; - assign _theResult___fst_sfd__h378422 = + _theResult___fst_exp__h595878 ; + assign _theResult___fst_sfd__h352009 = + (_theResult___fst_exp__h351411 == 8'd255) ? + sfdin__h351405[56:34] : + _theResult___fst_sfd__h352006 ; + assign _theResult___fst_sfd__h360591 = + (_theResult___fst_exp__h360067 == 8'd255) ? + _theResult___snd__h360018[56:34] : + _theResult___fst_sfd__h360588 ; + assign _theResult___fst_sfd__h369775 = + (_theResult___fst_exp__h369177 == 8'd255) ? + sfdin__h369171[56:34] : + _theResult___fst_sfd__h369772 ; + assign _theResult___fst_sfd__h378411 = + (_theResult___fst_exp__h377862 == 8'd255) ? + _theResult___snd__h377808[56:34] : + _theResult___fst_sfd__h378408 ; + assign _theResult___fst_sfd__h378420 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_sfd__h360596 : - _theResult___fst_sfd__h343285) : + _theResult___snd_fst_sfd__h360594 : + _theResult___fst_sfd__h343283) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_sfd__h378416 : - _theResult___fst_sfd__h343285) ; - assign _theResult___fst_sfd__h378428 = + _theResult___snd_fst_sfd__h378414 : + _theResult___fst_sfd__h343283) ; + assign _theResult___fst_sfd__h378426 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -25718,33 +25718,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h378422 ; - assign _theResult___fst_sfd__h397701 = - (_theResult___fst_exp__h397103 == 8'd255) ? - sfdin__h397097[56:34] : - _theResult___fst_sfd__h397698 ; - assign _theResult___fst_sfd__h406283 = - (_theResult___fst_exp__h405759 == 8'd255) ? - _theResult___snd__h405710[56:34] : - _theResult___fst_sfd__h406280 ; - assign _theResult___fst_sfd__h415467 = - (_theResult___fst_exp__h414869 == 8'd255) ? - sfdin__h414863[56:34] : - _theResult___fst_sfd__h415464 ; - assign _theResult___fst_sfd__h424103 = - (_theResult___fst_exp__h423554 == 8'd255) ? - _theResult___snd__h423500[56:34] : - _theResult___fst_sfd__h424100 ; - assign _theResult___fst_sfd__h424112 = + _theResult___fst_sfd__h378420 ; + assign _theResult___fst_sfd__h397699 = + (_theResult___fst_exp__h397101 == 8'd255) ? + sfdin__h397095[56:34] : + _theResult___fst_sfd__h397696 ; + assign _theResult___fst_sfd__h406281 = + (_theResult___fst_exp__h405757 == 8'd255) ? + _theResult___snd__h405708[56:34] : + _theResult___fst_sfd__h406278 ; + assign _theResult___fst_sfd__h415465 = + (_theResult___fst_exp__h414867 == 8'd255) ? + sfdin__h414861[56:34] : + _theResult___fst_sfd__h415462 ; + assign _theResult___fst_sfd__h424101 = + (_theResult___fst_exp__h423552 == 8'd255) ? + _theResult___snd__h423498[56:34] : + _theResult___fst_sfd__h424098 ; + assign _theResult___fst_sfd__h424110 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_sfd__h406286 : - _theResult___fst_sfd__h388977) : + _theResult___snd_fst_sfd__h406284 : + _theResult___fst_sfd__h388975) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_sfd__h424106 : - _theResult___fst_sfd__h388977) ; - assign _theResult___fst_sfd__h424118 = + _theResult___snd_fst_sfd__h424104 : + _theResult___fst_sfd__h388975) ; + assign _theResult___fst_sfd__h424116 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -25752,33 +25752,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h424112 ; - assign _theResult___fst_sfd__h443389 = - (_theResult___fst_exp__h442791 == 8'd255) ? - sfdin__h442785[56:34] : - _theResult___fst_sfd__h443386 ; - assign _theResult___fst_sfd__h451971 = - (_theResult___fst_exp__h451447 == 8'd255) ? - _theResult___snd__h451398[56:34] : - _theResult___fst_sfd__h451968 ; - assign _theResult___fst_sfd__h461155 = - (_theResult___fst_exp__h460557 == 8'd255) ? - sfdin__h460551[56:34] : - _theResult___fst_sfd__h461152 ; - assign _theResult___fst_sfd__h469791 = - (_theResult___fst_exp__h469242 == 8'd255) ? - _theResult___snd__h469188[56:34] : - _theResult___fst_sfd__h469788 ; - assign _theResult___fst_sfd__h469800 = + _theResult___fst_sfd__h424110 ; + assign _theResult___fst_sfd__h443387 = + (_theResult___fst_exp__h442789 == 8'd255) ? + sfdin__h442783[56:34] : + _theResult___fst_sfd__h443384 ; + assign _theResult___fst_sfd__h451969 = + (_theResult___fst_exp__h451445 == 8'd255) ? + _theResult___snd__h451396[56:34] : + _theResult___fst_sfd__h451966 ; + assign _theResult___fst_sfd__h461153 = + (_theResult___fst_exp__h460555 == 8'd255) ? + sfdin__h460549[56:34] : + _theResult___fst_sfd__h461150 ; + assign _theResult___fst_sfd__h469789 = + (_theResult___fst_exp__h469240 == 8'd255) ? + _theResult___snd__h469186[56:34] : + _theResult___fst_sfd__h469786 ; + assign _theResult___fst_sfd__h469798 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_sfd__h451974 : - _theResult___fst_sfd__h434665) : + _theResult___snd_fst_sfd__h451972 : + _theResult___fst_sfd__h434663) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_sfd__h469794 : - _theResult___fst_sfd__h434665) ; - assign _theResult___fst_sfd__h469806 = + _theResult___snd_fst_sfd__h469792 : + _theResult___fst_sfd__h434663) ; + assign _theResult___fst_sfd__h469804 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -25786,1320 +25786,1320 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h469800 ; - assign _theResult___fst_sfd__h483604 = + _theResult___fst_sfd__h469798 ; + assign _theResult___fst_sfd__h483602 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_sfd__h499432 = + assign _theResult___fst_sfd__h499430 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 : + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 ; - assign _theResult___fst_sfd__h499435 = - (_theResult___fst_exp__h498676 == 11'd2047) ? - _theResult___snd__h498627[56:5] : - _theResult___fst_sfd__h499432 ; - assign _theResult___fst_sfd__h509083 = + assign _theResult___fst_sfd__h499433 = + (_theResult___fst_exp__h498674 == 11'd2047) ? + _theResult___snd__h498625[56:5] : + _theResult___fst_sfd__h499430 ; + assign _theResult___fst_sfd__h509081 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 : + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 ; - assign _theResult___fst_sfd__h509086 = - (_theResult___fst_exp__h508253 == 11'd2047) ? - sfdin__h508247[56:5] : - _theResult___fst_sfd__h509083 ; - assign _theResult___fst_sfd__h517867 = + assign _theResult___fst_sfd__h509084 = + (_theResult___fst_exp__h508251 == 11'd2047) ? + sfdin__h508245[56:5] : + _theResult___fst_sfd__h509081 ; + assign _theResult___fst_sfd__h517865 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 : + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 ; - assign _theResult___fst_sfd__h517870 = - (_theResult___fst_exp__h517086 == 11'd2047) ? - _theResult___snd__h517032[56:5] : - _theResult___fst_sfd__h517867 ; - assign _theResult___fst_sfd__h517879 = + assign _theResult___fst_sfd__h517868 = + (_theResult___fst_exp__h517084 == 11'd2047) ? + _theResult___snd__h517030[56:5] : + _theResult___fst_sfd__h517865 ; + assign _theResult___fst_sfd__h517877 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_sfd__h499438 : - _theResult___fst_sfd__h483604) : + _theResult___snd_fst_sfd__h499436 : + _theResult___fst_sfd__h483602) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_sfd__h517873 : - _theResult___fst_sfd__h483604) ; - assign _theResult___fst_sfd__h517885 = + _theResult___snd_fst_sfd__h517871 : + _theResult___fst_sfd__h483602) ; + assign _theResult___fst_sfd__h517883 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h517879 ; - assign _theResult___fst_sfd__h522405 = + _theResult___fst_sfd__h517877 ; + assign _theResult___fst_sfd__h522403 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_sfd__h538233 = + assign _theResult___fst_sfd__h538231 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 : + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 ; - assign _theResult___fst_sfd__h538236 = - (_theResult___fst_exp__h537477 == 11'd2047) ? - _theResult___snd__h537428[56:5] : - _theResult___fst_sfd__h538233 ; - assign _theResult___fst_sfd__h547884 = + assign _theResult___fst_sfd__h538234 = + (_theResult___fst_exp__h537475 == 11'd2047) ? + _theResult___snd__h537426[56:5] : + _theResult___fst_sfd__h538231 ; + assign _theResult___fst_sfd__h547882 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 ; - assign _theResult___fst_sfd__h547887 = - (_theResult___fst_exp__h547054 == 11'd2047) ? - sfdin__h547048[56:5] : - _theResult___fst_sfd__h547884 ; - assign _theResult___fst_sfd__h556668 = + assign _theResult___fst_sfd__h547885 = + (_theResult___fst_exp__h547052 == 11'd2047) ? + sfdin__h547046[56:5] : + _theResult___fst_sfd__h547882 ; + assign _theResult___fst_sfd__h556666 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 : + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 ; - assign _theResult___fst_sfd__h556671 = - (_theResult___fst_exp__h555887 == 11'd2047) ? - _theResult___snd__h555833[56:5] : - _theResult___fst_sfd__h556668 ; - assign _theResult___fst_sfd__h556680 = + assign _theResult___fst_sfd__h556669 = + (_theResult___fst_exp__h555885 == 11'd2047) ? + _theResult___snd__h555831[56:5] : + _theResult___fst_sfd__h556666 ; + assign _theResult___fst_sfd__h556678 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_sfd__h538239 : - _theResult___fst_sfd__h522405) : + _theResult___snd_fst_sfd__h538237 : + _theResult___fst_sfd__h522403) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_sfd__h556674 : - _theResult___fst_sfd__h522405) ; - assign _theResult___fst_sfd__h556686 = + _theResult___snd_fst_sfd__h556672 : + _theResult___fst_sfd__h522403) ; + assign _theResult___fst_sfd__h556684 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h556680 ; - assign _theResult___fst_sfd__h561606 = + _theResult___fst_sfd__h556678 ; + assign _theResult___fst_sfd__h561604 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_sfd__h577434 = + assign _theResult___fst_sfd__h577432 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 : + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 ; - assign _theResult___fst_sfd__h577437 = - (_theResult___fst_exp__h576678 == 11'd2047) ? - _theResult___snd__h576629[56:5] : - _theResult___fst_sfd__h577434 ; - assign _theResult___fst_sfd__h587085 = + assign _theResult___fst_sfd__h577435 = + (_theResult___fst_exp__h576676 == 11'd2047) ? + _theResult___snd__h576627[56:5] : + _theResult___fst_sfd__h577432 ; + assign _theResult___fst_sfd__h587083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 ; - assign _theResult___fst_sfd__h587088 = - (_theResult___fst_exp__h586255 == 11'd2047) ? - sfdin__h586249[56:5] : - _theResult___fst_sfd__h587085 ; - assign _theResult___fst_sfd__h595869 = + assign _theResult___fst_sfd__h587086 = + (_theResult___fst_exp__h586253 == 11'd2047) ? + sfdin__h586247[56:5] : + _theResult___fst_sfd__h587083 ; + assign _theResult___fst_sfd__h595867 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 : + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 ; - assign _theResult___fst_sfd__h595872 = - (_theResult___fst_exp__h595088 == 11'd2047) ? - _theResult___snd__h595034[56:5] : - _theResult___fst_sfd__h595869 ; - assign _theResult___fst_sfd__h595881 = + assign _theResult___fst_sfd__h595870 = + (_theResult___fst_exp__h595086 == 11'd2047) ? + _theResult___snd__h595032[56:5] : + _theResult___fst_sfd__h595867 ; + assign _theResult___fst_sfd__h595879 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_sfd__h577440 : - _theResult___fst_sfd__h561606) : + _theResult___snd_fst_sfd__h577438 : + _theResult___fst_sfd__h561604) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_sfd__h595875 : - _theResult___fst_sfd__h561606) ; - assign _theResult___fst_sfd__h595887 = + _theResult___snd_fst_sfd__h595873 : + _theResult___fst_sfd__h561604) ; + assign _theResult___fst_sfd__h595885 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h595881 ; - assign _theResult___sfd__h351930 = - sfd__h351505[24] ? - ((_theResult___fst_exp__h351413 == 8'd254) ? + _theResult___fst_sfd__h595879 ; + assign _theResult___sfd__h351928 = + sfd__h351503[24] ? + ((_theResult___fst_exp__h351411 == 8'd254) ? 23'd0 : - sfd__h351505[23:1]) : - sfd__h351505[22:0] ; - assign _theResult___sfd__h360512 = - sfd__h360087[24] ? - ((_theResult___fst_exp__h360069 == 8'd254) ? + sfd__h351503[23:1]) : + sfd__h351503[22:0] ; + assign _theResult___sfd__h360510 = + sfd__h360085[24] ? + ((_theResult___fst_exp__h360067 == 8'd254) ? 23'd0 : - sfd__h360087[23:1]) : - sfd__h360087[22:0] ; - assign _theResult___sfd__h369696 = - sfd__h369271[24] ? - ((_theResult___fst_exp__h369179 == 8'd254) ? + sfd__h360085[23:1]) : + sfd__h360085[22:0] ; + assign _theResult___sfd__h369694 = + sfd__h369269[24] ? + ((_theResult___fst_exp__h369177 == 8'd254) ? 23'd0 : - sfd__h369271[23:1]) : - sfd__h369271[22:0] ; - assign _theResult___sfd__h378332 = - sfd__h377883[24] ? - ((_theResult___fst_exp__h377864 == 8'd254) ? + sfd__h369269[23:1]) : + sfd__h369269[22:0] ; + assign _theResult___sfd__h378330 = + sfd__h377881[24] ? + ((_theResult___fst_exp__h377862 == 8'd254) ? 23'd0 : - sfd__h377883[23:1]) : - sfd__h377883[22:0] ; - assign _theResult___sfd__h378434 = + sfd__h377881[23:1]) : + sfd__h377881[22:0] ; + assign _theResult___sfd__h378432 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h335647 : - _theResult___fst_sfd__h378428 ; - assign _theResult___sfd__h397620 = - sfd__h397195[24] ? - ((_theResult___fst_exp__h397103 == 8'd254) ? + _theResult___snd_fst_sfd__h335645 : + _theResult___fst_sfd__h378426 ; + assign _theResult___sfd__h397618 = + sfd__h397193[24] ? + ((_theResult___fst_exp__h397101 == 8'd254) ? 23'd0 : - sfd__h397195[23:1]) : - sfd__h397195[22:0] ; - assign _theResult___sfd__h406202 = - sfd__h405777[24] ? - ((_theResult___fst_exp__h405759 == 8'd254) ? + sfd__h397193[23:1]) : + sfd__h397193[22:0] ; + assign _theResult___sfd__h406200 = + sfd__h405775[24] ? + ((_theResult___fst_exp__h405757 == 8'd254) ? 23'd0 : - sfd__h405777[23:1]) : - sfd__h405777[22:0] ; - assign _theResult___sfd__h415386 = - sfd__h414961[24] ? - ((_theResult___fst_exp__h414869 == 8'd254) ? + sfd__h405775[23:1]) : + sfd__h405775[22:0] ; + assign _theResult___sfd__h415384 = + sfd__h414959[24] ? + ((_theResult___fst_exp__h414867 == 8'd254) ? 23'd0 : - sfd__h414961[23:1]) : - sfd__h414961[22:0] ; - assign _theResult___sfd__h424022 = - sfd__h423573[24] ? - ((_theResult___fst_exp__h423554 == 8'd254) ? + sfd__h414959[23:1]) : + sfd__h414959[22:0] ; + assign _theResult___sfd__h424020 = + sfd__h423571[24] ? + ((_theResult___fst_exp__h423552 == 8'd254) ? 23'd0 : - sfd__h423573[23:1]) : - sfd__h423573[22:0] ; - assign _theResult___sfd__h424124 = + sfd__h423571[23:1]) : + sfd__h423571[22:0] ; + assign _theResult___sfd__h424122 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h381342 : - _theResult___fst_sfd__h424118 ; - assign _theResult___sfd__h443308 = - sfd__h442883[24] ? - ((_theResult___fst_exp__h442791 == 8'd254) ? + _theResult___snd_fst_sfd__h381340 : + _theResult___fst_sfd__h424116 ; + assign _theResult___sfd__h443306 = + sfd__h442881[24] ? + ((_theResult___fst_exp__h442789 == 8'd254) ? 23'd0 : - sfd__h442883[23:1]) : - sfd__h442883[22:0] ; - assign _theResult___sfd__h451890 = - sfd__h451465[24] ? - ((_theResult___fst_exp__h451447 == 8'd254) ? + sfd__h442881[23:1]) : + sfd__h442881[22:0] ; + assign _theResult___sfd__h451888 = + sfd__h451463[24] ? + ((_theResult___fst_exp__h451445 == 8'd254) ? 23'd0 : - sfd__h451465[23:1]) : - sfd__h451465[22:0] ; - assign _theResult___sfd__h461074 = - sfd__h460649[24] ? - ((_theResult___fst_exp__h460557 == 8'd254) ? + sfd__h451463[23:1]) : + sfd__h451463[22:0] ; + assign _theResult___sfd__h461072 = + sfd__h460647[24] ? + ((_theResult___fst_exp__h460555 == 8'd254) ? 23'd0 : - sfd__h460649[23:1]) : - sfd__h460649[22:0] ; - assign _theResult___sfd__h469710 = - sfd__h469261[24] ? - ((_theResult___fst_exp__h469242 == 8'd254) ? + sfd__h460647[23:1]) : + sfd__h460647[22:0] ; + assign _theResult___sfd__h469708 = + sfd__h469259[24] ? + ((_theResult___fst_exp__h469240 == 8'd254) ? 23'd0 : - sfd__h469261[23:1]) : - sfd__h469261[22:0] ; - assign _theResult___sfd__h469812 = + sfd__h469259[23:1]) : + sfd__h469259[22:0] ; + assign _theResult___sfd__h469810 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h427030 : - _theResult___fst_sfd__h469806 ; - assign _theResult___sfd__h499332 = - sfd__h498694[53] ? - ((_theResult___fst_exp__h498676 == 11'd2046) ? + _theResult___snd_fst_sfd__h427028 : + _theResult___fst_sfd__h469804 ; + assign _theResult___sfd__h499330 = + sfd__h498692[53] ? + ((_theResult___fst_exp__h498674 == 11'd2046) ? 52'd0 : - sfd__h498694[52:1]) : - sfd__h498694[51:0] ; - assign _theResult___sfd__h508983 = - sfd__h508345[53] ? - ((_theResult___fst_exp__h508253 == 11'd2046) ? + sfd__h498692[52:1]) : + sfd__h498692[51:0] ; + assign _theResult___sfd__h508981 = + sfd__h508343[53] ? + ((_theResult___fst_exp__h508251 == 11'd2046) ? 52'd0 : - sfd__h508345[52:1]) : - sfd__h508345[51:0] ; - assign _theResult___sfd__h517767 = - sfd__h517105[53] ? - ((_theResult___fst_exp__h517086 == 11'd2046) ? + sfd__h508343[52:1]) : + sfd__h508343[51:0] ; + assign _theResult___sfd__h517765 = + sfd__h517103[53] ? + ((_theResult___fst_exp__h517084 == 11'd2046) ? 52'd0 : - sfd__h517105[52:1]) : - sfd__h517105[51:0] ; - assign _theResult___sfd__h538133 = - sfd__h537495[53] ? - ((_theResult___fst_exp__h537477 == 11'd2046) ? + sfd__h517103[52:1]) : + sfd__h517103[51:0] ; + assign _theResult___sfd__h538131 = + sfd__h537493[53] ? + ((_theResult___fst_exp__h537475 == 11'd2046) ? 52'd0 : - sfd__h537495[52:1]) : - sfd__h537495[51:0] ; - assign _theResult___sfd__h547784 = - sfd__h547146[53] ? - ((_theResult___fst_exp__h547054 == 11'd2046) ? + sfd__h537493[52:1]) : + sfd__h537493[51:0] ; + assign _theResult___sfd__h547782 = + sfd__h547144[53] ? + ((_theResult___fst_exp__h547052 == 11'd2046) ? 52'd0 : - sfd__h547146[52:1]) : - sfd__h547146[51:0] ; - assign _theResult___sfd__h556568 = - sfd__h555906[53] ? - ((_theResult___fst_exp__h555887 == 11'd2046) ? + sfd__h547144[52:1]) : + sfd__h547144[51:0] ; + assign _theResult___sfd__h556566 = + sfd__h555904[53] ? + ((_theResult___fst_exp__h555885 == 11'd2046) ? 52'd0 : - sfd__h555906[52:1]) : - sfd__h555906[51:0] ; - assign _theResult___sfd__h577334 = - sfd__h576696[53] ? - ((_theResult___fst_exp__h576678 == 11'd2046) ? + sfd__h555904[52:1]) : + sfd__h555904[51:0] ; + assign _theResult___sfd__h577332 = + sfd__h576694[53] ? + ((_theResult___fst_exp__h576676 == 11'd2046) ? 52'd0 : - sfd__h576696[52:1]) : - sfd__h576696[51:0] ; - assign _theResult___sfd__h586985 = - sfd__h586347[53] ? - ((_theResult___fst_exp__h586255 == 11'd2046) ? + sfd__h576694[52:1]) : + sfd__h576694[51:0] ; + assign _theResult___sfd__h586983 = + sfd__h586345[53] ? + ((_theResult___fst_exp__h586253 == 11'd2046) ? 52'd0 : - sfd__h586347[52:1]) : - sfd__h586347[51:0] ; - assign _theResult___sfd__h595769 = - sfd__h595107[53] ? - ((_theResult___fst_exp__h595088 == 11'd2046) ? + sfd__h586345[52:1]) : + sfd__h586345[51:0] ; + assign _theResult___sfd__h595767 = + sfd__h595105[53] ? + ((_theResult___fst_exp__h595086 == 11'd2046) ? 52'd0 : - sfd__h595107[52:1]) : - sfd__h595107[51:0] ; - assign _theResult___snd__h351424 = { _theResult____h343302[55:0], 1'd0 } ; - assign _theResult___snd__h351435 = - (!_theResult____h343302[56] && _theResult____h343302[55]) ? - _theResult___snd__h351437 : - _theResult___snd__h351447 ; - assign _theResult___snd__h351437 = { _theResult____h343302[54:0], 2'd0 } ; - assign _theResult___snd__h351447 = - (!_theResult____h343302[56] && !_theResult____h343302[55] && - !_theResult____h343302[54] && - !_theResult____h343302[53] && - !_theResult____h343302[52] && - !_theResult____h343302[51] && - !_theResult____h343302[50] && - !_theResult____h343302[49] && - !_theResult____h343302[48] && - !_theResult____h343302[47] && - !_theResult____h343302[46] && - !_theResult____h343302[45] && - !_theResult____h343302[44] && - !_theResult____h343302[43] && - !_theResult____h343302[42] && - !_theResult____h343302[41] && - !_theResult____h343302[40] && - !_theResult____h343302[39] && - !_theResult____h343302[38] && - !_theResult____h343302[37] && - !_theResult____h343302[36] && - !_theResult____h343302[35] && - !_theResult____h343302[34] && - !_theResult____h343302[33] && - !_theResult____h343302[32] && - !_theResult____h343302[31] && - !_theResult____h343302[30] && - !_theResult____h343302[29] && - !_theResult____h343302[28] && - !_theResult____h343302[27] && - !_theResult____h343302[26] && - !_theResult____h343302[25] && - !_theResult____h343302[24] && - !_theResult____h343302[23] && - !_theResult____h343302[22] && - !_theResult____h343302[21] && - !_theResult____h343302[20] && - !_theResult____h343302[19] && - !_theResult____h343302[18] && - !_theResult____h343302[17] && - !_theResult____h343302[16] && - !_theResult____h343302[15] && - !_theResult____h343302[14] && - !_theResult____h343302[13] && - !_theResult____h343302[12] && - !_theResult____h343302[11] && - !_theResult____h343302[10] && - !_theResult____h343302[9] && - !_theResult____h343302[8] && - !_theResult____h343302[7] && - !_theResult____h343302[6] && - !_theResult____h343302[5] && - !_theResult____h343302[4] && - !_theResult____h343302[3] && - !_theResult____h343302[2] && - !_theResult____h343302[1] && - !_theResult____h343302[0]) ? - _theResult____h343302 : - _theResult___snd__h351453 ; - assign _theResult___snd__h351453 = + sfd__h595105[52:1]) : + sfd__h595105[51:0] ; + assign _theResult___snd__h351422 = { _theResult____h343300[55:0], 1'd0 } ; + assign _theResult___snd__h351433 = + (!_theResult____h343300[56] && _theResult____h343300[55]) ? + _theResult___snd__h351435 : + _theResult___snd__h351445 ; + assign _theResult___snd__h351435 = { _theResult____h343300[54:0], 2'd0 } ; + assign _theResult___snd__h351445 = + (!_theResult____h343300[56] && !_theResult____h343300[55] && + !_theResult____h343300[54] && + !_theResult____h343300[53] && + !_theResult____h343300[52] && + !_theResult____h343300[51] && + !_theResult____h343300[50] && + !_theResult____h343300[49] && + !_theResult____h343300[48] && + !_theResult____h343300[47] && + !_theResult____h343300[46] && + !_theResult____h343300[45] && + !_theResult____h343300[44] && + !_theResult____h343300[43] && + !_theResult____h343300[42] && + !_theResult____h343300[41] && + !_theResult____h343300[40] && + !_theResult____h343300[39] && + !_theResult____h343300[38] && + !_theResult____h343300[37] && + !_theResult____h343300[36] && + !_theResult____h343300[35] && + !_theResult____h343300[34] && + !_theResult____h343300[33] && + !_theResult____h343300[32] && + !_theResult____h343300[31] && + !_theResult____h343300[30] && + !_theResult____h343300[29] && + !_theResult____h343300[28] && + !_theResult____h343300[27] && + !_theResult____h343300[26] && + !_theResult____h343300[25] && + !_theResult____h343300[24] && + !_theResult____h343300[23] && + !_theResult____h343300[22] && + !_theResult____h343300[21] && + !_theResult____h343300[20] && + !_theResult____h343300[19] && + !_theResult____h343300[18] && + !_theResult____h343300[17] && + !_theResult____h343300[16] && + !_theResult____h343300[15] && + !_theResult____h343300[14] && + !_theResult____h343300[13] && + !_theResult____h343300[12] && + !_theResult____h343300[11] && + !_theResult____h343300[10] && + !_theResult____h343300[9] && + !_theResult____h343300[8] && + !_theResult____h343300[7] && + !_theResult____h343300[6] && + !_theResult____h343300[5] && + !_theResult____h343300[4] && + !_theResult____h343300[3] && + !_theResult____h343300[2] && + !_theResult____h343300[1] && + !_theResult____h343300[0]) ? + _theResult____h343300 : + _theResult___snd__h351451 ; + assign _theResult___snd__h351451 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20[54:0], 2'd0 } ; - assign _theResult___snd__h351476 = - _theResult____h343302 << + assign _theResult___snd__h351474 = + _theResult____h343300 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ; - assign _theResult___snd__h360020 = + assign _theResult___snd__h360018 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h360029 : - _theResult___snd__h360022 ; - assign _theResult___snd__h360022 = + _theResult___snd__h360027 : + _theResult___snd__h360020 ; + assign _theResult___snd__h360020 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h360029 = + assign _theResult___snd__h360027 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335697 : - _theResult___snd__h360035 ; - assign _theResult___snd__h360035 = + sfd__h335695 : + _theResult___snd__h360033 ; + assign _theResult___snd__h360033 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22[54:0], 2'd0 } ; - assign _theResult___snd__h360058 = - sfd__h335697 << + assign _theResult___snd__h360056 = + sfd__h335695 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ; - assign _theResult___snd__h369190 = { _theResult____h360941[55:0], 1'd0 } ; - assign _theResult___snd__h369201 = - (!_theResult____h360941[56] && _theResult____h360941[55]) ? - _theResult___snd__h369203 : - _theResult___snd__h369213 ; - assign _theResult___snd__h369203 = { _theResult____h360941[54:0], 2'd0 } ; - assign _theResult___snd__h369213 = - (!_theResult____h360941[56] && !_theResult____h360941[55] && - !_theResult____h360941[54] && - !_theResult____h360941[53] && - !_theResult____h360941[52] && - !_theResult____h360941[51] && - !_theResult____h360941[50] && - !_theResult____h360941[49] && - !_theResult____h360941[48] && - !_theResult____h360941[47] && - !_theResult____h360941[46] && - !_theResult____h360941[45] && - !_theResult____h360941[44] && - !_theResult____h360941[43] && - !_theResult____h360941[42] && - !_theResult____h360941[41] && - !_theResult____h360941[40] && - !_theResult____h360941[39] && - !_theResult____h360941[38] && - !_theResult____h360941[37] && - !_theResult____h360941[36] && - !_theResult____h360941[35] && - !_theResult____h360941[34] && - !_theResult____h360941[33] && - !_theResult____h360941[32] && - !_theResult____h360941[31] && - !_theResult____h360941[30] && - !_theResult____h360941[29] && - !_theResult____h360941[28] && - !_theResult____h360941[27] && - !_theResult____h360941[26] && - !_theResult____h360941[25] && - !_theResult____h360941[24] && - !_theResult____h360941[23] && - !_theResult____h360941[22] && - !_theResult____h360941[21] && - !_theResult____h360941[20] && - !_theResult____h360941[19] && - !_theResult____h360941[18] && - !_theResult____h360941[17] && - !_theResult____h360941[16] && - !_theResult____h360941[15] && - !_theResult____h360941[14] && - !_theResult____h360941[13] && - !_theResult____h360941[12] && - !_theResult____h360941[11] && - !_theResult____h360941[10] && - !_theResult____h360941[9] && - !_theResult____h360941[8] && - !_theResult____h360941[7] && - !_theResult____h360941[6] && - !_theResult____h360941[5] && - !_theResult____h360941[4] && - !_theResult____h360941[3] && - !_theResult____h360941[2] && - !_theResult____h360941[1] && - !_theResult____h360941[0]) ? - _theResult____h360941 : - _theResult___snd__h369219 ; - assign _theResult___snd__h369219 = + assign _theResult___snd__h369188 = { _theResult____h360939[55:0], 1'd0 } ; + assign _theResult___snd__h369199 = + (!_theResult____h360939[56] && _theResult____h360939[55]) ? + _theResult___snd__h369201 : + _theResult___snd__h369211 ; + assign _theResult___snd__h369201 = { _theResult____h360939[54:0], 2'd0 } ; + assign _theResult___snd__h369211 = + (!_theResult____h360939[56] && !_theResult____h360939[55] && + !_theResult____h360939[54] && + !_theResult____h360939[53] && + !_theResult____h360939[52] && + !_theResult____h360939[51] && + !_theResult____h360939[50] && + !_theResult____h360939[49] && + !_theResult____h360939[48] && + !_theResult____h360939[47] && + !_theResult____h360939[46] && + !_theResult____h360939[45] && + !_theResult____h360939[44] && + !_theResult____h360939[43] && + !_theResult____h360939[42] && + !_theResult____h360939[41] && + !_theResult____h360939[40] && + !_theResult____h360939[39] && + !_theResult____h360939[38] && + !_theResult____h360939[37] && + !_theResult____h360939[36] && + !_theResult____h360939[35] && + !_theResult____h360939[34] && + !_theResult____h360939[33] && + !_theResult____h360939[32] && + !_theResult____h360939[31] && + !_theResult____h360939[30] && + !_theResult____h360939[29] && + !_theResult____h360939[28] && + !_theResult____h360939[27] && + !_theResult____h360939[26] && + !_theResult____h360939[25] && + !_theResult____h360939[24] && + !_theResult____h360939[23] && + !_theResult____h360939[22] && + !_theResult____h360939[21] && + !_theResult____h360939[20] && + !_theResult____h360939[19] && + !_theResult____h360939[18] && + !_theResult____h360939[17] && + !_theResult____h360939[16] && + !_theResult____h360939[15] && + !_theResult____h360939[14] && + !_theResult____h360939[13] && + !_theResult____h360939[12] && + !_theResult____h360939[11] && + !_theResult____h360939[10] && + !_theResult____h360939[9] && + !_theResult____h360939[8] && + !_theResult____h360939[7] && + !_theResult____h360939[6] && + !_theResult____h360939[5] && + !_theResult____h360939[4] && + !_theResult____h360939[3] && + !_theResult____h360939[2] && + !_theResult____h360939[1] && + !_theResult____h360939[0]) ? + _theResult____h360939 : + _theResult___snd__h369217 ; + assign _theResult___snd__h369217 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h369242 = - _theResult____h360941 << + assign _theResult___snd__h369240 = + _theResult____h360939 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ; - assign _theResult___snd__h377810 = + assign _theResult___snd__h377808 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h377824 : - _theResult___snd__h360022 ; - assign _theResult___snd__h377824 = + _theResult___snd__h377822 : + _theResult___snd__h360020 ; + assign _theResult___snd__h377822 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335697 : - _theResult___snd__h377830 ; - assign _theResult___snd__h377830 = + sfd__h335695 : + _theResult___snd__h377828 ; + assign _theResult___snd__h377828 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35[54:0], 2'd0 } ; - assign _theResult___snd__h377848 = - sfd__h335697 << + assign _theResult___snd__h377846 = + sfd__h335695 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ; - assign _theResult___snd__h397114 = { _theResult____h388994[55:0], 1'd0 } ; - assign _theResult___snd__h397125 = - (!_theResult____h388994[56] && _theResult____h388994[55]) ? - _theResult___snd__h397127 : - _theResult___snd__h397137 ; - assign _theResult___snd__h397127 = { _theResult____h388994[54:0], 2'd0 } ; - assign _theResult___snd__h397137 = - (!_theResult____h388994[56] && !_theResult____h388994[55] && - !_theResult____h388994[54] && - !_theResult____h388994[53] && - !_theResult____h388994[52] && - !_theResult____h388994[51] && - !_theResult____h388994[50] && - !_theResult____h388994[49] && - !_theResult____h388994[48] && - !_theResult____h388994[47] && - !_theResult____h388994[46] && - !_theResult____h388994[45] && - !_theResult____h388994[44] && - !_theResult____h388994[43] && - !_theResult____h388994[42] && - !_theResult____h388994[41] && - !_theResult____h388994[40] && - !_theResult____h388994[39] && - !_theResult____h388994[38] && - !_theResult____h388994[37] && - !_theResult____h388994[36] && - !_theResult____h388994[35] && - !_theResult____h388994[34] && - !_theResult____h388994[33] && - !_theResult____h388994[32] && - !_theResult____h388994[31] && - !_theResult____h388994[30] && - !_theResult____h388994[29] && - !_theResult____h388994[28] && - !_theResult____h388994[27] && - !_theResult____h388994[26] && - !_theResult____h388994[25] && - !_theResult____h388994[24] && - !_theResult____h388994[23] && - !_theResult____h388994[22] && - !_theResult____h388994[21] && - !_theResult____h388994[20] && - !_theResult____h388994[19] && - !_theResult____h388994[18] && - !_theResult____h388994[17] && - !_theResult____h388994[16] && - !_theResult____h388994[15] && - !_theResult____h388994[14] && - !_theResult____h388994[13] && - !_theResult____h388994[12] && - !_theResult____h388994[11] && - !_theResult____h388994[10] && - !_theResult____h388994[9] && - !_theResult____h388994[8] && - !_theResult____h388994[7] && - !_theResult____h388994[6] && - !_theResult____h388994[5] && - !_theResult____h388994[4] && - !_theResult____h388994[3] && - !_theResult____h388994[2] && - !_theResult____h388994[1] && - !_theResult____h388994[0]) ? - _theResult____h388994 : - _theResult___snd__h397143 ; - assign _theResult___snd__h397143 = + assign _theResult___snd__h397112 = { _theResult____h388992[55:0], 1'd0 } ; + assign _theResult___snd__h397123 = + (!_theResult____h388992[56] && _theResult____h388992[55]) ? + _theResult___snd__h397125 : + _theResult___snd__h397135 ; + assign _theResult___snd__h397125 = { _theResult____h388992[54:0], 2'd0 } ; + assign _theResult___snd__h397135 = + (!_theResult____h388992[56] && !_theResult____h388992[55] && + !_theResult____h388992[54] && + !_theResult____h388992[53] && + !_theResult____h388992[52] && + !_theResult____h388992[51] && + !_theResult____h388992[50] && + !_theResult____h388992[49] && + !_theResult____h388992[48] && + !_theResult____h388992[47] && + !_theResult____h388992[46] && + !_theResult____h388992[45] && + !_theResult____h388992[44] && + !_theResult____h388992[43] && + !_theResult____h388992[42] && + !_theResult____h388992[41] && + !_theResult____h388992[40] && + !_theResult____h388992[39] && + !_theResult____h388992[38] && + !_theResult____h388992[37] && + !_theResult____h388992[36] && + !_theResult____h388992[35] && + !_theResult____h388992[34] && + !_theResult____h388992[33] && + !_theResult____h388992[32] && + !_theResult____h388992[31] && + !_theResult____h388992[30] && + !_theResult____h388992[29] && + !_theResult____h388992[28] && + !_theResult____h388992[27] && + !_theResult____h388992[26] && + !_theResult____h388992[25] && + !_theResult____h388992[24] && + !_theResult____h388992[23] && + !_theResult____h388992[22] && + !_theResult____h388992[21] && + !_theResult____h388992[20] && + !_theResult____h388992[19] && + !_theResult____h388992[18] && + !_theResult____h388992[17] && + !_theResult____h388992[16] && + !_theResult____h388992[15] && + !_theResult____h388992[14] && + !_theResult____h388992[13] && + !_theResult____h388992[12] && + !_theResult____h388992[11] && + !_theResult____h388992[10] && + !_theResult____h388992[9] && + !_theResult____h388992[8] && + !_theResult____h388992[7] && + !_theResult____h388992[6] && + !_theResult____h388992[5] && + !_theResult____h388992[4] && + !_theResult____h388992[3] && + !_theResult____h388992[2] && + !_theResult____h388992[1] && + !_theResult____h388992[0]) ? + _theResult____h388992 : + _theResult___snd__h397141 ; + assign _theResult___snd__h397141 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55[54:0], 2'd0 } ; - assign _theResult___snd__h397166 = - _theResult____h388994 << + assign _theResult___snd__h397164 = + _theResult____h388992 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ; - assign _theResult___snd__h405710 = + assign _theResult___snd__h405708 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h405719 : - _theResult___snd__h405712 ; - assign _theResult___snd__h405712 = + _theResult___snd__h405717 : + _theResult___snd__h405710 ; + assign _theResult___snd__h405710 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h405719 = + assign _theResult___snd__h405717 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381392 : - _theResult___snd__h405725 ; - assign _theResult___snd__h405725 = + sfd__h381390 : + _theResult___snd__h405723 ; + assign _theResult___snd__h405723 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57[54:0], 2'd0 } ; - assign _theResult___snd__h405748 = - sfd__h381392 << + assign _theResult___snd__h405746 = + sfd__h381390 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ; - assign _theResult___snd__h414880 = { _theResult____h406631[55:0], 1'd0 } ; - assign _theResult___snd__h414891 = - (!_theResult____h406631[56] && _theResult____h406631[55]) ? - _theResult___snd__h414893 : - _theResult___snd__h414903 ; - assign _theResult___snd__h414893 = { _theResult____h406631[54:0], 2'd0 } ; - assign _theResult___snd__h414903 = - (!_theResult____h406631[56] && !_theResult____h406631[55] && - !_theResult____h406631[54] && - !_theResult____h406631[53] && - !_theResult____h406631[52] && - !_theResult____h406631[51] && - !_theResult____h406631[50] && - !_theResult____h406631[49] && - !_theResult____h406631[48] && - !_theResult____h406631[47] && - !_theResult____h406631[46] && - !_theResult____h406631[45] && - !_theResult____h406631[44] && - !_theResult____h406631[43] && - !_theResult____h406631[42] && - !_theResult____h406631[41] && - !_theResult____h406631[40] && - !_theResult____h406631[39] && - !_theResult____h406631[38] && - !_theResult____h406631[37] && - !_theResult____h406631[36] && - !_theResult____h406631[35] && - !_theResult____h406631[34] && - !_theResult____h406631[33] && - !_theResult____h406631[32] && - !_theResult____h406631[31] && - !_theResult____h406631[30] && - !_theResult____h406631[29] && - !_theResult____h406631[28] && - !_theResult____h406631[27] && - !_theResult____h406631[26] && - !_theResult____h406631[25] && - !_theResult____h406631[24] && - !_theResult____h406631[23] && - !_theResult____h406631[22] && - !_theResult____h406631[21] && - !_theResult____h406631[20] && - !_theResult____h406631[19] && - !_theResult____h406631[18] && - !_theResult____h406631[17] && - !_theResult____h406631[16] && - !_theResult____h406631[15] && - !_theResult____h406631[14] && - !_theResult____h406631[13] && - !_theResult____h406631[12] && - !_theResult____h406631[11] && - !_theResult____h406631[10] && - !_theResult____h406631[9] && - !_theResult____h406631[8] && - !_theResult____h406631[7] && - !_theResult____h406631[6] && - !_theResult____h406631[5] && - !_theResult____h406631[4] && - !_theResult____h406631[3] && - !_theResult____h406631[2] && - !_theResult____h406631[1] && - !_theResult____h406631[0]) ? - _theResult____h406631 : - _theResult___snd__h414909 ; - assign _theResult___snd__h414909 = + assign _theResult___snd__h414878 = { _theResult____h406629[55:0], 1'd0 } ; + assign _theResult___snd__h414889 = + (!_theResult____h406629[56] && _theResult____h406629[55]) ? + _theResult___snd__h414891 : + _theResult___snd__h414901 ; + assign _theResult___snd__h414891 = { _theResult____h406629[54:0], 2'd0 } ; + assign _theResult___snd__h414901 = + (!_theResult____h406629[56] && !_theResult____h406629[55] && + !_theResult____h406629[54] && + !_theResult____h406629[53] && + !_theResult____h406629[52] && + !_theResult____h406629[51] && + !_theResult____h406629[50] && + !_theResult____h406629[49] && + !_theResult____h406629[48] && + !_theResult____h406629[47] && + !_theResult____h406629[46] && + !_theResult____h406629[45] && + !_theResult____h406629[44] && + !_theResult____h406629[43] && + !_theResult____h406629[42] && + !_theResult____h406629[41] && + !_theResult____h406629[40] && + !_theResult____h406629[39] && + !_theResult____h406629[38] && + !_theResult____h406629[37] && + !_theResult____h406629[36] && + !_theResult____h406629[35] && + !_theResult____h406629[34] && + !_theResult____h406629[33] && + !_theResult____h406629[32] && + !_theResult____h406629[31] && + !_theResult____h406629[30] && + !_theResult____h406629[29] && + !_theResult____h406629[28] && + !_theResult____h406629[27] && + !_theResult____h406629[26] && + !_theResult____h406629[25] && + !_theResult____h406629[24] && + !_theResult____h406629[23] && + !_theResult____h406629[22] && + !_theResult____h406629[21] && + !_theResult____h406629[20] && + !_theResult____h406629[19] && + !_theResult____h406629[18] && + !_theResult____h406629[17] && + !_theResult____h406629[16] && + !_theResult____h406629[15] && + !_theResult____h406629[14] && + !_theResult____h406629[13] && + !_theResult____h406629[12] && + !_theResult____h406629[11] && + !_theResult____h406629[10] && + !_theResult____h406629[9] && + !_theResult____h406629[8] && + !_theResult____h406629[7] && + !_theResult____h406629[6] && + !_theResult____h406629[5] && + !_theResult____h406629[4] && + !_theResult____h406629[3] && + !_theResult____h406629[2] && + !_theResult____h406629[1] && + !_theResult____h406629[0]) ? + _theResult____h406629 : + _theResult___snd__h414907 ; + assign _theResult___snd__h414907 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h414932 = - _theResult____h406631 << + assign _theResult___snd__h414930 = + _theResult____h406629 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ; - assign _theResult___snd__h423500 = + assign _theResult___snd__h423498 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h423514 : - _theResult___snd__h405712 ; - assign _theResult___snd__h423514 = + _theResult___snd__h423512 : + _theResult___snd__h405710 ; + assign _theResult___snd__h423512 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381392 : - _theResult___snd__h423520 ; - assign _theResult___snd__h423520 = + sfd__h381390 : + _theResult___snd__h423518 ; + assign _theResult___snd__h423518 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70[54:0], 2'd0 } ; - assign _theResult___snd__h423538 = - sfd__h381392 << + assign _theResult___snd__h423536 = + sfd__h381390 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ; - assign _theResult___snd__h442802 = { _theResult____h434682[55:0], 1'd0 } ; - assign _theResult___snd__h442813 = - (!_theResult____h434682[56] && _theResult____h434682[55]) ? - _theResult___snd__h442815 : - _theResult___snd__h442825 ; - assign _theResult___snd__h442815 = { _theResult____h434682[54:0], 2'd0 } ; - assign _theResult___snd__h442825 = - (!_theResult____h434682[56] && !_theResult____h434682[55] && - !_theResult____h434682[54] && - !_theResult____h434682[53] && - !_theResult____h434682[52] && - !_theResult____h434682[51] && - !_theResult____h434682[50] && - !_theResult____h434682[49] && - !_theResult____h434682[48] && - !_theResult____h434682[47] && - !_theResult____h434682[46] && - !_theResult____h434682[45] && - !_theResult____h434682[44] && - !_theResult____h434682[43] && - !_theResult____h434682[42] && - !_theResult____h434682[41] && - !_theResult____h434682[40] && - !_theResult____h434682[39] && - !_theResult____h434682[38] && - !_theResult____h434682[37] && - !_theResult____h434682[36] && - !_theResult____h434682[35] && - !_theResult____h434682[34] && - !_theResult____h434682[33] && - !_theResult____h434682[32] && - !_theResult____h434682[31] && - !_theResult____h434682[30] && - !_theResult____h434682[29] && - !_theResult____h434682[28] && - !_theResult____h434682[27] && - !_theResult____h434682[26] && - !_theResult____h434682[25] && - !_theResult____h434682[24] && - !_theResult____h434682[23] && - !_theResult____h434682[22] && - !_theResult____h434682[21] && - !_theResult____h434682[20] && - !_theResult____h434682[19] && - !_theResult____h434682[18] && - !_theResult____h434682[17] && - !_theResult____h434682[16] && - !_theResult____h434682[15] && - !_theResult____h434682[14] && - !_theResult____h434682[13] && - !_theResult____h434682[12] && - !_theResult____h434682[11] && - !_theResult____h434682[10] && - !_theResult____h434682[9] && - !_theResult____h434682[8] && - !_theResult____h434682[7] && - !_theResult____h434682[6] && - !_theResult____h434682[5] && - !_theResult____h434682[4] && - !_theResult____h434682[3] && - !_theResult____h434682[2] && - !_theResult____h434682[1] && - !_theResult____h434682[0]) ? - _theResult____h434682 : - _theResult___snd__h442831 ; - assign _theResult___snd__h442831 = + assign _theResult___snd__h442800 = { _theResult____h434680[55:0], 1'd0 } ; + assign _theResult___snd__h442811 = + (!_theResult____h434680[56] && _theResult____h434680[55]) ? + _theResult___snd__h442813 : + _theResult___snd__h442823 ; + assign _theResult___snd__h442813 = { _theResult____h434680[54:0], 2'd0 } ; + assign _theResult___snd__h442823 = + (!_theResult____h434680[56] && !_theResult____h434680[55] && + !_theResult____h434680[54] && + !_theResult____h434680[53] && + !_theResult____h434680[52] && + !_theResult____h434680[51] && + !_theResult____h434680[50] && + !_theResult____h434680[49] && + !_theResult____h434680[48] && + !_theResult____h434680[47] && + !_theResult____h434680[46] && + !_theResult____h434680[45] && + !_theResult____h434680[44] && + !_theResult____h434680[43] && + !_theResult____h434680[42] && + !_theResult____h434680[41] && + !_theResult____h434680[40] && + !_theResult____h434680[39] && + !_theResult____h434680[38] && + !_theResult____h434680[37] && + !_theResult____h434680[36] && + !_theResult____h434680[35] && + !_theResult____h434680[34] && + !_theResult____h434680[33] && + !_theResult____h434680[32] && + !_theResult____h434680[31] && + !_theResult____h434680[30] && + !_theResult____h434680[29] && + !_theResult____h434680[28] && + !_theResult____h434680[27] && + !_theResult____h434680[26] && + !_theResult____h434680[25] && + !_theResult____h434680[24] && + !_theResult____h434680[23] && + !_theResult____h434680[22] && + !_theResult____h434680[21] && + !_theResult____h434680[20] && + !_theResult____h434680[19] && + !_theResult____h434680[18] && + !_theResult____h434680[17] && + !_theResult____h434680[16] && + !_theResult____h434680[15] && + !_theResult____h434680[14] && + !_theResult____h434680[13] && + !_theResult____h434680[12] && + !_theResult____h434680[11] && + !_theResult____h434680[10] && + !_theResult____h434680[9] && + !_theResult____h434680[8] && + !_theResult____h434680[7] && + !_theResult____h434680[6] && + !_theResult____h434680[5] && + !_theResult____h434680[4] && + !_theResult____h434680[3] && + !_theResult____h434680[2] && + !_theResult____h434680[1] && + !_theResult____h434680[0]) ? + _theResult____h434680 : + _theResult___snd__h442829 ; + assign _theResult___snd__h442829 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90[54:0], 2'd0 } ; - assign _theResult___snd__h442854 = - _theResult____h434682 << + assign _theResult___snd__h442852 = + _theResult____h434680 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ; - assign _theResult___snd__h451398 = + assign _theResult___snd__h451396 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h451407 : - _theResult___snd__h451400 ; - assign _theResult___snd__h451400 = + _theResult___snd__h451405 : + _theResult___snd__h451398 ; + assign _theResult___snd__h451398 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h451407 = + assign _theResult___snd__h451405 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427080 : - _theResult___snd__h451413 ; - assign _theResult___snd__h451413 = + sfd__h427078 : + _theResult___snd__h451411 ; + assign _theResult___snd__h451411 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92[54:0], 2'd0 } ; - assign _theResult___snd__h451436 = - sfd__h427080 << + assign _theResult___snd__h451434 = + sfd__h427078 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ; - assign _theResult___snd__h460568 = { _theResult____h452319[55:0], 1'd0 } ; - assign _theResult___snd__h460579 = - (!_theResult____h452319[56] && _theResult____h452319[55]) ? - _theResult___snd__h460581 : - _theResult___snd__h460591 ; - assign _theResult___snd__h460581 = { _theResult____h452319[54:0], 2'd0 } ; - assign _theResult___snd__h460591 = - (!_theResult____h452319[56] && !_theResult____h452319[55] && - !_theResult____h452319[54] && - !_theResult____h452319[53] && - !_theResult____h452319[52] && - !_theResult____h452319[51] && - !_theResult____h452319[50] && - !_theResult____h452319[49] && - !_theResult____h452319[48] && - !_theResult____h452319[47] && - !_theResult____h452319[46] && - !_theResult____h452319[45] && - !_theResult____h452319[44] && - !_theResult____h452319[43] && - !_theResult____h452319[42] && - !_theResult____h452319[41] && - !_theResult____h452319[40] && - !_theResult____h452319[39] && - !_theResult____h452319[38] && - !_theResult____h452319[37] && - !_theResult____h452319[36] && - !_theResult____h452319[35] && - !_theResult____h452319[34] && - !_theResult____h452319[33] && - !_theResult____h452319[32] && - !_theResult____h452319[31] && - !_theResult____h452319[30] && - !_theResult____h452319[29] && - !_theResult____h452319[28] && - !_theResult____h452319[27] && - !_theResult____h452319[26] && - !_theResult____h452319[25] && - !_theResult____h452319[24] && - !_theResult____h452319[23] && - !_theResult____h452319[22] && - !_theResult____h452319[21] && - !_theResult____h452319[20] && - !_theResult____h452319[19] && - !_theResult____h452319[18] && - !_theResult____h452319[17] && - !_theResult____h452319[16] && - !_theResult____h452319[15] && - !_theResult____h452319[14] && - !_theResult____h452319[13] && - !_theResult____h452319[12] && - !_theResult____h452319[11] && - !_theResult____h452319[10] && - !_theResult____h452319[9] && - !_theResult____h452319[8] && - !_theResult____h452319[7] && - !_theResult____h452319[6] && - !_theResult____h452319[5] && - !_theResult____h452319[4] && - !_theResult____h452319[3] && - !_theResult____h452319[2] && - !_theResult____h452319[1] && - !_theResult____h452319[0]) ? - _theResult____h452319 : - _theResult___snd__h460597 ; - assign _theResult___snd__h460597 = + assign _theResult___snd__h460566 = { _theResult____h452317[55:0], 1'd0 } ; + assign _theResult___snd__h460577 = + (!_theResult____h452317[56] && _theResult____h452317[55]) ? + _theResult___snd__h460579 : + _theResult___snd__h460589 ; + assign _theResult___snd__h460579 = { _theResult____h452317[54:0], 2'd0 } ; + assign _theResult___snd__h460589 = + (!_theResult____h452317[56] && !_theResult____h452317[55] && + !_theResult____h452317[54] && + !_theResult____h452317[53] && + !_theResult____h452317[52] && + !_theResult____h452317[51] && + !_theResult____h452317[50] && + !_theResult____h452317[49] && + !_theResult____h452317[48] && + !_theResult____h452317[47] && + !_theResult____h452317[46] && + !_theResult____h452317[45] && + !_theResult____h452317[44] && + !_theResult____h452317[43] && + !_theResult____h452317[42] && + !_theResult____h452317[41] && + !_theResult____h452317[40] && + !_theResult____h452317[39] && + !_theResult____h452317[38] && + !_theResult____h452317[37] && + !_theResult____h452317[36] && + !_theResult____h452317[35] && + !_theResult____h452317[34] && + !_theResult____h452317[33] && + !_theResult____h452317[32] && + !_theResult____h452317[31] && + !_theResult____h452317[30] && + !_theResult____h452317[29] && + !_theResult____h452317[28] && + !_theResult____h452317[27] && + !_theResult____h452317[26] && + !_theResult____h452317[25] && + !_theResult____h452317[24] && + !_theResult____h452317[23] && + !_theResult____h452317[22] && + !_theResult____h452317[21] && + !_theResult____h452317[20] && + !_theResult____h452317[19] && + !_theResult____h452317[18] && + !_theResult____h452317[17] && + !_theResult____h452317[16] && + !_theResult____h452317[15] && + !_theResult____h452317[14] && + !_theResult____h452317[13] && + !_theResult____h452317[12] && + !_theResult____h452317[11] && + !_theResult____h452317[10] && + !_theResult____h452317[9] && + !_theResult____h452317[8] && + !_theResult____h452317[7] && + !_theResult____h452317[6] && + !_theResult____h452317[5] && + !_theResult____h452317[4] && + !_theResult____h452317[3] && + !_theResult____h452317[2] && + !_theResult____h452317[1] && + !_theResult____h452317[0]) ? + _theResult____h452317 : + _theResult___snd__h460595 ; + assign _theResult___snd__h460595 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h460620 = - _theResult____h452319 << + assign _theResult___snd__h460618 = + _theResult____h452317 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ; - assign _theResult___snd__h469188 = + assign _theResult___snd__h469186 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h469202 : - _theResult___snd__h451400 ; - assign _theResult___snd__h469202 = + _theResult___snd__h469200 : + _theResult___snd__h451398 ; + assign _theResult___snd__h469200 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427080 : - _theResult___snd__h469208 ; - assign _theResult___snd__h469208 = + sfd__h427078 : + _theResult___snd__h469206 ; + assign _theResult___snd__h469206 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105[54:0], 2'd0 } ; - assign _theResult___snd__h469226 = - sfd__h427080 << + assign _theResult___snd__h469224 = + sfd__h427078 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ; - assign _theResult___snd__h498627 = + assign _theResult___snd__h498625 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h498636 : - _theResult___snd__h498629 ; - assign _theResult___snd__h498629 = + _theResult___snd__h498634 : + _theResult___snd__h498627 ; + assign _theResult___snd__h498627 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ; - assign _theResult___snd__h498636 = + assign _theResult___snd__h498634 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479675 : - _theResult___snd__h498642 ; - assign _theResult___snd__h498642 = + sfd__h479673 : + _theResult___snd__h498640 ; + assign _theResult___snd__h498640 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h498665 = - sfd__h479675 << + assign _theResult___snd__h498663 = + sfd__h479673 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 ; - assign _theResult___snd__h508264 = { _theResult____h500017[55:0], 1'd0 } ; - assign _theResult___snd__h508275 = - (!_theResult____h500017[56] && _theResult____h500017[55]) ? - _theResult___snd__h508277 : - _theResult___snd__h508287 ; - assign _theResult___snd__h508277 = { _theResult____h500017[54:0], 2'd0 } ; - assign _theResult___snd__h508287 = - (!_theResult____h500017[56] && !_theResult____h500017[55] && - !_theResult____h500017[54] && - !_theResult____h500017[53] && - !_theResult____h500017[52] && - !_theResult____h500017[51] && - !_theResult____h500017[50] && - !_theResult____h500017[49] && - !_theResult____h500017[48] && - !_theResult____h500017[47] && - !_theResult____h500017[46] && - !_theResult____h500017[45] && - !_theResult____h500017[44] && - !_theResult____h500017[43] && - !_theResult____h500017[42] && - !_theResult____h500017[41] && - !_theResult____h500017[40] && - !_theResult____h500017[39] && - !_theResult____h500017[38] && - !_theResult____h500017[37] && - !_theResult____h500017[36] && - !_theResult____h500017[35] && - !_theResult____h500017[34] && - !_theResult____h500017[33] && - !_theResult____h500017[32] && - !_theResult____h500017[31] && - !_theResult____h500017[30] && - !_theResult____h500017[29] && - !_theResult____h500017[28] && - !_theResult____h500017[27] && - !_theResult____h500017[26] && - !_theResult____h500017[25] && - !_theResult____h500017[24] && - !_theResult____h500017[23] && - !_theResult____h500017[22] && - !_theResult____h500017[21] && - !_theResult____h500017[20] && - !_theResult____h500017[19] && - !_theResult____h500017[18] && - !_theResult____h500017[17] && - !_theResult____h500017[16] && - !_theResult____h500017[15] && - !_theResult____h500017[14] && - !_theResult____h500017[13] && - !_theResult____h500017[12] && - !_theResult____h500017[11] && - !_theResult____h500017[10] && - !_theResult____h500017[9] && - !_theResult____h500017[8] && - !_theResult____h500017[7] && - !_theResult____h500017[6] && - !_theResult____h500017[5] && - !_theResult____h500017[4] && - !_theResult____h500017[3] && - !_theResult____h500017[2] && - !_theResult____h500017[1] && - !_theResult____h500017[0]) ? - _theResult____h500017 : - _theResult___snd__h508293 ; - assign _theResult___snd__h508293 = + assign _theResult___snd__h508262 = { _theResult____h500015[55:0], 1'd0 } ; + assign _theResult___snd__h508273 = + (!_theResult____h500015[56] && _theResult____h500015[55]) ? + _theResult___snd__h508275 : + _theResult___snd__h508285 ; + assign _theResult___snd__h508275 = { _theResult____h500015[54:0], 2'd0 } ; + assign _theResult___snd__h508285 = + (!_theResult____h500015[56] && !_theResult____h500015[55] && + !_theResult____h500015[54] && + !_theResult____h500015[53] && + !_theResult____h500015[52] && + !_theResult____h500015[51] && + !_theResult____h500015[50] && + !_theResult____h500015[49] && + !_theResult____h500015[48] && + !_theResult____h500015[47] && + !_theResult____h500015[46] && + !_theResult____h500015[45] && + !_theResult____h500015[44] && + !_theResult____h500015[43] && + !_theResult____h500015[42] && + !_theResult____h500015[41] && + !_theResult____h500015[40] && + !_theResult____h500015[39] && + !_theResult____h500015[38] && + !_theResult____h500015[37] && + !_theResult____h500015[36] && + !_theResult____h500015[35] && + !_theResult____h500015[34] && + !_theResult____h500015[33] && + !_theResult____h500015[32] && + !_theResult____h500015[31] && + !_theResult____h500015[30] && + !_theResult____h500015[29] && + !_theResult____h500015[28] && + !_theResult____h500015[27] && + !_theResult____h500015[26] && + !_theResult____h500015[25] && + !_theResult____h500015[24] && + !_theResult____h500015[23] && + !_theResult____h500015[22] && + !_theResult____h500015[21] && + !_theResult____h500015[20] && + !_theResult____h500015[19] && + !_theResult____h500015[18] && + !_theResult____h500015[17] && + !_theResult____h500015[16] && + !_theResult____h500015[15] && + !_theResult____h500015[14] && + !_theResult____h500015[13] && + !_theResult____h500015[12] && + !_theResult____h500015[11] && + !_theResult____h500015[10] && + !_theResult____h500015[9] && + !_theResult____h500015[8] && + !_theResult____h500015[7] && + !_theResult____h500015[6] && + !_theResult____h500015[5] && + !_theResult____h500015[4] && + !_theResult____h500015[3] && + !_theResult____h500015[2] && + !_theResult____h500015[1] && + !_theResult____h500015[0]) ? + _theResult____h500015 : + _theResult___snd__h508291 ; + assign _theResult___snd__h508291 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h508316 = - _theResult____h500017 << + assign _theResult___snd__h508314 = + _theResult____h500015 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 ; - assign _theResult___snd__h517032 = + assign _theResult___snd__h517030 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h517046 : - _theResult___snd__h498629 ; - assign _theResult___snd__h517046 = + _theResult___snd__h517044 : + _theResult___snd__h498627 ; + assign _theResult___snd__h517044 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479675 : - _theResult___snd__h517052 ; - assign _theResult___snd__h517052 = + sfd__h479673 : + _theResult___snd__h517050 ; + assign _theResult___snd__h517050 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h517070 = - sfd__h479675 << + assign _theResult___snd__h517068 = + sfd__h479673 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 ; - assign _theResult___snd__h537428 = + assign _theResult___snd__h537426 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h537437 : - _theResult___snd__h537430 ; - assign _theResult___snd__h537430 = + _theResult___snd__h537435 : + _theResult___snd__h537428 ; + assign _theResult___snd__h537428 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ; - assign _theResult___snd__h537437 = + assign _theResult___snd__h537435 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518617 : - _theResult___snd__h537443 ; - assign _theResult___snd__h537443 = + sfd__h518615 : + _theResult___snd__h537441 ; + assign _theResult___snd__h537441 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h537466 = - sfd__h518617 << + assign _theResult___snd__h537464 = + sfd__h518615 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 ; - assign _theResult___snd__h547065 = { _theResult____h538818[55:0], 1'd0 } ; - assign _theResult___snd__h547076 = - (!_theResult____h538818[56] && _theResult____h538818[55]) ? - _theResult___snd__h547078 : - _theResult___snd__h547088 ; - assign _theResult___snd__h547078 = { _theResult____h538818[54:0], 2'd0 } ; - assign _theResult___snd__h547088 = - (!_theResult____h538818[56] && !_theResult____h538818[55] && - !_theResult____h538818[54] && - !_theResult____h538818[53] && - !_theResult____h538818[52] && - !_theResult____h538818[51] && - !_theResult____h538818[50] && - !_theResult____h538818[49] && - !_theResult____h538818[48] && - !_theResult____h538818[47] && - !_theResult____h538818[46] && - !_theResult____h538818[45] && - !_theResult____h538818[44] && - !_theResult____h538818[43] && - !_theResult____h538818[42] && - !_theResult____h538818[41] && - !_theResult____h538818[40] && - !_theResult____h538818[39] && - !_theResult____h538818[38] && - !_theResult____h538818[37] && - !_theResult____h538818[36] && - !_theResult____h538818[35] && - !_theResult____h538818[34] && - !_theResult____h538818[33] && - !_theResult____h538818[32] && - !_theResult____h538818[31] && - !_theResult____h538818[30] && - !_theResult____h538818[29] && - !_theResult____h538818[28] && - !_theResult____h538818[27] && - !_theResult____h538818[26] && - !_theResult____h538818[25] && - !_theResult____h538818[24] && - !_theResult____h538818[23] && - !_theResult____h538818[22] && - !_theResult____h538818[21] && - !_theResult____h538818[20] && - !_theResult____h538818[19] && - !_theResult____h538818[18] && - !_theResult____h538818[17] && - !_theResult____h538818[16] && - !_theResult____h538818[15] && - !_theResult____h538818[14] && - !_theResult____h538818[13] && - !_theResult____h538818[12] && - !_theResult____h538818[11] && - !_theResult____h538818[10] && - !_theResult____h538818[9] && - !_theResult____h538818[8] && - !_theResult____h538818[7] && - !_theResult____h538818[6] && - !_theResult____h538818[5] && - !_theResult____h538818[4] && - !_theResult____h538818[3] && - !_theResult____h538818[2] && - !_theResult____h538818[1] && - !_theResult____h538818[0]) ? - _theResult____h538818 : - _theResult___snd__h547094 ; - assign _theResult___snd__h547094 = + assign _theResult___snd__h547063 = { _theResult____h538816[55:0], 1'd0 } ; + assign _theResult___snd__h547074 = + (!_theResult____h538816[56] && _theResult____h538816[55]) ? + _theResult___snd__h547076 : + _theResult___snd__h547086 ; + assign _theResult___snd__h547076 = { _theResult____h538816[54:0], 2'd0 } ; + assign _theResult___snd__h547086 = + (!_theResult____h538816[56] && !_theResult____h538816[55] && + !_theResult____h538816[54] && + !_theResult____h538816[53] && + !_theResult____h538816[52] && + !_theResult____h538816[51] && + !_theResult____h538816[50] && + !_theResult____h538816[49] && + !_theResult____h538816[48] && + !_theResult____h538816[47] && + !_theResult____h538816[46] && + !_theResult____h538816[45] && + !_theResult____h538816[44] && + !_theResult____h538816[43] && + !_theResult____h538816[42] && + !_theResult____h538816[41] && + !_theResult____h538816[40] && + !_theResult____h538816[39] && + !_theResult____h538816[38] && + !_theResult____h538816[37] && + !_theResult____h538816[36] && + !_theResult____h538816[35] && + !_theResult____h538816[34] && + !_theResult____h538816[33] && + !_theResult____h538816[32] && + !_theResult____h538816[31] && + !_theResult____h538816[30] && + !_theResult____h538816[29] && + !_theResult____h538816[28] && + !_theResult____h538816[27] && + !_theResult____h538816[26] && + !_theResult____h538816[25] && + !_theResult____h538816[24] && + !_theResult____h538816[23] && + !_theResult____h538816[22] && + !_theResult____h538816[21] && + !_theResult____h538816[20] && + !_theResult____h538816[19] && + !_theResult____h538816[18] && + !_theResult____h538816[17] && + !_theResult____h538816[16] && + !_theResult____h538816[15] && + !_theResult____h538816[14] && + !_theResult____h538816[13] && + !_theResult____h538816[12] && + !_theResult____h538816[11] && + !_theResult____h538816[10] && + !_theResult____h538816[9] && + !_theResult____h538816[8] && + !_theResult____h538816[7] && + !_theResult____h538816[6] && + !_theResult____h538816[5] && + !_theResult____h538816[4] && + !_theResult____h538816[3] && + !_theResult____h538816[2] && + !_theResult____h538816[1] && + !_theResult____h538816[0]) ? + _theResult____h538816 : + _theResult___snd__h547092 ; + assign _theResult___snd__h547092 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h547117 = - _theResult____h538818 << + assign _theResult___snd__h547115 = + _theResult____h538816 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 ; - assign _theResult___snd__h555833 = + assign _theResult___snd__h555831 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h555847 : - _theResult___snd__h537430 ; - assign _theResult___snd__h555847 = + _theResult___snd__h555845 : + _theResult___snd__h537428 ; + assign _theResult___snd__h555845 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518617 : - _theResult___snd__h555853 ; - assign _theResult___snd__h555853 = + sfd__h518615 : + _theResult___snd__h555851 ; + assign _theResult___snd__h555851 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h555871 = - sfd__h518617 << + assign _theResult___snd__h555869 = + sfd__h518615 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 ; - assign _theResult___snd__h576629 = + assign _theResult___snd__h576627 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h576638 : - _theResult___snd__h576631 ; - assign _theResult___snd__h576631 = + _theResult___snd__h576636 : + _theResult___snd__h576629 ; + assign _theResult___snd__h576629 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ; - assign _theResult___snd__h576638 = + assign _theResult___snd__h576636 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557818 : - _theResult___snd__h576644 ; - assign _theResult___snd__h576644 = + sfd__h557816 : + _theResult___snd__h576642 ; + assign _theResult___snd__h576642 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h576667 = - sfd__h557818 << + assign _theResult___snd__h576665 = + sfd__h557816 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 ; - assign _theResult___snd__h586266 = { _theResult____h578019[55:0], 1'd0 } ; - assign _theResult___snd__h586277 = - (!_theResult____h578019[56] && _theResult____h578019[55]) ? - _theResult___snd__h586279 : - _theResult___snd__h586289 ; - assign _theResult___snd__h586279 = { _theResult____h578019[54:0], 2'd0 } ; - assign _theResult___snd__h586289 = - (!_theResult____h578019[56] && !_theResult____h578019[55] && - !_theResult____h578019[54] && - !_theResult____h578019[53] && - !_theResult____h578019[52] && - !_theResult____h578019[51] && - !_theResult____h578019[50] && - !_theResult____h578019[49] && - !_theResult____h578019[48] && - !_theResult____h578019[47] && - !_theResult____h578019[46] && - !_theResult____h578019[45] && - !_theResult____h578019[44] && - !_theResult____h578019[43] && - !_theResult____h578019[42] && - !_theResult____h578019[41] && - !_theResult____h578019[40] && - !_theResult____h578019[39] && - !_theResult____h578019[38] && - !_theResult____h578019[37] && - !_theResult____h578019[36] && - !_theResult____h578019[35] && - !_theResult____h578019[34] && - !_theResult____h578019[33] && - !_theResult____h578019[32] && - !_theResult____h578019[31] && - !_theResult____h578019[30] && - !_theResult____h578019[29] && - !_theResult____h578019[28] && - !_theResult____h578019[27] && - !_theResult____h578019[26] && - !_theResult____h578019[25] && - !_theResult____h578019[24] && - !_theResult____h578019[23] && - !_theResult____h578019[22] && - !_theResult____h578019[21] && - !_theResult____h578019[20] && - !_theResult____h578019[19] && - !_theResult____h578019[18] && - !_theResult____h578019[17] && - !_theResult____h578019[16] && - !_theResult____h578019[15] && - !_theResult____h578019[14] && - !_theResult____h578019[13] && - !_theResult____h578019[12] && - !_theResult____h578019[11] && - !_theResult____h578019[10] && - !_theResult____h578019[9] && - !_theResult____h578019[8] && - !_theResult____h578019[7] && - !_theResult____h578019[6] && - !_theResult____h578019[5] && - !_theResult____h578019[4] && - !_theResult____h578019[3] && - !_theResult____h578019[2] && - !_theResult____h578019[1] && - !_theResult____h578019[0]) ? - _theResult____h578019 : - _theResult___snd__h586295 ; - assign _theResult___snd__h586295 = + assign _theResult___snd__h586264 = { _theResult____h578017[55:0], 1'd0 } ; + assign _theResult___snd__h586275 = + (!_theResult____h578017[56] && _theResult____h578017[55]) ? + _theResult___snd__h586277 : + _theResult___snd__h586287 ; + assign _theResult___snd__h586277 = { _theResult____h578017[54:0], 2'd0 } ; + assign _theResult___snd__h586287 = + (!_theResult____h578017[56] && !_theResult____h578017[55] && + !_theResult____h578017[54] && + !_theResult____h578017[53] && + !_theResult____h578017[52] && + !_theResult____h578017[51] && + !_theResult____h578017[50] && + !_theResult____h578017[49] && + !_theResult____h578017[48] && + !_theResult____h578017[47] && + !_theResult____h578017[46] && + !_theResult____h578017[45] && + !_theResult____h578017[44] && + !_theResult____h578017[43] && + !_theResult____h578017[42] && + !_theResult____h578017[41] && + !_theResult____h578017[40] && + !_theResult____h578017[39] && + !_theResult____h578017[38] && + !_theResult____h578017[37] && + !_theResult____h578017[36] && + !_theResult____h578017[35] && + !_theResult____h578017[34] && + !_theResult____h578017[33] && + !_theResult____h578017[32] && + !_theResult____h578017[31] && + !_theResult____h578017[30] && + !_theResult____h578017[29] && + !_theResult____h578017[28] && + !_theResult____h578017[27] && + !_theResult____h578017[26] && + !_theResult____h578017[25] && + !_theResult____h578017[24] && + !_theResult____h578017[23] && + !_theResult____h578017[22] && + !_theResult____h578017[21] && + !_theResult____h578017[20] && + !_theResult____h578017[19] && + !_theResult____h578017[18] && + !_theResult____h578017[17] && + !_theResult____h578017[16] && + !_theResult____h578017[15] && + !_theResult____h578017[14] && + !_theResult____h578017[13] && + !_theResult____h578017[12] && + !_theResult____h578017[11] && + !_theResult____h578017[10] && + !_theResult____h578017[9] && + !_theResult____h578017[8] && + !_theResult____h578017[7] && + !_theResult____h578017[6] && + !_theResult____h578017[5] && + !_theResult____h578017[4] && + !_theResult____h578017[3] && + !_theResult____h578017[2] && + !_theResult____h578017[1] && + !_theResult____h578017[0]) ? + _theResult____h578017 : + _theResult___snd__h586293 ; + assign _theResult___snd__h586293 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h586318 = - _theResult____h578019 << + assign _theResult___snd__h586316 = + _theResult____h578017 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 ; - assign _theResult___snd__h595034 = + assign _theResult___snd__h595032 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h595048 : - _theResult___snd__h576631 ; - assign _theResult___snd__h595048 = + _theResult___snd__h595046 : + _theResult___snd__h576629 ; + assign _theResult___snd__h595046 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557818 : - _theResult___snd__h595054 ; - assign _theResult___snd__h595054 = + sfd__h557816 : + _theResult___snd__h595052 ; + assign _theResult___snd__h595052 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h595072 = - sfd__h557818 << + assign _theResult___snd__h595070 = + sfd__h557816 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648 ; - assign _theResult___snd__h600262 = - b__h599840[63] ? b___1__h600311 : b__h599840 ; - assign _theResult___snd_fst_exp__h360595 = + assign _theResult___snd__h600260 = + b__h599838[63] ? b___1__h600309 : b__h599838 ; + assign _theResult___snd_fst_exp__h360593 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_exp__h352010 : - _theResult___fst_exp__h360592 ; - assign _theResult___snd_fst_exp__h378415 = + _theResult___fst_exp__h352008 : + _theResult___fst_exp__h360590 ; + assign _theResult___snd_fst_exp__h378413 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_exp__h369776 : - _theResult___fst_exp__h378412 ; - assign _theResult___snd_fst_exp__h406285 = + _theResult___fst_exp__h369774 : + _theResult___fst_exp__h378410 ; + assign _theResult___snd_fst_exp__h406283 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_exp__h397700 : - _theResult___fst_exp__h406282 ; - assign _theResult___snd_fst_exp__h424105 = + _theResult___fst_exp__h397698 : + _theResult___fst_exp__h406280 ; + assign _theResult___snd_fst_exp__h424103 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_exp__h415466 : - _theResult___fst_exp__h424102 ; - assign _theResult___snd_fst_exp__h451973 = + _theResult___fst_exp__h415464 : + _theResult___fst_exp__h424100 ; + assign _theResult___snd_fst_exp__h451971 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_exp__h443388 : - _theResult___fst_exp__h451970 ; - assign _theResult___snd_fst_exp__h469793 = + _theResult___fst_exp__h443386 : + _theResult___fst_exp__h451968 ; + assign _theResult___snd_fst_exp__h469791 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_exp__h461154 : - _theResult___fst_exp__h469790 ; - assign _theResult___snd_fst_exp__h499437 = + _theResult___fst_exp__h461152 : + _theResult___fst_exp__h469788 ; + assign _theResult___snd_fst_exp__h499435 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 11'd0 : - _theResult___fst_exp__h499434 ; - assign _theResult___snd_fst_exp__h517872 = + _theResult___fst_exp__h499432 ; + assign _theResult___snd_fst_exp__h517870 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_exp__h509085 : - _theResult___fst_exp__h517869 ; - assign _theResult___snd_fst_exp__h538238 = + _theResult___fst_exp__h509083 : + _theResult___fst_exp__h517867 ; + assign _theResult___snd_fst_exp__h538236 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 11'd0 : - _theResult___fst_exp__h538235 ; - assign _theResult___snd_fst_exp__h556673 = + _theResult___fst_exp__h538233 ; + assign _theResult___snd_fst_exp__h556671 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_exp__h547886 : - _theResult___fst_exp__h556670 ; - assign _theResult___snd_fst_exp__h577439 = + _theResult___fst_exp__h547884 : + _theResult___fst_exp__h556668 ; + assign _theResult___snd_fst_exp__h577437 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 11'd0 : - _theResult___fst_exp__h577436 ; - assign _theResult___snd_fst_exp__h595874 = + _theResult___fst_exp__h577434 ; + assign _theResult___snd_fst_exp__h595872 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_exp__h587087 : - _theResult___fst_exp__h595871 ; - assign _theResult___snd_fst_sfd__h335647 = + _theResult___fst_exp__h587085 : + _theResult___fst_exp__h595869 ; + assign _theResult___snd_fst_sfd__h335645 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h360596 = + assign _theResult___snd_fst_sfd__h360594 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_sfd__h352011 : - _theResult___fst_sfd__h360593 ; - assign _theResult___snd_fst_sfd__h378416 = + _theResult___fst_sfd__h352009 : + _theResult___fst_sfd__h360591 ; + assign _theResult___snd_fst_sfd__h378414 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_sfd__h369777 : - _theResult___fst_sfd__h378413 ; - assign _theResult___snd_fst_sfd__h381342 = + _theResult___fst_sfd__h369775 : + _theResult___fst_sfd__h378411 ; + assign _theResult___snd_fst_sfd__h381340 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h406286 = + assign _theResult___snd_fst_sfd__h406284 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_sfd__h397701 : - _theResult___fst_sfd__h406283 ; - assign _theResult___snd_fst_sfd__h424106 = + _theResult___fst_sfd__h397699 : + _theResult___fst_sfd__h406281 ; + assign _theResult___snd_fst_sfd__h424104 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_sfd__h415467 : - _theResult___fst_sfd__h424103 ; - assign _theResult___snd_fst_sfd__h427030 = + _theResult___fst_sfd__h415465 : + _theResult___fst_sfd__h424101 ; + assign _theResult___snd_fst_sfd__h427028 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h451974 = + assign _theResult___snd_fst_sfd__h451972 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_sfd__h443389 : - _theResult___fst_sfd__h451971 ; - assign _theResult___snd_fst_sfd__h469794 = + _theResult___fst_sfd__h443387 : + _theResult___fst_sfd__h451969 ; + assign _theResult___snd_fst_sfd__h469792 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_sfd__h461155 : - _theResult___fst_sfd__h469791 ; - assign _theResult___snd_fst_sfd__h479629 = + _theResult___fst_sfd__h461153 : + _theResult___fst_sfd__h469789 ; + assign _theResult___snd_fst_sfd__h479627 = (coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h479378 ; - assign _theResult___snd_fst_sfd__h499438 = + out___1_sfd__h479376 ; + assign _theResult___snd_fst_sfd__h499436 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 52'd0 : - _theResult___fst_sfd__h499435 ; - assign _theResult___snd_fst_sfd__h517873 = + _theResult___fst_sfd__h499433 ; + assign _theResult___snd_fst_sfd__h517871 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_sfd__h509086 : - _theResult___fst_sfd__h517870 ; - assign _theResult___snd_fst_sfd__h518571 = + _theResult___fst_sfd__h509084 : + _theResult___fst_sfd__h517868 ; + assign _theResult___snd_fst_sfd__h518569 = (coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h518320 ; - assign _theResult___snd_fst_sfd__h538239 = + out___1_sfd__h518318 ; + assign _theResult___snd_fst_sfd__h538237 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 52'd0 : - _theResult___fst_sfd__h538236 ; - assign _theResult___snd_fst_sfd__h556674 = + _theResult___fst_sfd__h538234 ; + assign _theResult___snd_fst_sfd__h556672 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_sfd__h547887 : - _theResult___fst_sfd__h556671 ; - assign _theResult___snd_fst_sfd__h557772 = + _theResult___fst_sfd__h547885 : + _theResult___fst_sfd__h556669 ; + assign _theResult___snd_fst_sfd__h557770 = (coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h557521 ; - assign _theResult___snd_fst_sfd__h577440 = + out___1_sfd__h557519 ; + assign _theResult___snd_fst_sfd__h577438 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 52'd0 : - _theResult___fst_sfd__h577437 ; - assign _theResult___snd_fst_sfd__h595875 = + _theResult___fst_sfd__h577435 ; + assign _theResult___snd_fst_sfd__h595873 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_sfd__h587088 : - _theResult___fst_sfd__h595872 ; - assign a___1__h599980 = + _theResult___fst_sfd__h587086 : + _theResult___fst_sfd__h595870 ; + assign a___1__h599978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 } ; - assign a___1__h600266 = 64'd0 - a__h599839 ; - assign a__h599839 = + assign a___1__h600264 = 64'd0 - a__h599837 ; + assign a__h599837 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h599980 : + a___1__h599978 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h599981 = + assign b___1__h599979 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h600311 = 64'd0 - b__h599840 ; - assign b__h599840 = + assign b___1__h600309 = 64'd0 - b__h599838 ; + assign b__h599838 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h599981 : + b___1__h599979 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h694791 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h694994 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h692189 = - commitStage_commitTrap[4] ? i__h692364 : i__h692204 ; + assign base__h694789 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h694992 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h692187 = + commitStage_commitTrap[4] ? i__h692362 : i__h692202 ; assign coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27353,7 +27353,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h252026 ; + y__h252024 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 || @@ -27707,44 +27707,44 @@ module mkCore(CLK, assign csrf_prv_reg_read__2633_ULT_IF_fetchStage_pipe_ETC___d12871 = csrf_prv_reg < IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[9:8] ; - assign data72481_BITS_31_TO_0__q5 = data__h472481[31:0] ; - assign data___1__h472207 = + assign data72479_BITS_31_TO_0__q5 = data__h472479[31:0] ; + assign data___1__h472205 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 } ; - assign data___1__h473015 = - { {32{data72481_BITS_31_TO_0__q5[31]}}, - data72481_BITS_31_TO_0__q5 } ; - assign data__h472481 = + assign data___1__h473013 = + { {32{data72479_BITS_31_TO_0__q5[31]}}, + data72479_BITS_31_TO_0__q5 } ; + assign data__h472479 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h472395 : - x_remainder__h472396 ; - assign din_inc___2_exp__h378446 = _theResult___fst_exp__h351413 + 8'd1 ; - assign din_inc___2_exp__h378470 = _theResult___fst_exp__h360069 + 8'd1 ; - assign din_inc___2_exp__h378500 = _theResult___fst_exp__h369179 + 8'd1 ; - assign din_inc___2_exp__h378524 = _theResult___fst_exp__h377864 + 8'd1 ; - assign din_inc___2_exp__h424136 = _theResult___fst_exp__h397103 + 8'd1 ; - assign din_inc___2_exp__h424160 = _theResult___fst_exp__h405759 + 8'd1 ; - assign din_inc___2_exp__h424190 = _theResult___fst_exp__h414869 + 8'd1 ; - assign din_inc___2_exp__h424214 = _theResult___fst_exp__h423554 + 8'd1 ; - assign din_inc___2_exp__h469824 = _theResult___fst_exp__h442791 + 8'd1 ; - assign din_inc___2_exp__h469848 = _theResult___fst_exp__h451447 + 8'd1 ; - assign din_inc___2_exp__h469878 = _theResult___fst_exp__h460557 + 8'd1 ; - assign din_inc___2_exp__h469902 = _theResult___fst_exp__h469242 + 8'd1 ; - assign din_inc___2_exp__h517926 = _theResult___fst_exp__h498676 + 11'd1 ; - assign din_inc___2_exp__h517961 = _theResult___fst_exp__h508253 + 11'd1 ; - assign din_inc___2_exp__h517987 = _theResult___fst_exp__h517086 + 11'd1 ; - assign din_inc___2_exp__h556727 = _theResult___fst_exp__h537477 + 11'd1 ; - assign din_inc___2_exp__h556762 = _theResult___fst_exp__h547054 + 11'd1 ; - assign din_inc___2_exp__h556788 = _theResult___fst_exp__h555887 + 11'd1 ; - assign din_inc___2_exp__h595928 = _theResult___fst_exp__h576678 + 11'd1 ; - assign din_inc___2_exp__h595963 = _theResult___fst_exp__h586255 + 11'd1 ; - assign din_inc___2_exp__h595989 = _theResult___fst_exp__h595088 + 11'd1 ; - assign enabled_ints___1__h645895 = pend_ints__h645396 & y__h645907 ; - assign enabled_ints__h645942 = - pend_ints__h645396 & - { r1__read_BITS_12_TO_0___h645918, csrf_mideleg_1_0_reg } ; - assign fcsr_csr__read__h606148 = { 56'd0, x__h608822 } ; + x_quotient__h472393 : + x_remainder__h472394 ; + assign din_inc___2_exp__h378444 = _theResult___fst_exp__h351411 + 8'd1 ; + assign din_inc___2_exp__h378468 = _theResult___fst_exp__h360067 + 8'd1 ; + assign din_inc___2_exp__h378498 = _theResult___fst_exp__h369177 + 8'd1 ; + assign din_inc___2_exp__h378522 = _theResult___fst_exp__h377862 + 8'd1 ; + assign din_inc___2_exp__h424134 = _theResult___fst_exp__h397101 + 8'd1 ; + assign din_inc___2_exp__h424158 = _theResult___fst_exp__h405757 + 8'd1 ; + assign din_inc___2_exp__h424188 = _theResult___fst_exp__h414867 + 8'd1 ; + assign din_inc___2_exp__h424212 = _theResult___fst_exp__h423552 + 8'd1 ; + assign din_inc___2_exp__h469822 = _theResult___fst_exp__h442789 + 8'd1 ; + assign din_inc___2_exp__h469846 = _theResult___fst_exp__h451445 + 8'd1 ; + assign din_inc___2_exp__h469876 = _theResult___fst_exp__h460555 + 8'd1 ; + assign din_inc___2_exp__h469900 = _theResult___fst_exp__h469240 + 8'd1 ; + assign din_inc___2_exp__h517924 = _theResult___fst_exp__h498674 + 11'd1 ; + assign din_inc___2_exp__h517959 = _theResult___fst_exp__h508251 + 11'd1 ; + assign din_inc___2_exp__h517985 = _theResult___fst_exp__h517084 + 11'd1 ; + assign din_inc___2_exp__h556725 = _theResult___fst_exp__h537475 + 11'd1 ; + assign din_inc___2_exp__h556760 = _theResult___fst_exp__h547052 + 11'd1 ; + assign din_inc___2_exp__h556786 = _theResult___fst_exp__h555885 + 11'd1 ; + assign din_inc___2_exp__h595926 = _theResult___fst_exp__h576676 + 11'd1 ; + assign din_inc___2_exp__h595961 = _theResult___fst_exp__h586253 + 11'd1 ; + assign din_inc___2_exp__h595987 = _theResult___fst_exp__h595086 + 11'd1 ; + assign enabled_ints___1__h645893 = pend_ints__h645394 & y__h645905 ; + assign enabled_ints__h645940 = + pend_ints__h645394 & + { r1__read_BITS_12_TO_0___h645916, csrf_mideleg_1_0_reg } ; + assign fcsr_csr__read__h606149 = { 56'd0, x__h608823 } ; assign fetchStage_RDY_pipelines_0_first__2602_AND_NOT_ETC___d13210 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -27841,8 +27841,8 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d12869 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h649453 != 5'd0 || - imm__h649454 != 32'd0) && + rs1__h649451 != 5'd0 || + imm__h649452 != 32'd0) && IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 = @@ -27969,82 +27969,82 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13709 ; - assign fflags__h705627 = + assign fflags__h705625 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_fst__h705687 : + y_avValue_snd_fst__h705685 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 ; - assign fflags_csr__read__h606123 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h606134 = { 61'd0, csrf_frm_reg } ; - assign guard__h343312 = - { IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21[1], - { sfdin__h351407[32:0], 23'd0 } != 56'd0 } ; - assign guard__h352021 = - { IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23[1], - { _theResult___snd__h360020[32:0], 23'd0 } != 56'd0 } ; - assign guard__h360951 = - { IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31[1], - { sfdin__h369173[32:0], 23'd0 } != 56'd0 } ; - assign guard__h361549 = x__h361651 != 57'd0 ; - assign guard__h369787 = - { IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36[1], - { _theResult___snd__h377810[32:0], 23'd0 } != 56'd0 } ; - assign guard__h389004 = - { IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56[1], - { sfdin__h397097[32:0], 23'd0 } != 56'd0 } ; - assign guard__h397711 = - { IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58[1], - { _theResult___snd__h405710[32:0], 23'd0 } != 56'd0 } ; - assign guard__h406641 = - { IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66[1], - { sfdin__h414863[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407239 = x__h407341 != 57'd0 ; - assign guard__h415477 = - { IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71[1], - { _theResult___snd__h423500[32:0], 23'd0 } != 56'd0 } ; - assign guard__h434692 = - { IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91[1], - { sfdin__h442785[32:0], 23'd0 } != 56'd0 } ; - assign guard__h443399 = - { IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93[1], - { _theResult___snd__h451398[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452329 = - { IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101[1], - { sfdin__h460551[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452927 = x__h453029 != 57'd0 ; - assign guard__h461165 = - { IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106[1], - { _theResult___snd__h469188[32:0], 23'd0 } != 56'd0 } ; - assign guard__h490715 = - { IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h498627[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500027 = - { IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h508247[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500625 = x__h500725 != 57'd0 ; - assign guard__h509096 = - { IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h517032[3:0], 52'd0 } != 56'd0 } ; - assign guard__h529516 = - { IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h537428[3:0], 52'd0 } != 56'd0 } ; - assign guard__h538828 = - { IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h547048[3:0], 52'd0 } != 56'd0 } ; - assign guard__h539426 = x__h539526 != 57'd0 ; - assign guard__h547897 = - { IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h555833[3:0], 52'd0 } != 56'd0 } ; - assign guard__h568717 = - { IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h576629[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578029 = - { IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h586249[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578627 = x__h578727 != 57'd0 ; - assign guard__h587098 = - { IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h595034[3:0], 52'd0 } != 56'd0 } ; - assign idx__h675479 = + assign fflags_csr__read__h606124 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h606135 = { 61'd0, csrf_frm_reg } ; + assign guard__h343310 = + { IF_sfdin51405_BIT_33_THEN_2_ELSE_0__q21[1], + { sfdin__h351405[32:0], 23'd0 } != 56'd0 } ; + assign guard__h352019 = + { IF_theResult___snd60018_BIT_33_THEN_2_ELSE_0__q23[1], + { _theResult___snd__h360018[32:0], 23'd0 } != 56'd0 } ; + assign guard__h360949 = + { IF_sfdin69171_BIT_33_THEN_2_ELSE_0__q31[1], + { sfdin__h369171[32:0], 23'd0 } != 56'd0 } ; + assign guard__h361547 = x__h361649 != 57'd0 ; + assign guard__h369785 = + { IF_theResult___snd77808_BIT_33_THEN_2_ELSE_0__q36[1], + { _theResult___snd__h377808[32:0], 23'd0 } != 56'd0 } ; + assign guard__h389002 = + { IF_sfdin97095_BIT_33_THEN_2_ELSE_0__q56[1], + { sfdin__h397095[32:0], 23'd0 } != 56'd0 } ; + assign guard__h397709 = + { IF_theResult___snd05708_BIT_33_THEN_2_ELSE_0__q58[1], + { _theResult___snd__h405708[32:0], 23'd0 } != 56'd0 } ; + assign guard__h406639 = + { IF_sfdin14861_BIT_33_THEN_2_ELSE_0__q66[1], + { sfdin__h414861[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407237 = x__h407339 != 57'd0 ; + assign guard__h415475 = + { IF_theResult___snd23498_BIT_33_THEN_2_ELSE_0__q71[1], + { _theResult___snd__h423498[32:0], 23'd0 } != 56'd0 } ; + assign guard__h434690 = + { IF_sfdin42783_BIT_33_THEN_2_ELSE_0__q91[1], + { sfdin__h442783[32:0], 23'd0 } != 56'd0 } ; + assign guard__h443397 = + { IF_theResult___snd51396_BIT_33_THEN_2_ELSE_0__q93[1], + { _theResult___snd__h451396[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452327 = + { IF_sfdin60549_BIT_33_THEN_2_ELSE_0__q101[1], + { sfdin__h460549[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452925 = x__h453027 != 57'd0 ; + assign guard__h461163 = + { IF_theResult___snd69186_BIT_33_THEN_2_ELSE_0__q106[1], + { _theResult___snd__h469186[32:0], 23'd0 } != 56'd0 } ; + assign guard__h490713 = + { IF_theResult___snd98625_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h498625[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500025 = + { IF_sfdin08245_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h508245[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500623 = x__h500723 != 57'd0 ; + assign guard__h509094 = + { IF_theResult___snd17030_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h517030[3:0], 52'd0 } != 56'd0 } ; + assign guard__h529514 = + { IF_theResult___snd37426_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h537426[3:0], 52'd0 } != 56'd0 } ; + assign guard__h538826 = + { IF_sfdin47046_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h547046[3:0], 52'd0 } != 56'd0 } ; + assign guard__h539424 = x__h539524 != 57'd0 ; + assign guard__h547895 = + { IF_theResult___snd55831_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h555831[3:0], 52'd0 } != 56'd0 } ; + assign guard__h568715 = + { IF_theResult___snd76627_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h576627[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578027 = + { IF_sfdin86247_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h586247[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578625 = x__h578725 != 57'd0 ; + assign guard__h587096 = + { IF_theResult___snd95032_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h595032[3:0], 52'd0 } != 56'd0 } ; + assign idx__h675477 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -28052,26 +28052,26 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13523) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign imm__h649454 = + assign imm__h649452 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h661045 = + assign k__h661043 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign mcause_csr__read__h607795 = - { r1__read__h610362, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h607540 = - { r1__read__h610349, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h607140 = - { r1__read__h610185, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h607235 = - { r1__read__h610202, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h607366 = - { r1__read__h610226, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h608035 = - { r1__read__h610368, csrf_software_int_pend_vec_0 } ; + assign mcause_csr__read__h607796 = + { r1__read__h610363, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h607541 = + { r1__read__h610350, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h607141 = + { r1__read__h610186, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h607236 = + { r1__read__h610203, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h607367 = + { r1__read__h610227, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h608036 = + { r1__read__h610369, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28148,40 +28148,40 @@ module mkCore(CLK, !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; assign msip__h75409 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h606992 = { r1__read__h610048, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h607448 = - { r1__read__h610344, csrf_mtvec_mode_low_reg } ; - assign n___1__h195752 = + assign mstatus_csr__read__h606993 = { r1__read__h610049, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h607449 = + { r1__read__h610345, csrf_mtvec_mode_low_reg } ; + assign n___1__h195750 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h194349[63:56], + x__h194347[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h194349[55:48], + x__h194347[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h194349[47:40], + x__h194347[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h194349[39:32], + x__h194347[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h194349[31:24], + x__h194347[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h194349[23:16], + x__h194347[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h194349[15:8], + x__h194347[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h194349[7:0] } ; - assign n__read__h608139 = + x__h194347[7:0] } ; + assign n__read__h608140 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h608330 = + assign n__read__h608331 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -28192,250 +28192,250 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h703199 = + assign n__read__h703197 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h294022 = + assign next_deqP___1__h294020 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h302018 = + assign next_deqP___1__h302016 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h308299 = + assign next_deqP___1__h308297 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h316153 = + assign next_deqP___1__h316151 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h326210 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h329435 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h702542 = + assign next_deqP___1__h326208 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h329433 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h702540 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign out___1_sfd__h479378 = + assign out___1_sfd__h479376 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ; - assign out___1_sfd__h518320 = + assign out___1_sfd__h518318 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ; - assign out___1_sfd__h557521 = + assign out___1_sfd__h557519 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ; - assign out_exp__h351932 = - sfdin__h351407[34] ? - _theResult___exp__h351929 : - _theResult___fst_exp__h351413 ; - assign out_exp__h360514 = - _theResult___snd__h360020[34] ? - _theResult___exp__h360511 : - _theResult___fst_exp__h360069 ; - assign out_exp__h369698 = - sfdin__h369173[34] ? - _theResult___exp__h369695 : - _theResult___fst_exp__h369179 ; - assign out_exp__h378334 = - _theResult___snd__h377810[34] ? - _theResult___exp__h378331 : - _theResult___fst_exp__h377864 ; - assign out_exp__h397622 = - sfdin__h397097[34] ? - _theResult___exp__h397619 : - _theResult___fst_exp__h397103 ; - assign out_exp__h406204 = - _theResult___snd__h405710[34] ? - _theResult___exp__h406201 : - _theResult___fst_exp__h405759 ; - assign out_exp__h415388 = - sfdin__h414863[34] ? - _theResult___exp__h415385 : - _theResult___fst_exp__h414869 ; - assign out_exp__h424024 = - _theResult___snd__h423500[34] ? - _theResult___exp__h424021 : - _theResult___fst_exp__h423554 ; - assign out_exp__h443310 = - sfdin__h442785[34] ? - _theResult___exp__h443307 : - _theResult___fst_exp__h442791 ; - assign out_exp__h451892 = - _theResult___snd__h451398[34] ? - _theResult___exp__h451889 : - _theResult___fst_exp__h451447 ; - assign out_exp__h461076 = - sfdin__h460551[34] ? - _theResult___exp__h461073 : - _theResult___fst_exp__h460557 ; - assign out_exp__h469712 = - _theResult___snd__h469188[34] ? - _theResult___exp__h469709 : - _theResult___fst_exp__h469242 ; - assign out_exp__h499334 = - _theResult___snd__h498627[5] ? - _theResult___exp__h499331 : - _theResult___fst_exp__h498676 ; - assign out_exp__h508985 = - sfdin__h508247[5] ? - _theResult___exp__h508982 : - _theResult___fst_exp__h508253 ; - assign out_exp__h517769 = - _theResult___snd__h517032[5] ? - _theResult___exp__h517766 : - _theResult___fst_exp__h517086 ; - assign out_exp__h538135 = - _theResult___snd__h537428[5] ? - _theResult___exp__h538132 : - _theResult___fst_exp__h537477 ; - assign out_exp__h547786 = - sfdin__h547048[5] ? - _theResult___exp__h547783 : - _theResult___fst_exp__h547054 ; - assign out_exp__h556570 = - _theResult___snd__h555833[5] ? - _theResult___exp__h556567 : - _theResult___fst_exp__h555887 ; - assign out_exp__h577336 = - _theResult___snd__h576629[5] ? - _theResult___exp__h577333 : - _theResult___fst_exp__h576678 ; - assign out_exp__h586987 = - sfdin__h586249[5] ? - _theResult___exp__h586984 : - _theResult___fst_exp__h586255 ; - assign out_exp__h595771 = - _theResult___snd__h595034[5] ? - _theResult___exp__h595768 : - _theResult___fst_exp__h595088 ; - assign out_f_exp__h378710 = - (_theResult___exp__h378433 == 8'd255 && - _theResult___sfd__h378434 != 23'd0 || + assign out_exp__h351930 = + sfdin__h351405[34] ? + _theResult___exp__h351927 : + _theResult___fst_exp__h351411 ; + assign out_exp__h360512 = + _theResult___snd__h360018[34] ? + _theResult___exp__h360509 : + _theResult___fst_exp__h360067 ; + assign out_exp__h369696 = + sfdin__h369171[34] ? + _theResult___exp__h369693 : + _theResult___fst_exp__h369177 ; + assign out_exp__h378332 = + _theResult___snd__h377808[34] ? + _theResult___exp__h378329 : + _theResult___fst_exp__h377862 ; + assign out_exp__h397620 = + sfdin__h397095[34] ? + _theResult___exp__h397617 : + _theResult___fst_exp__h397101 ; + assign out_exp__h406202 = + _theResult___snd__h405708[34] ? + _theResult___exp__h406199 : + _theResult___fst_exp__h405757 ; + assign out_exp__h415386 = + sfdin__h414861[34] ? + _theResult___exp__h415383 : + _theResult___fst_exp__h414867 ; + assign out_exp__h424022 = + _theResult___snd__h423498[34] ? + _theResult___exp__h424019 : + _theResult___fst_exp__h423552 ; + assign out_exp__h443308 = + sfdin__h442783[34] ? + _theResult___exp__h443305 : + _theResult___fst_exp__h442789 ; + assign out_exp__h451890 = + _theResult___snd__h451396[34] ? + _theResult___exp__h451887 : + _theResult___fst_exp__h451445 ; + assign out_exp__h461074 = + sfdin__h460549[34] ? + _theResult___exp__h461071 : + _theResult___fst_exp__h460555 ; + assign out_exp__h469710 = + _theResult___snd__h469186[34] ? + _theResult___exp__h469707 : + _theResult___fst_exp__h469240 ; + assign out_exp__h499332 = + _theResult___snd__h498625[5] ? + _theResult___exp__h499329 : + _theResult___fst_exp__h498674 ; + assign out_exp__h508983 = + sfdin__h508245[5] ? + _theResult___exp__h508980 : + _theResult___fst_exp__h508251 ; + assign out_exp__h517767 = + _theResult___snd__h517030[5] ? + _theResult___exp__h517764 : + _theResult___fst_exp__h517084 ; + assign out_exp__h538133 = + _theResult___snd__h537426[5] ? + _theResult___exp__h538130 : + _theResult___fst_exp__h537475 ; + assign out_exp__h547784 = + sfdin__h547046[5] ? + _theResult___exp__h547781 : + _theResult___fst_exp__h547052 ; + assign out_exp__h556568 = + _theResult___snd__h555831[5] ? + _theResult___exp__h556565 : + _theResult___fst_exp__h555885 ; + assign out_exp__h577334 = + _theResult___snd__h576627[5] ? + _theResult___exp__h577331 : + _theResult___fst_exp__h576676 ; + assign out_exp__h586985 = + sfdin__h586247[5] ? + _theResult___exp__h586982 : + _theResult___fst_exp__h586253 ; + assign out_exp__h595769 = + _theResult___snd__h595032[5] ? + _theResult___exp__h595766 : + _theResult___fst_exp__h595086 ; + assign out_f_exp__h378708 = + (_theResult___exp__h378431 == 8'd255 && + _theResult___sfd__h378432 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378424 ; - assign out_f_exp__h424400 = - (_theResult___exp__h424123 == 8'd255 && - _theResult___sfd__h424124 != 23'd0 || + _theResult___fst_exp__h378422 ; + assign out_f_exp__h424398 = + (_theResult___exp__h424121 == 8'd255 && + _theResult___sfd__h424122 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424114 ; - assign out_f_exp__h470088 = - (_theResult___exp__h469811 == 8'd255 && - _theResult___sfd__h469812 != 23'd0 || + _theResult___fst_exp__h424112 ; + assign out_f_exp__h470086 = + (_theResult___exp__h469809 == 8'd255 && + _theResult___sfd__h469810 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469802 ; - assign out_f_sfd__h378711 = - (_theResult___exp__h378433 == 8'd255 && - _theResult___sfd__h378434 != 23'd0) ? + _theResult___fst_exp__h469800 ; + assign out_f_sfd__h378709 = + (_theResult___exp__h378431 == 8'd255 && + _theResult___sfd__h378432 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h378434 ; - assign out_f_sfd__h424401 = - (_theResult___exp__h424123 == 8'd255 && - _theResult___sfd__h424124 != 23'd0) ? + _theResult___sfd__h378432 ; + assign out_f_sfd__h424399 = + (_theResult___exp__h424121 == 8'd255 && + _theResult___sfd__h424122 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h424124 ; - assign out_f_sfd__h470089 = - (_theResult___exp__h469811 == 8'd255 && - _theResult___sfd__h469812 != 23'd0) ? + _theResult___sfd__h424122 ; + assign out_f_sfd__h470087 = + (_theResult___exp__h469809 == 8'd255 && + _theResult___sfd__h469810 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h469812 ; - assign out_sfd__h351933 = - sfdin__h351407[34] ? - _theResult___sfd__h351930 : - sfdin__h351407[56:34] ; - assign out_sfd__h360515 = - _theResult___snd__h360020[34] ? - _theResult___sfd__h360512 : - _theResult___snd__h360020[56:34] ; - assign out_sfd__h369699 = - sfdin__h369173[34] ? - _theResult___sfd__h369696 : - sfdin__h369173[56:34] ; - assign out_sfd__h378335 = - _theResult___snd__h377810[34] ? - _theResult___sfd__h378332 : - _theResult___snd__h377810[56:34] ; - assign out_sfd__h397623 = - sfdin__h397097[34] ? - _theResult___sfd__h397620 : - sfdin__h397097[56:34] ; - assign out_sfd__h406205 = - _theResult___snd__h405710[34] ? - _theResult___sfd__h406202 : - _theResult___snd__h405710[56:34] ; - assign out_sfd__h415389 = - sfdin__h414863[34] ? - _theResult___sfd__h415386 : - sfdin__h414863[56:34] ; - assign out_sfd__h424025 = - _theResult___snd__h423500[34] ? - _theResult___sfd__h424022 : - _theResult___snd__h423500[56:34] ; - assign out_sfd__h443311 = - sfdin__h442785[34] ? - _theResult___sfd__h443308 : - sfdin__h442785[56:34] ; - assign out_sfd__h451893 = - _theResult___snd__h451398[34] ? - _theResult___sfd__h451890 : - _theResult___snd__h451398[56:34] ; - assign out_sfd__h461077 = - sfdin__h460551[34] ? - _theResult___sfd__h461074 : - sfdin__h460551[56:34] ; - assign out_sfd__h469713 = - _theResult___snd__h469188[34] ? - _theResult___sfd__h469710 : - _theResult___snd__h469188[56:34] ; - assign out_sfd__h499335 = - _theResult___snd__h498627[5] ? - _theResult___sfd__h499332 : - _theResult___snd__h498627[56:5] ; - assign out_sfd__h508986 = - sfdin__h508247[5] ? - _theResult___sfd__h508983 : - sfdin__h508247[56:5] ; - assign out_sfd__h517770 = - _theResult___snd__h517032[5] ? - _theResult___sfd__h517767 : - _theResult___snd__h517032[56:5] ; - assign out_sfd__h538136 = - _theResult___snd__h537428[5] ? - _theResult___sfd__h538133 : - _theResult___snd__h537428[56:5] ; - assign out_sfd__h547787 = - sfdin__h547048[5] ? - _theResult___sfd__h547784 : - sfdin__h547048[56:5] ; - assign out_sfd__h556571 = - _theResult___snd__h555833[5] ? - _theResult___sfd__h556568 : - _theResult___snd__h555833[56:5] ; - assign out_sfd__h577337 = - _theResult___snd__h576629[5] ? - _theResult___sfd__h577334 : - _theResult___snd__h576629[56:5] ; - assign out_sfd__h586988 = - sfdin__h586249[5] ? - _theResult___sfd__h586985 : - sfdin__h586249[56:5] ; - assign out_sfd__h595772 = - _theResult___snd__h595034[5] ? - _theResult___sfd__h595769 : - _theResult___snd__h595034[56:5] ; - assign pend_ints__h645396 = + _theResult___sfd__h469810 ; + assign out_sfd__h351931 = + sfdin__h351405[34] ? + _theResult___sfd__h351928 : + sfdin__h351405[56:34] ; + assign out_sfd__h360513 = + _theResult___snd__h360018[34] ? + _theResult___sfd__h360510 : + _theResult___snd__h360018[56:34] ; + assign out_sfd__h369697 = + sfdin__h369171[34] ? + _theResult___sfd__h369694 : + sfdin__h369171[56:34] ; + assign out_sfd__h378333 = + _theResult___snd__h377808[34] ? + _theResult___sfd__h378330 : + _theResult___snd__h377808[56:34] ; + assign out_sfd__h397621 = + sfdin__h397095[34] ? + _theResult___sfd__h397618 : + sfdin__h397095[56:34] ; + assign out_sfd__h406203 = + _theResult___snd__h405708[34] ? + _theResult___sfd__h406200 : + _theResult___snd__h405708[56:34] ; + assign out_sfd__h415387 = + sfdin__h414861[34] ? + _theResult___sfd__h415384 : + sfdin__h414861[56:34] ; + assign out_sfd__h424023 = + _theResult___snd__h423498[34] ? + _theResult___sfd__h424020 : + _theResult___snd__h423498[56:34] ; + assign out_sfd__h443309 = + sfdin__h442783[34] ? + _theResult___sfd__h443306 : + sfdin__h442783[56:34] ; + assign out_sfd__h451891 = + _theResult___snd__h451396[34] ? + _theResult___sfd__h451888 : + _theResult___snd__h451396[56:34] ; + assign out_sfd__h461075 = + sfdin__h460549[34] ? + _theResult___sfd__h461072 : + sfdin__h460549[56:34] ; + assign out_sfd__h469711 = + _theResult___snd__h469186[34] ? + _theResult___sfd__h469708 : + _theResult___snd__h469186[56:34] ; + assign out_sfd__h499333 = + _theResult___snd__h498625[5] ? + _theResult___sfd__h499330 : + _theResult___snd__h498625[56:5] ; + assign out_sfd__h508984 = + sfdin__h508245[5] ? + _theResult___sfd__h508981 : + sfdin__h508245[56:5] ; + assign out_sfd__h517768 = + _theResult___snd__h517030[5] ? + _theResult___sfd__h517765 : + _theResult___snd__h517030[56:5] ; + assign out_sfd__h538134 = + _theResult___snd__h537426[5] ? + _theResult___sfd__h538131 : + _theResult___snd__h537426[56:5] ; + assign out_sfd__h547785 = + sfdin__h547046[5] ? + _theResult___sfd__h547782 : + sfdin__h547046[56:5] ; + assign out_sfd__h556569 = + _theResult___snd__h555831[5] ? + _theResult___sfd__h556566 : + _theResult___snd__h555831[56:5] ; + assign out_sfd__h577335 = + _theResult___snd__h576627[5] ? + _theResult___sfd__h577332 : + _theResult___snd__h576627[56:5] ; + assign out_sfd__h586986 = + sfdin__h586247[5] ? + _theResult___sfd__h586983 : + sfdin__h586247[56:5] ; + assign out_sfd__h595770 = + _theResult___snd__h595032[5] ? + _theResult___sfd__h595767 : + _theResult___snd__h595032[56:5] ; + assign pend_ints__h645394 = { csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h707142 = csrf_prv_reg ; - assign prv__h707186 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h473080 = + assign prv__h707140 = csrf_prv_reg ; + assign prv__h707184 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h473078 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_12_TO_0___h645918 = + assign r1__read_BITS_12_TO_0___h645916 = { 3'd0, csrf_mideleg_11_reg, 1'b0, @@ -28443,126 +28443,126 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h649322 = csrf_fs_reg ; - assign r1__read_BIT_20___h649950 = csrf_tw_reg ; - assign r1__read__h608837 = { r1__read__h608839, csrf_ie_vec_1 } ; - assign r1__read__h608839 = { r1__read__h608841, 2'b0 } ; - assign r1__read__h608841 = { r1__read__h608843, csrf_prev_ie_vec_0 } ; - assign r1__read__h608843 = { r1__read__h608845, csrf_prev_ie_vec_1 } ; - assign r1__read__h608845 = { r1__read__h608847, 2'b0 } ; - assign r1__read__h608847 = { r1__read__h608849, csrf_spp_reg } ; - assign r1__read__h608849 = { r1__read__h608851, 4'b0 } ; - assign r1__read__h608851 = { r1__read__h608853, csrf_fs_reg } ; - assign r1__read__h608853 = { r1__read__h608855, 2'd0 } ; - assign r1__read__h608855 = { r1__read__h608857, 1'b0 } ; - assign r1__read__h608857 = { r1__read__h608859, csrf_sum_reg } ; - assign r1__read__h608859 = { r1__read__h608861, csrf_mxr_reg } ; - assign r1__read__h608861 = { r1__read__h608863, 12'b0 } ; - assign r1__read__h608863 = { r1__read__h608865, 2'b10 } ; - assign r1__read__h608865 = { r__h608869, 29'b0 } ; - assign r1__read__h609241 = - { r1__read__h609243, csrf_software_int_en_vec_1 } ; - assign r1__read__h609243 = { r1__read__h609245, 2'b0 } ; - assign r1__read__h609245 = { r1__read__h609247, csrf_timer_int_en_vec_0 } ; - assign r1__read__h609247 = { r1__read__h609249, csrf_timer_int_en_vec_1 } ; - assign r1__read__h609249 = { r1__read__h609251, 2'b0 } ; - assign r1__read__h609251 = - { r1__read__h609253, csrf_external_int_en_vec_0 } ; - assign r1__read__h609253 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h609771 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h609776 = { r1__read__h609778, csrf_scounteren_tm_reg } ; - assign r1__read__h609778 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h609789 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h609795 = - { r1__read__h609797, csrf_software_int_pend_vec_1 } ; - assign r1__read__h609797 = { r1__read__h609799, 2'b0 } ; - assign r1__read__h609799 = - { r1__read__h609801, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h609801 = - { r1__read__h609803, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h609803 = { r1__read__h609805, 2'b0 } ; - assign r1__read__h609805 = - { r1__read__h609807, csrf_external_int_pend_vec_0 } ; - assign r1__read__h609807 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610025 = { vm_mode_reg__read__h610031, 16'd0 } ; - assign r1__read__h610048 = { r1__read__h610050, csrf_ie_vec_1 } ; - assign r1__read__h610050 = { r1__read__h610052, 1'b0 } ; - assign r1__read__h610052 = { r1__read__h610054, csrf_ie_vec_3 } ; - assign r1__read__h610054 = { r1__read__h610056, csrf_prev_ie_vec_0 } ; - assign r1__read__h610056 = { r1__read__h610058, csrf_prev_ie_vec_1 } ; - assign r1__read__h610058 = { r1__read__h610060, 1'b0 } ; - assign r1__read__h610060 = { r1__read__h610062, csrf_prev_ie_vec_3 } ; - assign r1__read__h610062 = { r1__read__h610064, csrf_spp_reg } ; - assign r1__read__h610064 = { r1__read__h610066, 2'b0 } ; - assign r1__read__h610066 = { r1__read__h610068, csrf_mpp_reg } ; - assign r1__read__h610068 = { r1__read__h610070, csrf_fs_reg } ; - assign r1__read__h610070 = { r1__read__h610072, 2'd0 } ; - assign r1__read__h610072 = { r1__read__h610074, csrf_mprv_reg } ; - assign r1__read__h610074 = { r1__read__h610076, csrf_sum_reg } ; - assign r1__read__h610076 = { r1__read__h610078, csrf_mxr_reg } ; - assign r1__read__h610078 = { r1__read__h610080, csrf_tvm_reg } ; - assign r1__read__h610080 = { r1__read__h610082, csrf_tw_reg } ; - assign r1__read__h610082 = { r1__read__h610084, csrf_tsr_reg } ; - assign r1__read__h610084 = { r1__read__h610086, 9'b0 } ; - assign r1__read__h610086 = { r1__read__h610088, 2'b10 } ; - assign r1__read__h610088 = { r1__read__h610090, 2'b10 } ; - assign r1__read__h610090 = { r__h608869, 27'b0 } ; - assign r1__read__h610185 = { r1__read__h610187, 1'b0 } ; - assign r1__read__h610187 = { r1__read__h610189, csrf_medeleg_13_11_reg } ; - assign r1__read__h610189 = { r1__read__h610191, 1'b0 } ; - assign r1__read__h610191 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h610202 = { r1__read__h610204, 1'b0 } ; - assign r1__read__h610204 = { r1__read__h610206, csrf_mideleg_5_3_reg } ; - assign r1__read__h610206 = { r1__read__h610208, 1'b0 } ; - assign r1__read__h610208 = { r1__read__h610210, csrf_mideleg_9_7_reg } ; - assign r1__read__h610210 = { r1__read__h610212, 1'b0 } ; - assign r1__read__h610212 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h610226 = - { r1__read__h610228, csrf_software_int_en_vec_1 } ; - assign r1__read__h610228 = { r1__read__h610230, 1'b0 } ; - assign r1__read__h610230 = - { r1__read__h610232, csrf_software_int_en_vec_3 } ; - assign r1__read__h610232 = { r1__read__h610234, csrf_timer_int_en_vec_0 } ; - assign r1__read__h610234 = { r1__read__h610236, csrf_timer_int_en_vec_1 } ; - assign r1__read__h610236 = { r1__read__h610238, 1'b0 } ; - assign r1__read__h610238 = { r1__read__h610240, csrf_timer_int_en_vec_3 } ; - assign r1__read__h610240 = - { r1__read__h610242, csrf_external_int_en_vec_0 } ; - assign r1__read__h610242 = - { r1__read__h610244, csrf_external_int_en_vec_1 } ; - assign r1__read__h610244 = { r1__read__h610246, 1'b0 } ; - assign r1__read__h610246 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h610344 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h610349 = { r1__read__h610351, csrf_mcounteren_tm_reg } ; - assign r1__read__h610351 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h610362 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h610368 = - { r1__read__h610370, csrf_software_int_pend_vec_1 } ; - assign r1__read__h610370 = { r1__read__h610372, 1'b0 } ; - assign r1__read__h610372 = - { r1__read__h610374, csrf_software_int_pend_vec_3 } ; - assign r1__read__h610374 = - { r1__read__h610376, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h610376 = - { r1__read__h610378, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h610378 = { r1__read__h610380, 1'b0 } ; - assign r1__read__h610380 = - { r1__read__h610382, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h610382 = - { r1__read__h610384, csrf_external_int_pend_vec_0 } ; - assign r1__read__h610384 = - { r1__read__h610386, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610386 = { r1__read__h610388, 1'b0 } ; - assign r1__read__h610388 = - { r1__read__h610390, csrf_external_int_pend_vec_3 } ; - assign r1__read__h610390 = { r1__read__h610392, 2'b0 } ; - assign r1__read__h610392 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h478961 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h478962 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h473106 = + assign r1__read_BITS_13_TO_12___h649320 = csrf_fs_reg ; + assign r1__read_BIT_20___h649948 = csrf_tw_reg ; + assign r1__read__h608838 = { r1__read__h608840, csrf_ie_vec_1 } ; + assign r1__read__h608840 = { r1__read__h608842, 2'b0 } ; + assign r1__read__h608842 = { r1__read__h608844, csrf_prev_ie_vec_0 } ; + assign r1__read__h608844 = { r1__read__h608846, csrf_prev_ie_vec_1 } ; + assign r1__read__h608846 = { r1__read__h608848, 2'b0 } ; + assign r1__read__h608848 = { r1__read__h608850, csrf_spp_reg } ; + assign r1__read__h608850 = { r1__read__h608852, 4'b0 } ; + assign r1__read__h608852 = { r1__read__h608854, csrf_fs_reg } ; + assign r1__read__h608854 = { r1__read__h608856, 2'd0 } ; + assign r1__read__h608856 = { r1__read__h608858, 1'b0 } ; + assign r1__read__h608858 = { r1__read__h608860, csrf_sum_reg } ; + assign r1__read__h608860 = { r1__read__h608862, csrf_mxr_reg } ; + assign r1__read__h608862 = { r1__read__h608864, 12'b0 } ; + assign r1__read__h608864 = { r1__read__h608866, 2'b10 } ; + assign r1__read__h608866 = { r__h608870, 29'b0 } ; + assign r1__read__h609242 = + { r1__read__h609244, csrf_software_int_en_vec_1 } ; + assign r1__read__h609244 = { r1__read__h609246, 2'b0 } ; + assign r1__read__h609246 = { r1__read__h609248, csrf_timer_int_en_vec_0 } ; + assign r1__read__h609248 = { r1__read__h609250, csrf_timer_int_en_vec_1 } ; + assign r1__read__h609250 = { r1__read__h609252, 2'b0 } ; + assign r1__read__h609252 = + { r1__read__h609254, csrf_external_int_en_vec_0 } ; + assign r1__read__h609254 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h609772 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h609777 = { r1__read__h609779, csrf_scounteren_tm_reg } ; + assign r1__read__h609779 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h609790 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h609796 = + { r1__read__h609798, csrf_software_int_pend_vec_1 } ; + assign r1__read__h609798 = { r1__read__h609800, 2'b0 } ; + assign r1__read__h609800 = + { r1__read__h609802, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h609802 = + { r1__read__h609804, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h609804 = { r1__read__h609806, 2'b0 } ; + assign r1__read__h609806 = + { r1__read__h609808, csrf_external_int_pend_vec_0 } ; + assign r1__read__h609808 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610026 = { vm_mode_reg__read__h610032, 16'd0 } ; + assign r1__read__h610049 = { r1__read__h610051, csrf_ie_vec_1 } ; + assign r1__read__h610051 = { r1__read__h610053, 1'b0 } ; + assign r1__read__h610053 = { r1__read__h610055, csrf_ie_vec_3 } ; + assign r1__read__h610055 = { r1__read__h610057, csrf_prev_ie_vec_0 } ; + assign r1__read__h610057 = { r1__read__h610059, csrf_prev_ie_vec_1 } ; + assign r1__read__h610059 = { r1__read__h610061, 1'b0 } ; + assign r1__read__h610061 = { r1__read__h610063, csrf_prev_ie_vec_3 } ; + assign r1__read__h610063 = { r1__read__h610065, csrf_spp_reg } ; + assign r1__read__h610065 = { r1__read__h610067, 2'b0 } ; + assign r1__read__h610067 = { r1__read__h610069, csrf_mpp_reg } ; + assign r1__read__h610069 = { r1__read__h610071, csrf_fs_reg } ; + assign r1__read__h610071 = { r1__read__h610073, 2'd0 } ; + assign r1__read__h610073 = { r1__read__h610075, csrf_mprv_reg } ; + assign r1__read__h610075 = { r1__read__h610077, csrf_sum_reg } ; + assign r1__read__h610077 = { r1__read__h610079, csrf_mxr_reg } ; + assign r1__read__h610079 = { r1__read__h610081, csrf_tvm_reg } ; + assign r1__read__h610081 = { r1__read__h610083, csrf_tw_reg } ; + assign r1__read__h610083 = { r1__read__h610085, csrf_tsr_reg } ; + assign r1__read__h610085 = { r1__read__h610087, 9'b0 } ; + assign r1__read__h610087 = { r1__read__h610089, 2'b10 } ; + assign r1__read__h610089 = { r1__read__h610091, 2'b10 } ; + assign r1__read__h610091 = { r__h608870, 27'b0 } ; + assign r1__read__h610186 = { r1__read__h610188, 1'b0 } ; + assign r1__read__h610188 = { r1__read__h610190, csrf_medeleg_13_11_reg } ; + assign r1__read__h610190 = { r1__read__h610192, 1'b0 } ; + assign r1__read__h610192 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h610203 = { r1__read__h610205, 1'b0 } ; + assign r1__read__h610205 = { r1__read__h610207, csrf_mideleg_5_3_reg } ; + assign r1__read__h610207 = { r1__read__h610209, 1'b0 } ; + assign r1__read__h610209 = { r1__read__h610211, csrf_mideleg_9_7_reg } ; + assign r1__read__h610211 = { r1__read__h610213, 1'b0 } ; + assign r1__read__h610213 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h610227 = + { r1__read__h610229, csrf_software_int_en_vec_1 } ; + assign r1__read__h610229 = { r1__read__h610231, 1'b0 } ; + assign r1__read__h610231 = + { r1__read__h610233, csrf_software_int_en_vec_3 } ; + assign r1__read__h610233 = { r1__read__h610235, csrf_timer_int_en_vec_0 } ; + assign r1__read__h610235 = { r1__read__h610237, csrf_timer_int_en_vec_1 } ; + assign r1__read__h610237 = { r1__read__h610239, 1'b0 } ; + assign r1__read__h610239 = { r1__read__h610241, csrf_timer_int_en_vec_3 } ; + assign r1__read__h610241 = + { r1__read__h610243, csrf_external_int_en_vec_0 } ; + assign r1__read__h610243 = + { r1__read__h610245, csrf_external_int_en_vec_1 } ; + assign r1__read__h610245 = { r1__read__h610247, 1'b0 } ; + assign r1__read__h610247 = { 52'd4, csrf_external_int_en_vec_3 } ; + assign r1__read__h610345 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h610350 = { r1__read__h610352, csrf_mcounteren_tm_reg } ; + assign r1__read__h610352 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h610363 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h610369 = + { r1__read__h610371, csrf_software_int_pend_vec_1 } ; + assign r1__read__h610371 = { r1__read__h610373, 1'b0 } ; + assign r1__read__h610373 = + { r1__read__h610375, csrf_software_int_pend_vec_3 } ; + assign r1__read__h610375 = + { r1__read__h610377, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h610377 = + { r1__read__h610379, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h610379 = { r1__read__h610381, 1'b0 } ; + assign r1__read__h610381 = + { r1__read__h610383, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h610383 = + { r1__read__h610385, csrf_external_int_pend_vec_0 } ; + assign r1__read__h610385 = + { r1__read__h610387, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610387 = { r1__read__h610389, 1'b0 } ; + assign r1__read__h610389 = + { r1__read__h610391, csrf_external_int_pend_vec_3 } ; + assign r1__read__h610391 = { r1__read__h610393, 2'b0 } ; + assign r1__read__h610393 = { 49'b0, csrf_debug_int_pend } ; + assign rVal1__h478959 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h478960 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h473104 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h608869 = csrf_fs_reg == 2'b11 ; + assign r__h608870 = csrf_fs_reg == 2'b11 ; assign regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && @@ -28662,12 +28662,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign renaming_spec_bits__h675348 = + assign renaming_spec_bits__h675346 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h672114 : + y_avValue_snd_fst__h672112 : specTagManager$currentSpecBits ; - assign res_data__h335089 = { 32'd0, x__h335101 } ; - assign res_data__h335094 = + assign res_data__h335087 = { 32'd0, x__h335099 } ; + assign res_data__h335092 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28680,8 +28680,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h380784 = { 32'd0, x__h380796 } ; - assign res_data__h380789 = + assign res_data__h380782 = { 32'd0, x__h380794 } ; + assign res_data__h380787 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28694,8 +28694,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h426472 = { 32'd0, x__h426484 } ; - assign res_data__h426477 = + assign res_data__h426470 = { 32'd0, x__h426482 } ; + assign res_data__h426475 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28708,7 +28708,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h335090 = + assign res_fflags__h335088 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -28776,7 +28776,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ; - assign res_fflags__h380785 = + assign res_fflags__h380783 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -28844,7 +28844,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ; - assign res_fflags__h426473 = + assign res_fflags__h426471 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -28912,35 +28912,35 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ; - assign resp_addr__h289193 = + assign resp_addr__h289191 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h361554 = + assign result__h361552 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] | - guard__h361549 } ; - assign result__h407244 = + guard__h361547 } ; + assign result__h407242 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] | - guard__h407239 } ; - assign result__h452932 = + guard__h407237 } ; + assign result__h452930 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] | - guard__h452927 } ; - assign result__h500630 = + guard__h452925 } ; + assign result__h500628 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[0] | - guard__h500625 } ; - assign result__h539431 = + guard__h500623 } ; + assign result__h539429 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[0] | - guard__h539426 } ; - assign result__h578632 = + guard__h539424 } ; + assign result__h578630 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[0] | - guard__h578627 } ; - assign result__h641105 = w__h641100 & y__h641134 ; - assign result__h641156 = ~x__h641155 ; + guard__h578625 } ; + assign result__h641103 = w__h641098 & y__h641132 ; + assign result__h641154 = ~x__h641153 ; assign rob_RDY_enqPort_0_enq__2627_AND_regRenamingTab_ETC___d13095 = rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && @@ -28972,12 +28972,12 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q261 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h649453 = + assign rs1__h649451 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h606849 = { r1__read__h610025, csrf_ppn_reg } ; + assign satp_csr__read__h606850 = { r1__read__h610026, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 && @@ -29003,259 +29003,259 @@ module mkCore(CLK, coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h606647 = - { r1__read__h609789, csrf_scause_code_reg } ; - assign scounteren_csr__read__h606509 = - { r1__read__h609776, csrf_scounteren_cy_reg } ; - assign sfd__h335697 = { value__h343924, 3'd0 } ; - assign sfd__h351505 = + assign scause_csr__read__h606648 = + { r1__read__h609790, csrf_scause_code_reg } ; + assign scounteren_csr__read__h606510 = + { r1__read__h609777, csrf_scounteren_cy_reg } ; + assign sfd__h335695 = { value__h343922, 3'd0 } ; + assign sfd__h351503 = { 1'b0, - _theResult___fst_exp__h351413 != 8'd0, - sfdin__h351407[56:34] } + + _theResult___fst_exp__h351411 != 8'd0, + sfdin__h351405[56:34] } + 25'd1 ; - assign sfd__h360087 = + assign sfd__h360085 = { 1'b0, - _theResult___fst_exp__h360069 != 8'd0, - _theResult___snd__h360020[56:34] } + + _theResult___fst_exp__h360067 != 8'd0, + _theResult___snd__h360018[56:34] } + 25'd1 ; - assign sfd__h369271 = + assign sfd__h369269 = { 1'b0, - _theResult___fst_exp__h369179 != 8'd0, - sfdin__h369173[56:34] } + + _theResult___fst_exp__h369177 != 8'd0, + sfdin__h369171[56:34] } + 25'd1 ; - assign sfd__h377883 = + assign sfd__h377881 = { 1'b0, - _theResult___fst_exp__h377864 != 8'd0, - _theResult___snd__h377810[56:34] } + + _theResult___fst_exp__h377862 != 8'd0, + _theResult___snd__h377808[56:34] } + 25'd1 ; - assign sfd__h381392 = { value__h389614, 3'd0 } ; - assign sfd__h397195 = + assign sfd__h381390 = { value__h389612, 3'd0 } ; + assign sfd__h397193 = { 1'b0, - _theResult___fst_exp__h397103 != 8'd0, - sfdin__h397097[56:34] } + + _theResult___fst_exp__h397101 != 8'd0, + sfdin__h397095[56:34] } + 25'd1 ; - assign sfd__h405777 = + assign sfd__h405775 = { 1'b0, - _theResult___fst_exp__h405759 != 8'd0, - _theResult___snd__h405710[56:34] } + + _theResult___fst_exp__h405757 != 8'd0, + _theResult___snd__h405708[56:34] } + 25'd1 ; - assign sfd__h414961 = + assign sfd__h414959 = { 1'b0, - _theResult___fst_exp__h414869 != 8'd0, - sfdin__h414863[56:34] } + + _theResult___fst_exp__h414867 != 8'd0, + sfdin__h414861[56:34] } + 25'd1 ; - assign sfd__h423573 = + assign sfd__h423571 = { 1'b0, - _theResult___fst_exp__h423554 != 8'd0, - _theResult___snd__h423500[56:34] } + + _theResult___fst_exp__h423552 != 8'd0, + _theResult___snd__h423498[56:34] } + 25'd1 ; - assign sfd__h427080 = { value__h435302, 3'd0 } ; - assign sfd__h442883 = + assign sfd__h427078 = { value__h435300, 3'd0 } ; + assign sfd__h442881 = { 1'b0, - _theResult___fst_exp__h442791 != 8'd0, - sfdin__h442785[56:34] } + + _theResult___fst_exp__h442789 != 8'd0, + sfdin__h442783[56:34] } + 25'd1 ; - assign sfd__h451465 = + assign sfd__h451463 = { 1'b0, - _theResult___fst_exp__h451447 != 8'd0, - _theResult___snd__h451398[56:34] } + + _theResult___fst_exp__h451445 != 8'd0, + _theResult___snd__h451396[56:34] } + 25'd1 ; - assign sfd__h460649 = + assign sfd__h460647 = { 1'b0, - _theResult___fst_exp__h460557 != 8'd0, - sfdin__h460551[56:34] } + + _theResult___fst_exp__h460555 != 8'd0, + sfdin__h460549[56:34] } + 25'd1 ; - assign sfd__h469261 = + assign sfd__h469259 = { 1'b0, - _theResult___fst_exp__h469242 != 8'd0, - _theResult___snd__h469188[56:34] } + + _theResult___fst_exp__h469240 != 8'd0, + _theResult___snd__h469186[56:34] } + 25'd1 ; - assign sfd__h479675 = { value__h484233, 32'd0 } ; - assign sfd__h498694 = + assign sfd__h479673 = { value__h484231, 32'd0 } ; + assign sfd__h498692 = { 1'b0, - _theResult___fst_exp__h498676 != 11'd0, - _theResult___snd__h498627[56:5] } + + _theResult___fst_exp__h498674 != 11'd0, + _theResult___snd__h498625[56:5] } + 54'd1 ; - assign sfd__h508345 = + assign sfd__h508343 = { 1'b0, - _theResult___fst_exp__h508253 != 11'd0, - sfdin__h508247[56:5] } + + _theResult___fst_exp__h508251 != 11'd0, + sfdin__h508245[56:5] } + 54'd1 ; - assign sfd__h517105 = + assign sfd__h517103 = { 1'b0, - _theResult___fst_exp__h517086 != 11'd0, - _theResult___snd__h517032[56:5] } + + _theResult___fst_exp__h517084 != 11'd0, + _theResult___snd__h517030[56:5] } + 54'd1 ; - assign sfd__h518617 = { value__h523034, 32'd0 } ; - assign sfd__h537495 = + assign sfd__h518615 = { value__h523032, 32'd0 } ; + assign sfd__h537493 = { 1'b0, - _theResult___fst_exp__h537477 != 11'd0, - _theResult___snd__h537428[56:5] } + + _theResult___fst_exp__h537475 != 11'd0, + _theResult___snd__h537426[56:5] } + 54'd1 ; - assign sfd__h547146 = + assign sfd__h547144 = { 1'b0, - _theResult___fst_exp__h547054 != 11'd0, - sfdin__h547048[56:5] } + + _theResult___fst_exp__h547052 != 11'd0, + sfdin__h547046[56:5] } + 54'd1 ; - assign sfd__h555906 = + assign sfd__h555904 = { 1'b0, - _theResult___fst_exp__h555887 != 11'd0, - _theResult___snd__h555833[56:5] } + + _theResult___fst_exp__h555885 != 11'd0, + _theResult___snd__h555831[56:5] } + 54'd1 ; - assign sfd__h557818 = { value__h562235, 32'd0 } ; - assign sfd__h576696 = + assign sfd__h557816 = { value__h562233, 32'd0 } ; + assign sfd__h576694 = { 1'b0, - _theResult___fst_exp__h576678 != 11'd0, - _theResult___snd__h576629[56:5] } + + _theResult___fst_exp__h576676 != 11'd0, + _theResult___snd__h576627[56:5] } + 54'd1 ; - assign sfd__h586347 = + assign sfd__h586345 = { 1'b0, - _theResult___fst_exp__h586255 != 11'd0, - sfdin__h586249[56:5] } + + _theResult___fst_exp__h586253 != 11'd0, + sfdin__h586247[56:5] } + 54'd1 ; - assign sfd__h595107 = + assign sfd__h595105 = { 1'b0, - _theResult___fst_exp__h595088 != 11'd0, - _theResult___snd__h595034[56:5] } + + _theResult___fst_exp__h595086 != 11'd0, + _theResult___snd__h595032[56:5] } + 54'd1 ; - assign sfdin__h351407 = - _theResult____h343302[56] ? - _theResult___snd__h351424 : - _theResult___snd__h351435 ; - assign sfdin__h369173 = - _theResult____h360941[56] ? - _theResult___snd__h369190 : - _theResult___snd__h369201 ; - assign sfdin__h397097 = - _theResult____h388994[56] ? - _theResult___snd__h397114 : - _theResult___snd__h397125 ; - assign sfdin__h414863 = - _theResult____h406631[56] ? - _theResult___snd__h414880 : - _theResult___snd__h414891 ; - assign sfdin__h442785 = - _theResult____h434682[56] ? - _theResult___snd__h442802 : - _theResult___snd__h442813 ; - assign sfdin__h460551 = - _theResult____h452319[56] ? - _theResult___snd__h460568 : - _theResult___snd__h460579 ; - assign sfdin__h508247 = - _theResult____h500017[56] ? - _theResult___snd__h508264 : - _theResult___snd__h508275 ; - assign sfdin__h547048 = - _theResult____h538818[56] ? - _theResult___snd__h547065 : - _theResult___snd__h547076 ; - assign sfdin__h586249 = - _theResult____h578019[56] ? - _theResult___snd__h586266 : - _theResult___snd__h586277 ; - assign shiftData__h180516 = - coreFix_memExe_regToExeQ$first[75:12] << x__h180648 ; - assign sie_csr__read__h606413 = - { r1__read__h609241, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h606786 = - { r1__read__h609795, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h678443 = specTagManager$currentSpecBits | y__h678456 ; - assign sstatus_csr__read__h606344 = { r1__read__h608837, csrf_ie_vec_0 } ; - assign stvec_csr__read__h606456 = - { r1__read__h609771, csrf_stvec_mode_low_reg } ; + assign sfdin__h351405 = + _theResult____h343300[56] ? + _theResult___snd__h351422 : + _theResult___snd__h351433 ; + assign sfdin__h369171 = + _theResult____h360939[56] ? + _theResult___snd__h369188 : + _theResult___snd__h369199 ; + assign sfdin__h397095 = + _theResult____h388992[56] ? + _theResult___snd__h397112 : + _theResult___snd__h397123 ; + assign sfdin__h414861 = + _theResult____h406629[56] ? + _theResult___snd__h414878 : + _theResult___snd__h414889 ; + assign sfdin__h442783 = + _theResult____h434680[56] ? + _theResult___snd__h442800 : + _theResult___snd__h442811 ; + assign sfdin__h460549 = + _theResult____h452317[56] ? + _theResult___snd__h460566 : + _theResult___snd__h460577 ; + assign sfdin__h508245 = + _theResult____h500015[56] ? + _theResult___snd__h508262 : + _theResult___snd__h508273 ; + assign sfdin__h547046 = + _theResult____h538816[56] ? + _theResult___snd__h547063 : + _theResult___snd__h547074 ; + assign sfdin__h586247 = + _theResult____h578017[56] ? + _theResult___snd__h586264 : + _theResult___snd__h586275 ; + assign shiftData__h180514 = + coreFix_memExe_regToExeQ$first[75:12] << x__h180646 ; + assign sie_csr__read__h606414 = + { r1__read__h609242, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h606787 = + { r1__read__h609796, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h678441 = specTagManager$currentSpecBits | y__h678454 ; + assign sstatus_csr__read__h606345 = { r1__read__h608838, csrf_ie_vec_0 } ; + assign stvec_csr__read__h606457 = + { r1__read__h609772, csrf_stvec_mode_low_reg } ; assign upd__h3639 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; assign upd__h4956 = n__read__h6134 + 64'd1 ; - assign v__h293163 = + assign v__h293161 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ? - v__h293394 : + v__h293392 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h293394 = + assign v__h293392 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h296508 = + assign v__h296506 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ? - v__h297026 : + v__h297024 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h297026 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h307022 = + assign v__h297024 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h307020 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ? - v__h307253 : + v__h307251 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h307253 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h310898 = + assign v__h307251 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h310896 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ? - v__h311129 : + v__h311127 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h311129 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h325499 = + assign v__h311127 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h325497 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ? - v__h325730 : + v__h325728 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h325730 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h328724 = + assign v__h325728 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h328722 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ? - v__h328955 : + v__h328953 : coreFix_memExe_forwardQ_enqP ; - assign v__h328955 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h600774 = + assign v__h328953 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h600772 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h600784 : + v__h600782 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h600784 = + assign v__h600782 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h601419 = v__h600774 - 2'd1 ; - assign v__h604754 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605660 ; - assign v__h628444 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629197 ; - assign vaddr__h180511 = + assign v__h601417 = v__h600772 - 2'd1 ; + assign v__h604755 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605661 ; + assign v__h628443 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629196 ; + assign vaddr__h180509 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 } ; - assign value__h343924 = + assign value__h343922 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h389614 = + assign value__h389612 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h435302 = + assign value__h435300 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h484233 = + assign value__h484231 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ; - assign value__h523034 = + assign value__h523032 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ; - assign value__h562235 = + assign value__h562233 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ; - assign vm_mode_reg__read__h610031 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h641100 = + assign vm_mode_reg__read__h610032 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h641098 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h641156 : + result__h641154 : 12'd4095 ; assign x__h152884 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? @@ -29298,130 +29298,130 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h180425 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179513 ; - assign x__h180426 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180119 ; - assign x__h180648 = { vaddr__h180511[2:0], 3'b0 } ; - assign x__h190902 = + assign x__h180423 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179511 ; + assign x__h180424 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180117 ; + assign x__h180646 = { vaddr__h180509[2:0], 3'b0 } ; + assign x__h190900 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h190139[63:32] : - curData__h190139[31:0] ; + curData__h190137[63:32] : + curData__h190137[31:0] ; assign x__h20210 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h284501 = + assign x__h284499 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h284513 = + assign x__h284511 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h286367 = + assign x__h286365 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h299373 = + assign x__h299371 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h335101 = - { (_theResult___exp__h378433 != 8'd255 || - _theResult___sfd__h378434 == 23'd0) && + assign x__h335099 = + { (_theResult___exp__h378431 != 8'd255 || + _theResult___sfd__h378432 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - out_f_exp__h378710, - out_f_sfd__h378711 } ; - assign x__h361651 = - sfd__h335697 << (x__h361684[11] ? 12'hAAA : x__h361684) ; - assign x__h361684 = + out_f_exp__h378708, + out_f_sfd__h378709 } ; + assign x__h361649 = + sfd__h335695 << (x__h361682[11] ? 12'hAAA : x__h361682) ; + assign x__h361682 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ; - assign x__h380796 = - { (_theResult___exp__h424123 != 8'd255 || - _theResult___sfd__h424124 == 23'd0) && + assign x__h380794 = + { (_theResult___exp__h424121 != 8'd255 || + _theResult___sfd__h424122 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - out_f_exp__h424400, - out_f_sfd__h424401 } ; - assign x__h407341 = - sfd__h381392 << (x__h407374[11] ? 12'hAAA : x__h407374) ; - assign x__h407374 = + out_f_exp__h424398, + out_f_sfd__h424399 } ; + assign x__h407339 = + sfd__h381390 << (x__h407372[11] ? 12'hAAA : x__h407372) ; + assign x__h407372 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ; - assign x__h426484 = - { (_theResult___exp__h469811 != 8'd255 || - _theResult___sfd__h469812 == 23'd0) && + assign x__h426482 = + { (_theResult___exp__h469809 != 8'd255 || + _theResult___sfd__h469810 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - out_f_exp__h470088, - out_f_sfd__h470089 } ; - assign x__h453029 = - sfd__h427080 << (x__h453062[11] ? 12'hAAA : x__h453062) ; - assign x__h453062 = + out_f_exp__h470086, + out_f_sfd__h470087 } ; + assign x__h453027 = + sfd__h427078 << (x__h453060[11] ? 12'hAAA : x__h453060) ; + assign x__h453060 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ; assign x__h45579 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; + assign x__h478868 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476004 ; + assign x__h478869 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476612 ; assign x__h478870 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476006 ; - assign x__h478871 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476614 ; - assign x__h478872 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477216 ; + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477214 ; assign x__h48115 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h500725 = sfd__h479675 << x__h500758 ; - assign x__h500758 = + assign x__h500723 = sfd__h479673 << x__h500756 ; + assign x__h500756 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; - assign x__h539526 = sfd__h518617 << x__h539559 ; - assign x__h539559 = + assign x__h539524 = sfd__h518615 << x__h539557 ; + assign x__h539557 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; - assign x__h578727 = sfd__h557818 << x__h578760 ; - assign x__h578760 = + assign x__h578725 = sfd__h557816 << x__h578758 ; + assign x__h578758 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; - assign x__h600275 = a__h599839[63] ^ b__h599840[63] ; - assign x__h608822 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h613033 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h605870 : - v__h604754 ; + assign x__h600273 = a__h599837[63] ^ b__h599838[63] ; + assign x__h608823 = { csrf_frm_reg, csrf_fflags_reg } ; assign x__h613034 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610922 ; - assign x__h634256 = + coreFix_aluExe_1_dispToRegQ$first[131] ? + rVal1__h605871 : + v__h604755 ; + assign x__h613035 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610923 ; + assign x__h634254 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h629405 : - v__h628444 ; - assign x__h634257 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632155 ; - assign x__h641104 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h641155 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h688725 = + rVal1__h629404 : + v__h628443 ; + assign x__h634255 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632153 ; + assign x__h641102 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h641153 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h688723 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h694806 = { cause_code__h692189, 2'b0 } ; - assign x__h702602 = { 1'b0, csrf_spp_reg } ; - assign x__h705875 = + assign x__h694804 = { cause_code__h692187, 2'b0 } ; + assign x__h702600 = { 1'b0, csrf_spp_reg } ; + assign x__h705873 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_fst__h705697 : + y_avValue_snd_snd_snd_fst__h705695 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 ; assign x__h75524 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h311296 = + assign x_addr__h311294 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; @@ -29429,29 +29429,29 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h667949 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h682692 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h649137 = csrf_frm_reg ; - assign x_quotient__h472395 = + assign x_data_imm__h667947 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h682690 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h649135 = csrf_frm_reg ; + assign x_quotient__h472393 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h473080 : + q___1__h473078 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h606253 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h472396 = + assign x_reg_ifc__read__h606254 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h472394 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h473106 : + r___1__h473104 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h252026 = + assign y__h252024 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h641134 = ~x__h641104 ; - assign y__h645907 = + assign y__h641132 = ~x__h641102 ; + assign y__h645905 = { 3'd7, ~csrf_mideleg_11_reg, 1'd1, @@ -29460,71 +29460,71 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h678456 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h705650 = + assign y__h678454 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h705648 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_snd_snd__h705703 : + y_avValue_snd_snd_snd_snd_snd__h705701 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 ; - assign y_avValue__h179513 = + assign y_avValue__h179511 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ; - assign y_avValue__h180119 = + assign y_avValue__h180117 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ; - assign y_avValue__h476006 = + assign y_avValue__h476004 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ; - assign y_avValue__h476614 = + assign y_avValue__h476612 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ; - assign y_avValue__h477216 = + assign y_avValue__h477214 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ; - assign y_avValue__h605660 = + assign y_avValue__h605661 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11330 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11708 ; - assign y_avValue__h610922 = + assign y_avValue__h610923 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11358 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11720 ; - assign y_avValue__h629197 = + assign y_avValue__h629196 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12125 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12317 ; - assign y_avValue__h632155 = + assign y_avValue__h632153 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12153 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12329 ; - assign y_avValue__h693067 = + assign y_avValue__h693065 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694791 + { 58'd0, x__h694806 } : - base__h694791 ; - assign y_avValue__h694828 = + base__h694789 + { 58'd0, x__h694804 } : + base__h694789 ; + assign y_avValue__h694826 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694994 + { 58'd0, x__h694806 } : - base__h694994 ; - assign y_avValue_fst__h671840 = + base__h694992 + { 58'd0, x__h694804 } : + base__h694992 ; + assign y_avValue_fst__h671838 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h678443 : + spec_bits__h678441 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672114 = + assign y_avValue_snd_fst__h672112 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207) ? - y_avValue_snd_fst__h672149 : + y_avValue_snd_fst__h672147 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672149 = + assign y_avValue_snd_fst__h672147 = IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 ? - y_avValue_fst__h671840 : + y_avValue_fst__h671838 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h705134 = + assign y_avValue_snd_fst__h705132 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29538,7 +29538,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h705687 = + assign y_avValue_snd_fst__h705685 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29551,11 +29551,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 : - y_avValue_snd_fst__h705716 ; - assign y_avValue_snd_fst__h705716 = + y_avValue_snd_fst__h705714 ; + assign y_avValue_snd_fst__h705714 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_snd_snd_fst__h705144 = + assign y_avValue_snd_snd_snd_fst__h705142 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29569,7 +29569,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h705697 = + assign y_avValue_snd_snd_snd_fst__h705695 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29582,11 +29582,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 : - y_avValue_snd_snd_snd_fst__h705726 ; - assign y_avValue_snd_snd_snd_fst__h705726 = + y_avValue_snd_snd_snd_fst__h705724 ; + assign y_avValue_snd_snd_snd_fst__h705724 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705150 = + assign y_avValue_snd_snd_snd_snd_snd__h705148 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29600,7 +29600,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705703 = + assign y_avValue_snd_snd_snd_snd_snd__h705701 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29613,8 +29613,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 : - y_avValue_snd_snd_snd_snd_snd__h705732 ; - assign y_avValue_snd_snd_snd_snd_snd__h705732 = + y_avValue_snd_snd_snd_snd_snd__h705730 ; + assign y_avValue_snd_snd_snd_snd_snd__h705730 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -29633,28 +29633,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h194349 = + x__h194347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -29670,28 +29670,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h283068 = + x__h283066 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -29701,10 +29701,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h287289 = + addr__h287287 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h287289 = + addr__h287287 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -29713,36 +29713,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h190139 = + curData__h190137 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h693220 = commitStage_commitTrap[132:69]; - default: trap_val__h693220 = + 4'd0, 4'd3: trap_val__h693218 = commitStage_commitTrap[132:69]; + default: trap_val__h693218 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -29757,247 +29757,247 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h288836 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h288836 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h606123 or - frm_csr__read__h606134 or - fcsr_csr__read__h606148 or - sstatus_csr__read__h606344 or - sie_csr__read__h606413 or - stvec_csr__read__h606456 or - scounteren_csr__read__h606509 or + fflags_csr__read__h606124 or + frm_csr__read__h606135 or + fcsr_csr__read__h606149 or + sstatus_csr__read__h606345 or + sie_csr__read__h606414 or + stvec_csr__read__h606457 or + scounteren_csr__read__h606510 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606647 or + scause_csr__read__h606648 or csrf_stval_csr or - sip_csr__read__h606786 or - satp_csr__read__h606849 or - mstatus_csr__read__h606992 or - medeleg_csr__read__h607140 or - mideleg_csr__read__h607235 or - mie_csr__read__h607366 or - mtvec_csr__read__h607448 or - mcounteren_csr__read__h607540 or + sip_csr__read__h606787 or + satp_csr__read__h606850 or + mstatus_csr__read__h606993 or + medeleg_csr__read__h607141 or + mideleg_csr__read__h607236 or + mie_csr__read__h607367 or + mtvec_csr__read__h607449 or + mcounteren_csr__read__h607541 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607795 or + mcause_csr__read__h607796 or csrf_mtval_csr or - mip_csr__read__h608035 or - x_reg_ifc__read__h606253 or - n__read__h608139 or n__read__h608330 or csrf_time_reg) + mip_csr__read__h608036 or + x_reg_ifc__read__h606254 or + n__read__h608140 or n__read__h608331 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h605870 = fflags_csr__read__h606123; - 12'd2: rVal1__h605870 = frm_csr__read__h606134; - 12'd3: rVal1__h605870 = fcsr_csr__read__h606148; - 12'd256: rVal1__h605870 = sstatus_csr__read__h606344; - 12'd260: rVal1__h605870 = sie_csr__read__h606413; - 12'd261: rVal1__h605870 = stvec_csr__read__h606456; - 12'd262: rVal1__h605870 = scounteren_csr__read__h606509; - 12'd320: rVal1__h605870 = csrf_sscratch_csr; - 12'd321: rVal1__h605870 = csrf_sepc_csr; - 12'd322: rVal1__h605870 = scause_csr__read__h606647; - 12'd323: rVal1__h605870 = csrf_stval_csr; - 12'd324: rVal1__h605870 = sip_csr__read__h606786; - 12'd384: rVal1__h605870 = satp_csr__read__h606849; - 12'd768: rVal1__h605870 = mstatus_csr__read__h606992; - 12'd769: rVal1__h605870 = 64'h8000000000141129; - 12'd770: rVal1__h605870 = medeleg_csr__read__h607140; - 12'd771: rVal1__h605870 = mideleg_csr__read__h607235; - 12'd772: rVal1__h605870 = mie_csr__read__h607366; - 12'd773: rVal1__h605870 = mtvec_csr__read__h607448; - 12'd774: rVal1__h605870 = mcounteren_csr__read__h607540; - 12'd832: rVal1__h605870 = csrf_mscratch_csr; - 12'd833: rVal1__h605870 = csrf_mepc_csr; - 12'd834: rVal1__h605870 = mcause_csr__read__h607795; - 12'd835: rVal1__h605870 = csrf_mtval_csr; - 12'd836: rVal1__h605870 = mip_csr__read__h608035; - 12'd2048: rVal1__h605870 = 64'd0; - 12'd2049: rVal1__h605870 = x_reg_ifc__read__h606253; - 12'd2816, 12'd3072: rVal1__h605870 = n__read__h608139; - 12'd2818, 12'd3074: rVal1__h605870 = n__read__h608330; - 12'd3073: rVal1__h605870 = csrf_time_reg; - default: rVal1__h605870 = 64'd0; + 12'd1: rVal1__h605871 = fflags_csr__read__h606124; + 12'd2: rVal1__h605871 = frm_csr__read__h606135; + 12'd3: rVal1__h605871 = fcsr_csr__read__h606149; + 12'd256: rVal1__h605871 = sstatus_csr__read__h606345; + 12'd260: rVal1__h605871 = sie_csr__read__h606414; + 12'd261: rVal1__h605871 = stvec_csr__read__h606457; + 12'd262: rVal1__h605871 = scounteren_csr__read__h606510; + 12'd320: rVal1__h605871 = csrf_sscratch_csr; + 12'd321: rVal1__h605871 = csrf_sepc_csr; + 12'd322: rVal1__h605871 = scause_csr__read__h606648; + 12'd323: rVal1__h605871 = csrf_stval_csr; + 12'd324: rVal1__h605871 = sip_csr__read__h606787; + 12'd384: rVal1__h605871 = satp_csr__read__h606850; + 12'd768: rVal1__h605871 = mstatus_csr__read__h606993; + 12'd769: rVal1__h605871 = 64'h8000000000141129; + 12'd770: rVal1__h605871 = medeleg_csr__read__h607141; + 12'd771: rVal1__h605871 = mideleg_csr__read__h607236; + 12'd772: rVal1__h605871 = mie_csr__read__h607367; + 12'd773: rVal1__h605871 = mtvec_csr__read__h607449; + 12'd774: rVal1__h605871 = mcounteren_csr__read__h607541; + 12'd832: rVal1__h605871 = csrf_mscratch_csr; + 12'd833: rVal1__h605871 = csrf_mepc_csr; + 12'd834: rVal1__h605871 = mcause_csr__read__h607796; + 12'd835: rVal1__h605871 = csrf_mtval_csr; + 12'd836: rVal1__h605871 = mip_csr__read__h608036; + 12'd2048: rVal1__h605871 = 64'd0; + 12'd2049: rVal1__h605871 = x_reg_ifc__read__h606254; + 12'd2816, 12'd3072: rVal1__h605871 = n__read__h608140; + 12'd2818, 12'd3074: rVal1__h605871 = n__read__h608331; + 12'd3073: rVal1__h605871 = csrf_time_reg; + default: rVal1__h605871 = 64'd0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h606123 or - frm_csr__read__h606134 or - fcsr_csr__read__h606148 or - sstatus_csr__read__h606344 or - sie_csr__read__h606413 or - stvec_csr__read__h606456 or - scounteren_csr__read__h606509 or + fflags_csr__read__h606124 or + frm_csr__read__h606135 or + fcsr_csr__read__h606149 or + sstatus_csr__read__h606345 or + sie_csr__read__h606414 or + stvec_csr__read__h606457 or + scounteren_csr__read__h606510 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606647 or + scause_csr__read__h606648 or csrf_stval_csr or - sip_csr__read__h606786 or - satp_csr__read__h606849 or - mstatus_csr__read__h606992 or - medeleg_csr__read__h607140 or - mideleg_csr__read__h607235 or - mie_csr__read__h607366 or - mtvec_csr__read__h607448 or - mcounteren_csr__read__h607540 or + sip_csr__read__h606787 or + satp_csr__read__h606850 or + mstatus_csr__read__h606993 or + medeleg_csr__read__h607141 or + mideleg_csr__read__h607236 or + mie_csr__read__h607367 or + mtvec_csr__read__h607449 or + mcounteren_csr__read__h607541 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607795 or + mcause_csr__read__h607796 or csrf_mtval_csr or - mip_csr__read__h608035 or - x_reg_ifc__read__h606253 or - n__read__h608139 or n__read__h608330 or csrf_time_reg) + mip_csr__read__h608036 or + x_reg_ifc__read__h606254 or + n__read__h608140 or n__read__h608331 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h629405 = fflags_csr__read__h606123; - 12'd2: rVal1__h629405 = frm_csr__read__h606134; - 12'd3: rVal1__h629405 = fcsr_csr__read__h606148; - 12'd256: rVal1__h629405 = sstatus_csr__read__h606344; - 12'd260: rVal1__h629405 = sie_csr__read__h606413; - 12'd261: rVal1__h629405 = stvec_csr__read__h606456; - 12'd262: rVal1__h629405 = scounteren_csr__read__h606509; - 12'd320: rVal1__h629405 = csrf_sscratch_csr; - 12'd321: rVal1__h629405 = csrf_sepc_csr; - 12'd322: rVal1__h629405 = scause_csr__read__h606647; - 12'd323: rVal1__h629405 = csrf_stval_csr; - 12'd324: rVal1__h629405 = sip_csr__read__h606786; - 12'd384: rVal1__h629405 = satp_csr__read__h606849; - 12'd768: rVal1__h629405 = mstatus_csr__read__h606992; - 12'd769: rVal1__h629405 = 64'h8000000000141129; - 12'd770: rVal1__h629405 = medeleg_csr__read__h607140; - 12'd771: rVal1__h629405 = mideleg_csr__read__h607235; - 12'd772: rVal1__h629405 = mie_csr__read__h607366; - 12'd773: rVal1__h629405 = mtvec_csr__read__h607448; - 12'd774: rVal1__h629405 = mcounteren_csr__read__h607540; - 12'd832: rVal1__h629405 = csrf_mscratch_csr; - 12'd833: rVal1__h629405 = csrf_mepc_csr; - 12'd834: rVal1__h629405 = mcause_csr__read__h607795; - 12'd835: rVal1__h629405 = csrf_mtval_csr; - 12'd836: rVal1__h629405 = mip_csr__read__h608035; - 12'd2048: rVal1__h629405 = 64'd0; - 12'd2049: rVal1__h629405 = x_reg_ifc__read__h606253; - 12'd2816, 12'd3072: rVal1__h629405 = n__read__h608139; - 12'd2818, 12'd3074: rVal1__h629405 = n__read__h608330; - 12'd3073: rVal1__h629405 = csrf_time_reg; - default: rVal1__h629405 = 64'd0; + 12'd1: rVal1__h629404 = fflags_csr__read__h606124; + 12'd2: rVal1__h629404 = frm_csr__read__h606135; + 12'd3: rVal1__h629404 = fcsr_csr__read__h606149; + 12'd256: rVal1__h629404 = sstatus_csr__read__h606345; + 12'd260: rVal1__h629404 = sie_csr__read__h606414; + 12'd261: rVal1__h629404 = stvec_csr__read__h606457; + 12'd262: rVal1__h629404 = scounteren_csr__read__h606510; + 12'd320: rVal1__h629404 = csrf_sscratch_csr; + 12'd321: rVal1__h629404 = csrf_sepc_csr; + 12'd322: rVal1__h629404 = scause_csr__read__h606648; + 12'd323: rVal1__h629404 = csrf_stval_csr; + 12'd324: rVal1__h629404 = sip_csr__read__h606787; + 12'd384: rVal1__h629404 = satp_csr__read__h606850; + 12'd768: rVal1__h629404 = mstatus_csr__read__h606993; + 12'd769: rVal1__h629404 = 64'h8000000000141129; + 12'd770: rVal1__h629404 = medeleg_csr__read__h607141; + 12'd771: rVal1__h629404 = mideleg_csr__read__h607236; + 12'd772: rVal1__h629404 = mie_csr__read__h607367; + 12'd773: rVal1__h629404 = mtvec_csr__read__h607449; + 12'd774: rVal1__h629404 = mcounteren_csr__read__h607541; + 12'd832: rVal1__h629404 = csrf_mscratch_csr; + 12'd833: rVal1__h629404 = csrf_mepc_csr; + 12'd834: rVal1__h629404 = mcause_csr__read__h607796; + 12'd835: rVal1__h629404 = csrf_mtval_csr; + 12'd836: rVal1__h629404 = mip_csr__read__h608036; + 12'd2048: rVal1__h629404 = 64'd0; + 12'd2049: rVal1__h629404 = x_reg_ifc__read__h606254; + 12'd2816, 12'd3072: rVal1__h629404 = n__read__h608140; + 12'd2818, 12'd3074: rVal1__h629404 = n__read__h608331; + 12'd3073: rVal1__h629404 = csrf_time_reg; + default: rVal1__h629404 = 64'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h388976 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h388974 = 8'd255; 3'd2: - _theResult___fst_exp__h388976 = + _theResult___fst_exp__h388974 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h388976 = + _theResult___fst_exp__h388974 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h388976 = 8'd254; - default: _theResult___fst_exp__h388976 = 8'd0; + 3'd4: _theResult___fst_exp__h388974 = 8'd254; + default: _theResult___fst_exp__h388974 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h343284 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h343282 = 8'd255; 3'd2: - _theResult___fst_exp__h343284 = + _theResult___fst_exp__h343282 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h343284 = + _theResult___fst_exp__h343282 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h343284 = 8'd254; - default: _theResult___fst_exp__h343284 = 8'd0; + 3'd4: _theResult___fst_exp__h343282 = 8'd254; + default: _theResult___fst_exp__h343282 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h343285 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h343283 = 23'd0; 3'd2: - _theResult___fst_sfd__h343285 = + _theResult___fst_sfd__h343283 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h343285 = + _theResult___fst_sfd__h343283 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h343285 = 23'd8388607; - default: _theResult___fst_sfd__h343285 = 23'd0; + 3'd4: _theResult___fst_sfd__h343283 = 23'd8388607; + default: _theResult___fst_sfd__h343283 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h388977 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h388975 = 23'd0; 3'd2: - _theResult___fst_sfd__h388977 = + _theResult___fst_sfd__h388975 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h388977 = + _theResult___fst_sfd__h388975 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h388977 = 23'd8388607; - default: _theResult___fst_sfd__h388977 = 23'd0; + 3'd4: _theResult___fst_sfd__h388975 = 23'd8388607; + default: _theResult___fst_sfd__h388975 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h434664 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h434662 = 8'd255; 3'd2: - _theResult___fst_exp__h434664 = + _theResult___fst_exp__h434662 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h434664 = + _theResult___fst_exp__h434662 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h434664 = 8'd254; - default: _theResult___fst_exp__h434664 = 8'd0; + 3'd4: _theResult___fst_exp__h434662 = 8'd254; + default: _theResult___fst_exp__h434662 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h434665 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h434663 = 23'd0; 3'd2: - _theResult___fst_sfd__h434665 = + _theResult___fst_sfd__h434663 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h434665 = + _theResult___fst_sfd__h434663 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h434665 = 23'd8388607; - default: _theResult___fst_sfd__h434665 = 23'd0; + 3'd4: _theResult___fst_sfd__h434663 = 23'd8388607; + default: _theResult___fst_sfd__h434663 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -30124,16 +30124,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h692204 = commitStage_commitTrap[3:0]; - default: i__h692204 = 4'd15; + i__h692202 = commitStage_commitTrap[3:0]; + default: i__h692202 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11: - i__h692364 = commitStage_commitTrap[3:0]; - default: i__h692364 = 4'd14; + i__h692362 = commitStage_commitTrap[3:0]; + default: i__h692362 = 4'd14; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -30374,446 +30374,446 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352021 or - _theResult___fst_exp__h360069 or - out_exp__h360514 or _theResult___exp__h360511) + always@(guard__h352019 or + _theResult___fst_exp__h360067 or + out_exp__h360512 or _theResult___exp__h360509) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = - _theResult___fst_exp__h360069; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = + _theResult___fst_exp__h360067; 2'b10: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = - out_exp__h360514; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = + out_exp__h360512; 2'b11: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = - _theResult___exp__h360511; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 = + _theResult___exp__h360509; endcase end - always@(guard__h352021 or - _theResult___fst_exp__h360069 or _theResult___exp__h360511) + always@(guard__h352019 or + _theResult___fst_exp__h360067 or _theResult___exp__h360509) begin - case (guard__h352021) + case (guard__h352019) 2'b0: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = - _theResult___fst_exp__h360069; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 = + _theResult___fst_exp__h360067; 2'b01, 2'b10, 2'b11: - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = - _theResult___exp__h360511; + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 = + _theResult___exp__h360509; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 or - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 or + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24 or + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or - _theResult___fst_exp__h360069) + _theResult___fst_exp__h360067) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h360589 = - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24; + _theResult___fst_exp__h360587 = + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q24; 3'd1: - _theResult___fst_exp__h360589 = - CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25; + _theResult___fst_exp__h360587 = + CASE_guard52019_0b0_theResult___fst_exp60067_0_ETC__q25; 3'd2: - _theResult___fst_exp__h360589 = + _theResult___fst_exp__h360587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528; 3'd3: - _theResult___fst_exp__h360589 = + _theResult___fst_exp__h360587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530; - 3'd4: _theResult___fst_exp__h360589 = _theResult___fst_exp__h360069; - default: _theResult___fst_exp__h360589 = 8'd0; + 3'd4: _theResult___fst_exp__h360587 = _theResult___fst_exp__h360067; + default: _theResult___fst_exp__h360587 = 8'd0; endcase end - always@(guard__h343312 or - _theResult___fst_exp__h351413 or - out_exp__h351932 or _theResult___exp__h351929) + always@(guard__h343310 or + _theResult___fst_exp__h351411 or + out_exp__h351930 or _theResult___exp__h351927) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = - _theResult___fst_exp__h351413; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = + _theResult___fst_exp__h351411; 2'b10: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = - out_exp__h351932; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = + out_exp__h351930; 2'b11: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = - _theResult___exp__h351929; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 = + _theResult___exp__h351927; endcase end - always@(guard__h343312 or - _theResult___fst_exp__h351413 or _theResult___exp__h351929) + always@(guard__h343310 or + _theResult___fst_exp__h351411 or _theResult___exp__h351927) begin - case (guard__h343312) + case (guard__h343310) 2'b0: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = - _theResult___fst_exp__h351413; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 = + _theResult___fst_exp__h351411; 2'b01, 2'b10, 2'b11: - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = - _theResult___exp__h351929; + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 = + _theResult___exp__h351927; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 or - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 or + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26 or + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or - _theResult___fst_exp__h351413) + _theResult___fst_exp__h351411) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h352007 = - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26; + _theResult___fst_exp__h352005 = + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q26; 3'd1: - _theResult___fst_exp__h352007 = - CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27; + _theResult___fst_exp__h352005 = + CASE_guard43310_0b0_theResult___fst_exp51411_0_ETC__q27; 3'd2: - _theResult___fst_exp__h352007 = + _theResult___fst_exp__h352005 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306; 3'd3: - _theResult___fst_exp__h352007 = + _theResult___fst_exp__h352005 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309; - 3'd4: _theResult___fst_exp__h352007 = _theResult___fst_exp__h351413; - default: _theResult___fst_exp__h352007 = 8'd0; + 3'd4: _theResult___fst_exp__h352005 = _theResult___fst_exp__h351411; + default: _theResult___fst_exp__h352005 = 8'd0; endcase end - always@(guard__h360951 or - _theResult___fst_exp__h369179 or - out_exp__h369698 or _theResult___exp__h369695) + always@(guard__h360949 or + _theResult___fst_exp__h369177 or + out_exp__h369696 or _theResult___exp__h369693) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = - _theResult___fst_exp__h369179; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = + _theResult___fst_exp__h369177; 2'b10: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = - out_exp__h369698; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = + out_exp__h369696; 2'b11: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = - _theResult___exp__h369695; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 = + _theResult___exp__h369693; endcase end - always@(guard__h360951 or - _theResult___fst_exp__h369179 or _theResult___exp__h369695) + always@(guard__h360949 or + _theResult___fst_exp__h369177 or _theResult___exp__h369693) begin - case (guard__h360951) + case (guard__h360949) 2'b0: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = - _theResult___fst_exp__h369179; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 = + _theResult___fst_exp__h369177; 2'b01, 2'b10, 2'b11: - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = - _theResult___exp__h369695; + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 = + _theResult___exp__h369693; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 or - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 or + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32 or + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or - _theResult___fst_exp__h369179) + _theResult___fst_exp__h369177) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h369773 = - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32; + _theResult___fst_exp__h369771 = + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q32; 3'd1: - _theResult___fst_exp__h369773 = - CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33; + _theResult___fst_exp__h369771 = + CASE_guard60949_0b0_theResult___fst_exp69177_0_ETC__q33; 3'd2: - _theResult___fst_exp__h369773 = + _theResult___fst_exp__h369771 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853; 3'd3: - _theResult___fst_exp__h369773 = + _theResult___fst_exp__h369771 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855; - 3'd4: _theResult___fst_exp__h369773 = _theResult___fst_exp__h369179; - default: _theResult___fst_exp__h369773 = 8'd0; + 3'd4: _theResult___fst_exp__h369771 = _theResult___fst_exp__h369177; + default: _theResult___fst_exp__h369771 = 8'd0; endcase end - always@(guard__h369787 or - _theResult___fst_exp__h377864 or - out_exp__h378334 or _theResult___exp__h378331) + always@(guard__h369785 or + _theResult___fst_exp__h377862 or + out_exp__h378332 or _theResult___exp__h378329) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = - _theResult___fst_exp__h377864; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = + _theResult___fst_exp__h377862; 2'b10: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = - out_exp__h378334; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = + out_exp__h378332; 2'b11: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = - _theResult___exp__h378331; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 = + _theResult___exp__h378329; endcase end - always@(guard__h369787 or - _theResult___fst_exp__h377864 or _theResult___exp__h378331) + always@(guard__h369785 or + _theResult___fst_exp__h377862 or _theResult___exp__h378329) begin - case (guard__h369787) + case (guard__h369785) 2'b0: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = - _theResult___fst_exp__h377864; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 = + _theResult___fst_exp__h377862; 2'b01, 2'b10, 2'b11: - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = - _theResult___exp__h378331; + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 = + _theResult___exp__h378329; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 or - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 or + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37 or + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or - _theResult___fst_exp__h377864) + _theResult___fst_exp__h377862) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h378409 = - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37; + _theResult___fst_exp__h378407 = + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q37; 3'd1: - _theResult___fst_exp__h378409 = - CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38; + _theResult___fst_exp__h378407 = + CASE_guard69785_0b0_theResult___fst_exp77862_0_ETC__q38; 3'd2: - _theResult___fst_exp__h378409 = + _theResult___fst_exp__h378407 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922; 3'd3: - _theResult___fst_exp__h378409 = + _theResult___fst_exp__h378407 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924; - 3'd4: _theResult___fst_exp__h378409 = _theResult___fst_exp__h377864; - default: _theResult___fst_exp__h378409 = 8'd0; + 3'd4: _theResult___fst_exp__h378407 = _theResult___fst_exp__h377862; + default: _theResult___fst_exp__h378407 = 8'd0; endcase end - always@(guard__h352021 or - _theResult___snd__h360020 or - out_sfd__h360515 or _theResult___sfd__h360512) + always@(guard__h352019 or + _theResult___snd__h360018 or + out_sfd__h360513 or _theResult___sfd__h360510) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = - _theResult___snd__h360020[56:34]; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = + _theResult___snd__h360018[56:34]; 2'b10: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = - out_sfd__h360515; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = + out_sfd__h360513; 2'b11: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = - _theResult___sfd__h360512; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 = + _theResult___sfd__h360510; endcase end - always@(guard__h352021 or - _theResult___snd__h360020 or _theResult___sfd__h360512) + always@(guard__h352019 or + _theResult___snd__h360018 or _theResult___sfd__h360510) begin - case (guard__h352021) + case (guard__h352019) 2'b0: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = - _theResult___snd__h360020[56:34]; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 = + _theResult___snd__h360018[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = - _theResult___sfd__h360512; + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 = + _theResult___sfd__h360510; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 or - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 or + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39 or + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or - _theResult___snd__h360020) + _theResult___snd__h360018) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h360590 = - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39; + _theResult___fst_sfd__h360588 = + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q39; 3'd1: - _theResult___fst_sfd__h360590 = - CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40; + _theResult___fst_sfd__h360588 = + CASE_guard52019_0b0_theResult___snd60018_BITS__ETC__q40; 3'd2: - _theResult___fst_sfd__h360590 = + _theResult___fst_sfd__h360588 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972; 3'd3: - _theResult___fst_sfd__h360590 = + _theResult___fst_sfd__h360588 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974; - 3'd4: _theResult___fst_sfd__h360590 = _theResult___snd__h360020[56:34]; - default: _theResult___fst_sfd__h360590 = 23'd0; + 3'd4: _theResult___fst_sfd__h360588 = _theResult___snd__h360018[56:34]; + default: _theResult___fst_sfd__h360588 = 23'd0; endcase end - always@(guard__h343312 or - sfdin__h351407 or out_sfd__h351933 or _theResult___sfd__h351930) + always@(guard__h343310 or + sfdin__h351405 or out_sfd__h351931 or _theResult___sfd__h351928) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = - sfdin__h351407[56:34]; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = + sfdin__h351405[56:34]; 2'b10: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = - out_sfd__h351933; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = + out_sfd__h351931; 2'b11: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = - _theResult___sfd__h351930; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 = + _theResult___sfd__h351928; endcase end - always@(guard__h343312 or sfdin__h351407 or _theResult___sfd__h351930) + always@(guard__h343310 or sfdin__h351405 or _theResult___sfd__h351928) begin - case (guard__h343312) + case (guard__h343310) 2'b0: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = - sfdin__h351407[56:34]; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 = + sfdin__h351405[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h351930; + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h351928; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 or - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 or + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41 or + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or - sfdin__h351407) + sfdin__h351405) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h352008 = - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41; + _theResult___fst_sfd__h352006 = + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q41; 3'd1: - _theResult___fst_sfd__h352008 = - CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42; + _theResult___fst_sfd__h352006 = + CASE_guard43310_0b0_sfdin51405_BITS_56_TO_34_0_ETC__q42; 3'd2: - _theResult___fst_sfd__h352008 = + _theResult___fst_sfd__h352006 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953; 3'd3: - _theResult___fst_sfd__h352008 = + _theResult___fst_sfd__h352006 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955; - 3'd4: _theResult___fst_sfd__h352008 = sfdin__h351407[56:34]; - default: _theResult___fst_sfd__h352008 = 23'd0; + 3'd4: _theResult___fst_sfd__h352006 = sfdin__h351405[56:34]; + default: _theResult___fst_sfd__h352006 = 23'd0; endcase end - always@(guard__h360951 or - sfdin__h369173 or out_sfd__h369699 or _theResult___sfd__h369696) + always@(guard__h360949 or + sfdin__h369171 or out_sfd__h369697 or _theResult___sfd__h369694) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = - sfdin__h369173[56:34]; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = + sfdin__h369171[56:34]; 2'b10: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = - out_sfd__h369699; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = + out_sfd__h369697; 2'b11: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h369696; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h369694; endcase end - always@(guard__h360951 or sfdin__h369173 or _theResult___sfd__h369696) + always@(guard__h360949 or sfdin__h369171 or _theResult___sfd__h369694) begin - case (guard__h360951) + case (guard__h360949) 2'b0: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = - sfdin__h369173[56:34]; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 = + sfdin__h369171[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h369696; + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h369694; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 or - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 or + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43 or + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or - sfdin__h369173) + sfdin__h369171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h369774 = - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43; + _theResult___fst_sfd__h369772 = + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q43; 3'd1: - _theResult___fst_sfd__h369774 = - CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44; + _theResult___fst_sfd__h369772 = + CASE_guard60949_0b0_sfdin69171_BITS_56_TO_34_0_ETC__q44; 3'd2: - _theResult___fst_sfd__h369774 = + _theResult___fst_sfd__h369772 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999; 3'd3: - _theResult___fst_sfd__h369774 = + _theResult___fst_sfd__h369772 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001; - 3'd4: _theResult___fst_sfd__h369774 = sfdin__h369173[56:34]; - default: _theResult___fst_sfd__h369774 = 23'd0; + 3'd4: _theResult___fst_sfd__h369772 = sfdin__h369171[56:34]; + default: _theResult___fst_sfd__h369772 = 23'd0; endcase end - always@(guard__h369787 or - _theResult___snd__h377810 or - out_sfd__h378335 or _theResult___sfd__h378332) + always@(guard__h369785 or + _theResult___snd__h377808 or + out_sfd__h378333 or _theResult___sfd__h378330) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = - _theResult___snd__h377810[56:34]; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = + _theResult___snd__h377808[56:34]; 2'b10: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = - out_sfd__h378335; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = + out_sfd__h378333; 2'b11: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = - _theResult___sfd__h378332; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 = + _theResult___sfd__h378330; endcase end - always@(guard__h369787 or - _theResult___snd__h377810 or _theResult___sfd__h378332) + always@(guard__h369785 or + _theResult___snd__h377808 or _theResult___sfd__h378330) begin - case (guard__h369787) + case (guard__h369785) 2'b0: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = - _theResult___snd__h377810[56:34]; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 = + _theResult___snd__h377808[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = - _theResult___sfd__h378332; + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 = + _theResult___sfd__h378330; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 or - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 or + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45 or + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or - _theResult___snd__h377810) + _theResult___snd__h377808) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h378410 = - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45; + _theResult___fst_sfd__h378408 = + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q45; 3'd1: - _theResult___fst_sfd__h378410 = - CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46; + _theResult___fst_sfd__h378408 = + CASE_guard69785_0b0_theResult___snd77808_BITS__ETC__q46; 3'd2: - _theResult___fst_sfd__h378410 = + _theResult___fst_sfd__h378408 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; 3'd3: - _theResult___fst_sfd__h378410 = + _theResult___fst_sfd__h378408 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; - 3'd4: _theResult___fst_sfd__h378410 = _theResult___snd__h377810[56:34]; - default: _theResult___fst_sfd__h378410 = 23'd0; + 3'd4: _theResult___fst_sfd__h378408 = _theResult___snd__h377808[56:34]; + default: _theResult___fst_sfd__h378408 = 23'd0; endcase end - always@(guard__h343312 or + always@(guard__h343310 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01, 2'b10: - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = - guard__h343312 == 2'b11 && + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + guard__h343310 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or - guard__h343312) + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or + guard__h343310) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; + CASE_guard43310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - (guard__h343312 == 2'b0) ? + (guard__h343310 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h343312 == 2'b01 || guard__h343312 == 2'b10 || - guard__h343312 == 2'b11) && + (guard__h343310 == 2'b01 || guard__h343310 == 2'b10 || + guard__h343310 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = @@ -30824,34 +30824,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352021 or + always@(guard__h352019 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01, 2'b10: - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h352021 == 2'b11 && + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h352019 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h352021) + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h352019) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard52019_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - (guard__h352021 == 2'b0) ? + (guard__h352019 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h352021 == 2'b01 || guard__h352021 == 2'b10 || - guard__h352021 == 2'b11) && + (guard__h352019 == 2'b01 || guard__h352019 == 2'b10 || + guard__h352019 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = @@ -30862,34 +30862,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h343312 or + always@(guard__h343310 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343312) + case (guard__h343310) 2'b0, 2'b01, 2'b10: - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h343312 != 2'b11 || + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h343310 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h343312) + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h343310) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + CASE_guard43310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - (guard__h343312 == 2'b0) ? + (guard__h343310 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h343312 != 2'b01 && guard__h343312 != 2'b10 && - guard__h343312 != 2'b11 || + guard__h343310 != 2'b01 && guard__h343310 != 2'b10 && + guard__h343310 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = @@ -30900,34 +30900,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352021 or + always@(guard__h352019 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352021) + case (guard__h352019) 2'b0, 2'b01, 2'b10: - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = - guard__h352021 != 2'b11 || + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + guard__h352019 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or - guard__h352021) + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or + guard__h352019) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; + CASE_guard52019_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - (guard__h352021 == 2'b0) ? + (guard__h352019 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h352021 != 2'b01 && guard__h352021 != 2'b10 && - guard__h352021 != 2'b11 || + guard__h352019 != 2'b01 && guard__h352019 != 2'b10 && + guard__h352019 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = @@ -30938,34 +30938,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360951 or + always@(guard__h360949 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01, 2'b10: - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = - guard__h360951 == 2'b11 && + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + guard__h360949 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or - guard__h360951) + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or + guard__h360949) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; + CASE_guard60949_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - (guard__h360951 == 2'b0) ? + (guard__h360949 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h360951 == 2'b01 || guard__h360951 == 2'b10 || - guard__h360951 == 2'b11) && + (guard__h360949 == 2'b01 || guard__h360949 == 2'b10 || + guard__h360949 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = @@ -30976,34 +30976,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369787 or + always@(guard__h369785 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01, 2'b10: - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h369787 == 2'b11 && + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h369785 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h369787) + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h369785) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard69785_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - (guard__h369787 == 2'b0) ? + (guard__h369785 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h369787 == 2'b01 || guard__h369787 == 2'b10 || - guard__h369787 == 2'b11) && + (guard__h369785 == 2'b01 || guard__h369785 == 2'b10 || + guard__h369785 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = @@ -31014,34 +31014,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360951 or + always@(guard__h360949 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360951) + case (guard__h360949) 2'b0, 2'b01, 2'b10: - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h360951 != 2'b11 || + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h360949 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h360951) + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h360949) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard60949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - (guard__h360951 == 2'b0) ? + (guard__h360949 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h360951 != 2'b01 && guard__h360951 != 2'b10 && - guard__h360951 != 2'b11 || + guard__h360949 != 2'b01 && guard__h360949 != 2'b10 && + guard__h360949 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = @@ -31052,34 +31052,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369787 or + always@(guard__h369785 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369787) + case (guard__h369785) 2'b0, 2'b01, 2'b10: - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = - guard__h369787 != 2'b11 || + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + guard__h369785 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or - guard__h369787) + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or + guard__h369785) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; + CASE_guard69785_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - (guard__h369787 == 2'b0) ? + (guard__h369785 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h369787 != 2'b01 && guard__h369787 != 2'b10 && - guard__h369787 != 2'b11 || + guard__h369785 != 2'b01 && guard__h369785 != 2'b10 && + guard__h369785 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = @@ -31103,446 +31103,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h397711 or - _theResult___fst_exp__h405759 or - out_exp__h406204 or _theResult___exp__h406201) + always@(guard__h397709 or + _theResult___fst_exp__h405757 or + out_exp__h406202 or _theResult___exp__h406199) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = - _theResult___fst_exp__h405759; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = + _theResult___fst_exp__h405757; 2'b10: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = - out_exp__h406204; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = + out_exp__h406202; 2'b11: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = - _theResult___exp__h406201; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 = + _theResult___exp__h406199; endcase end - always@(guard__h397711 or - _theResult___fst_exp__h405759 or _theResult___exp__h406201) + always@(guard__h397709 or + _theResult___fst_exp__h405757 or _theResult___exp__h406199) begin - case (guard__h397711) + case (guard__h397709) 2'b0: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = - _theResult___fst_exp__h405759; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 = + _theResult___fst_exp__h405757; 2'b01, 2'b10, 2'b11: - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = - _theResult___exp__h406201; + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 = + _theResult___exp__h406199; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 or - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 or + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59 or + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or - _theResult___fst_exp__h405759) + _theResult___fst_exp__h405757) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h406279 = - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59; + _theResult___fst_exp__h406277 = + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q59; 3'd1: - _theResult___fst_exp__h406279 = - CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60; + _theResult___fst_exp__h406277 = + CASE_guard97709_0b0_theResult___fst_exp05757_0_ETC__q60; 3'd2: - _theResult___fst_exp__h406279 = + _theResult___fst_exp__h406277 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920; 3'd3: - _theResult___fst_exp__h406279 = + _theResult___fst_exp__h406277 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922; - 3'd4: _theResult___fst_exp__h406279 = _theResult___fst_exp__h405759; - default: _theResult___fst_exp__h406279 = 8'd0; + 3'd4: _theResult___fst_exp__h406277 = _theResult___fst_exp__h405757; + default: _theResult___fst_exp__h406277 = 8'd0; endcase end - always@(guard__h389004 or - _theResult___fst_exp__h397103 or - out_exp__h397622 or _theResult___exp__h397619) + always@(guard__h389002 or + _theResult___fst_exp__h397101 or + out_exp__h397620 or _theResult___exp__h397617) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = - _theResult___fst_exp__h397103; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = + _theResult___fst_exp__h397101; 2'b10: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = - out_exp__h397622; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = + out_exp__h397620; 2'b11: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = - _theResult___exp__h397619; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 = + _theResult___exp__h397617; endcase end - always@(guard__h389004 or - _theResult___fst_exp__h397103 or _theResult___exp__h397619) + always@(guard__h389002 or + _theResult___fst_exp__h397101 or _theResult___exp__h397617) begin - case (guard__h389004) + case (guard__h389002) 2'b0: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = - _theResult___fst_exp__h397103; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 = + _theResult___fst_exp__h397101; 2'b01, 2'b10, 2'b11: - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = - _theResult___exp__h397619; + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 = + _theResult___exp__h397617; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 or - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 or + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61 or + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or - _theResult___fst_exp__h397103) + _theResult___fst_exp__h397101) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h397697 = - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61; + _theResult___fst_exp__h397695 = + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q61; 3'd1: - _theResult___fst_exp__h397697 = - CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62; + _theResult___fst_exp__h397695 = + CASE_guard89002_0b0_theResult___fst_exp97101_0_ETC__q62; 3'd2: - _theResult___fst_exp__h397697 = + _theResult___fst_exp__h397695 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698; 3'd3: - _theResult___fst_exp__h397697 = + _theResult___fst_exp__h397695 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701; - 3'd4: _theResult___fst_exp__h397697 = _theResult___fst_exp__h397103; - default: _theResult___fst_exp__h397697 = 8'd0; + 3'd4: _theResult___fst_exp__h397695 = _theResult___fst_exp__h397101; + default: _theResult___fst_exp__h397695 = 8'd0; endcase end - always@(guard__h406641 or - _theResult___fst_exp__h414869 or - out_exp__h415388 or _theResult___exp__h415385) + always@(guard__h406639 or + _theResult___fst_exp__h414867 or + out_exp__h415386 or _theResult___exp__h415383) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = - _theResult___fst_exp__h414869; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = + _theResult___fst_exp__h414867; 2'b10: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = - out_exp__h415388; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = + out_exp__h415386; 2'b11: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = - _theResult___exp__h415385; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 = + _theResult___exp__h415383; endcase end - always@(guard__h406641 or - _theResult___fst_exp__h414869 or _theResult___exp__h415385) + always@(guard__h406639 or + _theResult___fst_exp__h414867 or _theResult___exp__h415383) begin - case (guard__h406641) + case (guard__h406639) 2'b0: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = - _theResult___fst_exp__h414869; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 = + _theResult___fst_exp__h414867; 2'b01, 2'b10, 2'b11: - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = - _theResult___exp__h415385; + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 = + _theResult___exp__h415383; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 or - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 or + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67 or + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or - _theResult___fst_exp__h414869) + _theResult___fst_exp__h414867) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h415463 = - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67; + _theResult___fst_exp__h415461 = + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q67; 3'd1: - _theResult___fst_exp__h415463 = - CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68; + _theResult___fst_exp__h415461 = + CASE_guard06639_0b0_theResult___fst_exp14867_0_ETC__q68; 3'd2: - _theResult___fst_exp__h415463 = + _theResult___fst_exp__h415461 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245; 3'd3: - _theResult___fst_exp__h415463 = + _theResult___fst_exp__h415461 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247; - 3'd4: _theResult___fst_exp__h415463 = _theResult___fst_exp__h414869; - default: _theResult___fst_exp__h415463 = 8'd0; + 3'd4: _theResult___fst_exp__h415461 = _theResult___fst_exp__h414867; + default: _theResult___fst_exp__h415461 = 8'd0; endcase end - always@(guard__h415477 or - _theResult___fst_exp__h423554 or - out_exp__h424024 or _theResult___exp__h424021) + always@(guard__h415475 or + _theResult___fst_exp__h423552 or + out_exp__h424022 or _theResult___exp__h424019) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = - _theResult___fst_exp__h423554; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = + _theResult___fst_exp__h423552; 2'b10: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = - out_exp__h424024; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = + out_exp__h424022; 2'b11: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = - _theResult___exp__h424021; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 = + _theResult___exp__h424019; endcase end - always@(guard__h415477 or - _theResult___fst_exp__h423554 or _theResult___exp__h424021) + always@(guard__h415475 or + _theResult___fst_exp__h423552 or _theResult___exp__h424019) begin - case (guard__h415477) + case (guard__h415475) 2'b0: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = - _theResult___fst_exp__h423554; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 = + _theResult___fst_exp__h423552; 2'b01, 2'b10, 2'b11: - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = - _theResult___exp__h424021; + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 = + _theResult___exp__h424019; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 or - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 or + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72 or + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or - _theResult___fst_exp__h423554) + _theResult___fst_exp__h423552) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h424099 = - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72; + _theResult___fst_exp__h424097 = + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q72; 3'd1: - _theResult___fst_exp__h424099 = - CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73; + _theResult___fst_exp__h424097 = + CASE_guard15475_0b0_theResult___fst_exp23552_0_ETC__q73; 3'd2: - _theResult___fst_exp__h424099 = + _theResult___fst_exp__h424097 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314; 3'd3: - _theResult___fst_exp__h424099 = + _theResult___fst_exp__h424097 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316; - 3'd4: _theResult___fst_exp__h424099 = _theResult___fst_exp__h423554; - default: _theResult___fst_exp__h424099 = 8'd0; + 3'd4: _theResult___fst_exp__h424097 = _theResult___fst_exp__h423552; + default: _theResult___fst_exp__h424097 = 8'd0; endcase end - always@(guard__h397711 or - _theResult___snd__h405710 or - out_sfd__h406205 or _theResult___sfd__h406202) + always@(guard__h397709 or + _theResult___snd__h405708 or + out_sfd__h406203 or _theResult___sfd__h406200) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = - _theResult___snd__h405710[56:34]; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = + _theResult___snd__h405708[56:34]; 2'b10: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = - out_sfd__h406205; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = + out_sfd__h406203; 2'b11: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = - _theResult___sfd__h406202; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 = + _theResult___sfd__h406200; endcase end - always@(guard__h397711 or - _theResult___snd__h405710 or _theResult___sfd__h406202) + always@(guard__h397709 or + _theResult___snd__h405708 or _theResult___sfd__h406200) begin - case (guard__h397711) + case (guard__h397709) 2'b0: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = - _theResult___snd__h405710[56:34]; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 = + _theResult___snd__h405708[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = - _theResult___sfd__h406202; + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 = + _theResult___sfd__h406200; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 or - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 or + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74 or + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or - _theResult___snd__h405710) + _theResult___snd__h405708) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h406280 = - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74; + _theResult___fst_sfd__h406278 = + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q74; 3'd1: - _theResult___fst_sfd__h406280 = - CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75; + _theResult___fst_sfd__h406278 = + CASE_guard97709_0b0_theResult___snd05708_BITS__ETC__q75; 3'd2: - _theResult___fst_sfd__h406280 = + _theResult___fst_sfd__h406278 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364; 3'd3: - _theResult___fst_sfd__h406280 = + _theResult___fst_sfd__h406278 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366; - 3'd4: _theResult___fst_sfd__h406280 = _theResult___snd__h405710[56:34]; - default: _theResult___fst_sfd__h406280 = 23'd0; + 3'd4: _theResult___fst_sfd__h406278 = _theResult___snd__h405708[56:34]; + default: _theResult___fst_sfd__h406278 = 23'd0; endcase end - always@(guard__h389004 or - sfdin__h397097 or out_sfd__h397623 or _theResult___sfd__h397620) + always@(guard__h389002 or + sfdin__h397095 or out_sfd__h397621 or _theResult___sfd__h397618) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = - sfdin__h397097[56:34]; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = + sfdin__h397095[56:34]; 2'b10: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = - out_sfd__h397623; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = + out_sfd__h397621; 2'b11: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h397620; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 = + _theResult___sfd__h397618; endcase end - always@(guard__h389004 or sfdin__h397097 or _theResult___sfd__h397620) + always@(guard__h389002 or sfdin__h397095 or _theResult___sfd__h397618) begin - case (guard__h389004) + case (guard__h389002) 2'b0: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = - sfdin__h397097[56:34]; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 = + sfdin__h397095[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h397620; + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h397618; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 or - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 or + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76 or + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or - sfdin__h397097) + sfdin__h397095) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h397698 = - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76; + _theResult___fst_sfd__h397696 = + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q76; 3'd1: - _theResult___fst_sfd__h397698 = - CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h397696 = + CASE_guard89002_0b0_sfdin97095_BITS_56_TO_34_0_ETC__q77; 3'd2: - _theResult___fst_sfd__h397698 = + _theResult___fst_sfd__h397696 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; 3'd3: - _theResult___fst_sfd__h397698 = + _theResult___fst_sfd__h397696 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; - 3'd4: _theResult___fst_sfd__h397698 = sfdin__h397097[56:34]; - default: _theResult___fst_sfd__h397698 = 23'd0; + 3'd4: _theResult___fst_sfd__h397696 = sfdin__h397095[56:34]; + default: _theResult___fst_sfd__h397696 = 23'd0; endcase end - always@(guard__h406641 or - sfdin__h414863 or out_sfd__h415389 or _theResult___sfd__h415386) + always@(guard__h406639 or + sfdin__h414861 or out_sfd__h415387 or _theResult___sfd__h415384) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = - sfdin__h414863[56:34]; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = + sfdin__h414861[56:34]; 2'b10: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = - out_sfd__h415389; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = + out_sfd__h415387; 2'b11: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h415386; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h415384; endcase end - always@(guard__h406641 or sfdin__h414863 or _theResult___sfd__h415386) + always@(guard__h406639 or sfdin__h414861 or _theResult___sfd__h415384) begin - case (guard__h406641) + case (guard__h406639) 2'b0: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = - sfdin__h414863[56:34]; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 = + sfdin__h414861[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h415386; + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h415384; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 or - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 or + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78 or + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or - sfdin__h414863) + sfdin__h414861) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h415464 = - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h415462 = + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q78; 3'd1: - _theResult___fst_sfd__h415464 = - CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h415462 = + CASE_guard06639_0b0_sfdin14861_BITS_56_TO_34_0_ETC__q79; 3'd2: - _theResult___fst_sfd__h415464 = + _theResult___fst_sfd__h415462 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391; 3'd3: - _theResult___fst_sfd__h415464 = + _theResult___fst_sfd__h415462 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393; - 3'd4: _theResult___fst_sfd__h415464 = sfdin__h414863[56:34]; - default: _theResult___fst_sfd__h415464 = 23'd0; + 3'd4: _theResult___fst_sfd__h415462 = sfdin__h414861[56:34]; + default: _theResult___fst_sfd__h415462 = 23'd0; endcase end - always@(guard__h415477 or - _theResult___snd__h423500 or - out_sfd__h424025 or _theResult___sfd__h424022) + always@(guard__h415475 or + _theResult___snd__h423498 or + out_sfd__h424023 or _theResult___sfd__h424020) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = - _theResult___snd__h423500[56:34]; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = + _theResult___snd__h423498[56:34]; 2'b10: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = - out_sfd__h424025; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = + out_sfd__h424023; 2'b11: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = - _theResult___sfd__h424022; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 = + _theResult___sfd__h424020; endcase end - always@(guard__h415477 or - _theResult___snd__h423500 or _theResult___sfd__h424022) + always@(guard__h415475 or + _theResult___snd__h423498 or _theResult___sfd__h424020) begin - case (guard__h415477) + case (guard__h415475) 2'b0: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = - _theResult___snd__h423500[56:34]; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 = + _theResult___snd__h423498[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = - _theResult___sfd__h424022; + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 = + _theResult___sfd__h424020; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 or - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 or + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80 or + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or - _theResult___snd__h423500) + _theResult___snd__h423498) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h424100 = - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80; + _theResult___fst_sfd__h424098 = + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q80; 3'd1: - _theResult___fst_sfd__h424100 = - CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81; + _theResult___fst_sfd__h424098 = + CASE_guard15475_0b0_theResult___snd23498_BITS__ETC__q81; 3'd2: - _theResult___fst_sfd__h424100 = + _theResult___fst_sfd__h424098 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410; 3'd3: - _theResult___fst_sfd__h424100 = + _theResult___fst_sfd__h424098 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412; - 3'd4: _theResult___fst_sfd__h424100 = _theResult___snd__h423500[56:34]; - default: _theResult___fst_sfd__h424100 = 23'd0; + 3'd4: _theResult___fst_sfd__h424098 = _theResult___snd__h423498[56:34]; + default: _theResult___fst_sfd__h424098 = 23'd0; endcase end - always@(guard__h389004 or + always@(guard__h389002 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01, 2'b10: - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = - guard__h389004 == 2'b11 && + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + guard__h389002 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or - guard__h389004) + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or + guard__h389002) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; + CASE_guard89002_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - (guard__h389004 == 2'b0) ? + (guard__h389002 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h389004 == 2'b01 || guard__h389004 == 2'b10 || - guard__h389004 == 2'b11) && + (guard__h389002 == 2'b01 || guard__h389002 == 2'b10 || + guard__h389002 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = @@ -31553,34 +31553,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h389004 or + always@(guard__h389002 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389004) + case (guard__h389002) 2'b0, 2'b01, 2'b10: - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = - guard__h389004 != 2'b11 || + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + guard__h389002 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or - guard__h389004) + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or + guard__h389002) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; + CASE_guard89002_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - (guard__h389004 == 2'b0) ? + (guard__h389002 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h389004 != 2'b01 && guard__h389004 != 2'b10 && - guard__h389004 != 2'b11 || + guard__h389002 != 2'b01 && guard__h389002 != 2'b10 && + guard__h389002 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = @@ -31591,34 +31591,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397711 or + always@(guard__h397709 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01, 2'b10: - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = - guard__h397711 == 2'b11 && + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + guard__h397709 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or - guard__h397711) + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or + guard__h397709) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; + CASE_guard97709_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - (guard__h397711 == 2'b0) ? + (guard__h397709 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h397711 == 2'b01 || guard__h397711 == 2'b10 || - guard__h397711 == 2'b11) && + (guard__h397709 == 2'b01 || guard__h397709 == 2'b10 || + guard__h397709 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = @@ -31629,34 +31629,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397711 or + always@(guard__h397709 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397711) + case (guard__h397709) 2'b0, 2'b01, 2'b10: - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = - guard__h397711 != 2'b11 || + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + guard__h397709 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or - guard__h397711) + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or + guard__h397709) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; + CASE_guard97709_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - (guard__h397711 == 2'b0) ? + (guard__h397709 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h397711 != 2'b01 && guard__h397711 != 2'b10 && - guard__h397711 != 2'b11 || + guard__h397709 != 2'b01 && guard__h397709 != 2'b10 && + guard__h397709 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = @@ -31667,34 +31667,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406641 or + always@(guard__h406639 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01, 2'b10: - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = - guard__h406641 == 2'b11 && + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + guard__h406639 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or - guard__h406641) + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or + guard__h406639) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; + CASE_guard06639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - (guard__h406641 == 2'b0) ? + (guard__h406639 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h406641 == 2'b01 || guard__h406641 == 2'b10 || - guard__h406641 == 2'b11) && + (guard__h406639 == 2'b01 || guard__h406639 == 2'b10 || + guard__h406639 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = @@ -31705,34 +31705,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406641 or + always@(guard__h406639 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406641) + case (guard__h406639) 2'b0, 2'b01, 2'b10: - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = - guard__h406641 != 2'b11 || + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + guard__h406639 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or - guard__h406641) + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or + guard__h406639) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; + CASE_guard06639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - (guard__h406641 == 2'b0) ? + (guard__h406639 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h406641 != 2'b01 && guard__h406641 != 2'b10 && - guard__h406641 != 2'b11 || + guard__h406639 != 2'b01 && guard__h406639 != 2'b10 && + guard__h406639 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = @@ -31743,34 +31743,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415477 or + always@(guard__h415475 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01, 2'b10: - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = - guard__h415477 == 2'b11 && + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + guard__h415475 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or - guard__h415477) + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or + guard__h415475) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; + CASE_guard15475_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - (guard__h415477 == 2'b0) ? + (guard__h415475 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h415477 == 2'b01 || guard__h415477 == 2'b10 || - guard__h415477 == 2'b11) && + (guard__h415475 == 2'b01 || guard__h415475 == 2'b10 || + guard__h415475 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = @@ -31781,34 +31781,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415477 or + always@(guard__h415475 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415477) + case (guard__h415475) 2'b0, 2'b01, 2'b10: - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = - guard__h415477 != 2'b11 || + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + guard__h415475 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or - guard__h415477) + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or + guard__h415475) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; + CASE_guard15475_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - (guard__h415477 == 2'b0) ? + (guard__h415475 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h415477 != 2'b01 && guard__h415477 != 2'b10 && - guard__h415477 != 2'b11 || + guard__h415475 != 2'b01 && guard__h415475 != 2'b10 && + guard__h415475 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = @@ -31845,446 +31845,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h443399 or - _theResult___fst_exp__h451447 or - out_exp__h451892 or _theResult___exp__h451889) + always@(guard__h443397 or + _theResult___fst_exp__h451445 or + out_exp__h451890 or _theResult___exp__h451887) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = - _theResult___fst_exp__h451447; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = + _theResult___fst_exp__h451445; 2'b10: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = - out_exp__h451892; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = + out_exp__h451890; 2'b11: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = - _theResult___exp__h451889; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 = + _theResult___exp__h451887; endcase end - always@(guard__h443399 or - _theResult___fst_exp__h451447 or _theResult___exp__h451889) + always@(guard__h443397 or + _theResult___fst_exp__h451445 or _theResult___exp__h451887) begin - case (guard__h443399) + case (guard__h443397) 2'b0: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = - _theResult___fst_exp__h451447; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 = + _theResult___fst_exp__h451445; 2'b01, 2'b10, 2'b11: - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = - _theResult___exp__h451889; + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 = + _theResult___exp__h451887; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 or - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 or + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94 or + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or - _theResult___fst_exp__h451447) + _theResult___fst_exp__h451445) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h451967 = - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94; + _theResult___fst_exp__h451965 = + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q94; 3'd1: - _theResult___fst_exp__h451967 = - CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95; + _theResult___fst_exp__h451965 = + CASE_guard43397_0b0_theResult___fst_exp51445_0_ETC__q95; 3'd2: - _theResult___fst_exp__h451967 = + _theResult___fst_exp__h451965 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312; 3'd3: - _theResult___fst_exp__h451967 = + _theResult___fst_exp__h451965 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314; - 3'd4: _theResult___fst_exp__h451967 = _theResult___fst_exp__h451447; - default: _theResult___fst_exp__h451967 = 8'd0; + 3'd4: _theResult___fst_exp__h451965 = _theResult___fst_exp__h451445; + default: _theResult___fst_exp__h451965 = 8'd0; endcase end - always@(guard__h434692 or - _theResult___fst_exp__h442791 or - out_exp__h443310 or _theResult___exp__h443307) + always@(guard__h434690 or + _theResult___fst_exp__h442789 or + out_exp__h443308 or _theResult___exp__h443305) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = - _theResult___fst_exp__h442791; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = + _theResult___fst_exp__h442789; 2'b10: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = - out_exp__h443310; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = + out_exp__h443308; 2'b11: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = - _theResult___exp__h443307; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 = + _theResult___exp__h443305; endcase end - always@(guard__h434692 or - _theResult___fst_exp__h442791 or _theResult___exp__h443307) + always@(guard__h434690 or + _theResult___fst_exp__h442789 or _theResult___exp__h443305) begin - case (guard__h434692) + case (guard__h434690) 2'b0: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = - _theResult___fst_exp__h442791; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 = + _theResult___fst_exp__h442789; 2'b01, 2'b10, 2'b11: - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = - _theResult___exp__h443307; + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 = + _theResult___exp__h443305; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 or - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 or + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96 or + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or - _theResult___fst_exp__h442791) + _theResult___fst_exp__h442789) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h443385 = - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96; + _theResult___fst_exp__h443383 = + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q96; 3'd1: - _theResult___fst_exp__h443385 = - CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97; + _theResult___fst_exp__h443383 = + CASE_guard34690_0b0_theResult___fst_exp42789_0_ETC__q97; 3'd2: - _theResult___fst_exp__h443385 = + _theResult___fst_exp__h443383 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090; 3'd3: - _theResult___fst_exp__h443385 = + _theResult___fst_exp__h443383 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093; - 3'd4: _theResult___fst_exp__h443385 = _theResult___fst_exp__h442791; - default: _theResult___fst_exp__h443385 = 8'd0; + 3'd4: _theResult___fst_exp__h443383 = _theResult___fst_exp__h442789; + default: _theResult___fst_exp__h443383 = 8'd0; endcase end - always@(guard__h452329 or - _theResult___fst_exp__h460557 or - out_exp__h461076 or _theResult___exp__h461073) + always@(guard__h452327 or + _theResult___fst_exp__h460555 or + out_exp__h461074 or _theResult___exp__h461071) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = - _theResult___fst_exp__h460557; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = + _theResult___fst_exp__h460555; 2'b10: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = - out_exp__h461076; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = + out_exp__h461074; 2'b11: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = - _theResult___exp__h461073; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 = + _theResult___exp__h461071; endcase end - always@(guard__h452329 or - _theResult___fst_exp__h460557 or _theResult___exp__h461073) + always@(guard__h452327 or + _theResult___fst_exp__h460555 or _theResult___exp__h461071) begin - case (guard__h452329) + case (guard__h452327) 2'b0: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = - _theResult___fst_exp__h460557; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 = + _theResult___fst_exp__h460555; 2'b01, 2'b10, 2'b11: - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = - _theResult___exp__h461073; + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 = + _theResult___exp__h461071; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 or - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 or + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102 or + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or - _theResult___fst_exp__h460557) + _theResult___fst_exp__h460555) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h461151 = - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102; + _theResult___fst_exp__h461149 = + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q102; 3'd1: - _theResult___fst_exp__h461151 = - CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103; + _theResult___fst_exp__h461149 = + CASE_guard52327_0b0_theResult___fst_exp60555_0_ETC__q103; 3'd2: - _theResult___fst_exp__h461151 = + _theResult___fst_exp__h461149 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637; 3'd3: - _theResult___fst_exp__h461151 = + _theResult___fst_exp__h461149 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639; - 3'd4: _theResult___fst_exp__h461151 = _theResult___fst_exp__h460557; - default: _theResult___fst_exp__h461151 = 8'd0; + 3'd4: _theResult___fst_exp__h461149 = _theResult___fst_exp__h460555; + default: _theResult___fst_exp__h461149 = 8'd0; endcase end - always@(guard__h461165 or - _theResult___fst_exp__h469242 or - out_exp__h469712 or _theResult___exp__h469709) + always@(guard__h461163 or + _theResult___fst_exp__h469240 or + out_exp__h469710 or _theResult___exp__h469707) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = - _theResult___fst_exp__h469242; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = + _theResult___fst_exp__h469240; 2'b10: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = - out_exp__h469712; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = + out_exp__h469710; 2'b11: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = - _theResult___exp__h469709; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 = + _theResult___exp__h469707; endcase end - always@(guard__h461165 or - _theResult___fst_exp__h469242 or _theResult___exp__h469709) + always@(guard__h461163 or + _theResult___fst_exp__h469240 or _theResult___exp__h469707) begin - case (guard__h461165) + case (guard__h461163) 2'b0: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = - _theResult___fst_exp__h469242; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 = + _theResult___fst_exp__h469240; 2'b01, 2'b10, 2'b11: - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = - _theResult___exp__h469709; + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 = + _theResult___exp__h469707; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 or - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 or + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107 or + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or - _theResult___fst_exp__h469242) + _theResult___fst_exp__h469240) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h469787 = - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107; + _theResult___fst_exp__h469785 = + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q107; 3'd1: - _theResult___fst_exp__h469787 = - CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108; + _theResult___fst_exp__h469785 = + CASE_guard61163_0b0_theResult___fst_exp69240_0_ETC__q108; 3'd2: - _theResult___fst_exp__h469787 = + _theResult___fst_exp__h469785 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706; 3'd3: - _theResult___fst_exp__h469787 = + _theResult___fst_exp__h469785 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708; - 3'd4: _theResult___fst_exp__h469787 = _theResult___fst_exp__h469242; - default: _theResult___fst_exp__h469787 = 8'd0; + 3'd4: _theResult___fst_exp__h469785 = _theResult___fst_exp__h469240; + default: _theResult___fst_exp__h469785 = 8'd0; endcase end - always@(guard__h443399 or - _theResult___snd__h451398 or - out_sfd__h451893 or _theResult___sfd__h451890) + always@(guard__h443397 or + _theResult___snd__h451396 or + out_sfd__h451891 or _theResult___sfd__h451888) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = - _theResult___snd__h451398[56:34]; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = + _theResult___snd__h451396[56:34]; 2'b10: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = - out_sfd__h451893; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = + out_sfd__h451891; 2'b11: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = - _theResult___sfd__h451890; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 = + _theResult___sfd__h451888; endcase end - always@(guard__h443399 or - _theResult___snd__h451398 or _theResult___sfd__h451890) + always@(guard__h443397 or + _theResult___snd__h451396 or _theResult___sfd__h451888) begin - case (guard__h443399) + case (guard__h443397) 2'b0: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = - _theResult___snd__h451398[56:34]; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 = + _theResult___snd__h451396[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = - _theResult___sfd__h451890; + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 = + _theResult___sfd__h451888; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 or - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 or + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109 or + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or - _theResult___snd__h451398) + _theResult___snd__h451396) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h451968 = - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109; + _theResult___fst_sfd__h451966 = + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q109; 3'd1: - _theResult___fst_sfd__h451968 = - CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110; + _theResult___fst_sfd__h451966 = + CASE_guard43397_0b0_theResult___snd51396_BITS__ETC__q110; 3'd2: - _theResult___fst_sfd__h451968 = + _theResult___fst_sfd__h451966 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756; 3'd3: - _theResult___fst_sfd__h451968 = + _theResult___fst_sfd__h451966 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758; - 3'd4: _theResult___fst_sfd__h451968 = _theResult___snd__h451398[56:34]; - default: _theResult___fst_sfd__h451968 = 23'd0; + 3'd4: _theResult___fst_sfd__h451966 = _theResult___snd__h451396[56:34]; + default: _theResult___fst_sfd__h451966 = 23'd0; endcase end - always@(guard__h434692 or - sfdin__h442785 or out_sfd__h443311 or _theResult___sfd__h443308) + always@(guard__h434690 or + sfdin__h442783 or out_sfd__h443309 or _theResult___sfd__h443306) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = - sfdin__h442785[56:34]; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = + sfdin__h442783[56:34]; 2'b10: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = - out_sfd__h443311; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = + out_sfd__h443309; 2'b11: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = - _theResult___sfd__h443308; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 = + _theResult___sfd__h443306; endcase end - always@(guard__h434692 or sfdin__h442785 or _theResult___sfd__h443308) + always@(guard__h434690 or sfdin__h442783 or _theResult___sfd__h443306) begin - case (guard__h434692) + case (guard__h434690) 2'b0: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = - sfdin__h442785[56:34]; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 = + sfdin__h442783[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h443308; + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h443306; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 or - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 or + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111 or + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or - sfdin__h442785) + sfdin__h442783) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h443386 = - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111; + _theResult___fst_sfd__h443384 = + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q111; 3'd1: - _theResult___fst_sfd__h443386 = - CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h443384 = + CASE_guard34690_0b0_sfdin42783_BITS_56_TO_34_0_ETC__q112; 3'd2: - _theResult___fst_sfd__h443386 = + _theResult___fst_sfd__h443384 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737; 3'd3: - _theResult___fst_sfd__h443386 = + _theResult___fst_sfd__h443384 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739; - 3'd4: _theResult___fst_sfd__h443386 = sfdin__h442785[56:34]; - default: _theResult___fst_sfd__h443386 = 23'd0; + 3'd4: _theResult___fst_sfd__h443384 = sfdin__h442783[56:34]; + default: _theResult___fst_sfd__h443384 = 23'd0; endcase end - always@(guard__h452329 or - sfdin__h460551 or out_sfd__h461077 or _theResult___sfd__h461074) + always@(guard__h452327 or + sfdin__h460549 or out_sfd__h461075 or _theResult___sfd__h461072) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = - sfdin__h460551[56:34]; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = + sfdin__h460549[56:34]; 2'b10: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = - out_sfd__h461077; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = + out_sfd__h461075; 2'b11: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h461074; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h461072; endcase end - always@(guard__h452329 or sfdin__h460551 or _theResult___sfd__h461074) + always@(guard__h452327 or sfdin__h460549 or _theResult___sfd__h461072) begin - case (guard__h452329) + case (guard__h452327) 2'b0: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = - sfdin__h460551[56:34]; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 = + sfdin__h460549[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h461074; + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h461072; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 or - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 or + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113 or + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or - sfdin__h460551) + sfdin__h460549) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h461152 = - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h461150 = + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q113; 3'd1: - _theResult___fst_sfd__h461152 = - CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h461150 = + CASE_guard52327_0b0_sfdin60549_BITS_56_TO_34_0_ETC__q114; 3'd2: - _theResult___fst_sfd__h461152 = + _theResult___fst_sfd__h461150 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783; 3'd3: - _theResult___fst_sfd__h461152 = + _theResult___fst_sfd__h461150 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785; - 3'd4: _theResult___fst_sfd__h461152 = sfdin__h460551[56:34]; - default: _theResult___fst_sfd__h461152 = 23'd0; + 3'd4: _theResult___fst_sfd__h461150 = sfdin__h460549[56:34]; + default: _theResult___fst_sfd__h461150 = 23'd0; endcase end - always@(guard__h461165 or - _theResult___snd__h469188 or - out_sfd__h469713 or _theResult___sfd__h469710) + always@(guard__h461163 or + _theResult___snd__h469186 or + out_sfd__h469711 or _theResult___sfd__h469708) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = - _theResult___snd__h469188[56:34]; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = + _theResult___snd__h469186[56:34]; 2'b10: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = - out_sfd__h469713; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = + out_sfd__h469711; 2'b11: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = - _theResult___sfd__h469710; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 = + _theResult___sfd__h469708; endcase end - always@(guard__h461165 or - _theResult___snd__h469188 or _theResult___sfd__h469710) + always@(guard__h461163 or + _theResult___snd__h469186 or _theResult___sfd__h469708) begin - case (guard__h461165) + case (guard__h461163) 2'b0: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = - _theResult___snd__h469188[56:34]; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 = + _theResult___snd__h469186[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = - _theResult___sfd__h469710; + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 = + _theResult___sfd__h469708; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 or - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 or + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115 or + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or - _theResult___snd__h469188) + _theResult___snd__h469186) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h469788 = - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115; + _theResult___fst_sfd__h469786 = + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q115; 3'd1: - _theResult___fst_sfd__h469788 = - CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116; + _theResult___fst_sfd__h469786 = + CASE_guard61163_0b0_theResult___snd69186_BITS__ETC__q116; 3'd2: - _theResult___fst_sfd__h469788 = + _theResult___fst_sfd__h469786 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802; 3'd3: - _theResult___fst_sfd__h469788 = + _theResult___fst_sfd__h469786 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804; - 3'd4: _theResult___fst_sfd__h469788 = _theResult___snd__h469188[56:34]; - default: _theResult___fst_sfd__h469788 = 23'd0; + 3'd4: _theResult___fst_sfd__h469786 = _theResult___snd__h469186[56:34]; + default: _theResult___fst_sfd__h469786 = 23'd0; endcase end - always@(guard__h434692 or + always@(guard__h434690 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01, 2'b10: - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = - guard__h434692 == 2'b11 && + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + guard__h434690 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or - guard__h434692) + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or + guard__h434690) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; + CASE_guard34690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - (guard__h434692 == 2'b0) ? + (guard__h434690 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h434692 == 2'b01 || guard__h434692 == 2'b10 || - guard__h434692 == 2'b11) && + (guard__h434690 == 2'b01 || guard__h434690 == 2'b10 || + guard__h434690 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = @@ -32295,34 +32295,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h434692 or + always@(guard__h434690 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434692) + case (guard__h434690) 2'b0, 2'b01, 2'b10: - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = - guard__h434692 != 2'b11 || + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + guard__h434690 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or - guard__h434692) + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or + guard__h434690) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; + CASE_guard34690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - (guard__h434692 == 2'b0) ? + (guard__h434690 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h434692 != 2'b01 && guard__h434692 != 2'b10 && - guard__h434692 != 2'b11 || + guard__h434690 != 2'b01 && guard__h434690 != 2'b10 && + guard__h434690 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = @@ -32333,34 +32333,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443399 or + always@(guard__h443397 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01, 2'b10: - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = - guard__h443399 == 2'b11 && + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h443397 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or - guard__h443399) + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h443397) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + CASE_guard43397_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - (guard__h443399 == 2'b0) ? + (guard__h443397 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h443399 == 2'b01 || guard__h443399 == 2'b10 || - guard__h443399 == 2'b11) && + (guard__h443397 == 2'b01 || guard__h443397 == 2'b10 || + guard__h443397 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = @@ -32371,34 +32371,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443399 or + always@(guard__h443397 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443399) + case (guard__h443397) 2'b0, 2'b01, 2'b10: - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h443399 != 2'b11 || + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h443397 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h443399) + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h443397) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + CASE_guard43397_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - (guard__h443399 == 2'b0) ? + (guard__h443397 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h443399 != 2'b01 && guard__h443399 != 2'b10 && - guard__h443399 != 2'b11 || + guard__h443397 != 2'b01 && guard__h443397 != 2'b10 && + guard__h443397 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = @@ -32409,34 +32409,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452329 or + always@(guard__h452327 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01, 2'b10: - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = - guard__h452329 == 2'b11 && + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + guard__h452327 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or - guard__h452329) + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or + guard__h452327) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; + CASE_guard52327_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - (guard__h452329 == 2'b0) ? + (guard__h452327 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h452329 == 2'b01 || guard__h452329 == 2'b10 || - guard__h452329 == 2'b11) && + (guard__h452327 == 2'b01 || guard__h452327 == 2'b10 || + guard__h452327 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = @@ -32447,34 +32447,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452329 or + always@(guard__h452327 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452329) + case (guard__h452327) 2'b0, 2'b01, 2'b10: - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = - guard__h452329 != 2'b11 || + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + guard__h452327 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or - guard__h452329) + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or + guard__h452327) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; + CASE_guard52327_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - (guard__h452329 == 2'b0) ? + (guard__h452327 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h452329 != 2'b01 && guard__h452329 != 2'b10 && - guard__h452329 != 2'b11 || + guard__h452327 != 2'b01 && guard__h452327 != 2'b10 && + guard__h452327 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = @@ -32485,34 +32485,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461165 or + always@(guard__h461163 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01, 2'b10: - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h461165 == 2'b11 && + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + guard__h461163 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h461165) + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or + guard__h461163) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; + CASE_guard61163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - (guard__h461165 == 2'b0) ? + (guard__h461163 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h461165 == 2'b01 || guard__h461165 == 2'b10 || - guard__h461165 == 2'b11) && + (guard__h461163 == 2'b01 || guard__h461163 == 2'b10 || + guard__h461163 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = @@ -32523,34 +32523,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461165 or + always@(guard__h461163 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461165) + case (guard__h461163) 2'b0, 2'b01, 2'b10: - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = - guard__h461165 != 2'b11 || + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + guard__h461163 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or - guard__h461165) + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or + guard__h461163) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; + CASE_guard61163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - (guard__h461165 == 2'b0) ? + (guard__h461163 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h461165 != 2'b01 && guard__h461165 != 2'b10 && - guard__h461165 != 2'b11 || + guard__h461163 != 2'b01 && guard__h461163 != 2'b10 && + guard__h461163 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = @@ -32607,28 +32607,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h490715 or - _theResult___fst_exp__h498676 or _theResult___exp__h499331) + always@(guard__h490713 or + _theResult___fst_exp__h498674 or _theResult___exp__h499329) begin - case (guard__h490715) + case (guard__h490713) 2'b0: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = - _theResult___fst_exp__h498676; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135 = + _theResult___fst_exp__h498674; 2'b01, 2'b10, 2'b11: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = - _theResult___exp__h499331; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135 = + _theResult___exp__h499329; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h498676 or + _theResult___fst_exp__h498674 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 or - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135) + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - _theResult___fst_exp__h498676; + _theResult___fst_exp__h498674; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007; @@ -32637,40 +32637,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = 11'd0; endcase end - always@(guard__h490715 or - _theResult___fst_exp__h498676 or - out_exp__h499334 or _theResult___exp__h499331) + always@(guard__h490713 or + _theResult___fst_exp__h498674 or + out_exp__h499332 or _theResult___exp__h499329) begin - case (guard__h490715) + case (guard__h490713) 2'b0, 2'b01: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = - _theResult___fst_exp__h498676; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = + _theResult___fst_exp__h498674; 2'b10: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = - out_exp__h499334; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = + out_exp__h499332; 2'b11: - CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = - _theResult___exp__h499331; + CASE_guard90713_0b0_theResult___fst_exp98674_0_ETC__q136 = + _theResult___exp__h499329; endcase end - always@(guard__h490715 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h490713 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h490715) + case (guard__h490713) 2'b0, 2'b01, 2'b10: - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h490715 == 2'b11 && + CASE_guard90713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h490713 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490715) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490713) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32678,29 +32678,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h490715 == 2'b0) ? + (guard__h490713 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h490715 == 2'b01 || guard__h490715 == 2'b10 || - guard__h490715 == 2'b11) && + (guard__h490713 == 2'b01 || guard__h490713 == 2'b10 || + guard__h490713 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h500027 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h500025 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h500027) + case (guard__h500025) 2'b0, 2'b01, 2'b10: - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h500027 == 2'b11 && + CASE_guard00025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h500025 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500027) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500025) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32708,29 +32708,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h500027 == 2'b0) ? + (guard__h500025 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h500027 == 2'b01 || guard__h500027 == 2'b10 || - guard__h500027 == 2'b11) && + (guard__h500025 == 2'b01 || guard__h500025 == 2'b10 || + guard__h500025 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h509096 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h509094 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h509096) + case (guard__h509094) 2'b0, 2'b01, 2'b10: - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h509096 == 2'b11 && + CASE_guard09094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h509094 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509096) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509094) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32738,38 +32738,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h509096 == 2'b0) ? + (guard__h509094 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h509096 == 2'b01 || guard__h509096 == 2'b10 || - guard__h509096 == 2'b11) && + (guard__h509094 == 2'b01 || guard__h509094 == 2'b10 || + guard__h509094 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h568717 or - _theResult___fst_exp__h576678 or _theResult___exp__h577333) + always@(guard__h568715 or + _theResult___fst_exp__h576676 or _theResult___exp__h577331) begin - case (guard__h568717) + case (guard__h568715) 2'b0: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = - _theResult___fst_exp__h576678; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152 = + _theResult___fst_exp__h576676; 2'b01, 2'b10, 2'b11: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = - _theResult___exp__h577333; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152 = + _theResult___exp__h577331; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h576678 or + _theResult___fst_exp__h576676 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 or - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152) + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - _theResult___fst_exp__h576678; + _theResult___fst_exp__h576676; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717; @@ -32778,40 +32778,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = 11'd0; endcase end - always@(guard__h568717 or - _theResult___fst_exp__h576678 or - out_exp__h577336 or _theResult___exp__h577333) + always@(guard__h568715 or + _theResult___fst_exp__h576676 or + out_exp__h577334 or _theResult___exp__h577331) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = - _theResult___fst_exp__h576678; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = + _theResult___fst_exp__h576676; 2'b10: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = - out_exp__h577336; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = + out_exp__h577334; 2'b11: - CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = - _theResult___exp__h577333; + CASE_guard68715_0b0_theResult___fst_exp76676_0_ETC__q153 = + _theResult___exp__h577331; endcase end - always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568715 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01, 2'b10: - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h568717 == 2'b11 && + CASE_guard68715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h568715 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568715) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32819,29 +32819,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h568717 == 2'b0) ? + (guard__h568715 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h568717 == 2'b01 || guard__h568717 == 2'b10 || - guard__h568717 == 2'b11) && + (guard__h568715 == 2'b01 || guard__h568715 == 2'b10 || + guard__h568715 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578027 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01, 2'b10: - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h578029 == 2'b11 && + CASE_guard78027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h578027 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578027) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32849,29 +32849,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h578029 == 2'b0) ? + (guard__h578027 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h578029 == 2'b01 || guard__h578029 == 2'b10 || - guard__h578029 == 2'b11) && + (guard__h578027 == 2'b01 || guard__h578027 == 2'b10 || + guard__h578027 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587096 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01, 2'b10: - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h587098 == 2'b11 && + CASE_guard87096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h587096 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587096) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32879,29 +32879,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h587098 == 2'b0) ? + (guard__h587096 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h587098 == 2'b01 || guard__h587098 == 2'b10 || - guard__h587098 == 2'b11) && + (guard__h587096 == 2'b01 || guard__h587096 == 2'b10 || + guard__h587096 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578027 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01, 2'b10: - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h578029 != 2'b11 || + CASE_guard78027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h578027 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578027) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32909,29 +32909,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h578029 == 2'b0) ? + (guard__h578027 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h578029 != 2'b01 && guard__h578029 != 2'b10 && - guard__h578029 != 2'b11 || + guard__h578027 != 2'b01 && guard__h578027 != 2'b10 && + guard__h578027 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587096 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01, 2'b10: - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h587098 != 2'b11 || + CASE_guard87096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h587096 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587096) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32939,29 +32939,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h587098 == 2'b0) ? + (guard__h587096 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h587098 != 2'b01 && guard__h587098 != 2'b10 && - guard__h587098 != 2'b11 || + guard__h587096 != 2'b01 && guard__h587096 != 2'b10 && + guard__h587096 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568715 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01, 2'b10: - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h568717 != 2'b11 || + CASE_guard68715_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h568715 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568715) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32969,38 +32969,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h568717 == 2'b0) ? + (guard__h568715 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h568717 != 2'b01 && guard__h568717 != 2'b10 && - guard__h568717 != 2'b11 || + guard__h568715 != 2'b01 && guard__h568715 != 2'b10 && + guard__h568715 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h529516 or - _theResult___fst_exp__h537477 or _theResult___exp__h538132) + always@(guard__h529514 or + _theResult___fst_exp__h537475 or _theResult___exp__h538130) begin - case (guard__h529516) + case (guard__h529514) 2'b0: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = - _theResult___fst_exp__h537477; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175 = + _theResult___fst_exp__h537475; 2'b01, 2'b10, 2'b11: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = - _theResult___exp__h538132; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175 = + _theResult___exp__h538130; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h537477 or + _theResult___fst_exp__h537475 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 or - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175) + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - _theResult___fst_exp__h537477; + _theResult___fst_exp__h537475; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480; @@ -33009,49 +33009,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = 11'd0; endcase end - always@(guard__h529516 or - _theResult___fst_exp__h537477 or - out_exp__h538135 or _theResult___exp__h538132) + always@(guard__h529514 or + _theResult___fst_exp__h537475 or + out_exp__h538133 or _theResult___exp__h538130) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = - _theResult___fst_exp__h537477; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = + _theResult___fst_exp__h537475; 2'b10: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = - out_exp__h538135; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = + out_exp__h538133; 2'b11: - CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = - _theResult___exp__h538132; + CASE_guard29514_0b0_theResult___fst_exp37475_0_ETC__q176 = + _theResult___exp__h538130; endcase end - always@(guard__h538828 or - _theResult___fst_exp__h547054 or _theResult___exp__h547783) + always@(guard__h538826 or + _theResult___fst_exp__h547052 or _theResult___exp__h547781) begin - case (guard__h538828) + case (guard__h538826) 2'b0: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = - _theResult___fst_exp__h547054; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177 = + _theResult___fst_exp__h547052; 2'b01, 2'b10, 2'b11: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = - _theResult___exp__h547783; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177 = + _theResult___exp__h547781; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h547054 or + _theResult___fst_exp__h547052 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 or - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177) + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - _theResult___fst_exp__h547054; + _theResult___fst_exp__h547052; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518; @@ -33060,49 +33060,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = 11'd0; endcase end - always@(guard__h538828 or - _theResult___fst_exp__h547054 or - out_exp__h547786 or _theResult___exp__h547783) + always@(guard__h538826 or + _theResult___fst_exp__h547052 or + out_exp__h547784 or _theResult___exp__h547781) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = - _theResult___fst_exp__h547054; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = + _theResult___fst_exp__h547052; 2'b10: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = - out_exp__h547786; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = + out_exp__h547784; 2'b11: - CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = - _theResult___exp__h547783; + CASE_guard38826_0b0_theResult___fst_exp47052_0_ETC__q178 = + _theResult___exp__h547781; endcase end - always@(guard__h547897 or - _theResult___fst_exp__h555887 or _theResult___exp__h556567) + always@(guard__h547895 or + _theResult___fst_exp__h555885 or _theResult___exp__h556565) begin - case (guard__h547897) + case (guard__h547895) 2'b0: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = - _theResult___fst_exp__h555887; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179 = + _theResult___fst_exp__h555885; 2'b01, 2'b10, 2'b11: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = - _theResult___exp__h556567; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179 = + _theResult___exp__h556565; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h555887 or + _theResult___fst_exp__h555885 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 or - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179) + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - _theResult___fst_exp__h555887; + _theResult___fst_exp__h555885; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549; @@ -33111,49 +33111,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = 11'd0; endcase end - always@(guard__h547897 or - _theResult___fst_exp__h555887 or - out_exp__h556570 or _theResult___exp__h556567) + always@(guard__h547895 or + _theResult___fst_exp__h555885 or + out_exp__h556568 or _theResult___exp__h556565) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = - _theResult___fst_exp__h555887; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = + _theResult___fst_exp__h555885; 2'b10: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = - out_exp__h556570; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = + out_exp__h556568; 2'b11: - CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = - _theResult___exp__h556567; + CASE_guard47895_0b0_theResult___fst_exp55885_0_ETC__q180 = + _theResult___exp__h556565; endcase end - always@(guard__h587098 or - _theResult___fst_exp__h595088 or _theResult___exp__h595768) + always@(guard__h587096 or + _theResult___fst_exp__h595086 or _theResult___exp__h595766) begin - case (guard__h587098) + case (guard__h587096) 2'b0: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = - _theResult___fst_exp__h595088; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181 = + _theResult___fst_exp__h595086; 2'b01, 2'b10, 2'b11: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = - _theResult___exp__h595768; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181 = + _theResult___exp__h595766; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h595088 or + _theResult___fst_exp__h595086 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 or - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181) + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - _theResult___fst_exp__h595088; + _theResult___fst_exp__h595086; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786; @@ -33162,49 +33162,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = 11'd0; endcase end - always@(guard__h587098 or - _theResult___fst_exp__h595088 or - out_exp__h595771 or _theResult___exp__h595768) + always@(guard__h587096 or + _theResult___fst_exp__h595086 or + out_exp__h595769 or _theResult___exp__h595766) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = - _theResult___fst_exp__h595088; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = + _theResult___fst_exp__h595086; 2'b10: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = - out_exp__h595771; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = + out_exp__h595769; 2'b11: - CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = - _theResult___exp__h595768; + CASE_guard87096_0b0_theResult___fst_exp95086_0_ETC__q182 = + _theResult___exp__h595766; endcase end - always@(guard__h578029 or - _theResult___fst_exp__h586255 or _theResult___exp__h586984) + always@(guard__h578027 or + _theResult___fst_exp__h586253 or _theResult___exp__h586982) begin - case (guard__h578029) + case (guard__h578027) 2'b0: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = - _theResult___fst_exp__h586255; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183 = + _theResult___fst_exp__h586253; 2'b01, 2'b10, 2'b11: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = - _theResult___exp__h586984; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183 = + _theResult___exp__h586982; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h586255 or + _theResult___fst_exp__h586253 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 or - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183) + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - _theResult___fst_exp__h586255; + _theResult___fst_exp__h586253; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755; @@ -33213,40 +33213,40 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = 11'd0; endcase end - always@(guard__h578029 or - _theResult___fst_exp__h586255 or - out_exp__h586987 or _theResult___exp__h586984) + always@(guard__h578027 or + _theResult___fst_exp__h586253 or + out_exp__h586985 or _theResult___exp__h586982) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = - _theResult___fst_exp__h586255; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = + _theResult___fst_exp__h586253; 2'b10: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = - out_exp__h586987; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = + out_exp__h586985; 2'b11: - CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = - _theResult___exp__h586984; + CASE_guard78027_0b0_theResult___fst_exp86253_0_ETC__q184 = + _theResult___exp__h586982; endcase end - always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529514 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01, 2'b10: - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h529516 == 2'b11 && + CASE_guard29514_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h529514 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529514) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33254,29 +33254,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h529516 == 2'b0) ? + (guard__h529514 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h529516 == 2'b01 || guard__h529516 == 2'b10 || - guard__h529516 == 2'b11) && + (guard__h529514 == 2'b01 || guard__h529514 == 2'b10 || + guard__h529514 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538826 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01, 2'b10: - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h538828 == 2'b11 && + CASE_guard38826_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h538826 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538826) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33284,29 +33284,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h538828 == 2'b0) ? + (guard__h538826 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h538828 == 2'b01 || guard__h538828 == 2'b10 || - guard__h538828 == 2'b11) && + (guard__h538826 == 2'b01 || guard__h538826 == 2'b10 || + guard__h538826 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547895 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01, 2'b10: - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h547897 == 2'b11 && + CASE_guard47895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h547895 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547895) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33314,29 +33314,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h547897 == 2'b0) ? + (guard__h547895 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h547897 == 2'b01 || guard__h547897 == 2'b10 || - guard__h547897 == 2'b11) && + (guard__h547895 == 2'b01 || guard__h547895 == 2'b10 || + guard__h547895 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538826 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01, 2'b10: - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h538828 != 2'b11 || + CASE_guard38826_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h538826 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538826) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33344,29 +33344,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h538828 == 2'b0) ? + (guard__h538826 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h538828 != 2'b01 && guard__h538828 != 2'b10 && - guard__h538828 != 2'b11 || + guard__h538826 != 2'b01 && guard__h538826 != 2'b10 && + guard__h538826 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547895 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01, 2'b10: - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h547897 != 2'b11 || + CASE_guard47895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h547895 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547895) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33374,29 +33374,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h547897 == 2'b0) ? + (guard__h547895 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h547897 != 2'b01 && guard__h547897 != 2'b10 && - guard__h547897 != 2'b11 || + guard__h547895 != 2'b01 && guard__h547895 != 2'b10 && + guard__h547895 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529514 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01, 2'b10: - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h529516 != 2'b11 || + CASE_guard29514_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h529514 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529514) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33404,38 +33404,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h529516 == 2'b0) ? + (guard__h529514 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h529516 != 2'b01 && guard__h529516 != 2'b10 && - guard__h529516 != 2'b11 || + guard__h529514 != 2'b01 && guard__h529514 != 2'b10 && + guard__h529514 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529516 or - _theResult___snd__h537428 or _theResult___sfd__h538133) + always@(guard__h529514 or + _theResult___snd__h537426 or _theResult___sfd__h538131) begin - case (guard__h529516) + case (guard__h529514) 2'b0: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = - _theResult___snd__h537428[56:5]; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197 = + _theResult___snd__h537426[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = - _theResult___sfd__h538133; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197 = + _theResult___sfd__h538131; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h537428 or + _theResult___snd__h537426 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 or - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197) + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - _theResult___snd__h537428[56:5]; + _theResult___snd__h537426[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575; @@ -33444,48 +33444,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = 52'd0; endcase end - always@(guard__h529516 or - _theResult___snd__h537428 or - out_sfd__h538136 or _theResult___sfd__h538133) + always@(guard__h529514 or + _theResult___snd__h537426 or + out_sfd__h538134 or _theResult___sfd__h538131) begin - case (guard__h529516) + case (guard__h529514) 2'b0, 2'b01: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = - _theResult___snd__h537428[56:5]; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = + _theResult___snd__h537426[56:5]; 2'b10: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = - out_sfd__h538136; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = + out_sfd__h538134; 2'b11: - CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = - _theResult___sfd__h538133; + CASE_guard29514_0b0_theResult___snd37426_BITS__ETC__q198 = + _theResult___sfd__h538131; endcase end - always@(guard__h538828 or sfdin__h547048 or _theResult___sfd__h547784) + always@(guard__h538826 or sfdin__h547046 or _theResult___sfd__h547782) begin - case (guard__h538828) + case (guard__h538826) 2'b0: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h547048[56:5]; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199 = + sfdin__h547046[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h547784; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199 = + _theResult___sfd__h547782; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h547048 or + sfdin__h547046 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 or - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199) + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - sfdin__h547048[56:5]; + sfdin__h547046[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601; @@ -33494,48 +33494,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = 52'd0; endcase end - always@(guard__h538828 or - sfdin__h547048 or out_sfd__h547787 or _theResult___sfd__h547784) + always@(guard__h538826 or + sfdin__h547046 or out_sfd__h547785 or _theResult___sfd__h547782) begin - case (guard__h538828) + case (guard__h538826) 2'b0, 2'b01: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h547048[56:5]; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = + sfdin__h547046[56:5]; 2'b10: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h547787; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = + out_sfd__h547785; 2'b11: - CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h547784; + CASE_guard38826_0b0_sfdin47046_BITS_56_TO_5_0b_ETC__q200 = + _theResult___sfd__h547782; endcase end - always@(guard__h547897 or - _theResult___snd__h555833 or _theResult___sfd__h556568) + always@(guard__h547895 or + _theResult___snd__h555831 or _theResult___sfd__h556566) begin - case (guard__h547897) + case (guard__h547895) 2'b0: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = - _theResult___snd__h555833[56:5]; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201 = + _theResult___snd__h555831[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = - _theResult___sfd__h556568; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201 = + _theResult___sfd__h556566; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h555833 or + _theResult___snd__h555831 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 or - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201) + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - _theResult___snd__h555833[56:5]; + _theResult___snd__h555831[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620; @@ -33544,49 +33544,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = 52'd0; endcase end - always@(guard__h547897 or - _theResult___snd__h555833 or - out_sfd__h556571 or _theResult___sfd__h556568) + always@(guard__h547895 or + _theResult___snd__h555831 or + out_sfd__h556569 or _theResult___sfd__h556566) begin - case (guard__h547897) + case (guard__h547895) 2'b0, 2'b01: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = - _theResult___snd__h555833[56:5]; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = + _theResult___snd__h555831[56:5]; 2'b10: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = - out_sfd__h556571; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = + out_sfd__h556569; 2'b11: - CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = - _theResult___sfd__h556568; + CASE_guard47895_0b0_theResult___snd55831_BITS__ETC__q202 = + _theResult___sfd__h556566; endcase end - always@(guard__h500027 or - _theResult___fst_exp__h508253 or _theResult___exp__h508982) + always@(guard__h500025 or + _theResult___fst_exp__h508251 or _theResult___exp__h508980) begin - case (guard__h500027) + case (guard__h500025) 2'b0: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = - _theResult___fst_exp__h508253; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203 = + _theResult___fst_exp__h508251; 2'b01, 2'b10, 2'b11: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = - _theResult___exp__h508982; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203 = + _theResult___exp__h508980; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h508253 or + _theResult___fst_exp__h508251 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 or - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203) + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - _theResult___fst_exp__h508253; + _theResult___fst_exp__h508251; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050; @@ -33595,49 +33595,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = 11'd0; endcase end - always@(guard__h500027 or - _theResult___fst_exp__h508253 or - out_exp__h508985 or _theResult___exp__h508982) + always@(guard__h500025 or + _theResult___fst_exp__h508251 or + out_exp__h508983 or _theResult___exp__h508980) begin - case (guard__h500027) + case (guard__h500025) 2'b0, 2'b01: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = - _theResult___fst_exp__h508253; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = + _theResult___fst_exp__h508251; 2'b10: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = - out_exp__h508985; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = + out_exp__h508983; 2'b11: - CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = - _theResult___exp__h508982; + CASE_guard00025_0b0_theResult___fst_exp08251_0_ETC__q204 = + _theResult___exp__h508980; endcase end - always@(guard__h509096 or - _theResult___fst_exp__h517086 or _theResult___exp__h517766) + always@(guard__h509094 or + _theResult___fst_exp__h517084 or _theResult___exp__h517764) begin - case (guard__h509096) + case (guard__h509094) 2'b0: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = - _theResult___fst_exp__h517086; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205 = + _theResult___fst_exp__h517084; 2'b01, 2'b10, 2'b11: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = - _theResult___exp__h517766; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205 = + _theResult___exp__h517764; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h517086 or + _theResult___fst_exp__h517084 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 or - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205) + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - _theResult___fst_exp__h517086; + _theResult___fst_exp__h517084; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081; @@ -33646,49 +33646,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = 11'd0; endcase end - always@(guard__h509096 or - _theResult___fst_exp__h517086 or - out_exp__h517769 or _theResult___exp__h517766) + always@(guard__h509094 or + _theResult___fst_exp__h517084 or + out_exp__h517767 or _theResult___exp__h517764) begin - case (guard__h509096) + case (guard__h509094) 2'b0, 2'b01: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = - _theResult___fst_exp__h517086; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = + _theResult___fst_exp__h517084; 2'b10: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = - out_exp__h517769; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = + out_exp__h517767; 2'b11: - CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = - _theResult___exp__h517766; + CASE_guard09094_0b0_theResult___fst_exp17084_0_ETC__q206 = + _theResult___exp__h517764; endcase end - always@(guard__h490715 or - _theResult___snd__h498627 or _theResult___sfd__h499332) + always@(guard__h490713 or + _theResult___snd__h498625 or _theResult___sfd__h499330) begin - case (guard__h490715) + case (guard__h490713) 2'b0: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = - _theResult___snd__h498627[56:5]; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207 = + _theResult___snd__h498625[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = - _theResult___sfd__h499332; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207 = + _theResult___sfd__h499330; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h498627 or + _theResult___snd__h498625 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 or - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207) + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - _theResult___snd__h498627[56:5]; + _theResult___snd__h498625[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107; @@ -33697,49 +33697,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = 52'd0; endcase end - always@(guard__h490715 or - _theResult___snd__h498627 or - out_sfd__h499335 or _theResult___sfd__h499332) + always@(guard__h490713 or + _theResult___snd__h498625 or + out_sfd__h499333 or _theResult___sfd__h499330) begin - case (guard__h490715) + case (guard__h490713) 2'b0, 2'b01: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = - _theResult___snd__h498627[56:5]; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = + _theResult___snd__h498625[56:5]; 2'b10: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = - out_sfd__h499335; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = + out_sfd__h499333; 2'b11: - CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = - _theResult___sfd__h499332; + CASE_guard90713_0b0_theResult___snd98625_BITS__ETC__q208 = + _theResult___sfd__h499330; endcase end - always@(guard__h509096 or - _theResult___snd__h517032 or _theResult___sfd__h517767) + always@(guard__h509094 or + _theResult___snd__h517030 or _theResult___sfd__h517765) begin - case (guard__h509096) + case (guard__h509094) 2'b0: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = - _theResult___snd__h517032[56:5]; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209 = + _theResult___snd__h517030[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = - _theResult___sfd__h517767; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209 = + _theResult___sfd__h517765; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h517032 or + _theResult___snd__h517030 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 or - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209) + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - _theResult___snd__h517032[56:5]; + _theResult___snd__h517030[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153; @@ -33748,48 +33748,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = 52'd0; endcase end - always@(guard__h509096 or - _theResult___snd__h517032 or - out_sfd__h517770 or _theResult___sfd__h517767) + always@(guard__h509094 or + _theResult___snd__h517030 or + out_sfd__h517768 or _theResult___sfd__h517765) begin - case (guard__h509096) + case (guard__h509094) 2'b0, 2'b01: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = - _theResult___snd__h517032[56:5]; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = + _theResult___snd__h517030[56:5]; 2'b10: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = - out_sfd__h517770; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = + out_sfd__h517768; 2'b11: - CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = - _theResult___sfd__h517767; + CASE_guard09094_0b0_theResult___snd17030_BITS__ETC__q210 = + _theResult___sfd__h517765; endcase end - always@(guard__h500027 or sfdin__h508247 or _theResult___sfd__h508983) + always@(guard__h500025 or sfdin__h508245 or _theResult___sfd__h508981) begin - case (guard__h500027) + case (guard__h500025) 2'b0: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = - sfdin__h508247[56:5]; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211 = + sfdin__h508245[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = - _theResult___sfd__h508983; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211 = + _theResult___sfd__h508981; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h508247 or + sfdin__h508245 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 or - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211) + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - sfdin__h508247[56:5]; + sfdin__h508245[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134; @@ -33798,48 +33798,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = 52'd0; endcase end - always@(guard__h500027 or - sfdin__h508247 or out_sfd__h508986 or _theResult___sfd__h508983) + always@(guard__h500025 or + sfdin__h508245 or out_sfd__h508984 or _theResult___sfd__h508981) begin - case (guard__h500027) + case (guard__h500025) 2'b0, 2'b01: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = - sfdin__h508247[56:5]; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = + sfdin__h508245[56:5]; 2'b10: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = - out_sfd__h508986; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = + out_sfd__h508984; 2'b11: - CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = - _theResult___sfd__h508983; + CASE_guard00025_0b0_sfdin08245_BITS_56_TO_5_0b_ETC__q212 = + _theResult___sfd__h508981; endcase end - always@(guard__h568717 or - _theResult___snd__h576629 or _theResult___sfd__h577334) + always@(guard__h568715 or + _theResult___snd__h576627 or _theResult___sfd__h577332) begin - case (guard__h568717) + case (guard__h568715) 2'b0: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = - _theResult___snd__h576629[56:5]; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213 = + _theResult___snd__h576627[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = - _theResult___sfd__h577334; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213 = + _theResult___sfd__h577332; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h576629 or + _theResult___snd__h576627 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 or - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213) + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - _theResult___snd__h576629[56:5]; + _theResult___snd__h576627[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812; @@ -33848,48 +33848,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = 52'd0; endcase end - always@(guard__h568717 or - _theResult___snd__h576629 or - out_sfd__h577337 or _theResult___sfd__h577334) + always@(guard__h568715 or + _theResult___snd__h576627 or + out_sfd__h577335 or _theResult___sfd__h577332) begin - case (guard__h568717) + case (guard__h568715) 2'b0, 2'b01: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = - _theResult___snd__h576629[56:5]; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = + _theResult___snd__h576627[56:5]; 2'b10: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = - out_sfd__h577337; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = + out_sfd__h577335; 2'b11: - CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = - _theResult___sfd__h577334; + CASE_guard68715_0b0_theResult___snd76627_BITS__ETC__q214 = + _theResult___sfd__h577332; endcase end - always@(guard__h578029 or sfdin__h586249 or _theResult___sfd__h586985) + always@(guard__h578027 or sfdin__h586247 or _theResult___sfd__h586983) begin - case (guard__h578029) + case (guard__h578027) 2'b0: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h586249[56:5]; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h586247[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h586985; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h586983; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h586249 or + sfdin__h586247 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 or - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215) + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - sfdin__h586249[56:5]; + sfdin__h586247[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838; @@ -33898,24 +33898,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = 52'd0; endcase end - always@(guard__h578029 or - sfdin__h586249 or out_sfd__h586988 or _theResult___sfd__h586985) + always@(guard__h578027 or + sfdin__h586247 or out_sfd__h586986 or _theResult___sfd__h586983) begin - case (guard__h578029) + case (guard__h578027) 2'b0, 2'b01: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h586249[56:5]; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h586247[56:5]; 2'b10: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h586988; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h586986; 2'b11: - CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h586985; + CASE_guard78027_0b0_sfdin86247_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h586983; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -33950,28 +33950,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830; endcase end - always@(guard__h587098 or - _theResult___snd__h595034 or _theResult___sfd__h595769) + always@(guard__h587096 or + _theResult___snd__h595032 or _theResult___sfd__h595767) begin - case (guard__h587098) + case (guard__h587096) 2'b0: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = - _theResult___snd__h595034[56:5]; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217 = + _theResult___snd__h595032[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = - _theResult___sfd__h595769; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217 = + _theResult___sfd__h595767; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h595034 or + _theResult___snd__h595032 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 or - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217) + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - _theResult___snd__h595034[56:5]; + _theResult___snd__h595032[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857; @@ -33980,25 +33980,25 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = 52'd0; endcase end - always@(guard__h587098 or - _theResult___snd__h595034 or - out_sfd__h595772 or _theResult___sfd__h595769) + always@(guard__h587096 or + _theResult___snd__h595032 or + out_sfd__h595770 or _theResult___sfd__h595767) begin - case (guard__h587098) + case (guard__h587096) 2'b0, 2'b01: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = - _theResult___snd__h595034[56:5]; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = + _theResult___snd__h595032[56:5]; 2'b10: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = - out_sfd__h595772; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = + out_sfd__h595770; 2'b11: - CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = - _theResult___sfd__h595769; + CASE_guard87096_0b0_theResult___snd95032_BITS__ETC__q218 = + _theResult___sfd__h595767; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34311,10 +34311,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h661045 or + always@(k__h661043 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661045) + case (k__h661043) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 = coreFix_aluExe_0_rsAlu$canEnq; @@ -34353,10 +34353,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(k__h661045 or + always@(k__h661043 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661045) + case (k__h661043) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -34498,14 +34498,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h675479 or + always@(idx__h675477 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13509 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675479) + case (idx__h675477) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 = fetchStage$pipelines_0_canDeq && @@ -34641,15 +34641,15 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494; endcase end - always@(k__h661045 or + always@(k__h661043 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h661045) + case (k__h661043) 1'd0: - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61043_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -34752,14 +34752,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(idx__h675479 or + always@(idx__h675477 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13731 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13738 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675479) + case (idx__h675477) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 = (!fetchStage$pipelines_0_canDeq || @@ -37751,7 +37751,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h600774 == 2'd0) + v__h600772 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index 8a98286..88a0737 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v index 1a41e81..681bff9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v index 5c00da0..87a58eb 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_CSR_Tap.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_CSR_Tap.v index a3bcf6f..029d85d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_CSR_Tap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_CSR_Tap.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_GPR_Tap.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_GPR_Tap.v index be8b221..1e9a074 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_GPR_Tap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_GPR_Tap.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v index 9996cf1..3e9ea1b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Mem_Tap.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v index 935f2d7..62280a6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v index 2f1561d..2b68dc4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v index f6ead5f..659476b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v index 2843207..16f6afa 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v index 9f748f7..b30df25 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v index 32b8295..0d6421c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v index 1a3ba20..7eb91a4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v index 8f7dfb4..d7ed640 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v index 5e92dd3..053bf66 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v index 5d2e0d5..a75a034 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v index 8b1becd..22b5f44 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v index 9d6c366..7242060 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v index e6946a8..ccb122d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v index 25e8f29..31207ea 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v index 6f1d821..d9cea29 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -786,8 +786,8 @@ module mkFetchStage(CLK, out_fifo_enqueueElement_1_dummy_1_0$wget, out_fifo_enqueueFifo_lat_0$whas, out_fifo_enqueueFifo_lat_1$whas, - pc_reg_lat_0$whas, - pc_reg_lat_1$whas; + pc_reg_dummy_1_0$whas, + pc_reg_lat_0$whas; // register decode_epoch reg decode_epoch; @@ -4818,7 +4818,7 @@ module mkFetchStage(CLK, // inlined wires assign pc_reg_lat_0$whas = EN_start || WILL_FIRE_RL_doFetch1 ; - assign pc_reg_lat_1$whas = + assign pc_reg_dummy_1_0$whas = WILL_FIRE_RL_doDecode && SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5447 ; @@ -9130,7 +9130,7 @@ module mkFetchStage(CLK, // submodule pc_reg_dummy2_1 assign pc_reg_dummy2_1$D_IN = 1'd1 ; - assign pc_reg_dummy2_1$EN = pc_reg_lat_1$whas ; + assign pc_reg_dummy2_1$EN = pc_reg_dummy_1_0$whas ; // submodule pc_reg_dummy2_2 assign pc_reg_dummy2_2$D_IN = 1'd1 ; @@ -11527,7 +11527,7 @@ module mkFetchStage(CLK, assign IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337 = x__h115849 + 64'd4 ; assign IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d9 = - pc_reg_lat_1$whas ? + pc_reg_dummy_1_0$whas ? upd__h1659 : (pc_reg_lat_0$whas ? upd__h1686 : pc_reg_rl) ; assign IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986 = diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v index 9bec235..19077ae 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v index 3999df6..1ac4e8b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v index 2a255b9..15d044c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v index 5c24b1f..582c46c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v index a94e505..a99ba17 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v index b420b9a..8f2496d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v index f9897e7..633084f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v index ab96233..fb6650c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v index 87e4954..0f647fc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v index 434f48e..a18b0ec 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v index ba18f4f..5290f98 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v index cc3465d..3234ef8 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v index c5a0864..8337f28 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v index 805dcc5..6cbc0b2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v index 41a36dc..b2795ea 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v index f15ec88..b9ad56d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v index b4fa4a6..4b0453f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v index 63a9d74..68735ad 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v index 08033b6..b0ef48d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v index b7a1045..b257c36 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v index 0848cfa..2eea032 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v index 3e2332b..7254a62 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v index 8ce1ce4..62600d8 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v index 086d61c..7ef963e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v index a7de61e..a186981 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index e4d4458..382f1e2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -1347,9 +1347,9 @@ module mkP3_Core(CLK, .axi_out_tlast(tv_xactor$axi_out_tlast)); // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = + assign CAN_FIRE_RL_rl_once = WILL_FIRE_RL_rl_once ; + assign WILL_FIRE_RL_rl_once = corew$RDY_cpu_reset_server_request_put && !rg_once ; - assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; // rule RL_rl_reset_response assign CAN_FIRE_RL_rl_reset_response = @@ -1637,7 +1637,7 @@ module mkP3_Core(CLK, assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; + assign corew$EN_cpu_reset_server_request_put = WILL_FIRE_RL_rl_once ; assign corew$EN_cpu_reset_server_response_get = corew$RDY_cpu_reset_server_response_get ; assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v index 7dfaf3e..7490ccc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index d10f5a0..969e53c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v index 955c79f..a181d0f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v index 0399a9b..9192168 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v index 473ebaa..7b123fe 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v index 3e76786..bc0bb5b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v index c07ff78..a7070c3 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v index 35e774f..b21ff7c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v index 7350806..62c6ac0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v index 2725b41..5153b0f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v index 6bc3736..46f17d4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v index e1af2db..6c29b38 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v index 2aafd79..4071131 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v index f161a85..689b342 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v index cc2c578..ea8ce28 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v index fd3654a..4437b39 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v index 1762326..a0aef54 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v index e064e0f..e492bcf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v b/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v index 5c7edaa..00ef896 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTV_Encode.v b/src_SSITH_P3/xilinx_ip/hdl/mkTV_Encode.v index ef33452..5348886 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTV_Encode.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTV_Encode.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v b/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v index d07abc0..4ce5fb1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v index d7059a8..a049da6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v index f4f9439..6cef5a7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v index 417af0c..7ab9bb7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v index faa8cb7..6614f96 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v index 4053473..279d862 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v index 7bdbe69..e610c1f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v index 9e9d6fe..dc53756 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v index 14f72ed..65ad672 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v index c39d9cd..544866c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v index 318d1f5..0d705fd 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v index 7421709..0114038 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v index 128468d..85ac1bf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v index a3dc704..3ca27d9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v index b602264..9ec85ca 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v index b530943..fe0dcca 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v index 062a838..c47f51b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v index fcd8244..2ffba0b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v index e98a4f4..b645a07 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v index 1e08888..8d04782 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v index b9f2cd4..76da3ab 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v index 1c8195c..edefcc7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v b/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v index da452c1..9e73d6c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_Testbench/SoC/SoC_Map.bsv b/src_Testbench/SoC/SoC_Map.bsv index fa0c9aa..22f3abb 100644 --- a/src_Testbench/SoC/SoC_Map.bsv +++ b/src_Testbench/SoC/SoC_Map.bsv @@ -63,14 +63,24 @@ typedef struct { deriving (FShow); SoC_Map_Struct soc_map_struct = +`ifndef RVFI_DII SoC_Map_Struct { near_mem_io_addr_base: 'h_0200_0000, main_mem_addr_base: 'h_8000_0000, main_mem_addr_size: 'h_1000_0000, - pc_reset_value: 'h_0000_1000 }; +`else +SoC_Map_Struct { + near_mem_io_addr_base: 'h_0200_0000, + + main_mem_addr_base: 'h_8000_0000, + main_mem_addr_size: 'h_0001_0000, + pc_reset_value: 'h_8000_0000 + }; +`endif + // ================================================================ // Interface and module for the address map diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index e0d466c..1668dbd 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -1,5 +1,15 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved. +//- +// RVFI_DII modifications: +// Copyright (c) 2018 Peter Rugg +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package SoC_Top; // ================================================================ @@ -61,6 +71,11 @@ import Accel_AES :: *; import TV_Info :: *; `endif +`ifdef RVFI_DII +import RVFI_DII :: *; +import Types :: *; +`endif + `ifdef INCLUDE_GDB_CONTROL import External_Control :: *; // Control requests/responses from HSFE import Debug_Module :: *; @@ -87,6 +102,8 @@ interface SoC_Top_IFC; `ifdef INCLUDE_TANDEM_VERIF // To tandem verifier interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get; +`elsif RVFI_DII + interface Toooba_RVFI_DII_Server rvfi_dii_server; `endif // External real memory @@ -325,8 +342,8 @@ module mkSoC_Top (SoC_Top_IFC); // ================================================================ // INTERFACE - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - corew.set_verbosity (verbosity, logdelay); + method Action set_verbosity (Bit #(4) new_verbosity, Bit #(64) logdelay); + corew.set_verbosity (new_verbosity, logdelay); endmethod // To external controller (E.g., GDB) @@ -337,6 +354,8 @@ module mkSoC_Top (SoC_Top_IFC); `ifdef INCLUDE_TANDEM_VERIF // To tandem verifier interface tv_verifier_info_get = corew.tv_verifier_info_get; +`elsif RVFI_DII + interface rvfi_dii_server = corew.rvfi_dii_server; `endif // External real memory diff --git a/src_Testbench/Top/Top_HW_Side.bsv b/src_Testbench/Top/Top_HW_Side.bsv index 63fad9a..1c55a53 100644 --- a/src_Testbench/Top/Top_HW_Side.bsv +++ b/src_Testbench/Top/Top_HW_Side.bsv @@ -1,5 +1,16 @@ // Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved. +//- +// RVFI_DII modifications: +// Copyright (c) 2018 Peter Rugg +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Top_HW_Side; // ================================================================ @@ -50,14 +61,22 @@ import C_Imports :: *; import External_Control :: *; `endif +`ifdef RVFI_DII +import RVFI_DII :: *; +import Types :: *; +`endif + // ================================================================ // Top-level module. // Instantiates the SoC. // Instantiates a memory model. +`ifndef RVFI_DII (* synthesize *) -module mkTop_HW_Side (Empty) ; - +module mkTop_HW_Side (Empty); +`else +module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); +`endif SoC_Top_IFC soc_top <- mkSoC_Top; Mem_Model_IFC mem_model <- mkMem_Model; @@ -67,6 +86,7 @@ module mkTop_HW_Side (Empty) ; // ================================================================ // BEHAVIOR +`ifndef RVFI_DII Reg #(Bool) rg_banner_printed <- mkReg (False); // Display a banner @@ -132,6 +152,7 @@ module mkTop_HW_Side (Empty) ; `endif endrule +`endif // ================================================================ // Tandem verifier: drain and output vectors of bytes @@ -261,9 +282,51 @@ module mkTop_HW_Side (Empty) ; // INTERFACE // None (this is top-level) + + // Except RVFI_DII interface if enabled +`ifdef RVFI_DII + return soc_top.rvfi_dii_server; +`endif endmodule // ================================================================ +`ifdef RVFI_DII +// ================================================================ +// mkPiccolo_RVFI_DII instantiates the toplevel with the RVFI_DII +// interfaces enabled, allowing testing with directly +// ================================================================ + +(* synthesize *) +module mkTop_HW_Side(Empty) + provisos (Add#(a__, TDiv#(DataSz,8), 8), Add#(b__, DataSz, 64), Add#(c__, TDiv#(DataSz,8), 8), Add#(d__, DataSz, 64)); + + Reg #(Bool) rg_banner_printed <- mkReg (False); + + // Display a banner + rule rl_step0 (! rg_banner_printed); + $display ("================================================================"); + $display ("Bluespec RISC-V standalone system simulation v1.2"); + $display ("Copyright (c) 2017-2018 Bluespec, Inc. All Rights Reserved."); + $display ("================================================================"); + + rg_banner_printed <= True; + endrule + + RVFI_DII_Bridge #(DataSz, DataSz, SEQ_LEN) bridge <- mkRVFI_DII_Bridge("", 5001); + let dut <- mkPre_Top_HW_Side(reset_by bridge.new_rst); + mkConnection(bridge.client.report, dut.trace_report); + + (* descending_urgency = "bridge.handleReset, rl_provide_instr" *) + rule rl_provide_instr; + Dii_Id req <- dut.seqReq.get; + Bit#(32) inst <- bridge.client.getInst(req); + dut.inst.put(tuple2(inst, req)); + endrule +endmodule + +`endif +// ================================================================ + endpackage: Top_HW_Side diff --git a/src_Verifier/Toooba_RVFI_DII_Bridge.bsv b/src_Verifier/Toooba_RVFI_DII_Bridge.bsv new file mode 100644 index 0000000..378ff38 --- /dev/null +++ b/src_Verifier/Toooba_RVFI_DII_Bridge.bsv @@ -0,0 +1,131 @@ +/*- + * Copyright (c) 2018-2019 Peter Rugg + * Copyright (c) 2020 Jonathan Woodruff + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * @BERI_LICENSE_HEADER_START@ + * + * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor + * license agreements. See the NOTICE file distributed with this work for + * additional information regarding copyright ownership. BERI licenses this + * file to you under the BERI Hardware-Software License, Version 1.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * + * http://www.beri-open-systems.org/legal/license-1-0.txt + * + * Unless required by applicable law or agreed to in writing, Work distributed + * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @BERI_LICENSE_HEADER_END@ + */ + +package Toooba_RVFI_DII_Bridge; + +// ================================================================ +// BSV library imports + +import Vector :: *; +import FIFO :: *; +import FIFOF :: *; +import SpecialFIFOs :: *; +import GetPut :: *; +import ClientServer :: *; +import ConfigReg :: *; + +// ================================================================ +// Project imports + +import Types::*; +import ProcTypes::*; + +//import Verifier :: *; +import RVFI_DII :: *; + +// ================================================================ + +interface Toooba_RVFI_DII_Bridge_IFC; + interface Toooba_RVFI_DII_Server rvfi_dii_server; + interface Server#(Dii_Id, InstsAndIDs) dii; + interface Put#(Rvfi_Traces) rvfi; +endinterface + +module mkTooobaRVFIDIIBridge(Toooba_RVFI_DII_Bridge_IFC); + // DII state + FIFOF#(Tuple2#(Bit#(32), Dii_Id)) dii_in <- mkUGFIFOF; + Reg#(InstsAndIDs) buff <- mkConfigRegU; + FIFOF#(InstsAndIDs) instrs <- mkSizedFIFOF(128); + // RVFI state + FIFO#(Rvfi_Traces) report_vectors <- mkSizedFIFO(128); + FIFO#(RVFI_DII_Execution#(DataSz,DataSz)) reports <- mkSizedFIFO(256); + // Request ID + FIFO#(Dii_Id) seq_req <- mkFIFO; + + Bit#(32) nop = 'h01FFF033; + + Bool verbose = True; + + function Bool validReport(RVFI_DII_Execution#(DataSz,DataSz) trace); + return (trace.rvfi_order != -1 && trace.rvfi_insn != nop); + endfunction + + Reg#(SupWaySel) report_select <- mkReg(0); + rule split_report_vectors; + RVFI_DII_Execution#(DataSz,DataSz) report = report_vectors.first[report_select]; + if (verbose) + $display("%t RVFI response: ", $time, + fshow(report_vectors.first[report_select]) + ); + if (validReport(report)) reports.enq(report); + if (report_select == -1) report_vectors.deq(); + report_select <= report_select + 1; + endrule + + Reg#(SupWaySel) buffLvl <- mkConfigReg(0); + rule bufferInsts(buffLvl != 0 || dii_in.notEmpty); + InstsAndIDs cb = buff; + Bit#(32) ins = nop; + Dii_Id id = ?; + if (dii_in.notEmpty) {ins, id} = dii_in.first; + cb.insts[buffLvl] = tagged Valid ins; + cb.ids[buffLvl] = id; + if (buffLvl == -1) begin + instrs.enq(cb); + cb.insts = replicate(tagged Invalid); + end + buff <= cb; + buffLvl <= buffLvl + 1; + endrule + + interface Toooba_RVFI_DII_Server rvfi_dii_server; + interface Get seqReq = toGet(seq_req); + interface Put inst = toPut(dii_in); + interface Get trace_report = toGet(reports); + endinterface + + interface Server dii; + interface Put request = toPut(seq_req); + interface Get response; + method ActionValue#(InstsAndIDs) get; + InstsAndIDs insts = instrs.first(); + instrs.deq(); + if (verbose) + $display("%t DII injection: ", $time, + fshow(insts) + ); + return insts; + endmethod + endinterface + endinterface + + interface Put rvfi = toPut(report_vectors); +endmodule + +endpackage diff --git a/src_Verifier/Verif_IFC.bsv b/src_Verifier/Verif_IFC.bsv new file mode 100644 index 0000000..5050c74 --- /dev/null +++ b/src_Verifier/Verif_IFC.bsv @@ -0,0 +1,62 @@ +/*- + * Copyright (c) 2018 Jack Deeley + * Copyright (c) 2018 Peter Rugg + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * @BERI_LICENSE_HEADER_START@ + * + * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor + * license agreements. See the NOTICE file distributed with this work for + * additional information regarding copyright ownership. BERI licenses this + * file to you under the BERI Hardware-Software License, Version 1.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * + * http://www.beri-open-systems.org/legal/license-1-0.txt + * + * Unless required by applicable law or agreed to in writing, Work distributed + * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @BERI_LICENSE_HEADER_END@ + */ + +package Verif_IFC; + +import Memory :: *; +import GetPut :: *; +import ClientServer :: *; + +import Verifier :: *; +import ISA_Decls :: *; +import RVFI_DII :: *; + +import Fabric_Defs :: *; +import AXI4_Lite_Types :: *; +import CPU_Globals :: *; + +interface Verif_IFC; + // Standard CPU interfaces that we will pass through + + // coherent caches to LLC + interface ChildCacheToParent#(L1Way, void) dCacheToParent; + interface ChildCacheToParent#(L1Way, void) iCacheToParent; + // DMA to LLC + interface TlbMemClient tlbToMem; + + interface Server #(Token, Token) hart0_server_reset; + + method Action external_interrupt_req (Bool set_not_clear); + method Action timer_interrupt_req (Bool set_not_clear); + method Action software_interrupt_req (Bool set_not_clear); + + interface Toooba_RVFI_DII_Server rvfi_dii_server; +endinterface + +endpackage diff --git a/src_Verifier/Verifier.bsv b/src_Verifier/Verifier.bsv new file mode 100644 index 0000000..a3b198f --- /dev/null +++ b/src_Verifier/Verifier.bsv @@ -0,0 +1,137 @@ +/*- + * Copyright (c) 2018 Jack Deeley + * Copyright (c) 2018-2019 Peter Rugg + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * @BERI_LICENSE_HEADER_START@ + * + * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor + * license agreements. See the NOTICE file distributed with this work for + * additional information regarding copyright ownership. BERI licenses this + * file to you under the BERI Hardware-Software License, Version 1.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * + * http://www.beri-open-systems.org/legal/license-1-0.txt + * + * Unless required by applicable law or agreed to in writing, Work distributed + * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @BERI_LICENSE_HEADER_END@ + */ + +package Verifier; + +import RVFI_DII :: *; +import ISA_Decls :: *; +import CPU_Globals :: *; +`ifdef ISA_CHERI +import CHERICap :: *; +import CHERICC_Fat :: *; +`endif + +`ifdef RVFI +// This function relies on info that is only passed in RVFI-mode. + +Bit#(32) ecall_insn = 32'h73; + +function RVFI_DII_Execution #(XLEN,MEMWIDTH) getRVFIInfoCondensed( + // Using the full data gives us access to rd_valid and a few other fields. + Data_Stage2_to_Stage3 data_s2_s3, + WordXL trapPC, + Bit#(64) order, + Bool isTrap, + Exc_Code exc, + Bool handler, + Bool halted + ); + + Data_RVFI_Stage2 s2 = data_s2_s3.info_RVFI_s2; + Data_RVFI_Stage1 s1 = s2.stage1; + + return RVFI_DII_Execution { + rvfi_order: order, + // Not all traps are relevant in the Clifford-RVFI framework, e.g. page faults. + rvfi_trap: isTrap, + rvfi_halt: (halted) ? True : (data_s2_s3.instr == ecall_insn), + rvfi_intr: handler, + rvfi_insn: data_s2_s3.instr, + rvfi_rs1_addr: s1.rs1_addr, + rvfi_rs2_addr: s1.rs2_addr, + rvfi_rd_addr: data_s2_s3.rd_valid ? data_s2_s3.rd : 0, + rvfi_rs1_data: s1.rs1_data, + rvfi_rs2_data: s1.rs2_data, +`ifdef ISA_CHERI + rvfi_rd_wdata: data_s2_s3.rd == 0 ? 0 : getAddr(data_s2_s3.rd_val), +`else + rvfi_rd_wdata: data_s2_s3.rd == 0 ? 0 : data_s2_s3.rd_val, +`endif + rvfi_pc_rdata: data_s2_s3.pc, + rvfi_pc_wdata: isTrap ? trapPC : s1.pc_wdata, + rvfi_mem_wdata: s1.mem_wdata, + rvfi_mem_addr: s1.mem_addr, + rvfi_mem_rmask: s2.mem_rmask, + rvfi_mem_wmask: s2.mem_wmask, +`ifdef ISA_CHERI + rvfi_mem_rdata: getAddr(data_s2_s3.rd_val) +`else + rvfi_mem_rdata: data_s2_s3.rd_val +`endif + }; +endfunction : getRVFIInfoCondensed + + + +function RVFI_DII_Execution #(XLEN,MEMWIDTH) getRVFIInfoS1 ( + Data_Stage1_to_Stage2 data_s1_s2, + WordXL next_pc, + Bit#(64) order, + Bool isTrap, + Exc_Code exc, + Bool handler, + Bool halted + ); + + Data_RVFI_Stage1 s1 = data_s1_s2.info_RVFI_s1; + + return RVFI_DII_Execution { + rvfi_order: order, + rvfi_trap: isTrap, + rvfi_halt: (halted) ? True : (data_s1_s2.instr == ecall_insn), + rvfi_intr: handler, + rvfi_insn: data_s1_s2.instr, + rvfi_rs1_addr: s1.rs1_addr, + rvfi_rs2_addr: s1.rs2_addr, + rvfi_rs1_data: s1.rs1_data, + rvfi_rs2_data: s1.rs2_data, + rvfi_pc_rdata: data_s1_s2.pc, + rvfi_pc_wdata: isTrap ? next_pc : s1.pc_wdata, + rvfi_mem_addr: s1.mem_addr, + // Although we know what rd *would* be, the fact that we're using this function + // means we can't have actually written to it. + rvfi_rd_addr: 0, + rvfi_rd_wdata: 0, + rvfi_mem_rmask: 0, + rvfi_mem_wmask: 0, + rvfi_mem_wdata: 0, + rvfi_mem_rdata: 0 + }; +endfunction : getRVFIInfoS1 + +function Bit #(TDiv#(MEMWIDTH,8)) getMemMask(Bit #(3) width_code, Bit #(XLEN) addr); + Bit #(5) width = 5'b1 << width_code; + Bit #(TDiv#(MEMWIDTH,8)) result = truncate((9'b1 << width) - 9'b1); + return result; +endfunction : getMemMask + +`endif + +endpackage + diff --git a/src_Verifier/Verifier_CPU.bsv b/src_Verifier/Verifier_CPU.bsv new file mode 100644 index 0000000..693f31a --- /dev/null +++ b/src_Verifier/Verifier_CPU.bsv @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2018 Jack Deeley + * Copyright (c) 2018 Peter Rugg + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * @BERI_LICENSE_HEADER_START@ + * + * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor + * license agreements. See the NOTICE file distributed with this work for + * additional information regarding copyright ownership. BERI licenses this + * file to you under the BERI Hardware-Software License, Version 1.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * + * http://www.beri-open-systems.org/legal/license-1-0.txt + * + * Unless required by applicable law or agreed to in writing, Work distributed + * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @BERI_LICENSE_HEADER_END@ + */ + +package Verifier_CPU; + +//export mkVerifier_CPU, Verif_IFC(..); + +import Memory :: *; +import GetPut :: *; +import ClientServer :: *; + +import Verifier :: *; +import ISA_Decls :: *; +import RVFI_DII :: *; + +import Core :: *; +import Verif_IFC :: *; +import Fabric_Defs :: *; +import AXI4_Lite_Types :: *; +import CPU_Globals :: *; +import FIFOF :: *; + +module mkVerifier_CPU #(parameter Bit#(64) pc_reset_value) (Verif_IFC); + + // The core we are going to verify + Core core <- mkCore(0); + + rule displayData; + + RVFI_DII_Execution #(XLEN) x <- core.to_verifier.get; + $display("[[0x%4h]] insn:0x%8h, pc:0x%8h, rd:0x%8h, mem_addr:0x%8h, mem_wdata:0x%8h", + x.rvfi_order,x.rvfi_insn,x.rvfi_pc_rdata[31:0],x.rvfi_rd_wdata[31:0], + x.rvfi_mem_addr[31:0],x.rvfi_mem_wdata[31:0]); + //$display("[[%4d]] pc: 0x%0h, insn: 0x%0h, wmask: 0x%0h, rmask: 0x%0h, + // mem_rdata: 0x%0h, rs1_data: 0x%0h, rs2_data: 0x%0h", x.rvfi_order, + // x.rvfi_pc_rdata, x.rvfi_insn, x.rvfi_mem_wmask, x.rvfi_mem_rmask, + // x.rvfi_mem_rdata, x.rvfi_rs1_data, x.rvfi_rs2_data); + endrule + + interface RVFI_DII_Server rvfi_dii_server = core.rvfi_dii_server; + + interface iCacheToParent = core.iCacheToParent; + interface dCacheToParent = core.dCacheToParent; + interface tlbToMem = core.tlbToMem; + +endmodule : mkVerifier_CPU + +endpackage