Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.

Browse Source 
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty".  Tandem Verification
trace-generation was not reporting this update.
This commit is contained in:
rsnikhil
2020-03-08 21:29:30 -04:00
parent fafd99c983
commit 976494a8ff
50 changed files with 260262 additions and 240548 deletions
Download Patch File Download Diff File Expand all files Collapse all files

162
src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v
View File

@@ -160,8 +160,8 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q76,
CASE_guard2759_0b0_0_0b1_0_0b10_out_exp3175_0b_ETC__q143,
CASE_guard2759_0b0_0_0b1_theResult___exp3172_0_ETC__q144,
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103,
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104,
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q105,
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q106,
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_theRe_ETC__q146,
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_x3300_ETC__q147,
CASE_guard3586_0b0_0_0b1_0_0b10_out_exp4002_0b_ETC__q128,
@@ -170,8 +170,8 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
CASE_guard3886_0b0_0_0b1_theResult___exp4299_0_ETC__q75,
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_theRe_ETC__q129,
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_x4128_ETC__q130,
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105,
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106,
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q103,
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q104,
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_theRe_ETC__q152,
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_x4427_ETC__q153,
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q101,
@@ -1051,7 +1051,6 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4_AND_ETC___d2281,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683,
execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_OR_ETC___d4052,
@@ -1084,7 +1083,6 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
guard__h34751,
saturated_bit__h5778,
saturated_bit__h94531,
value_BIT_23___h109067,
x__h176800,
x__h176927,
x__h177049,
@@ -1097,7 +1095,14 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_fpu_inst[0] ?
{ IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2186,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4_AND_ETC___d2281,
execFpuSimple_fpu_inst[8:4] == 5'd10 &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
@@ -2423,7 +2428,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2294 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
@@ -2437,7 +2442,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2485 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
@@ -5516,7 +5521,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 :
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q104 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 ;
assign _theResult___fst_exp__h43006 =
(_theResult___fst_exp__h42379 == 8'd255) ?
@@ -5546,7 +5551,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 :
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q106 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 ;
assign _theResult___fst_exp__h51672 =
(_theResult___fst_exp__h51094 == 8'd255) ?
@@ -6568,14 +6573,6 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
assign dst_sfd__h96995 = { 51'd0, x__h176800 } ;
assign dst_sfd__h97055 = { 51'd0, x__h176927 } ;
assign dst_sfd__h97115 = { 51'd0, x__h177049 } ;
assign execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4_AND_ETC___d2281 =
execFpuSimple_fpu_inst[8:4] == 5'd10 &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 || execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277 ;
assign execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263 =
execFpuSimple_fpu_inst[8:4] == 5'd14 &&
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
@@ -7318,9 +7315,10 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
(int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63]) ?
~int_val_rnd__h94501[31:0] + 32'd1 :
int_val_rnd__h94501[31:0] ;
assign value_BIT_23___h109067 = execFpuSimple_rVal1[30:23] != 8'd0 ;
assign value__h101927 =
{ 1'b0, value_BIT_23___h109067, execFpuSimple_rVal1[22:0] } ;
{ 1'b0,
execFpuSimple_rVal1[30:23] != 8'd0,
execFpuSimple_rVal1[22:0] } ;
assign value__h136414 =
execFpuSimple_rVal1[31] ?
-execFpuSimple_rVal1[31:0] :
@@ -9004,7 +9002,6 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
always@(execFpuSimple_fpu_inst or
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263 or
execFpuSimple_rVal1 or
value_BIT_23___h109067 or
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239 or
int_val_rnd__h94501 or
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175 or
@@ -9017,7 +9014,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239;
5'd11:
@@ -9087,7 +9084,6 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579 or
value_BIT_23___h109067 or
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537 or
@@ -9108,7 +9104,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522;
5'd11:
@@ -9263,66 +9259,15 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
_theResult___exp__h33664;
endcase
end
always@(guard__h43017 or
_theResult___fst_exp__h51094 or _theResult___exp__h51571)
begin
case (guard__h43017)
2'b0:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103 =
_theResult___fst_exp__h51094;
2'b01, 2'b10, 2'b11:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103 =
_theResult___exp__h51571;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h51094 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702 or
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
_theResult___fst_exp__h51094;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
8'd0;
endcase
end
always@(guard__h43017 or
_theResult___fst_exp__h51094 or
out_exp__h51574 or _theResult___exp__h51571)
begin
case (guard__h43017)
2'b0, 2'b01:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 =
_theResult___fst_exp__h51094;
2'b10:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 =
out_exp__h51574;
2'b11:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 =
_theResult___exp__h51571;
endcase
end
always@(guard__h34153 or
_theResult___fst_exp__h42379 or _theResult___exp__h42905)
begin
case (guard__h34153)
2'b0:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105 =
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q103 =
_theResult___fst_exp__h42379;
2'b01, 2'b10, 2'b11:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105 =
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q103 =
_theResult___exp__h42905;
endcase
end
@@ -9330,7 +9275,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
_theResult___fst_exp__h42379 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633 or
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105)
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q103)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
@@ -9344,7 +9289,7 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 =
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105;
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q103;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 =
8'd0;
endcase
@@ -9355,16 +9300,67 @@ module module_execFpuSimple(execFpuSimple_fpu_inst,
begin
case (guard__h34153)
2'b0, 2'b01:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 =
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q104 =
_theResult___fst_exp__h42379;
2'b10:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 =
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q104 =
out_exp__h42908;
2'b11:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 =
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q104 =
_theResult___exp__h42905;
endcase
end
always@(guard__h43017 or
_theResult___fst_exp__h51094 or _theResult___exp__h51571)
begin
case (guard__h43017)
2'b0:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q105 =
_theResult___fst_exp__h51094;
2'b01, 2'b10, 2'b11:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q105 =
_theResult___exp__h51571;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h51094 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702 or
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q105)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
_theResult___fst_exp__h51094;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q105;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
8'd0;
endcase
end
always@(guard__h43017 or
_theResult___fst_exp__h51094 or
out_exp__h51574 or _theResult___exp__h51571)
begin
case (guard__h43017)
2'b0, 2'b01:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q106 =
_theResult___fst_exp__h51094;
2'b10:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q106 =
out_exp__h51574;
2'b11:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q106 =
_theResult___exp__h51571;
endcase
end
always@(guard__h16427 or sfdin__h24520 or _theResult___sfd__h25053)
begin
case (guard__h16427)