From 98e15acb3d4372e4a8db3db9e1a8141bd1e011b8 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Fri, 18 Nov 2022 12:07:24 +0000 Subject: [PATCH] Bump BlueStuff + use _Periph versions of parameters where needed --- libs/BlueStuff | 2 +- src_Core/CPU/Proc_IFC.bsv | 5 +-- src_Core/Core/CoreW.bsv | 34 +++++++++++++------ src_Core/Core/Fabric_Defs.bsv | 5 +++ src_Core/Debug_Module/DM_System_Bus.bsv | 10 +++--- src_Core/Debug_Module/Debug_Module.bsv | 4 +-- .../RISCY_OOO/procs/lib/LLCDmaConnect.bsv | 4 +-- 7 files changed, 41 insertions(+), 23 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 48ca4c3..4dec54b 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 48ca4c33911a86d562804defa4dfebaf28ade54b +Subproject commit 4dec54bc42f1705ecd5066bc0d65cd64ab12e32e diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index 60e0053..056ffc3 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -107,8 +107,9 @@ interface Proc_IFC; // Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory) interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User) debug_module_mem_server; + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph) + debug_module_mem_server; `ifdef RVFI_DII interface Toooba_RVFI_DII_Server rvfi_dii_server; diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index e8af566..2fbfe97 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -127,8 +127,8 @@ typedef WindCoreMid #( // AXI lite subordinate control port parameters , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0 // AXI subordinate 0 port parameters , Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph // Number of interrupt lines , t_n_irq) CoreW_IFC #(numeric type t_n_irq); @@ -225,8 +225,10 @@ module mkCoreW_reset #(Reset porReset) Proc_IFC proc <- mkProc (reset_by all_harts_reset); // handle uncached interface - let proc_uncached = - prepend_AXI4_Master_id (0, zero_AXI4_Master_user (proc.master1)); + AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph ) proc_uncached = + prepend_AXI4_Master_id (0, zero_AXI4_Master_user (proc.master1)); // Bridge for uncached expernal bus transactions. let uncached_mem_shim <- mkAXI4ShimFF(reset_by all_harts_reset); @@ -364,7 +366,10 @@ module mkCoreW_reset #(Reset porReset) // Create a tap for DM's memory-writes to the bus, and merge-in the trace data. DM_Mem_Tap_IFC dm_mem_tap <- mkDM_Mem_Tap; mkConnection (debug_module.master, dm_mem_tap.slave); - let dm_master_local = dm_mem_tap.master; + AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph ) + dm_master_local = dm_mem_tap.master; rule rl_merge_dm_mem_trace_data; let tmp <- dm_mem_tap.trace_data_out.get; @@ -430,7 +435,10 @@ module mkCoreW_reset #(Reset porReset) mkConnection (debug_module.harts_csr_mem_client, proc.harts_csr_mem_server, reset_by porReset); // DM's bus master is directly the bus master - let dm_master_local = debug_module.master; + AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph ) + dm_master_local = debug_module.master; // END SECTION: DM, no TV // ================================================================ @@ -441,7 +449,10 @@ module mkCoreW_reset #(Reset porReset) // BEGIN SECTION: no DM // No DM, so 'DM bus master' is AXI4 dummy - let dm_master_local = culDeSac; + AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph ) + dm_master_local = culDeSac; `ifdef INCLUDE_TANDEM_VERIF // TV, no DM: stub out the dm input to TV @@ -462,8 +473,9 @@ module mkCoreW_reset #(Reset porReset) // Masters on the local bus Vector #( CoreW_Bus_Num_Masters , AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User)) + , Wd_AW_User_Periph, Wd_W_User_Periph + , Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph )) master_vector = newVector; master_vector[cpu_uncached_master_num] = proc_uncached; master_vector[debug_module_sba_master_num] = dm_master_local; @@ -473,8 +485,8 @@ module mkCoreW_reset #(Reset porReset) // default slave is forwarded out directly to the Core interface Vector #( CoreW_Bus_Num_Slaves , AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User)) + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph )) slave_vector = newVector; slave_vector[default_slave_num] = uncached_mem_shim.slave; slave_vector[llc_slave_num] = proc.debug_module_mem_server; diff --git a/src_Core/Core/Fabric_Defs.bsv b/src_Core/Core/Fabric_Defs.bsv index 26de07f..d6255cc 100644 --- a/src_Core/Core/Fabric_Defs.bsv +++ b/src_Core/Core/Fabric_Defs.bsv @@ -118,6 +118,11 @@ Bit#(Wd_W_User) fabric_default_wuser = 0; Bit#(Wd_B_User) fabric_default_buser = 0; Bit#(Wd_AR_User) fabric_default_aruser = 0; Bit#(Wd_R_User) fabric_default_ruser = 0; +Bit#(Wd_AW_User_Periph) fabric_default_awuser_periph = 0; +Bit#(Wd_W_User_Periph) fabric_default_wuser_periph = 0; +Bit#(Wd_B_User_Periph) fabric_default_buser_periph = 0; +Bit#(Wd_AR_User_Periph) fabric_default_aruser_periph = 0; +Bit#(Wd_R_User_Periph) fabric_default_ruser_periph = 0; // ================================================================ diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index bf77653..b04d252 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -55,8 +55,8 @@ interface DM_System_Bus_IFC; // ---------------- // Facing System interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User) master; + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph) master; endinterface // ================================================================ @@ -292,7 +292,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); arprot: fabric_default_prot, arqos: fabric_default_qos, arregion: fabric_default_region, - aruser: fabric_default_aruser}; + aruser: fabric_default_aruser_periph}; axiShim.slave.ar.put(rda); // Save read-address for byte-lane extraction from later response @@ -333,13 +333,13 @@ module mkDM_System_Bus (DM_System_Bus_IFC); awprot: fabric_default_prot, awqos: fabric_default_qos, awregion: fabric_default_region, - awuser: fabric_default_awuser}; + awuser: fabric_default_awuser_periph}; axiShim.slave.aw.put(wra); let wrd = AXI4_WFlit {wdata: fabric_data, wstrb: fabric_strb, wlast: True, - wuser: fabric_default_wuser}; + wuser: fabric_default_wuser_periph}; axiShim.slave.w.put(wrd); if (verbosity != 0) begin diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index d3546cb..dfd73a5 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -138,8 +138,8 @@ interface Debug_Module_IFC; // Read/Write RISC-V memory interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User) master; + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph) master; endinterface // ================================================================ diff --git a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv index da0cb3c..0f9b2af 100644 --- a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv +++ b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv @@ -132,8 +132,8 @@ module mkLLCDmaConnect #( DmaServer#(LLCDmaReqId) llc //, MemLoaderMemClient memLoader , Vector#(CoreNum, TlbMemClient) tlb ) (AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User)) + , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph + , Wd_AR_User_Periph, Wd_R_User_Periph )) provisos (Alias #(dmaRqT, DmaRq #(LLCDmaReqId))); Bool verbose = False;