From 994321e527da77ec656d6c7ad1f05967736c6293 Mon Sep 17 00:00:00 2001
From: jon <>
Date: Wed, 7 Jul 2021 11:26:34 +0100
Subject: [PATCH] Potential fix for lockup condition where the (undefined) bits
 of instruction returned for an invalid fetch (that is, with a valid cause)
 indicate a 2-fragment instruction but where a second fragment is not
 available.

---
 src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index e04b216..44cc2eb 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -624,7 +624,7 @@ module mkFetchStage(FetchStage);
                   doAssert(prev_frag.dii_pid+1 == frag.dii_pid, "Attached fragments with non-contigious DII IDs");
 `endif
                end
-            end else if (is_16b_inst(frag.inst_frag)) begin // 16-bit instruction
+            end else if (is_16b_inst(frag.inst_frag) || isValid(frag.cause)) begin // 16-bit instruction
                new_pick = tagged Valid fetch3_2_instC(frag,
                                                       fv_decode_C (misa, misa_mxl_64, getFlags(decompressPc(frag.pc))==1, frag.inst_frag),
                                                       zeroExtend(frag.inst_frag));