diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index 6ea183e..7ab1e72 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -646,11 +646,6 @@ module mkFetchStage(FetchStage);
          end
    endrule: doDecodeFlush
 
-   rule printStuff;
-      $display("main_epoch_spec.first.spec_bits: %x, main_epoch_spec.notEmpty: %x, isCurrent: %x, f_main_epoch: %x, next_epoch: %x",
-                main_epoch_spec.first.spec_bits, main_epoch_spec.notEmpty, isCurrent(f32d.deqS[0].first), f_main_epoch, f32d.deqS[0].first.main_epoch);
-   endrule
-
    Vector#(SupSize, Maybe#(InstrFromFetch3)) decodeIn = replicate(Invalid);
    // Express the incoming fragments as a vector of maybes.
    Vector#(SupSizeX2, Maybe#(Fetch3ToDecode)) frags;
@@ -912,10 +907,6 @@ module mkFetchStage(FetchStage);
        dirPred.nextPc(decode_pc_reg[decode_pc_final_port]);
    endrule
 
-   rule displayRedirects;
-        $display("%d : dr: %d er: %d", cur_cycle, decode_redirect_count, execute_redirect_count);
-   endrule
-
     // train next addr pred: we use a wire to catch outputs of napTrainByDecQ.
     // This prevents napTrainByDecQ from clogging doDecode rule when
     // superscalar size is large
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
index c600714..a979432 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
@@ -817,10 +817,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
         return rdy[idx] ? Valid (idx) : Invalid;
     endfunction
 
-    rule displayRenameCount;
-        $display("%d : rc:%d", cur_cycle, supRenameCnt);
-    endrule
-
     // rename correct path inst
     rule doRenaming(
         !inIfc.pendingMMIOPRq // stall when MMIO pRq is pending