diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index 6ad9794..6bc4201 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -5,6 +5,62 @@ ssith_processor 1.0 + + tv_verifier_info_tx + + + + + + + TDATA + + + tv_verifier_info_tx_tdata + + + + + TSTRB + + + tv_verifier_info_tx_tstrb + + + + + TKEEP + + + tv_verifier_info_tx_tkeep + + + + + TLAST + + + tv_verifier_info_tx_tlast + + + + + TVALID + + + tv_verifier_info_tx_tvalid + + + + + TREADY + + + tv_verifier_info_tx_tready + + + + master0 @@ -705,70 +761,10 @@ ASSOCIATED_BUSIF - master0:master1:tv_verifier_info_tx - - - ASSOCIATED_RESET - RST_N + tv_verifier_info_tx:master0:master1 - - tv_verifier_info_tx - - - - - - - TDATA - - - tv_verifier_info_tx_tdata - - - - - TSTRB - - - tv_verifier_info_tx_tstrb - - - - - TKEEP - - - tv_verifier_info_tx_tkeep - - - - - TLAST - - - tv_verifier_info_tx_tlast - - - - - TVALID - - - tv_verifier_info_tx_tvalid - - - - - TREADY - - - tv_verifier_info_tx_tready - - - - @@ -789,14 +785,23 @@ Synthesis :vivado.xilinx.com:synthesis Verilog - mkP2_Core + mkP3_Core + + xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_div_gen_5_1__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_floating_point_7_1__ref_view_fileset + xilinx_anylanguagesynthesis_view_fileset viewChecksum - 073ddeff + 63c940c2 @@ -805,14 +810,23 @@ Simulation :vivado.xilinx.com:simulation Verilog - mkP2_Core + mkP3_Core + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_div_gen_5_1__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_floating_point_7_1__ref_view_fileset + xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum - a38db3fe + 63c940c2 @@ -2180,6 +2194,19 @@ 15 0 + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + debug_external_interrupt_req_set_not_clear + + in std_logic @@ -2373,7 +2400,7 @@ xilinx_anylanguagesynthesis_view_fileset - src/p2_constraints.xdc + src/p3_constraints.xdc xdc USED_IN_implementation USED_IN_synthesis @@ -2381,354 +2408,1114 @@ hdl/BRAM2.v verilogSource + IMPORTED_FILE hdl/FIFO1.v verilogSource + IMPORTED_FILE + + + hdl/FIFO10.v + verilogSource + IMPORTED_FILE hdl/FIFO2.v verilogSource + IMPORTED_FILE hdl/FIFO20.v verilogSource + IMPORTED_FILE hdl/MakeClock.v verilogSource + IMPORTED_FILE hdl/RegFile.v verilogSource + IMPORTED_FILE + + + hdl/RevertReg.v + verilogSource + IMPORTED_FILE hdl/SizedFIFO.v verilogSource + IMPORTED_FILE hdl/SizedFIFO0.v verilogSource + IMPORTED_FILE hdl/SyncFIFOLevel.v verilogSource + IMPORTED_FILE hdl/SyncHandshake.v verilogSource + IMPORTED_FILE hdl/SyncResetA.v verilogSource + IMPORTED_FILE - hdl/mkBranch_Predictor.v + hdl/mkAluDispToRegFifo.v verilogSource + IMPORTED_FILE - hdl/mkCPU.v + hdl/mkAluExeToFinFifo.v verilogSource + IMPORTED_FILE - hdl/mkCSR_MIE.v - verilogSource - - - hdl/mkCSR_MIP.v - verilogSource - - - hdl/mkCSR_RegFile.v + hdl/mkAluRegToExeFifo.v verilogSource + IMPORTED_FILE hdl/mkCore.v verilogSource + IMPORTED_FILE + + + hdl/mkCoreW.v + verilogSource + IMPORTED_FILE + + + hdl/mkDCRqMshrWrapper.v + verilogSource + IMPORTED_FILE hdl/mkDM_Abstract_Commands.v verilogSource - - - hdl/mkDM_Run_Control.v - verilogSource - - - hdl/mkDM_System_Bus.v - verilogSource - - - hdl/mkDebug_Module.v - verilogSource - - - hdl/mkGPR_RegFile.v - verilogSource - - - hdl/mkJtagTap.v - verilogSource - - - hdl/mkMMU_Cache.v - verilogSource - - - hdl/mkNear_Mem.v - verilogSource - - - hdl/mkRISCV_MBox.v - verilogSource - - - hdl/mkSoC_Map.v - verilogSource - - - hdl/mkTLB.v - verilogSource - - - hdl/mkP2_Core.v - verilogSource - CHECKSUM_d463a775 - - - hdl/mkDM_Mem_Tap.v - verilogSource - xil_defaultlib - - - hdl/mkIntMul_32.v - verilogSource + IMPORTED_FILE hdl/mkDM_CSR_Tap.v verilogSource - xil_defaultlib - - - hdl/mkTV_Encode.v - verilogSource - xil_defaultlib - - - hdl/ClockGen.v - verilogSource + IMPORTED_FILE hdl/mkDM_GPR_Tap.v verilogSource - xil_defaultlib + IMPORTED_FILE - hdl/mkTV_Xactor.v + hdl/mkDM_Mem_Tap.v verilogSource - xil_defaultlib + IMPORTED_FILE - hdl/mkIntMul_64.v + hdl/mkDM_Run_Control.v verilogSource + IMPORTED_FILE + + + hdl/mkDM_System_Bus.v + verilogSource + IMPORTED_FILE + + + hdl/mkDPRqMshrWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkDPipeline.v + verilogSource + IMPORTED_FILE + + + hdl/mkDTlbSynth.v + verilogSource + IMPORTED_FILE + + + hdl/mkDebug_Module.v + verilogSource + IMPORTED_FILE + + + hdl/mkDirPredictor.v + verilogSource + IMPORTED_FILE + + + hdl/mkDivExecQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkDoubleDiv.v + verilogSource + IMPORTED_FILE + + + hdl/mkDoubleFMA.v + verilogSource + IMPORTED_FILE + + + hdl/mkDoubleSqrt.v + verilogSource + IMPORTED_FILE + + + hdl/mkEpochManager.v + verilogSource + IMPORTED_FILE hdl/mkFabric_2x3.v verilogSource + IMPORTED_FILE - hdl/mkNear_Mem_IO_AXI4.v + hdl/mkFetchStage.v verilogSource + IMPORTED_FILE + + + hdl/mkFmaExecQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkFpuMulDivDispToRegFifo.v + verilogSource + IMPORTED_FILE + + + hdl/mkFpuMulDivRegToExeFifo.v + verilogSource + IMPORTED_FILE + + + hdl/mkIBankWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkICRqMshrWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkICoCache.v + verilogSource + IMPORTED_FILE + + + hdl/mkIPRqMshrWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkIPipeline.v + verilogSource + IMPORTED_FILE + + + hdl/mkITlb.v + verilogSource + IMPORTED_FILE + + + hdl/mkJtagTap.v + verilogSource + IMPORTED_FILE + + + hdl/mkL2Tlb.v + verilogSource + IMPORTED_FILE + + + hdl/mkLLCache.v + verilogSource + IMPORTED_FILE + + + hdl/mkLLPipeline.v + verilogSource + IMPORTED_FILE + + + hdl/mkLSQIssueLdQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkLastLvCRqMshr.v + verilogSource + IMPORTED_FILE + + + hdl/mkMMIOInst.v + verilogSource + IMPORTED_FILE + + + hdl/mkMemDispToRegFifo.v + verilogSource + IMPORTED_FILE + + + hdl/mkMemRegToExeFifo.v + verilogSource + IMPORTED_FILE + + + hdl/mkMinimumExecQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkMulExecQ.v + verilogSource + IMPORTED_FILE hdl/mkPLIC_16_2_7.v verilogSource + IMPORTED_FILE - hdl/mkFBox_Core.v + hdl/mkProc.v + verilogSource + IMPORTED_FILE + + + hdl/mkRFileSynth.v + verilogSource + IMPORTED_FILE + + + hdl/mkRas.v + verilogSource + IMPORTED_FILE + + + hdl/mkRegRenamingTable.v + verilogSource + IMPORTED_FILE + + + hdl/mkReorderBufferSynth.v + verilogSource + IMPORTED_FILE + + + hdl/mkReservationStationAlu.v + verilogSource + IMPORTED_FILE + + + hdl/mkReservationStationFpuMulDiv.v + verilogSource + IMPORTED_FILE + + + hdl/mkReservationStationMem.v + verilogSource + IMPORTED_FILE + + + hdl/mkRobRowSynth.v + verilogSource + IMPORTED_FILE + + + hdl/mkScoreboardAggr.v + verilogSource + IMPORTED_FILE + + + hdl/mkScoreboardCons.v + verilogSource + IMPORTED_FILE + + + hdl/mkSimpleRespQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkSoC_Map.v + verilogSource + IMPORTED_FILE + + + hdl/mkSpecTagManager.v + verilogSource + IMPORTED_FILE + + + hdl/mkSplitLSQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkSplitTransCache.v + verilogSource + IMPORTED_FILE + + + hdl/mkStoreBufferEhr.v + verilogSource + IMPORTED_FILE + + + hdl/mkTV_Encode.v + verilogSource + IMPORTED_FILE + + + hdl/mkTV_Xactor.v + verilogSource + IMPORTED_FILE + + + hdl/mkTourGHistReg.v + verilogSource + IMPORTED_FILE + + + hdl/mkTourPred.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpDiv.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpDivIP.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpFma.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpFmaIP.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpSqrt.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpSqrtIP.v + verilogSource + IMPORTED_FILE + + + hdl/module_alu.v + verilogSource + IMPORTED_FILE + + + hdl/module_aluBr.v + verilogSource + IMPORTED_FILE + + + hdl/module_amoExec.v + verilogSource + IMPORTED_FILE + + + hdl/module_basicExec.v + verilogSource + IMPORTED_FILE + + + hdl/module_brAddrCalc.v + verilogSource + IMPORTED_FILE + + + hdl/module_checkForException.v + verilogSource + IMPORTED_FILE + + + hdl/module_decode.v + verilogSource + IMPORTED_FILE + + + hdl/module_decodeBrPred.v + verilogSource + IMPORTED_FILE + + + hdl/module_execFpuSimple.v + verilogSource + IMPORTED_FILE + + + hdl/reset_guard.v + verilogSource + IMPORTED_FILE + + + src/int_mul_unsigned/int_mul_unsigned.xci + xci + IMPORTED_FILE + + + src/int_mul_signed_unsigned/int_mul_signed_unsigned.xci + xci + IMPORTED_FILE + + + src/int_mul_signed/int_mul_signed.xci + xci + IMPORTED_FILE + + + src/int_div_unsigned/int_div_unsigned.xci + xci + IMPORTED_FILE + + + src/fp_sqrt/fp_sqrt.xci + xci + IMPORTED_FILE + + + src/fp_fma/fp_fma.xci + xci + IMPORTED_FILE + + + src/fp_div/fp_div.xci + xci + IMPORTED_FILE + + + hdl/mkP3_Core.v + verilogSource + CHECKSUM_a15c10a8 + IMPORTED_FILE + + + hdl/MakeResetA.v verilogSource - hdl/mkFBox_Top.v + hdl/ResetEither.v verilogSource - - hdl/mkFPR_RegFile.v - verilogSource - - - hdl/mkFPU.v - verilogSource - - - hdl/FIFOL1.v - verilogSource - CHECKSUM_bfe3b3df - + + + xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_div_gen_5_1__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_floating_point_7_1__ref_view_fileset + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset hdl/BRAM2.v verilogSource + IMPORTED_FILE hdl/FIFO1.v verilogSource + IMPORTED_FILE + + + hdl/FIFO10.v + verilogSource + IMPORTED_FILE hdl/FIFO2.v verilogSource + IMPORTED_FILE hdl/FIFO20.v verilogSource + IMPORTED_FILE hdl/MakeClock.v verilogSource + IMPORTED_FILE hdl/RegFile.v verilogSource + IMPORTED_FILE + + + hdl/RevertReg.v + verilogSource + IMPORTED_FILE hdl/SizedFIFO.v verilogSource + IMPORTED_FILE hdl/SizedFIFO0.v verilogSource + IMPORTED_FILE hdl/SyncFIFOLevel.v verilogSource + IMPORTED_FILE hdl/SyncHandshake.v verilogSource + IMPORTED_FILE hdl/SyncResetA.v verilogSource + IMPORTED_FILE - hdl/mkBranch_Predictor.v + hdl/mkAluDispToRegFifo.v verilogSource + IMPORTED_FILE - hdl/mkCPU.v + hdl/mkAluExeToFinFifo.v verilogSource + IMPORTED_FILE - hdl/mkCSR_MIE.v - verilogSource - - - hdl/mkCSR_MIP.v - verilogSource - - - hdl/mkCSR_RegFile.v + hdl/mkAluRegToExeFifo.v verilogSource + IMPORTED_FILE hdl/mkCore.v verilogSource + IMPORTED_FILE + + + hdl/mkCoreW.v + verilogSource + IMPORTED_FILE + + + hdl/mkDCRqMshrWrapper.v + verilogSource + IMPORTED_FILE hdl/mkDM_Abstract_Commands.v verilogSource + IMPORTED_FILE + + + hdl/mkDM_CSR_Tap.v + verilogSource + IMPORTED_FILE + + + hdl/mkDM_GPR_Tap.v + verilogSource + IMPORTED_FILE + + + hdl/mkDM_Mem_Tap.v + verilogSource + IMPORTED_FILE hdl/mkDM_Run_Control.v verilogSource + IMPORTED_FILE hdl/mkDM_System_Bus.v verilogSource + IMPORTED_FILE + + + hdl/mkDPRqMshrWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkDPipeline.v + verilogSource + IMPORTED_FILE + + + hdl/mkDTlbSynth.v + verilogSource + IMPORTED_FILE hdl/mkDebug_Module.v verilogSource + IMPORTED_FILE - hdl/mkGPR_RegFile.v + hdl/mkDirPredictor.v verilogSource + IMPORTED_FILE - hdl/mkJtagTap.v + hdl/mkDivExecQ.v verilogSource + IMPORTED_FILE - hdl/mkMMU_Cache.v + hdl/mkDoubleDiv.v verilogSource + IMPORTED_FILE - hdl/mkNear_Mem.v + hdl/mkDoubleFMA.v verilogSource + IMPORTED_FILE - hdl/mkRISCV_MBox.v + hdl/mkDoubleSqrt.v verilogSource + IMPORTED_FILE - hdl/mkSoC_Map.v - verilogSource - - - hdl/mkTLB.v - verilogSource - - - hdl/mkP2_Core.v - verilogSource - - - hdl/ClockGen.v + hdl/mkEpochManager.v verilogSource + IMPORTED_FILE hdl/mkFabric_2x3.v verilogSource + IMPORTED_FILE - hdl/mkIntMul_32.v + hdl/mkFetchStage.v verilogSource + IMPORTED_FILE - hdl/mkIntMul_64.v + hdl/mkFmaExecQ.v verilogSource + IMPORTED_FILE - hdl/mkNear_Mem_IO_AXI4.v + hdl/mkFpuMulDivDispToRegFifo.v verilogSource + IMPORTED_FILE + + + hdl/mkFpuMulDivRegToExeFifo.v + verilogSource + IMPORTED_FILE + + + hdl/mkIBankWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkICRqMshrWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkICoCache.v + verilogSource + IMPORTED_FILE + + + hdl/mkIPRqMshrWrapper.v + verilogSource + IMPORTED_FILE + + + hdl/mkIPipeline.v + verilogSource + IMPORTED_FILE + + + hdl/mkITlb.v + verilogSource + IMPORTED_FILE + + + hdl/mkJtagTap.v + verilogSource + IMPORTED_FILE + + + hdl/mkL2Tlb.v + verilogSource + IMPORTED_FILE + + + hdl/mkLLCache.v + verilogSource + IMPORTED_FILE + + + hdl/mkLLPipeline.v + verilogSource + IMPORTED_FILE + + + hdl/mkLSQIssueLdQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkLastLvCRqMshr.v + verilogSource + IMPORTED_FILE + + + hdl/mkMMIOInst.v + verilogSource + IMPORTED_FILE + + + hdl/mkMemDispToRegFifo.v + verilogSource + IMPORTED_FILE + + + hdl/mkMemRegToExeFifo.v + verilogSource + IMPORTED_FILE + + + hdl/mkMinimumExecQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkMulExecQ.v + verilogSource + IMPORTED_FILE hdl/mkPLIC_16_2_7.v verilogSource + IMPORTED_FILE - hdl/mkFBox_Core.v + hdl/mkProc.v + verilogSource + IMPORTED_FILE + + + hdl/mkRFileSynth.v + verilogSource + IMPORTED_FILE + + + hdl/mkRas.v + verilogSource + IMPORTED_FILE + + + hdl/mkRegRenamingTable.v + verilogSource + IMPORTED_FILE + + + hdl/mkReorderBufferSynth.v + verilogSource + IMPORTED_FILE + + + hdl/mkReservationStationAlu.v + verilogSource + IMPORTED_FILE + + + hdl/mkReservationStationFpuMulDiv.v + verilogSource + IMPORTED_FILE + + + hdl/mkReservationStationMem.v + verilogSource + IMPORTED_FILE + + + hdl/mkRobRowSynth.v + verilogSource + IMPORTED_FILE + + + hdl/mkScoreboardAggr.v + verilogSource + IMPORTED_FILE + + + hdl/mkScoreboardCons.v + verilogSource + IMPORTED_FILE + + + hdl/mkSimpleRespQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkSoC_Map.v + verilogSource + IMPORTED_FILE + + + hdl/mkSpecTagManager.v + verilogSource + IMPORTED_FILE + + + hdl/mkSplitLSQ.v + verilogSource + IMPORTED_FILE + + + hdl/mkSplitTransCache.v + verilogSource + IMPORTED_FILE + + + hdl/mkStoreBufferEhr.v + verilogSource + IMPORTED_FILE + + + hdl/mkTV_Encode.v + verilogSource + IMPORTED_FILE + + + hdl/mkTV_Xactor.v + verilogSource + IMPORTED_FILE + + + hdl/mkTourGHistReg.v + verilogSource + IMPORTED_FILE + + + hdl/mkTourPred.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpDiv.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpDivIP.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpFma.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpFmaIP.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpSqrt.v + verilogSource + IMPORTED_FILE + + + hdl/mkXilinxFpSqrtIP.v + verilogSource + IMPORTED_FILE + + + hdl/module_alu.v + verilogSource + IMPORTED_FILE + + + hdl/module_aluBr.v + verilogSource + IMPORTED_FILE + + + hdl/module_amoExec.v + verilogSource + IMPORTED_FILE + + + hdl/module_basicExec.v + verilogSource + IMPORTED_FILE + + + hdl/module_brAddrCalc.v + verilogSource + IMPORTED_FILE + + + hdl/module_checkForException.v + verilogSource + IMPORTED_FILE + + + hdl/module_decode.v + verilogSource + IMPORTED_FILE + + + hdl/module_decodeBrPred.v + verilogSource + IMPORTED_FILE + + + hdl/module_execFpuSimple.v + verilogSource + IMPORTED_FILE + + + hdl/reset_guard.v + verilogSource + IMPORTED_FILE + + + src/int_mul_unsigned/int_mul_unsigned.xci + xci + IMPORTED_FILE + + + src/int_mul_signed_unsigned/int_mul_signed_unsigned.xci + xci + IMPORTED_FILE + + + src/int_mul_signed/int_mul_signed.xci + xci + IMPORTED_FILE + + + src/int_div_unsigned/int_div_unsigned.xci + xci + IMPORTED_FILE + + + src/fp_sqrt/fp_sqrt.xci + xci + IMPORTED_FILE + + + src/fp_fma/fp_fma.xci + xci + IMPORTED_FILE + + + src/fp_div/fp_div.xci + xci + IMPORTED_FILE + + + hdl/mkP3_Core.v + verilogSource + IMPORTED_FILE + + + hdl/MakeResetA.v verilogSource - hdl/mkFBox_Top.v - verilogSource - - - hdl/mkFPR_RegFile.v - verilogSource - - - hdl/mkFPU.v - verilogSource - - - hdl/FIFOL1.v + hdl/ResetEither.v verilogSource + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_div_gen_5_1__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_floating_point_7_1__ref_view_fileset + + + + + + + + xilinx_xpgui_view_fileset @@ -2739,56 +3526,41 @@ - mkP2_Core_v1_0 + mkP3_Core_v1_0 Component_Name - mkP2_Core_v1_0 + mkP3_Core_v1_0 - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu virtexuplus - kintexuplus - zynquplus - kintexu /UserIP - mkP2_Core_v1_0 + mkP3_Core_v1_0 package_project - 6 - 2019-03-16T16:37:14Z + 1 + + user.org:user:mkP3_Core:1.0 + + 2019-04-07T20:09:49Z - - /export/home/stoy/examples/galois/gfe1/bluespec-processors/P2/Flute/src_SSITH_P2/xilinx_ip + /home/charlie/ssith_processor + /home/charlie/ssith_processor + /home/charlie/ssith_processor 2017.4 - + - - - + + + diff --git a/src_SSITH_P3/xilinx_ip/hdl/FIFO10.v b/src_SSITH_P3/xilinx_ip/hdl/FIFO10.v new file mode 100644 index 0000000..eb488b1 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/FIFO10.v @@ -0,0 +1,134 @@ + +// Copyright (c) 2000-2012 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + +`ifdef BSV_ASYNC_RESET + `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST +`else + `define BSV_ARESET_EDGE_META +`endif + + +// Depth 1 FIFO data size 0! +module FIFO10(CLK, + RST, + ENQ, + FULL_N, + DEQ, + EMPTY_N, + CLR + ); + + parameter guarded = 1; + + input CLK; + input RST; + input ENQ; + input DEQ; + input CLR ; + + output FULL_N; + output EMPTY_N; + + reg empty_reg ; + + assign EMPTY_N = empty_reg ; + +`ifdef BSV_NO_INITIAL_BLOCKS +`else // not BSV_NO_INITIAL_BLOCKS + // synopsys translate_off + initial + begin + empty_reg = 1'b0; + end // initial begin + // synopsys translate_on +`endif // BSV_NO_INITIAL_BLOCKS + + + assign FULL_N = !empty_reg; + + always@(posedge CLK `BSV_ARESET_EDGE_META) + begin + if (RST == `BSV_RESET_VALUE) + begin + empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; + end // if (RST == `BSV_RESET_VALUE) + else + begin + if (CLR) + begin + empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; + end + else if (ENQ) + begin + empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; + end + else if (DEQ) + begin + empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; + end // if (DEQ) + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + + // synopsys translate_off + always@(posedge CLK) + begin: error_checks + reg deqerror, enqerror ; + + deqerror = 0; + enqerror = 0; + if (RST == ! `BSV_RESET_VALUE) + begin + if ( ! empty_reg && DEQ ) + begin + deqerror = 1 ; + $display( "Warning: FIFO10: %m -- Dequeuing from empty fifo" ) ; + end + if ( ! FULL_N && ENQ && (!DEQ || guarded) ) + begin + enqerror = 1 ; + $display( "Warning: FIFO10: %m -- Enqueuing to a full fifo" ) ; + end + end // if (RST == ! `BSV_RESET_VALUE) + end + // synopsys translate_on + +endmodule + + + + diff --git a/src_SSITH_P3/xilinx_ip/hdl/RegFileLoad.v b/src_SSITH_P3/xilinx_ip/hdl/RegFileLoad.v new file mode 100644 index 0000000..4cfe073 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/RegFileLoad.v @@ -0,0 +1,119 @@ + +// Copyright (c) 2000-2009 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision: 24080 $ +// $Date: 2011-05-18 15:32:52 -0400 (Wed, 18 May 2011) $ + +`ifdef BSV_WARN_REGFILE_ADDR_RANGE +`else +`define BSV_WARN_REGFILE_ADDR_RANGE 0 +`endif + +`ifdef BSV_ASSIGNMENT_DELAY +`else +`define BSV_ASSIGNMENT_DELAY +`endif + + +// Multi-ported Register File -- initializable from a file. +module RegFileLoad(CLK, + ADDR_IN, D_IN, WE, + ADDR_1, D_OUT_1, + ADDR_2, D_OUT_2, + ADDR_3, D_OUT_3, + ADDR_4, D_OUT_4, + ADDR_5, D_OUT_5 + ); + parameter file = ""; + parameter addr_width = 1; + parameter data_width = 1; + parameter lo = 0; + parameter hi = 1; + parameter binary = 0; + + input CLK; + input [addr_width - 1 : 0] ADDR_IN; + input [data_width - 1 : 0] D_IN; + input WE; + + input [addr_width - 1 : 0] ADDR_1; + output [data_width - 1 : 0] D_OUT_1; + + input [addr_width - 1 : 0] ADDR_2; + output [data_width - 1 : 0] D_OUT_2; + + input [addr_width - 1 : 0] ADDR_3; + output [data_width - 1 : 0] D_OUT_3; + + input [addr_width - 1 : 0] ADDR_4; + output [data_width - 1 : 0] D_OUT_4; + + input [addr_width - 1 : 0] ADDR_5; + output [data_width - 1 : 0] D_OUT_5; + + reg [data_width - 1 : 0] arr[lo:hi]; + + + initial + begin : init_rom_block + if (binary) + $readmemb(file, arr, lo, hi); + else + $readmemh(file, arr, lo, hi); + end // initial begin + + + always@(posedge CLK) + begin + if (WE) + arr[ADDR_IN] <= `BSV_ASSIGNMENT_DELAY D_IN; + end // always@ (posedge CLK) + + assign D_OUT_1 = arr[ADDR_1]; + assign D_OUT_2 = arr[ADDR_2]; + assign D_OUT_3 = arr[ADDR_3]; + assign D_OUT_4 = arr[ADDR_4]; + assign D_OUT_5 = arr[ADDR_5]; + + // synopsys translate_off + always@(posedge CLK) + begin : runtime_check + reg enable_check; + enable_check = `BSV_WARN_REGFILE_ADDR_RANGE ; + if ( enable_check ) + begin + if (( ADDR_1 < lo ) || (ADDR_1 > hi) ) + $display( "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", ADDR_1 ) ; + if (( ADDR_2 < lo ) || (ADDR_2 > hi) ) + $display( "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", ADDR_2 ) ; + if (( ADDR_3 < lo ) || (ADDR_3 > hi) ) + $display( "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", ADDR_3 ) ; + if (( ADDR_4 < lo ) || (ADDR_4 > hi) ) + $display( "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", ADDR_4 ) ; + if (( ADDR_5 < lo ) || (ADDR_5 > hi) ) + $display( "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", ADDR_5 ) ; + if ( WE && ( ADDR_IN < lo ) || (ADDR_IN > hi) ) + $display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ; + end + end + // synopsys translate_on + +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/RevertReg.v b/src_SSITH_P3/xilinx_ip/hdl/RevertReg.v new file mode 100644 index 0000000..df45aa6 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/RevertReg.v @@ -0,0 +1,41 @@ + +// Copyright (c) 2000-2009 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else +`define BSV_ASSIGNMENT_DELAY +`endif + +module RevertReg(CLK, Q_OUT, D_IN, EN); + + parameter width = 1; + parameter init = { width {1'b0} } ; + + input CLK; + input EN; + input [width - 1 : 0] D_IN; + output [width - 1 : 0] Q_OUT; + + assign Q_OUT = init; +endmodule diff --git a/src_SSITH_P3/xilinx_ip/hdl/reset_guard.v b/src_SSITH_P3/xilinx_ip/hdl/reset_guard.v new file mode 100644 index 0000000..cc9f0e5 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/hdl/reset_guard.v @@ -0,0 +1,69 @@ + +// Copyright (c) 2017 Massachusetts Institute of Technology +// +// Permission is hereby granted, free of charge, to any person +// obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without +// restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies +// of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be +// included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +// This module outputs a 1-bit signal +// The signal is initially 0 after programming the FPGA +// XXX: everything should be inited to 0 after programming + +// When a reset arrives, the module starts counting +// In N cycles after the reset, the signal becomes 1 +// This signal can be used as a guard for sync fifo operations + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module reset_guard( + input CLK, + input RST, + output IS_READY +); + reg ready = 0; + reg rst_done = 0; + + always@(posedge CLK) begin + if(RST == `BSV_RESET_VALUE) begin + ready <= 0; + rst_done <= 1; + // synopsys translate_off + if(!rst_done) begin + $display("[reset_guard] %t %m reset happen", $time); + end + // synopsys translate_on + end + else if(rst_done) begin + ready <= 1; + // synopsys translate_off + if(!ready) begin + $display("[reset_guard] %t %m guard ready", $time); + end + // synopsys translate_on + end + end + + assign IS_READY = ready; +endmodule diff --git a/src_SSITH_P3/xilinx_ip/src/fp_div/fp_div.xci b/src_SSITH_P3/xilinx_ip/src/fp_div/fp_div.xci new file mode 100755 index 0000000..5c1e618 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/fp_div/fp_div.xci @@ -0,0 +1,263 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fp_div + + + ACTIVE_LOW + + 10000000 + 0.000 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 32 + -31 + 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file mode 100644 index 0000000..b9cadfb --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/fp_div/fp_div.xml @@ -0,0 +1,2172 @@ + + + xilinx.com + customized_ip + fp_div + 1.0 + + + S_AXIS_A + S_AXIS_A + + + + + + + TDATA + + + s_axis_a_tdata + + + + + TLAST + + + s_axis_a_tlast + + + + + TREADY + + + s_axis_a_tready + + + + + TUSER + + + s_axis_a_tuser + + + + + TVALID + + + s_axis_a_tvalid + + + + + + TDATA_NUM_BYTES + 8 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + aclk_intf + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A + + + 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+ + C_HAS_INVALID_OP + 1 + + + C_HAS_DIVIDE_BY_ZERO + 1 + + + C_HAS_ACCUM_OVERFLOW + 0 + + + C_HAS_ACCUM_INPUT_OVERFLOW + 0 + + + C_HAS_ACLKEN + 0 + + + C_HAS_ARESETN + 0 + + + C_THROTTLE_SCHEME + 1 + + + C_HAS_A_TUSER + 0 + + + C_HAS_A_TLAST + 0 + + + C_HAS_B + 1 + + + C_HAS_B_TUSER + 0 + + + C_HAS_B_TLAST + 0 + + + C_HAS_C + 0 + + + C_HAS_C_TUSER + 0 + + + C_HAS_C_TLAST + 0 + + + C_HAS_OPERATION + 0 + + + C_HAS_OPERATION_TUSER + 0 + + + C_HAS_OPERATION_TLAST + 0 + + + C_HAS_RESULT_TUSER + 1 + + + C_HAS_RESULT_TLAST + 0 + + + C_TLAST_RESOLUTION + 0 + + + C_A_TDATA_WIDTH + 64 + + + C_A_TUSER_WIDTH + 1 + + + C_B_TDATA_WIDTH + 64 + + + C_B_TUSER_WIDTH + 1 + + + C_C_TDATA_WIDTH + 64 + + + C_C_TUSER_WIDTH + 1 + + + C_OPERATION_TDATA_WIDTH + 8 + + + C_OPERATION_TUSER_WIDTH + 1 + + + C_RESULT_TDATA_WIDTH + 64 + + + C_RESULT_TUSER_WIDTH + 4 + + + C_FIXED_DATA_UNSIGNED + 0 + + + + + + choice_list_3da56d14 + Both + Add + Subtract + + + choice_list_4a7739a0 + Half + Single + Double + Custom + + + choice_list_4f849371 + Blocking + NonBlocking + + + choice_list_68e59635 + Null + + + choice_list_e1b2f991 + Resources + Performance + + + choice_pairs_14eb01f2 + Absolute + Accumulator + Add_Subtract + Compare + Divide + Exponential + Fixed_to_float + Float_to_fixed + Float_to_float + FMA + Logarithm + Multiply + Reciprocal + Rec_Square_Root + Square_root + + + choice_pairs_3ca5e07e + Speed_Optimized + Low_Latency + + + choice_pairs_6385fb7a + No_Usage + + + choice_pairs_b847e975 + No_Usage + Full_Usage + + + choice_pairs_eed18387 + Programmable + Unordered + Less_Than + Equal + Less_Than_Or_Equal + Greater_Than + Not_Equal + Greater_Than_Or_Equal + Condition_Code + + + The Xilinx Floating-Point Operator is capable of being configured to provide a range of floating-point operations. The core offers addition, subtraction, accumulation, multiplication, fused multiply-add, division, reciprocal, square-root, reciprocal-square-root, absolute value, logarithm, exponential, compare and conversion operations. High-speed, single-cycle throughput is provided at a wide range of wordlengths that include half, single and double precision. DSP48 slices can be used with certain operations. + + + Component_Name + fp_div + + + Operation_Type + Divide + + + Add_Sub_Value + Both + + + C_Compare_Operation + Programmable + + + A_Precision_Type + Double + + + C_A_Exponent_Width + 11 + + + C_A_Fraction_Width + 53 + + + Result_Precision_Type + Double + + + C_Result_Exponent_Width + 11 + + + C_Result_Fraction_Width + 53 + + + C_Accum_Msb + 32 + + + C_Accum_Lsb + -31 + + + C_Accum_Input_Msb + 32 + + + C_Optimization + Speed_Optimized + + + C_Mult_Usage + No_Usage + + + C_BRAM_Usage + No_Usage + + + Flow_Control + Blocking + + + Axi_Optimize_Goal + Resources + + + Has_RESULT_TREADY + true + + + Maximum_Latency + false + + + C_Latency + 12 + + + C_Rate + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + C_Has_UNDERFLOW + true + + + C_Has_OVERFLOW + true + + + C_Has_INVALID_OP + true + + + C_Has_DIVIDE_BY_ZERO + true + + + C_Has_ACCUM_OVERFLOW + false + + + C_Has_ACCUM_INPUT_OVERFLOW + false + + + Has_A_TLAST + false + + + Has_A_TUSER + false + + + A_TUSER_Width + 1 + + + Has_B_TLAST + false + + + Has_B_TUSER + false + + + B_TUSER_Width + 1 + + + Has_C_TLAST + false + + + Has_C_TUSER + false + + + C_TUSER_Width + 1 + + + Has_OPERATION_TLAST + false + + + Has_OPERATION_TUSER + false + + + OPERATION_TUSER_Width + 1 + + + RESULT_TLAST_Behv + Null + + + + + Floating-point + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/fp_fma/fp_fma.xci b/src_SSITH_P3/xilinx_ip/src/fp_fma/fp_fma.xci new file mode 100755 index 0000000..0fed26d --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/fp_fma/fp_fma.xci @@ -0,0 +1,262 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fp_fma + + + ACTIVE_LOW + + 10000000 + 0.000 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 3 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 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+ + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/fp_fma/fp_fma.xml b/src_SSITH_P3/xilinx_ip/src/fp_fma/fp_fma.xml new file mode 100644 index 0000000..ffcaabc --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/fp_fma/fp_fma.xml @@ -0,0 +1,2172 @@ + + + xilinx.com + customized_ip + fp_fma + 1.0 + + + S_AXIS_A + S_AXIS_A + + + + + + + TDATA + + + s_axis_a_tdata + + + + + TLAST + + + s_axis_a_tlast + + + + + TREADY + + + s_axis_a_tready + + + + + TUSER + + + s_axis_a_tuser + + + + + TVALID + + + s_axis_a_tvalid + + + + + + TDATA_NUM_BYTES + 8 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + aclk_intf + + + + + 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dummy_view + + + + 0 + + + + + + true + + + + + + m_axis_result_tlast + + out + + + std_logic + dummy_view + + + + 0x0 + + + + + + false + + + + + + + + C_XDEVICEFAMILY + virtexuplus + + + C_HAS_ADD + 0 + + + C_HAS_SUBTRACT + 0 + + + C_HAS_MULTIPLY + 0 + + + C_HAS_DIVIDE + 0 + + + C_HAS_SQRT + 0 + + + C_HAS_COMPARE + 0 + + + C_HAS_FIX_TO_FLT + 0 + + + C_HAS_FLT_TO_FIX + 0 + + + C_HAS_FLT_TO_FLT + 0 + + + C_HAS_RECIP + 0 + + + C_HAS_RECIP_SQRT + 0 + + + C_HAS_ABSOLUTE + 0 + + + C_HAS_LOGARITHM + 0 + + + C_HAS_EXPONENTIAL + 0 + + + C_HAS_FMA + 1 + + + C_HAS_FMS + 0 + + + C_HAS_ACCUMULATOR_A + 0 + + + C_HAS_ACCUMULATOR_S + 0 + + + C_A_WIDTH + 64 + + + C_A_FRACTION_WIDTH + 53 + + + C_B_WIDTH + 64 + + + C_B_FRACTION_WIDTH + 53 + + + C_C_WIDTH + 64 + + + C_C_FRACTION_WIDTH + 53 + + + C_RESULT_WIDTH + 64 + + + C_RESULT_FRACTION_WIDTH + 53 + + + C_COMPARE_OPERATION + 8 + + + C_LATENCY + 3 + + + C_OPTIMIZATION + 1 + + + C_MULT_USAGE + 2 + + + C_BRAM_USAGE + 0 + + + C_RATE + 1 + + + C_ACCUM_INPUT_MSB + 32 + + + C_ACCUM_MSB + 32 + + + C_ACCUM_LSB + -31 + + + C_HAS_UNDERFLOW + 1 + + + C_HAS_OVERFLOW + 1 + + + C_HAS_INVALID_OP + 1 + + + C_HAS_DIVIDE_BY_ZERO + 0 + + + C_HAS_ACCUM_OVERFLOW + 0 + + + C_HAS_ACCUM_INPUT_OVERFLOW + 0 + + + C_HAS_ACLKEN + 0 + + + C_HAS_ARESETN + 0 + + + C_THROTTLE_SCHEME + 1 + + + C_HAS_A_TUSER + 0 + + + C_HAS_A_TLAST + 0 + + + C_HAS_B + 1 + + + C_HAS_B_TUSER + 0 + + + C_HAS_B_TLAST + 0 + + + C_HAS_C + 1 + + + C_HAS_C_TUSER + 0 + + + C_HAS_C_TLAST + 0 + + + C_HAS_OPERATION + 0 + + + C_HAS_OPERATION_TUSER + 0 + + + C_HAS_OPERATION_TLAST + 0 + + + C_HAS_RESULT_TUSER + 1 + + + C_HAS_RESULT_TLAST + 0 + + + C_TLAST_RESOLUTION + 0 + + + C_A_TDATA_WIDTH + 64 + + + C_A_TUSER_WIDTH + 1 + + + C_B_TDATA_WIDTH + 64 + + + C_B_TUSER_WIDTH + 1 + + + C_C_TDATA_WIDTH + 64 + + + C_C_TUSER_WIDTH + 1 + + + C_OPERATION_TDATA_WIDTH + 8 + + + C_OPERATION_TUSER_WIDTH + 1 + + + C_RESULT_TDATA_WIDTH + 64 + + + C_RESULT_TUSER_WIDTH + 3 + + + C_FIXED_DATA_UNSIGNED + 0 + + + + + + choice_list_3da56d14 + Both + Add + Subtract + + + choice_list_4a7739a0 + Half + Single + Double + Custom + + + choice_list_4f849371 + Blocking + NonBlocking + + + choice_list_68e59635 + Null + + + choice_list_e1b2f991 + Resources + Performance + + + choice_pairs_14eb01f2 + Absolute + Accumulator + Add_Subtract + Compare + Divide + Exponential + Fixed_to_float + Float_to_fixed + Float_to_float + FMA + Logarithm + Multiply + Reciprocal + Rec_Square_Root + Square_root + + + choice_pairs_3ca5e07e + Speed_Optimized + Low_Latency + + + choice_pairs_b847e975 + No_Usage + Full_Usage + + + choice_pairs_e2ed2704 + Medium_Usage + Full_Usage + + + choice_pairs_eed18387 + Programmable + Unordered + Less_Than + Equal + Less_Than_Or_Equal + Greater_Than + Not_Equal + Greater_Than_Or_Equal + Condition_Code + + + The Xilinx Floating-Point Operator is capable of being configured to provide a range of floating-point operations. The core offers addition, subtraction, accumulation, multiplication, fused multiply-add, division, reciprocal, square-root, reciprocal-square-root, absolute value, logarithm, exponential, compare and conversion operations. High-speed, single-cycle throughput is provided at a wide range of wordlengths that include half, single and double precision. DSP48 slices can be used with certain operations. + + + Component_Name + fp_fma + + + Operation_Type + FMA + + + Add_Sub_Value + Add + + + C_Compare_Operation + Programmable + + + A_Precision_Type + Double + + + C_A_Exponent_Width + 11 + + + C_A_Fraction_Width + 53 + + + Result_Precision_Type + Double + + + C_Result_Exponent_Width + 11 + + + C_Result_Fraction_Width + 53 + + + C_Accum_Msb + 32 + + + C_Accum_Lsb + -31 + + + C_Accum_Input_Msb + 32 + + + C_Optimization + Speed_Optimized + + + C_Mult_Usage + Full_Usage + + + C_BRAM_Usage + No_Usage + + + Flow_Control + Blocking + + + Axi_Optimize_Goal + Resources + + + Has_RESULT_TREADY + true + + + Maximum_Latency + false + + + C_Latency + 3 + + + C_Rate + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + C_Has_UNDERFLOW + true + + + C_Has_OVERFLOW + true + + + C_Has_INVALID_OP + true + + + C_Has_DIVIDE_BY_ZERO + false + + + C_Has_ACCUM_OVERFLOW + false + + + C_Has_ACCUM_INPUT_OVERFLOW + false + + + Has_A_TLAST + false + + + Has_A_TUSER + false + + + A_TUSER_Width + 1 + + + Has_B_TLAST + false + + + Has_B_TUSER + false + + + B_TUSER_Width + 1 + + + Has_C_TLAST + false + + + Has_C_TUSER + false + + + C_TUSER_Width + 1 + + + Has_OPERATION_TLAST + false + + + Has_OPERATION_TUSER + false + + + OPERATION_TUSER_Width + 1 + + + RESULT_TLAST_Behv + Null + + + + + Floating-point + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/fp_sqrt/fp_sqrt.xci b/src_SSITH_P3/xilinx_ip/src/fp_sqrt/fp_sqrt.xci new file mode 100755 index 0000000..57d0c07 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/fp_sqrt/fp_sqrt.xci @@ -0,0 +1,261 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fp_sqrt + + + ACTIVE_LOW + + 10000000 + 0.000 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 1 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 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+ + + + + + + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/fp_sqrt/fp_sqrt.xml b/src_SSITH_P3/xilinx_ip/src/fp_sqrt/fp_sqrt.xml new file mode 100644 index 0000000..e5ee9de --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/fp_sqrt/fp_sqrt.xml @@ -0,0 +1,2170 @@ + + + xilinx.com + customized_ip + fp_sqrt + 1.0 + + + S_AXIS_A + S_AXIS_A + + + + + + + TDATA + + + s_axis_a_tdata + + + + + TLAST + + + s_axis_a_tlast + + + + + TREADY + + + s_axis_a_tready + + + + + TUSER + + + s_axis_a_tuser + + + + + TVALID + + + s_axis_a_tvalid + + + + + + TDATA_NUM_BYTES + 8 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + aclk_intf + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A + + + ASSOCIATED_RESET + aresetn + + + ASSOCIATED_CLKEN + aclken + + + FREQ_HZ + aclk + 10000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + + true + + + + + + aresetn_intf + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + true + + + + + + aclken_intf + + + + + + + CE + + + aclken + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + + true + + + + + + S_AXIS_B + S_AXIS_B + + + + + + + TDATA + + + s_axis_b_tdata + + + + + TLAST + + + s_axis_b_tlast + + + + + TREADY + + + s_axis_b_tready + + + + + TUSER + + + s_axis_b_tuser + + + + + TVALID + + + s_axis_b_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + 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none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + false + + + + + + + + + aclk + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + + true + + + + + + aclken + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + false + + + + + + aresetn + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + false + + + + + + s_axis_a_tvalid + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + s_axis_a_tready + + out + + + std_logic + dummy_view + + + + 0x0 + + + + + + true + + + + + + s_axis_a_tdata + + in + + 63 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + s_axis_a_tuser + + in + + 0 + 0 + + + + std_logic_vector + dummy_view + + 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+ + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + m_axis_result_tlast + + out + + + std_logic + dummy_view + + + + 0x0 + + + + + + false + + + + + + + + C_XDEVICEFAMILY + virtexuplus + + + C_HAS_ADD + 0 + + + C_HAS_SUBTRACT + 0 + + + C_HAS_MULTIPLY + 0 + + + C_HAS_DIVIDE + 0 + + + C_HAS_SQRT + 1 + + + C_HAS_COMPARE + 0 + + + C_HAS_FIX_TO_FLT + 0 + + + C_HAS_FLT_TO_FIX + 0 + + + C_HAS_FLT_TO_FLT + 0 + + + C_HAS_RECIP + 0 + + + C_HAS_RECIP_SQRT + 0 + + + C_HAS_ABSOLUTE + 0 + + + C_HAS_LOGARITHM + 0 + + + C_HAS_EXPONENTIAL + 0 + + + C_HAS_FMA + 0 + + + C_HAS_FMS + 0 + + + C_HAS_ACCUMULATOR_A + 0 + + + C_HAS_ACCUMULATOR_S + 0 + + + C_A_WIDTH + 64 + + + C_A_FRACTION_WIDTH + 53 + + + C_B_WIDTH + 64 + + + C_B_FRACTION_WIDTH + 53 + + + C_C_WIDTH + 64 + + + C_C_FRACTION_WIDTH + 53 + + + C_RESULT_WIDTH + 64 + + + C_RESULT_FRACTION_WIDTH + 53 + + + C_COMPARE_OPERATION + 8 + + + C_LATENCY + 12 + + + C_OPTIMIZATION + 1 + + + C_MULT_USAGE + 0 + + + C_BRAM_USAGE + 0 + + + C_RATE + 1 + + + C_ACCUM_INPUT_MSB + 32 + + + C_ACCUM_MSB + 32 + + + C_ACCUM_LSB + -31 + + + C_HAS_UNDERFLOW + 0 + + + C_HAS_OVERFLOW + 0 + + + C_HAS_INVALID_OP + 1 + + + C_HAS_DIVIDE_BY_ZERO + 0 + + + C_HAS_ACCUM_OVERFLOW + 0 + + + C_HAS_ACCUM_INPUT_OVERFLOW + 0 + + + C_HAS_ACLKEN + 0 + + + C_HAS_ARESETN + 0 + + + C_THROTTLE_SCHEME + 1 + + + C_HAS_A_TUSER + 0 + + + C_HAS_A_TLAST + 0 + + + C_HAS_B + 0 + + + C_HAS_B_TUSER + 0 + + + C_HAS_B_TLAST + 0 + + + C_HAS_C + 0 + + + C_HAS_C_TUSER + 0 + + + C_HAS_C_TLAST + 0 + + + C_HAS_OPERATION + 0 + + + C_HAS_OPERATION_TUSER + 0 + + + C_HAS_OPERATION_TLAST + 0 + + + C_HAS_RESULT_TUSER + 1 + + + C_HAS_RESULT_TLAST + 0 + + + C_TLAST_RESOLUTION + 0 + + + C_A_TDATA_WIDTH + 64 + + + C_A_TUSER_WIDTH + 1 + + + C_B_TDATA_WIDTH + 64 + + + C_B_TUSER_WIDTH + 1 + + + C_C_TDATA_WIDTH + 64 + + + C_C_TUSER_WIDTH + 1 + + + C_OPERATION_TDATA_WIDTH + 8 + + + C_OPERATION_TUSER_WIDTH + 1 + + + C_RESULT_TDATA_WIDTH + 64 + + + C_RESULT_TUSER_WIDTH + 1 + + + C_FIXED_DATA_UNSIGNED + 0 + + + + + + choice_list_3da56d14 + Both + Add + Subtract + + + choice_list_4a7739a0 + Half + Single + Double + Custom + + + choice_list_4f849371 + Blocking + NonBlocking + + + choice_list_68e59635 + Null + + + choice_list_e1b2f991 + Resources + Performance + + + choice_pairs_14eb01f2 + Absolute + Accumulator + Add_Subtract + Compare + Divide + Exponential + Fixed_to_float + Float_to_fixed + Float_to_float + FMA + Logarithm + Multiply + Reciprocal + Rec_Square_Root + Square_root + + + choice_pairs_3ca5e07e + Speed_Optimized + Low_Latency + + + choice_pairs_6385fb7a + No_Usage + + + choice_pairs_b847e975 + No_Usage + Full_Usage + + + choice_pairs_eed18387 + Programmable + Unordered + Less_Than + Equal + Less_Than_Or_Equal + Greater_Than + Not_Equal + Greater_Than_Or_Equal + Condition_Code + + + The Xilinx Floating-Point Operator is capable of being configured to provide a range of floating-point operations. The core offers addition, subtraction, accumulation, multiplication, fused multiply-add, division, reciprocal, square-root, reciprocal-square-root, absolute value, logarithm, exponential, compare and conversion operations. High-speed, single-cycle throughput is provided at a wide range of wordlengths that include half, single and double precision. DSP48 slices can be used with certain operations. + + + Component_Name + fp_sqrt + + + Operation_Type + Square_root + + + Add_Sub_Value + Both + + + C_Compare_Operation + Programmable + + + A_Precision_Type + Double + + + C_A_Exponent_Width + 11 + + + C_A_Fraction_Width + 53 + + + Result_Precision_Type + Double + + + C_Result_Exponent_Width + 11 + + + C_Result_Fraction_Width + 53 + + + C_Accum_Msb + 32 + + + C_Accum_Lsb + -31 + + + C_Accum_Input_Msb + 32 + + + C_Optimization + Speed_Optimized + + + C_Mult_Usage + No_Usage + + + C_BRAM_Usage + No_Usage + + + Flow_Control + Blocking + + + Axi_Optimize_Goal + Resources + + + Has_RESULT_TREADY + true + + + Maximum_Latency + false + + + C_Latency + 12 + + + C_Rate + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + C_Has_UNDERFLOW + false + + + C_Has_OVERFLOW + false + + + C_Has_INVALID_OP + true + + + C_Has_DIVIDE_BY_ZERO + false + + + C_Has_ACCUM_OVERFLOW + false + + + C_Has_ACCUM_INPUT_OVERFLOW + false + + + Has_A_TLAST + false + + + Has_A_TUSER + false + + + A_TUSER_Width + 1 + + + Has_B_TLAST + false + + + Has_B_TUSER + false + + + B_TUSER_Width + 1 + + + Has_C_TLAST + false + + + Has_C_TUSER + false + + + C_TUSER_Width + 1 + + + Has_OPERATION_TLAST + false + + + Has_OPERATION_TUSER + false + + + OPERATION_TUSER_Width + 1 + + + RESULT_TLAST_Behv + Null + + + + + Floating-point + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_div_unsigned/int_div_unsigned.xci b/src_SSITH_P3/xilinx_ip/src/int_div_unsigned/int_div_unsigned.xci new file mode 100755 index 0000000..e76693d --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_div_unsigned/int_div_unsigned.xci @@ -0,0 +1,155 @@ + + + xilinx.com + xci + unknown + 1.0 + + + int_div_unsigned + + + ACTIVE_LOW + + 1000000 + 0.000 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 16 + 0 + 0 + 76 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 76 + + 100000000 + 0 + 0 + 1 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 12 + 128 + 76 + 64 + 76 + 64 + 1 + 1 + 0 + virtexuplus + 1 + 64 + 64 + 0 + 64 + 0 + false + false + int_div_unsigned + Blocking + Resources + Null + true + Radix2 + 1 + false + 64 + false + true + 76 + false + false + 1 + 64 + 64 + 12 + Manual + Unsigned + Remainder + virtexuplus + xilinx.com:vcu118:part0:2.0 + xcvu9p + flga2104 + VERILOG + + MIXED + -2L + E + TRUE + TRUE + IP_Flow + 12 + TRUE + . + + . + 2017.4 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_div_unsigned/int_div_unsigned.xml b/src_SSITH_P3/xilinx_ip/src/int_div_unsigned/int_div_unsigned.xml new file mode 100644 index 0000000..43a3149 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_div_unsigned/int_div_unsigned.xml @@ -0,0 +1,1251 @@ + + + xilinx.com + customized_ip + int_div_unsigned + 1.0 + + + M_AXIS_DOUT + M_AXIS_DOUT + + + + + + + TDATA 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C_M_AXIS_DOUT_TDATA_WIDTH + 128 + + + C_M_AXIS_DOUT_TUSER_WIDTH + 76 + + + + + + choice_list_68e59635 + Null + + + choice_list_82e3e7ac + Unsigned + Signed + + + choice_list_93ab811d + Automatic + Manual + + + choice_list_a47a4c93 + Remainder + Fractional + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_e1b2f991 + Resources + Performance + + + choice_pairs_08e5ea6d + Blocking + NonBlocking + + + choice_pairs_4f8dd3d5 + High_Radix + LutMult + Radix2 + + + This core provides division using one of three algorithms. The LUT-Mult algorithm is suitable for very small operands. The Radix-2 algorithm provides a solution suitable for small to medium operand division, and High Radix algorithm provides a solution based upon XtremeDSP slices and so is well suited to larger operands (that is, above about 16 bits wide). + + + Component_Name + int_div_unsigned + + + algorithm_type + Radix2 + + + dividend_and_quotient_width + 64 + + + dividend_has_tuser + true + + + dividend_tuser_width + 76 + + + dividend_has_tlast + false + + + divisor_width + 64 + + + divisor_has_tuser + false + + + divisor_tuser_width + 1 + + + divisor_has_tlast + false + + + remainder_type + Remainder + + + fractional_width + 64 + + + operand_sign + Unsigned + + + clocks_per_division + 1 + + + divide_by_zero_detect + false + + + FlowControl + Blocking + + + OptimizeGoal + Resources + + + OutTready + true + + + OutTLASTBehv + Null + + + latency_configuration + Manual + + + latency + 12 + + + ACLKEN + false + + + ARESETN + false + + + + + Divider Generator + 12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_mul_signed/int_mul_signed.xci b/src_SSITH_P3/xilinx_ip/src/int_mul_signed/int_mul_signed.xci new file mode 100755 index 0000000..b9ec103 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_mul_signed/int_mul_signed.xci @@ -0,0 +1,93 @@ + + + xilinx.com + xci + unknown + 1.0 + + + int_mul_signed + + + undef + undef + ACTIVE_LOW + + 10000000 + 0.000 + undef + 0 + 64 + 0 + 10000001 + 64 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 1 + 1 + 127 + 0 + 0 + 0 + 0 + virtexuplus + Distributed_Memory + false + int_mul_signed + 129 + 0 + Parallel_Multiplier + Use_Mults + Speed + 127 + 0 + 2 + Signed + 64 + Signed + 64 + 0 + SCLR_Overrides_CE + false + false + false + false + virtexuplus + xilinx.com:vcu118:part0:2.0 + xcvu9p + flga2104 + VERILOG + + MIXED + -2L + E + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2017.4 + GLOBAL + + + + + + + + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_mul_signed/int_mul_signed.xml b/src_SSITH_P3/xilinx_ip/src/int_mul_signed/int_mul_signed.xml new file mode 100644 index 0000000..21b5191 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_mul_signed/int_mul_signed.xml @@ -0,0 +1,724 @@ + + + xilinx.com + customized_ip + int_mul_signed + 1.0 + + + a_intf + + + + + + + DATA + + + A + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + clk_intf + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + p_intf:b_intf:a_intf + + + ASSOCIATED_RESET + sclr + + + ASSOCIATED_CLKEN + ce + + + FREQ_HZ + clk + 10000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + sclr_intf + + + + + + + RST + + + SCLR + + + + + + POLARITY + ACTIVE_HIGH + + + + + ce_intf + + + + + + + CE + + + CE + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + b_intf + + + + + + + DATA + + + B + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + p_intf + + + + + + + DATA + + + P + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + + + CLK + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + true + + + + + + A + + in + + 63 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + B + + in + + 63 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + CE + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + false + + + + + + SCLR + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + + false + + + + + + P + + out + + 127 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + + C_VERBOSITY + 0 + + + C_MODEL_TYPE + 0 + + + C_OPTIMIZE_GOAL + 1 + + + C_XDEVICEFAMILY + virtexuplus + + + C_HAS_CE + 0 + + + C_HAS_SCLR + 0 + + + C_LATENCY + 2 + + + C_A_WIDTH + 64 + + + C_A_TYPE + 0 + + + C_B_WIDTH + 64 + + + C_B_TYPE + 0 + + + C_OUT_HIGH + 127 + + + C_OUT_LOW + 0 + + + C_MULT_TYPE + 1 + + + C_CE_OVERRIDES_SCLR + 0 + + + C_CCM_IMP + 0 + + + C_B_VALUE + 10000001 + + + C_HAS_ZERO_DETECT + 0 + + + C_ROUND_OUTPUT + 0 + + + C_ROUND_PT + 0 + + + + + + choice_list_504a4ed8 + Distributed_Memory + Block_Memory + Dedicated_Multiplier + + + choice_list_8506c89f + Signed + Unsigned + + + choice_list_8efb0c2d + Parallel_Multiplier + Constant_Coefficient_Multiplier + + + choice_list_a8a38fa5 + Use_LUTs + Use_Mults + + + choice_list_ae2447ac + -1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + + + choice_list_e025b2e6 + SCLR_Overrides_CE + CE_Overrides_SCLR + + + choice_pairs_1f05ab61 + Area + Speed + + + Multiplication is a fundamental DSP operation. This core allows parallel and constant-coefficient multipliers to be generated. The user can specify if DSP48 Slices, LUTs or a combination of resources should be utilized. + + + InternalUser + 0 + + + + true + + + + + + Component_Name + int_mul_signed + + + MultType + Parallel_Multiplier + + + + true + + + + + + PortAType + Signed + + + + true + + + + + + PortAWidth + 64 + + + + true + + + + + + PortBType + Signed + + + + true + + + + + + PortBWidth + 64 + + + + true + + + + + + ConstValue + 129 + + + + false + + + + + + CcmImp + Distributed_Memory + + + + true + + + + + + Multiplier_Construction + Use_Mults + + + + true + + + + + + OptGoal + Speed + + + + false + + + + + + Use_Custom_Output_Width + false + + + + true + + + + + + OutputWidthHigh + 127 + + + + false + + + + + + OutputWidthLow + 0 + + + + false + + + + + + UseRounding + false + + + + false + + + + + + RoundPoint + 0 + + + + false + + + + + + PipeStages + 2 + + + + true + + + + + + ClockEnable + false + + + + true + + + + + + SyncClear + false + + + + true + + + + + + SclrCePriority + SCLR_Overrides_CE + + + + false + + + + + + ZeroDetect + false + + + + true + + + + + + + + Multiplier + 13 + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_mul_signed_unsigned/int_mul_signed_unsigned.xci b/src_SSITH_P3/xilinx_ip/src/int_mul_signed_unsigned/int_mul_signed_unsigned.xci new file mode 100755 index 0000000..b680e5e --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_mul_signed_unsigned/int_mul_signed_unsigned.xci @@ -0,0 +1,94 @@ + + + xilinx.com + xci + unknown + 1.0 + + + int_mul_signed_unsigned + + + undef + undef + ACTIVE_LOW + + 10000000 + 0.000 + undef + 0 + 64 + 1 + 10000001 + 64 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 1 + 1 + 127 + 0 + 0 + 0 + 0 + virtexuplus + Distributed_Memory + false + int_mul_signed_unsigned + 129 + 0 + Parallel_Multiplier + Use_Mults + Speed + 127 + 0 + 2 + Signed + 64 + Unsigned + 64 + 0 + SCLR_Overrides_CE + false + false + false + false + virtexuplus + xilinx.com:vcu118:part0:2.0 + xcvu9p + flga2104 + VERILOG + + MIXED + -2L + E + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2017.4 + GLOBAL + + + + + + + + + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_mul_signed_unsigned/int_mul_signed_unsigned.xml b/src_SSITH_P3/xilinx_ip/src/int_mul_signed_unsigned/int_mul_signed_unsigned.xml new file mode 100644 index 0000000..8b7bb50 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_mul_signed_unsigned/int_mul_signed_unsigned.xml @@ -0,0 +1,725 @@ + + + xilinx.com + customized_ip + int_mul_signed_unsigned + 1.0 + + + a_intf + + + + + + + DATA + + + A + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + clk_intf + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + p_intf:b_intf:a_intf + + + ASSOCIATED_RESET + sclr + + + ASSOCIATED_CLKEN + ce + + + FREQ_HZ + clk + 10000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + sclr_intf + + + + + + + RST + + + SCLR + + + + + + POLARITY + ACTIVE_HIGH + + + + + ce_intf + + + + + + + CE + + + CE + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + b_intf + + + + + + + DATA + + + B + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + p_intf + + + + + + + DATA + + + P + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + + + CLK + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + true + + + + + + A + + in + + 63 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + B + + in + + 63 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + CE + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + false + + + + + + SCLR + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + + false + + + + + + P + + out + + 127 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + + C_VERBOSITY + 0 + + + C_MODEL_TYPE + 0 + + + C_OPTIMIZE_GOAL + 1 + + + C_XDEVICEFAMILY + virtexuplus + + + C_HAS_CE + 0 + + + C_HAS_SCLR + 0 + + + C_LATENCY + 2 + + + C_A_WIDTH + 64 + + + C_A_TYPE + 0 + + + C_B_WIDTH + 64 + + + C_B_TYPE + 1 + + + C_OUT_HIGH + 127 + + + C_OUT_LOW + 0 + + + C_MULT_TYPE + 1 + + + C_CE_OVERRIDES_SCLR + 0 + + + C_CCM_IMP + 0 + + + C_B_VALUE + 10000001 + + + C_HAS_ZERO_DETECT + 0 + + + C_ROUND_OUTPUT + 0 + + + C_ROUND_PT + 0 + + + + + + choice_list_504a4ed8 + Distributed_Memory + Block_Memory + Dedicated_Multiplier + + + choice_list_8506c89f + Signed + Unsigned + + + choice_list_8efb0c2d + Parallel_Multiplier + Constant_Coefficient_Multiplier + + + choice_list_a8a38fa5 + Use_LUTs + Use_Mults + + + choice_list_ae2447ac + -1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + + + choice_list_e025b2e6 + SCLR_Overrides_CE + CE_Overrides_SCLR + + + choice_pairs_1f05ab61 + Area + Speed + + + Multiplication is a fundamental DSP operation. This core allows parallel and constant-coefficient multipliers to be generated. The user can specify if DSP48 Slices, LUTs or a combination of resources should be utilized. + + + InternalUser + 0 + + + + true + + + + + + Component_Name + int_mul_signed_unsigned + + + MultType + Parallel_Multiplier + + + + true + + + + + + PortAType + Signed + + + + true + + + + + + PortAWidth + 64 + + + + true + + + + + + PortBType + Unsigned + + + + true + + + + + + PortBWidth + 64 + + + + true + + + + + + ConstValue + 129 + + + + false + + + + + + CcmImp + Distributed_Memory + + + + true + + + + + + Multiplier_Construction + Use_Mults + + + + true + + + + + + OptGoal + Speed + + + + false + + + + + + Use_Custom_Output_Width + false + + + + true + + + + + + OutputWidthHigh + 127 + + + + false + + + + + + OutputWidthLow + 0 + + + + false + + + + + + UseRounding + false + + + + false + + + + + + RoundPoint + 0 + + + + false + + + + + + PipeStages + 2 + + + + true + + + + + + ClockEnable + false + + + + true + + + + + + SyncClear + false + + + + true + + + + + + SclrCePriority + SCLR_Overrides_CE + + + + false + + + + + + ZeroDetect + false + + + + true + + + + + + + + Multiplier + 13 + + + + + + + + + + + 2017.4 + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_mul_unsigned/int_mul_unsigned.xci b/src_SSITH_P3/xilinx_ip/src/int_mul_unsigned/int_mul_unsigned.xci new file mode 100755 index 0000000..ab373c1 --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_mul_unsigned/int_mul_unsigned.xci @@ -0,0 +1,95 @@ + + + xilinx.com + xci + unknown + 1.0 + + + int_mul_unsigned + + + undef + undef + ACTIVE_LOW + + 10000000 + 0.000 + undef + 1 + 64 + 1 + 10000001 + 64 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 1 + 1 + 127 + 0 + 0 + 0 + 0 + virtexuplus + Distributed_Memory + false + int_mul_unsigned + 129 + 0 + Parallel_Multiplier + Use_Mults + Speed + 127 + 0 + 2 + Unsigned + 64 + Unsigned + 64 + 0 + SCLR_Overrides_CE + false + false + false + false + virtexuplus + xilinx.com:vcu118:part0:2.0 + xcvu9p + flga2104 + VERILOG + + MIXED + -2L + E + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2017.4 + GLOBAL + + + + + + + + + + + + + + + + + diff --git a/src_SSITH_P3/xilinx_ip/src/int_mul_unsigned/int_mul_unsigned.xml b/src_SSITH_P3/xilinx_ip/src/int_mul_unsigned/int_mul_unsigned.xml new file mode 100644 index 0000000..913043e --- /dev/null +++ b/src_SSITH_P3/xilinx_ip/src/int_mul_unsigned/int_mul_unsigned.xml @@ -0,0 +1,726 @@ + + + xilinx.com + customized_ip + int_mul_unsigned + 1.0 + + + a_intf + + + + + + + DATA + + + A + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + clk_intf + + + + + + + CLK + + + CLK + + + + + + ASSOCIATED_BUSIF + p_intf:b_intf:a_intf + + + ASSOCIATED_RESET + sclr + + + ASSOCIATED_CLKEN + ce + + + FREQ_HZ + clk + 10000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + sclr_intf + + + + + + + RST + + + SCLR + + + + + + POLARITY + ACTIVE_HIGH + + + + + ce_intf + + + + + + + CE + + + CE + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + b_intf + + + + + + + DATA + + + B + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + p_intf + + + + + + + DATA + + + P + + + + + + LAYERED_METADATA + undef + + + none + + + + + + + + + + CLK + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + true + + + + + + A + + in + + 63 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + B + + in + + 63 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + true + + + + + + CE + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + + false + + + + + + SCLR + + in + + + std_logic + dummy_view + + + + 0x0 + + + + + + false + + + + + + P + + out + + 127 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + + + C_VERBOSITY + 0 + + + C_MODEL_TYPE + 0 + + + C_OPTIMIZE_GOAL + 1 + + + C_XDEVICEFAMILY + virtexuplus + + + C_HAS_CE + 0 + + + C_HAS_SCLR + 0 + + + C_LATENCY + 2 + + + C_A_WIDTH + 64 + + + C_A_TYPE + 1 + + + C_B_WIDTH + 64 + + + C_B_TYPE + 1 + + + C_OUT_HIGH + 127 + + + C_OUT_LOW + 0 + + + C_MULT_TYPE + 1 + + + C_CE_OVERRIDES_SCLR + 0 + + + C_CCM_IMP + 0 + + + C_B_VALUE + 10000001 + + + C_HAS_ZERO_DETECT + 0 + + + C_ROUND_OUTPUT + 0 + + + C_ROUND_PT + 0 + + + + + + choice_list_504a4ed8 + Distributed_Memory + Block_Memory + Dedicated_Multiplier + + + choice_list_8506c89f + Signed + Unsigned + + + choice_list_8efb0c2d + Parallel_Multiplier + Constant_Coefficient_Multiplier + + + choice_list_a8a38fa5 + Use_LUTs + Use_Mults + + + choice_list_ae2447ac + -1 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + + + choice_list_e025b2e6 + SCLR_Overrides_CE + CE_Overrides_SCLR + + + choice_pairs_1f05ab61 + Area + Speed + + + Multiplication is a fundamental DSP operation. This core allows parallel and constant-coefficient multipliers to be generated. The user can specify if DSP48 Slices, LUTs or a combination of resources should be utilized. + + + InternalUser + 0 + + + + true + + + + + + Component_Name + int_mul_unsigned + + + MultType + Parallel_Multiplier + + + + true + + + + + + PortAType + Unsigned + + + + true + + + + + + PortAWidth + 64 + + + + true + + + + + + PortBType + Unsigned + + + + true + + + + + + PortBWidth + 64 + + + + true + + + + + + ConstValue + 129 + + + + false + + + + + + CcmImp + Distributed_Memory + + + + true + + + + + + Multiplier_Construction + Use_Mults + + + + true + + + + + + OptGoal + Speed + + + + false + + + + + + Use_Custom_Output_Width + false + + + + true + + + + + + OutputWidthHigh + 127 + + + + false + + + + + + OutputWidthLow + 0 + + + + false + + + + + + UseRounding + false + + + + false + + + + + + RoundPoint + 0 + + + + false + + + + + + PipeStages + 2 + + + + true + + + + + + ClockEnable + false + + + + true + + + + + + SyncClear + false + + + + true + + + + + + SclrCePriority + SCLR_Overrides_CE + + + + false + + + + + + ZeroDetect + false + + + + true + + + + + + + + Multiplier + 13 + + + + + + + + + + + + 2017.4 + + + + + + + +