diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
index ffea7f1..eb856e4 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -207,7 +207,7 @@ function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot,
         end
         case (rot.ppc_vaddr_csrData) matches
             tagged VAddr .vaddr: begin
-                addr = getAddr(vaddr);
+                addr = vaddr;
                 case (rot.lsqTag) matches
                     tagged Ld .l: rmask = rot.traceBundle.memByteEn;
                     tagged St .s: begin
@@ -652,7 +652,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
             vaddr = getAddr(x.pc);
         end
         else if(x.ppc_vaddr_csrData matches tagged VAddr .va) begin
-            vaddr = getAddr(va);
+            vaddr = va;
         end
         let commitTrap_val = Valid (CommitTrap {
             trap: trap,
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index 073a1fd..bc615ed 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -178,7 +178,7 @@ interface MemExeInput;
     // ROB
     method CapMem rob_getPC(InstTag t);
     method Action rob_setExecuted_doFinishMem(InstTag t,
-                                              CapMem vaddr,
+                                              Addr vaddr,
                                               Data store_data, ByteEn store_data_BE,
                                               Bool access_at_commit, Bool non_mmio_st_done
 `ifdef RVFI
@@ -603,7 +603,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         if (x.capException matches tagged Valid .c) cause = Valid(CapException(c));
         Bool access_at_commit = !isValid(cause) && (isMMIO || isLrScAmo);
         Bool non_mmio_st_done = !isValid(cause) && !isMMIO && x.mem_func == St;
-        inIfc.rob_setExecuted_doFinishMem(x.tag, cast(x.vaddr), store_data, store_data_BE,
+        inIfc.rob_setExecuted_doFinishMem(x.tag, getAddr(x.vaddr), store_data, store_data_BE,
                                           access_at_commit, non_mmio_st_done
 `ifdef RVFI
                                           , ExtraTraceBundle{
diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
index 89dad0e..7e36b06 100755
--- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
@@ -62,7 +62,7 @@ import Cur_Cycle :: *;
 // vaddr is only used by mem inst in page fault
 typedef union tagged {
     CapMem PPC; // at default store ppc
-    CapMem VAddr; // for mem inst, store vaddr
+    Addr   VAddr; // for mem inst, store vaddr
     CapMem CSRData; // for Csr inst, store csr_data
 } PPCVAddrCSRData deriving(Bits, FShow);
 
@@ -169,7 +169,7 @@ interface ReorderBufferRowEhr#(numeric type aluExeNum, numeric type fpuMulDivExe
     // perform), and non-MMIO St can become Executed (NOTE faulting
     // instructions are not Executed, they are set at deqLSQ time)
 
-    method Action setExecuted_doFinishMem(CapMem vaddr,
+    method Action setExecuted_doFinishMem(Addr vaddr,
                                           Data store_data, ByteEn store_data_BE,
                                           Bool access_at_commit, Bool non_mmio_st_done
 `ifdef RVFI
@@ -362,9 +362,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
 
     interface setExecuted_doFinishFpuMulDiv = fpuMulDivExe;
 
-    method Action setExecuted_doFinishMem(CapMem vaddr,
-                                          Data   store_data, ByteEn store_data_BE,
-                                          Bool   access_at_commit, Bool non_mmio_st_done
+    method Action setExecuted_doFinishMem(Addr vaddr,
+                                          Data store_data, ByteEn store_data_BE,
+                                          Bool access_at_commit, Bool non_mmio_st_done
 `ifdef RVFI
                                           , ExtraTraceBundle tb
 `endif
@@ -625,7 +625,7 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum
     interface Vector#(fpuMulDivExeNum, ROB_setExecuted_doFinishFpuMulDiv) setExecuted_doFinishFpuMulDiv;
     // doFinishMem, after addr translation
     method Action setExecuted_doFinishMem(InstTag x,
-                                          CapMem vaddr,
+                                          Addr vaddr,
                                           Data store_data, ByteEn store_data_BE,
                                           Bool access_at_commit, Bool non_mmio_st_done
 `ifdef RVFI
@@ -1248,7 +1248,7 @@ module mkSupReorderBuffer#(
     interface setExecuted_doFinishFpuMulDiv = fpuMulDivSetExeIfc;
 
     method Action setExecuted_doFinishMem(
-        InstTag x, CapMem vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit,
+        InstTag x, Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit,
         Bool non_mmio_st_done
 `ifdef RVFI
         , tb