From 9ec9b343765ea6707f8856013a35ea7c1e376c82 Mon Sep 17 00:00:00 2001 From: jon Date: Sat, 6 Jun 2020 09:42:11 +0100 Subject: [PATCH] Don't overwrite earlier exception in Execute. --- src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index ba1a4a0..7c9f08f 100755 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -305,7 +305,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p else begin ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= PPC (cast(cf.nextPc)); end - if (cause matches tagged Valid .exp) begin + if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishAlu_port(i)])) begin trap[trap_finishAlu_port(i)] <= Valid (CapException (exp)); tval[trap_finishAlu_port(i)] <= tval[trap_finishAlu_port(i)]; end @@ -333,7 +333,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p rg_dst_data <= nullWithAddr(dst_data); // update fflags fflags[fflags_finishFpuMulDiv_port(i)] <= new_fflags; - if (cause matches tagged Valid .exp) begin + if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishFpuMulDiv_port(i)])) begin trap[trap_finishFpuMulDiv_port(i)] <= Valid (Exception (exp)); tval[trap_finishFpuMulDiv_port(i)] <= tval[trap_finishAlu_port(i)]; end