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Added verbosity guards around $displays to dial down log verbosity

Browse Source 
To get the instruction trace back, set verbosity to 1 in CommitStage.bsv.
Regressions: RV64ADFIMSU_Tooba_verilator: 199/227 PASS (1 test hangs)
This commit is contained in:
rsnikhil
2019-04-01 20:35:52 -04:00
parent 4e305ac98d
commit 9f94c9176e
64 changed files with 128077 additions and 235362 deletions
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2
src_Core/CPU/Core.bsv
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@@ -151,7 +151,7 @@ endinterface
(* synthesize *)
module mkCore#(CoreId coreId)(Core);
let verbose = True;
let verbose = False;
Reg#(Bool) outOfReset <- mkReg(False);
rule rl_outOfReset if (!outOfReset);
$fwrite(stderr, "mkProc came out of reset\n");

2
src_Core/CPU/LLC_AXI4_Adapter.bsv
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@@ -52,7 +52,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
Add#(SizeOf#(Line), 0, 512)); // assert Line sz = 512
// Verbosity: 0: quiet; 1: LLC transactions; 2: loop detail
Integer verbosity = 2;
Integer verbosity = 0;
Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
// ================================================================

2
src_Core/CPU/MMIOPlatform.bsv
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@@ -238,7 +238,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
provisos (Bits #(Data, 64)); // this module assumes Data is 64-bit wide
Integer verbosity = 1;
Integer verbosity = 0;
// mtimecmp
Vector#(CoreNum, Reg#(Data)) mtimecmp <- replicateM(mkReg(0));

2
src_Core/CPU/MMIO_AXI4_Adapter.bsv
View File

@@ -47,7 +47,7 @@ endinterface
module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// Verbosity: 0: quiet; 1: transactions
Integer verbosity = 2;
Integer verbosity = 0;
Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
// ================================================================

4
src_Core/RISCY_OOO/coherence/src/CrossBar.bsv
View File

@@ -47,6 +47,8 @@ module mkXBar#(
Bits#(dstDataT, _dstDataSz),
FShow#(dstDataT)
);
Bool verbose = False;
// proposed data transfer by each src
Vector#(srcNum, Ehr#(2, Maybe#(dstIdxT))) propDstIdx <- replicateM(mkEhr(Invalid));
Vector#(srcNum, Ehr#(2, dstDataT)) propDstData <- replicateM(mkEhr(?));
@@ -116,6 +118,7 @@ module mkXBar#(
for(Integer i = 0; i < valueOf(srcNum); i = i+1) begin
if(isDeqSrc(fromInteger(i))) begin
propDstIdx[i][1] <= Invalid;
if (verbose)
$display("%t XBar %m: deq src %d", $time, i);
doAssert(isValid(propDstIdx[i][1]), "src must be proposing");
end
@@ -130,6 +133,7 @@ module mkXBar#(
rule doEnq(enqDst[i][1] matches tagged Valid .d);
dstIfc[i].put(d);
enqDst[i][1] <= Invalid; // reset enq command
if (verbose)
$display("%t XBAR %m: enq dst %d ; ", $time, i, fshow(d));
endrule
end

28
src_Core/RISCY_OOO/coherence/src/IBank.bsv
View File

@@ -121,6 +121,8 @@ module mkIBank#(
Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)
);
Bool verbose = False;
ICRqMshr#(cRqNum, wayT, tagT, procRqT, resultT) cRqMshr <- mkICRqMshrLocal;
IPRqMshr#(pRqNum) pRqMshr <- mkIPRqMshrLocal;
@@ -216,6 +218,7 @@ module mkIBank#(
// performance counter: cRq type
incrReqCnt;
`endif
if (verbose)
$display("%t I %m cRqTransfer: ", $time,
fshow(n), " ; ",
fshow(r)
@@ -232,6 +235,7 @@ module mkIBank#(
addr: req.addr,
mshrIdx: n
}));
if (verbose)
$display("%t I %m pRqTransfer: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -248,6 +252,7 @@ module mkIBank#(
data: resp.data,
way: resp.id
}));
if (verbose)
$display("%t I %m pRsTransfer: ", $time, fshow(resp));
doAssert(resp.toState == S && isValid(resp.data), "I$ must upgrade to S with data");
endrule
@@ -286,6 +291,7 @@ module mkIBank#(
flushReqDone <= True;
end
end
if (verbose)
$display("%t I %m flushTransfer: ", $time, fshow(n), " ; ",
fshow(flushIndex), " ; ", fshow(flushWay));
endrule
@@ -307,6 +313,7 @@ module mkIBank#(
// req parent for upgrade now
// (prevent parent resp from coming to release MSHR entry before replace resp is sent)
rqToPIndexQ_sendRsToP.enq(n);
if (verbose)
$display("%t I %m sendRsToP: ", $time,
fshow(rsToPIndexQ.first)," ; ",
fshow(req), " ; ",
@@ -327,6 +334,7 @@ module mkIBank#(
};
rsToPQ.enq(resp);
pRqMshr.sendRsToP_pRq.releaseEntry(n); // mshr entry released
if (verbose)
$display("%t I %m sendRsToP: ", $time,
fshow(rsToPIndexQ.first), " ; ",
fshow(req), " ; ",
@@ -349,6 +357,7 @@ module mkIBank#(
child: ?
};
rqToPQ.enq(cRqToP);
if (verbose)
$display("%t I %m sendRqToP: ", $time,
fshow(n), " ; ",
fshow(req), " ; ",
@@ -405,6 +414,7 @@ module mkIBank#(
// function to process cRq hit (MSHR slot may have garbage)
function Action cRqHit(cRqIdxT n, procRqT req);
action
if (verbose)
$display("%t I %m pipelineResp: Hit func: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -431,6 +441,7 @@ module mkIBank#(
let instResult = readInst(ram.line, req.addr);
cRqMshr.pipelineResp.setResult(n, instResult);
cRqMshr.pipelineResp.setStateSlot(n, Done, ?);
if (verbose)
$display("%t I %m pipelineResp: Hit func: update ram: ", $time,
fshow(succ), " ; ", fshow(instResult)
);
@@ -445,9 +456,11 @@ module mkIBank#(
endfunction
rule pipelineResp_cRq(pipeOut.cmd matches tagged L1CRq .n);
if (verbose)
$display("%t I %m pipelineResp: ", $time, fshow(pipeOut));
procRqT procRq = pipeOutCRq;
if (verbose)
$display("%t I %m pipelineResp: cRq: ", $time, fshow(n), " ; ", fshow(procRq));
// find end of dependency chain
@@ -532,6 +545,7 @@ module mkIBank#(
doAssert(isValid(cRqEOC), "cRq hit on another cRq, cRqEOC must be true");
cRqMshr.pipelineResp.setSucc(fromMaybe(?, cRqEOC), Valid (n));
cRqSetDepNoCacheChange;
if (verbose)
$display("%t I %m pipelineResp: cRq: own by other cRq ", $time,
fshow(cOwner), ", depend on cRq ", fshow(cRqEOC)
);
@@ -543,6 +557,7 @@ module mkIBank#(
"cRq swapped in by previous cRq, tag must match & cs = S"
);
// Hit
if (verbose)
$display("%t I %m pipelineResp: cRq: own by itself, hit", $time);
cRqHit(n, procRq);
end
@@ -551,6 +566,7 @@ module mkIBank#(
// cache has no owner, cRq must just go through tag match
// check for cRqEOC to append to dependency chain
if(cRqEOC matches tagged Valid .k) begin
if (verbose)
$display("%t I %m pipelineResp: cRq: no owner, depend on cRq ", $time, fshow(k));
cRqMshr.pipelineResp.setSucc(k, Valid (n));
cRqSetDepNoCacheChange;
@@ -558,15 +574,18 @@ module mkIBank#(
else if(ram.info.cs == I || ram.info.tag == getTag(procRq.addr)) begin
// No Replacement necessary
if(ram.info.cs > I) begin
if (verbose)
$display("%t I %m pipelineResp: cRq: no owner, hit", $time);
cRqHit(n, procRq);
end
else begin
if (verbose)
$display("%t I %m pipelineResp: cRq: no owner, miss no replace", $time);
cRqMissNoReplacement;
end
end
else begin
if (verbose)
$display("%t I %m pipelineResp: cRq: no owner, replace", $time);
cRqReplacement;
end
@@ -574,8 +593,10 @@ module mkIBank#(
endrule
rule pipelineResp_pRs(pipeOut.cmd == L1PRs);
if (verbose) begin
$display("%t I %m pipelineResp: ", $time, fshow(pipeOut));
$display("%t I %m pipelineResp: pRs: ", $time);
end
if(ram.info.owner matches tagged Valid .cOwner) begin
procRqT procRq = pipeOutCRq;
@@ -595,6 +616,7 @@ module mkIBank#(
rule pipelineResp_pRq(pipeOut.cmd matches tagged L1PRq .n);
pRqFromPT pRq = pRqMshr.pipelineResp.getRq(n);
if (verbose)
$display("%t I %m pipelineResp: pRq: ", $time, fshow(n), " ; ", fshow(pRq));
doAssert(pRq.toState == I, "I$ pRq only downgrade to I");
@@ -605,12 +627,14 @@ module mkIBank#(
// pRq is always directly handled: either dropped or Done
if(pipeOut.pRqMiss) begin
if (verbose)
$display("%t I %m pipelineResp: pRq: drop", $time);
// pRq can be directly dropped, no successor (since just go through pipeline)
pRqMshr.pipelineResp.releaseEntry(n);
pipeline.deqWrite(Invalid, pipeOut.ram, False);
end
else begin
if (verbose)
$display("%t I %m pipelineResp: pRq: valid process", $time);
// should process pRq
doAssert(ram.info.cs == S && pRq.toState == I && ram.info.tag == getTag(pRq.addr),
@@ -644,6 +668,7 @@ module mkIBank#(
pipeOut.cmd matches tagged L1Flush .flush
);
pRqIdxT n = flush.mshrIdx;
if (verbose)
$display("%t I %m pipelineResp: flush: ", $time, fshow(flush));
// During flush, cRq MSHR is empty, so cache line cannot have owner
@@ -652,11 +677,13 @@ module mkIBank#(
// flush always goes through cache pipeline, and is directly handled
// here: either dropped or Done
if(ram.info.cs == I) begin
if (verbose)
$display("%t I %m pipelineResp: flush: drop", $time);
// flush can be directly dropped
pRqMshr.pipelineResp.releaseEntry(n);
end
else begin
if (verbose)
$display("%t I %m pipelineResp: flush: valid process", $time);
pRqMshr.pipelineResp.setDone(n);
rsToPIndexQ.enq(PRq (n));
@@ -724,6 +751,7 @@ module mkIBank#(
);
cRqIndexQ.deq;
cRqMshr.sendRsToC.releaseEntry(cRqIndexQ.first); // release MSHR entry
if (verbose)
$display("%t I %m sendRsToC: ", $time,
fshow(cRqIndexQ.first), " ; ",
fshow(inst)

3
src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv
View File

@@ -175,6 +175,8 @@ module mkICRqMshrSafe#(
Bits#(reqT, _reqSz),
Bits#(resultT, _resultTSz)
);
Bool verbose = False;
// EHR ports
// We put pipelineResp < transfer to cater for deq < enq of cache pipeline
Integer cRqTransfer_port = 2;
@@ -208,6 +210,7 @@ module mkICRqMshrSafe#(
initIdx <= initIdx + 1;
if(initIdx == fromInteger(valueOf(cRqNum) - 1)) begin
inited <= True;
if (verbose)
$display("%t ICRqMshrSafe %m: init empty entry done", $time);
end
endrule

3
src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv
View File

@@ -89,6 +89,8 @@ module mkIPRqMshrSafe(
) provisos(
Alias#(pRqIndexT, Bit#(TLog#(pRqNum)))
);
Bool verbose = False;
// EHR port
// We put pipelineResp < transfer to cater for deq < enq of cache pipeline
Integer pRqTransfer_port = 2;
@@ -114,6 +116,7 @@ module mkIPRqMshrSafe(
initIdx <= initIdx + 1;
if(initIdx == fromInteger(valueOf(pRqNum) - 1)) begin
inited <= True;
if (verbose)
$display("%t IPRqMshrSafe %m: init empty entry done", $time);
end
endrule

35
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
View File

@@ -134,6 +134,8 @@ module mkL1Bank#(
Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)
);
Bool verbose = False;
L1CRqMshr#(cRqNum, wayT, tagT, procRqT) cRqMshr <- mkL1CRqMshrLocal;
L1PRqMshr#(pRqNum) pRqMshr <- mkL1PRqMshrLocal;
@@ -241,6 +243,7 @@ module mkL1Bank#(
addr: req.addr,
mshrIdx: n
}));
if (verbose)
$display("%t L1 %m cRqTransfer_retry: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -262,6 +265,7 @@ module mkL1Bank#(
// performance counter: cRq type
incrReqCnt(r.op);
`endif
if (verbose)
$display("%t L1 %m cRqTransfer_new: ", $time,
fshow(n), " ; ",
fshow(r)
@@ -277,6 +281,7 @@ module mkL1Bank#(
addr: req.addr,
mshrIdx: n
}));
if (verbose)
$display("%t L1 %m pRqTransfer: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -292,6 +297,7 @@ module mkL1Bank#(
data: resp.data,
way: resp.id
}));
if (verbose)
$display("%t L1 %m pRsTransfer: ", $time, fshow(resp));
endrule
@@ -329,6 +335,7 @@ module mkL1Bank#(
flushReqDone <= True;
end
end
if (verbose)
$display("%t L1 %m flushTransfer: ", $time, fshow(n), " ; ",
fshow(flushIndex), " ; ", fshow(flushWay));
endrule
@@ -362,6 +369,7 @@ module mkL1Bank#(
});
// inform processor of line eviction
procResp.evict(getLineAddr(resp.addr));
if (verbose)
$display("%t L1 %m sendRsToP: ", $time,
fshow(rsToPIndexQ.first)," ; ",
fshow(req), " ; ",
@@ -384,6 +392,7 @@ module mkL1Bank#(
pRqMshr.sendRsToP_pRq.releaseEntry(n); // mshr entry released
// inform processor of line eviction
procResp.evict(getLineAddr(resp.addr));
if (verbose)
$display("%t L1 %m sendRsToP: ", $time,
fshow(rsToPIndexQ.first), " ; ",
fshow(req), " ; ",
@@ -405,6 +414,7 @@ module mkL1Bank#(
child: ?
};
rqToPQ.enq(cRqToP);
if (verbose)
$display("%t L1 %m sendRqToP: ", $time,
fshow(n), " ; ",
fshow(req), " ; ",
@@ -442,6 +452,7 @@ module mkL1Bank#(
// function to process cRq hit (MSHR slot may have garbage)
function Action cRqHit(cRqIdxT n, procRqT req);
action
if (verbose)
$display("%t L1 %m pipelineResp: Hit func: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -509,6 +520,7 @@ module mkL1Bank#(
},
line: newLine // write new data into cache
}, True); // hit, so update rep info
if (verbose)
$display("%t L1 %m pipelineResp: Hit func: update ram: ", $time,
fshow(newLine), " ; ",
fshow(succ)
@@ -522,6 +534,7 @@ module mkL1Bank#(
req: req,
succ: succ
});
if (verbose)
$display("%t L1 %m pipelineResp: Hit func: AMO process in next cycle", $time);
end
endaction
@@ -557,6 +570,7 @@ module mkL1Bank#(
line: newLine // write new data into cache
}, True); // hit, so update rep info
doAssert(req.toState == M, "AMO must req for M");
if (verbose)
$display("%t L1 %m processAmo: update ram: ", $time,
fshow(newLine), " ; ",
fshow(succ)
@@ -568,9 +582,11 @@ module mkL1Bank#(
endrule
rule pipelineResp_cRq(!isValid(processAmo) &&& pipeOut.cmd matches tagged L1CRq .n);
if (verbose)
$display("%t L1 %m pipelineResp: ", $time, fshow(pipeOut));
procRqT procRq = pipeOutCRq;
if (verbose)
$display("%t L1 %m pipelineResp: cRq: ", $time, fshow(n), " ; ", fshow(procRq));
// find end of dependency chain
@@ -602,6 +618,7 @@ module mkL1Bank#(
end
// release MSHR entry
cRqMshr.pipelineResp.releaseEntry(n);
if (verbose)
$display("%t L1 %m pipelineResp: Sc early fail func: ", $time,
fshow(resetOwner), " ; ",
fshow(succ)
@@ -705,6 +722,7 @@ module mkL1Bank#(
doAssert(isValid(cRqEOC), ("cRq hit on another cRq, cRqEOC must be true"));
cRqMshr.pipelineResp.setSucc(fromMaybe(?, cRqEOC), Valid (n));
cRqSetDepNoCacheChange;
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by other cRq ", $time,
fshow(cOwner), ", depend on cRq ", fshow(cRqEOC)
);
@@ -718,6 +736,7 @@ module mkL1Bank#(
);
// Hit or Miss (but no replacement)
if(enough_cs) begin
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by itself, hit", $time);
cRqHit(n, procRq);
end
@@ -725,12 +744,14 @@ module mkL1Bank#(
// Sc already fails, so we don't need to req parent. Since
// Sc is the owner of the line, we need to reset owner to
// Invalid.
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by itself, Sc early fails, ",
$time, fshow(linkAddr)
);
cRqScEarlyFail(True);
end
else begin
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by itself, miss no replace", $time);
cRqMissNoReplacement;
end
@@ -746,6 +767,7 @@ module mkL1Bank#(
// check for cRqEOC to append to dependency chain
// Only append to dep-chain if is in Init state
if(cRqEOC matches tagged Valid .k &&& cState == Init) begin
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, depend on cRq, ", $time,
fshow(cState), " ; ", fshow(cRqEOC)
);
@@ -757,6 +779,7 @@ module mkL1Bank#(
if(tag_match && enough_cs) begin
// Hit
doAssert(cs_valid, "hit, so cs must > I");
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, hit", $time);
cRqHit(n, procRq);
end
@@ -764,6 +787,7 @@ module mkL1Bank#(
// Sc already fails, so we don't need to req parent. Since
// there is no owner of the line, we can reset owner to
// Invalid.
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, Sc early fails, ",
$time, fshow(linkAddr)
);
@@ -771,10 +795,12 @@ module mkL1Bank#(
end
else if(cs_valid && !tag_match) begin
// Req parent, need replacement
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, replace", $time);
cRqReplacement;
end
else begin
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, miss no replace", $time);
// Req parent, no replacement needed
cRqMissNoReplacement;
@@ -784,8 +810,10 @@ module mkL1Bank#(
endrule
rule pipelineResp_pRs(!isValid(processAmo) &&& pipeOut.cmd == L1PRs);
if (verbose) begin
$display("%t L1 %m pipelineResp: ", $time, fshow(pipeOut));
$display("%t L1 %m pipelineResp: pRs: ", $time);
end
if(ram.info.owner matches tagged Valid .cOwner) begin
procRqT procRq = pipeOutCRq;
@@ -805,6 +833,7 @@ module mkL1Bank#(
rule pipelineResp_pRq(!isValid(processAmo) &&& pipeOut.cmd matches tagged L1PRq .n);
pRqFromPT pRq = pRqMshr.pipelineResp.getRq(n);
if (verbose)
$display("%t L1 %m pipelineResp: pRq: ", $time, fshow(n), " ; ", fshow(pRq));
// pRq is never in dependency chain, so it is never swapped in
@@ -812,6 +841,7 @@ module mkL1Bank#(
// and pRq is always directly handled: either dropped or Done
if(pipeOut.pRqMiss || ram.info.cs <= pRq.toState || ram.info.tag != getTag(pRq.addr)) begin
if (verbose)
$display("%t L1 %m pipelineResp: pRq: drop", $time);
// pRq can be directly dropped
// must go through tag match, no successor
@@ -829,6 +859,7 @@ module mkL1Bank#(
// must be the case the pRq overtakes cRq
L1CRqState cState = pipeOutCState;
cRqSlotT cSlot = pipeOutCSlot;
if (verbose)
$display("%t L1 %m pipelineResp: pRq: overtake cRq: ", $time,
fshow(cOwner), " ; ",
fshow(cRq), " ; ",
@@ -860,6 +891,7 @@ module mkL1Bank#(
});
end
else begin
if (verbose)
$display("%t L1 %m pipelineResp: pRq: valid process", $time);
// line must NOT be owned
doAssert(ram.info.owner == Invalid,
@@ -896,6 +928,7 @@ module mkL1Bank#(
pipeOut.cmd matches tagged L1Flush .flush
);
pRqIdxT n = flush.mshrIdx;
if (verbose)
$display("%t L1 %m pipelineResp: flush: ", $time, fshow(flush));
// During flush, cRq MSHR is empty, so cache line cannot have owner
@@ -904,11 +937,13 @@ module mkL1Bank#(
// flush always goes through cache pipeline, and is directly handled
// here: either dropped or Done
if(ram.info.cs == I) begin
if (verbose)
$display("%t L1 %m pipelineResp: flush: drop", $time);
// flush can be directly dropped
pRqMshr.pipelineResp.releaseEntry(n);
end
else begin
if (verbose)
$display("%t L1 %m pipelineResp: flush: valid process", $time);
pRqMshr.pipelineResp.setDone_setData(n, ram.info.cs == M ? Valid (ram.line) : Invalid);
rsToPIndexQ.enq(PRq (n));

3
src_Core/RISCY_OOO/coherence/src/L1CRqMshr.bsv
View File

@@ -184,6 +184,8 @@ module mkL1CRqMshrSafe#(
Alias#(tagT, Bit#(_tagSz)),
Bits#(reqT, _reqSz)
);
Bool verbose = False;
// EHR ports
// We put pipelineResp < transfer to cater for deq < enq of cache pipeline
Integer flush_port = 0; // flush port is read only
@@ -218,6 +220,7 @@ module mkL1CRqMshrSafe#(
initIdx <= initIdx + 1;
if(initIdx == fromInteger(valueOf(cRqNum) - 1)) begin
inited <= True;
if (verbose)
$display("%t L1CRqMshrSafe %m: init empty entry done", $time);
end
endrule

4
src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv
View File

@@ -92,6 +92,9 @@ module mkL1PRqMshrSafe(
) provisos(
Alias#(pRqIndexT, Bit#(TLog#(pRqNum)))
);
Bool verbose = False;
// EHR port
// We put pipelineResp < transfer to cater for deq < enq of cache pipeline
Integer sendRsToP_pRq_port = 0;
@@ -121,6 +124,7 @@ module mkL1PRqMshrSafe(
initIdx <= initIdx + 1;
if(initIdx == fromInteger(valueOf(pRqNum) - 1)) begin
inited <= True;
if (verbose)
$display("%t L1PRqMshrSafe %m: init empty entry done", $time);
end
endrule

4
src_Core/RISCY_OOO/coherence/src/L1Pipe.bsv
View File

@@ -169,6 +169,9 @@ module mkL1Pipe(
Add#(indexSz, a__, AddrSz),
Add#(tagSz, b__, AddrSz)
);
Bool verbose = False;
// RAMs
Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCore);
RWBramCore#(indexT, repT) repRam <- mkRandRepRam;
@@ -227,6 +230,7 @@ module mkL1Pipe(
return actionvalue
function tagT getTag(Addr a) = truncateLSB(a);
if (verbose)
$display("%t L1 %m tagMatch: ", $time,
fshow(cmd), " ; ",
fshow(getTag(getAddrFromCmd(cmd))),

39
src_Core/RISCY_OOO/coherence/src/LLBank.bsv
View File

@@ -165,6 +165,8 @@ module mkLLBank#(
Add#(cRqNum, b__, wayNum)
);
Bool verbose = False;
LLCRqMshr#(cRqNum, wayT, tagT, Vector#(childNum, DirPend), cRqT) cRqMshr <- mkLLMshr;
LLPipe#(lgBankNum, childNum, wayNum, indexT, tagT, cRqIndexT) pipeline <- mkLLPipeline;
@@ -300,6 +302,7 @@ module mkLLBank#(
addr: req.addr,
mshrIdx: n
}));
if (verbose)
$display("%t LL %m cRqTransfer_retry: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -357,6 +360,7 @@ module mkLLBank#(
}));
// change round robin
flipPriorNewCRqSrc;
if (verbose)
$display("%t LL %m cRqTransfer_new_child: ", $time,
fshow(n), " ; ",
fshow(r), " ; ",
@@ -408,6 +412,7 @@ module mkLLBank#(
}));
// change round robin
flipPriorNewCRqSrc;
if (verbose)
$display("%t LL %m cRqTransfer_new_dma: ", $time,
fshow(n), " ; ",
fshow(r), " ; ",
@@ -452,6 +457,7 @@ module mkLLBank#(
rsFromCQ.deq;
cRsFromCT cRs = rsFromCQ.first;
pipeline.send(CRs (cRs));
if (verbose)
$display("%t LL %m cRsTransfer: ", $time, fshow(cRs));
`ifdef PERF_COUNT
if(doStats) begin
@@ -490,6 +496,7 @@ module mkLLBank#(
data: respData,
way: cSlot.way
}));
if (verbose)
$display("%t LL %m mRsTransfer: ", $time,
fshow(mRs), " ; ",
fshow(cRq), " ; ",
@@ -505,6 +512,7 @@ module mkLLBank#(
rule mRsDeq_nonRefill(!rsFromMQ.first.id.refill);
rsFromMQ.deq;
memRsT mRs = rsFromMQ.first;
if (verbose)
$display("%t LL %m mRsDeq_nonRefill: ", $time, fshow(mRs));
// save data into cRq mshr & send to DMA resp IndexQ
cRqMshr.mRsDeq.setData(mRs.id.mshrIdx, Valid (mRs.data));
@@ -525,6 +533,7 @@ module mkLLBank#(
cRqT cRq = cRqMshr.sendToM.getRq(n);
cRqSlotT cSlot = cRqMshr.sendToM.getSlot(n);
Maybe#(Line) data = cRqMshr.sendToM.getData(n);
if (verbose)
$display("%t LL %m sendToM: ", $time,
fshow(toMInfoQ.first), " ; ",
fshow(cRq), " ; ",
@@ -546,6 +555,7 @@ module mkLLBank#(
});
toMQ.enq(msg);
toMInfoQ.deq; // deq info
if (verbose)
$display("%t LL %m sendToM: load only: ", $time, fshow(msg));
doAssert(!isValid(data), "cannot have data");
doAssert(!doLdAfterReplace, "doLdAfterReplace should be false");
@@ -570,6 +580,7 @@ module mkLLBank#(
toMInfoQ.deq; // deq info
// dma write can be resp (i.e. mshr entry can be released)
rsStToDmaIndexQ_sendToM.enq(n);
if (verbose)
$display("%t LL %m sendToM: dma write: ", $time, fshow(msg));
doAssert(isRqFromDma(cRq.id), "must be dma write");
doAssert(isValid(data), "dma write must have data");
@@ -593,6 +604,7 @@ module mkLLBank#(
// whole thing is done, reset bit and deq info
toMInfoQ.deq;
doLdAfterReplace <= False;
if (verbose)
$display("%t LL %m sendToM: rep then ld: ld: ", $time, fshow(msg));
`ifdef PERF_COUNT
// performance counter: start miss timer
@@ -608,6 +620,7 @@ module mkLLBank#(
toMQ.enq(msg);
// don't deq info, do ld next time
doLdAfterReplace <= True;
if (verbose)
$display("%t LL %m sendToM: rep then ld: rep: ", $time, fshow(msg));
end
doAssert(isRqFromC(cRq.id), "must be child req");
@@ -624,6 +637,7 @@ module mkLLBank#(
cRqIndexT n = rsLdToDmaIndexQ.first;
cRqT cRq = cRqMshr.sendRsToDmaC.getRq(n);
Maybe#(Line) data = cRqMshr.sendRsToDmaC.getData(n);
if (verbose)
$display("%t LL %m sendRsToDma: Ld: ", $time,
fshow(n), " ; ",
fshow(cRq), " ; ",
@@ -648,6 +662,7 @@ module mkLLBank#(
rsStToDmaIndexQ.deq;
cRqIndexT n = rsStToDmaIndexQ.first;
cRqT cRq = cRqMshr.sendRsToDmaC.getRq(n);
if (verbose)
$display("%t LL %m sendRsToDma: St: ", $time,
fshow(n), " ; ",
fshow(cRq)
@@ -671,6 +686,7 @@ module mkLLBank#(
Msi toState = rsToCIndexQ.first.toState;
cRqT cRq = cRqMshr.sendRsToDmaC.getRq(n);
Maybe#(Line) rsData = cRqMshr.sendRsToDmaC.getData(n);
if (verbose)
$display("%t LL %m sendRsToC: ", $time,
fshow(n), " ; ",
fshow(cRq), " ; ",
@@ -777,6 +793,7 @@ module mkLLBank#(
waitP: cSlot.waitP,
dirPend: newDirPend
});
if (verbose)
$display("%t LL %m sendRqToC: ", $time,
fshow(n), " ; ",
fshow(cRq), " ; ",
@@ -810,6 +827,7 @@ module mkLLBank#(
// function to process cRq hit (MSHR slot may have garbage)
function Action cRqFromCHit(cRqIndexT n, cRqT cRq, Bool isMRs);
action
if (verbose)
$display("%t LL %m pipelineResp: cRq from child Hit func: ", $time,
fshow(n), " ; ",
fshow(cRq)
@@ -867,6 +885,7 @@ module mkLLBank#(
// function to process DMA req hit (MSHR slot may have garbage)
function Action cRqFromDmaHit(cRqIndexT n, cRqT cRq);
action
if (verbose)
$display("%t LL %m pipelineResp: cRq from dma Hit func: ", $time,
fshow(n), " ; ",
fshow(cRq)
@@ -973,10 +992,12 @@ module mkLLBank#(
// handle cRq
rule pipelineResp_cRq(pipeOut.cmd matches tagged LLCRq .n);
if (verbose)
$display("%t LL %m pipelineResp: ", $time, fshow(pipeOut));
// cs and dir in ram have been merged with modification caused by mRs/cRs cmd
cRqT cRq = pipeOutCRq;
if (verbose)
$display("%t LL %m pipelineResp: cRq: ", $time, fshow(n), " ; ", fshow(cRq));
// find end of dependency chain
@@ -1147,6 +1168,7 @@ module mkLLBank#(
// add to same addr dependency
cRqMshr.pipelineResp.setAddrSucc(m, Valid (n));
cRqSetDepNoCacheChange;
if (verbose)
$display("%t LL %m pipelineResp: cRq: own by other cRq, same addr dep: ", $time,
fshow(cOwner), " ; ", fshow(cRqEOC)
);
@@ -1156,6 +1178,7 @@ module mkLLBank#(
// add to rep dependency
cRqMshr.pipelineResp.setRepSucc(cOwner.mshrIdx, Valid (n));
cRqSetDepNoCacheChange;
if (verbose)
$display("%t LL %m pipelineResp: cRq: own by other cRq, rep dep: ", $time,
fshow(cOwner)
);
@@ -1177,10 +1200,12 @@ module mkLLBank#(
// req from child, get dir pend
Vector#(childNum, DirPend) dirPend = getDirPendNonCompatForChild;
if(dirPend == replicate(Invalid)) begin
if (verbose)
$display("%t LL %m pipelineResp: cRq from child: own by itself, hit", $time);
cRqFromCHit(n, cRq, False);
end
else begin
if (verbose)
$display("%t LL %m pipelineResp: cRq from child: own by itself, miss no replace: ", $time,
fshow(dirPend)
);
@@ -1191,10 +1216,12 @@ module mkLLBank#(
// req from DMA, get dir pend
Vector#(childNum, DirPend) dirPend = getDirPendNonCompatForDma;
if(dirPend == replicate(Invalid)) begin
if (verbose)
$display("%t LL %m pipelineResp: cRq from dma: own by itself, hit", $time);
cRqFromDmaHit(n, cRq);
end
else begin
if (verbose)
$display("%t LL %m pipelineResp: cRq from dma: own by itself, miss by children: ", $time);
cRqFromDmaMissByChildren(dirPend);
end
@@ -1210,6 +1237,7 @@ module mkLLBank#(
// only check for cRqEOC to append to dependency chain when firt time go through tag match
if(cRqEOC matches tagged Valid .m &&& cState == Init) begin
if (verbose)
$display("%t LL %m pipelineResp: cRq: no owner, depend on cRq ", $time,
fshow(cState), " ; ",
fshow(cRqEOC)
@@ -1225,10 +1253,12 @@ module mkLLBank#(
// No Replacement necessary, check dir
Vector#(childNum, DirPend) dirPend = getDirPendNonCompatForChild;
if(ram.info.cs > I && dirPend == replicate(Invalid)) begin
if (verbose)
$display("%t LL %m pipelineResp: cRq: no owner, hit", $time);
cRqFromCHit(n, cRq, False);
end
else begin
if (verbose)
$display("%t LL %m pipelineResp: cRq: no owner, miss no replace: ", $time,
fshow(dirPend)
);
@@ -1238,6 +1268,7 @@ module mkLLBank#(
else begin
// need replacement, check dir
Vector#(childNum, DirPend) dirPend = getDirPendNonI;
if (verbose)
$display("%t LL %m pipelineResp: cRq: no owner, replace: ", $time,
fshow(dirPend)
);
@@ -1258,6 +1289,7 @@ module mkLLBank#(
end
else begin
// miss in LLC, so req mem and req is done!
if (verbose)
$display("%t LL %m pipelineResp: cRq from dma: no owner, miss req mem", $time);
toMInfoQ.enq(ToMemInfo {
mshrIdx: n,
@@ -1288,6 +1320,7 @@ module mkLLBank#(
// process cRq
cRqT cRq = pipeOutCRq;
cRqSlotT cSlot = pipeOutCSlot;
if (verbose)
$display("%t LL %m pipelineResp: mRs: ", $time,
fshow(cOwner), " ; ",
fshow(cRq), " ; ",
@@ -1313,6 +1346,7 @@ module mkLLBank#(
// cRs from child
// XXX CCPipe has already updated ram.info and ram.line properly,
// particularly for E->M case.
if (verbose)
$display("%t LL %m pipelineResp: cRs: ", $time, fshow(child));
// cs should be not I
doAssert(ram.info.cs > I, "cRs should hit on a line");
@@ -1321,6 +1355,7 @@ module mkLLBank#(
cRqT cRq = pipeOutCRq;
cRqSlotT cSlot = pipeOutCSlot;
LLCRqState cState = pipeOutCState;
if (verbose)
$display("%t LL %m pipelineResp: cRs: match cRq: ", $time,
fshow(cOwner), " ; ",
fshow(cRq), " ; ",
@@ -1345,6 +1380,7 @@ module mkLLBank#(
// replacement done, evict line
Maybe#(cRqIndexT) repSucc = pipeOutRepSucc;
cRqFromCEvict(cOwner.mshrIdx, cRq, repSucc);
if (verbose)
$display("%t LL %m pipelineResp: cRs: match cRq: replace done: ", $time,
fshow(repSucc)
);
@@ -1358,6 +1394,7 @@ module mkLLBank#(
waitP: cSlot.waitP,
dirPend: newDirPend
});
if (verbose)
$display("%t LL %m pipelineResp: cRs: match cRq: replace not done: ", $time,
fshow(newDirPend)
);
@@ -1382,6 +1419,7 @@ module mkLLBank#(
end
end
endcase
if (verbose)
$display("%t LL %m pipelineResp: cRs: match cRq: cRq in WaitSt: ", $time,
fshow(newDirPend)
);
@@ -1408,6 +1446,7 @@ module mkLLBank#(
end
else begin
// does not match any cRq, so just deq pipe & write ram
if (verbose)
$display("%t LL %m pipelineResp: cRs: no owner: ", $time);
pipeline.deqWrite(Invalid, ram, False);
end

4
src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv
View File

@@ -205,6 +205,9 @@ module mkLLCRqMshr#(
Bits#(dirPendT, _dirPendSz),
Bits#(reqT, _reqSz)
);
Bool verbose = False;
slotT slotInitVal = getLLCRqSlotInitVal(dirPendInitVal);
// logical ordering: sendToM < sendRqToC < sendRsToDma/C < mRsDeq < pipelineResp < transfer
@@ -247,6 +250,7 @@ module mkLLCRqMshr#(
initIdx <= initIdx + 1;
if(initIdx == fromInteger(valueOf(cRqNum) - 1)) begin
inited <= True;
if (verbose)
$display("%t LLCRqMshrSafe %m: init empty entry done", $time);
end
endrule

4
src_Core/RISCY_OOO/coherence/src/LLPipe.bsv
View File

@@ -145,6 +145,9 @@ module mkLLPipe(
Add#(indexSz, a__, AddrSz),
Add#(tagSz, b__, AddrSz)
);
Bool verbose = False;
// RAMs
Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCore);
RWBramCore#(indexT, repT) repRam <- mkRandRepRam;
@@ -199,6 +202,7 @@ module mkLLPipe(
return actionvalue
function tagT getTag(Addr a) = truncateLSB(a);
if (verbose)
$display("%t LL %m tagMatch: ", $time,
fshow(cmd), " ; ",
fshow(getTag(getAddrFromCmd(cmd))), " ; ",

20
src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
View File

@@ -118,6 +118,8 @@ module mkSelfInvIBank#(
Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)
);
Bool verbose = False;
ICRqMshr#(cRqNum, wayT, tagT, procRqT, resultT) cRqMshr <- mkICRqMshrLocal;
SelfInvIPipe#(lgBankNum, wayNum, indexT, tagT, cRqIdxT) pipeline <- mkIPipeline;
@@ -198,6 +200,7 @@ module mkSelfInvIBank#(
// performance counter: cRq type
incrReqCnt;
`endif
if (verbose)
$display("%t I %m cRqTransfer: ", $time,
fshow(n), " ; ",
fshow(r)
@@ -209,6 +212,7 @@ module mkSelfInvIBank#(
(* descending_urgency = "pRqTransfer, cRqTransfer" *)
rule pRqTransfer(fromPQ.first matches tagged PRq .req);
fromPQ.deq;
if (verbose)
$display("%t I %m pRqTransfer: ", $time, fshow(req));
doAssert(False, "should not have pRq");
endrule
@@ -223,6 +227,7 @@ module mkSelfInvIBank#(
data: resp.data,
way: resp.id
}));
if (verbose)
$display("%t I %m pRsTransfer: ", $time, fshow(resp));
doAssert(resp.toState == S && isValid(resp.data), "I$ must upgrade to S with data");
endrule
@@ -241,6 +246,7 @@ module mkSelfInvIBank#(
child: ?
};
rqToPQ.enq(cRqToP);
if (verbose)
$display("%t I %m sendRqToP: ", $time,
fshow(n), " ; ",
fshow(req), " ; ",
@@ -297,6 +303,7 @@ module mkSelfInvIBank#(
// function to process cRq hit (MSHR slot may have garbage)
function Action cRqHit(cRqIdxT n, procRqT req);
action
if (verbose)
$display("%t I %m pipelineResp: Hit func: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -323,6 +330,7 @@ module mkSelfInvIBank#(
let instResult = readInst(ram.line, req.addr);
cRqMshr.pipelineResp.setResult(n, instResult);
cRqMshr.pipelineResp.setStateSlot(n, Done, ?);
if (verbose)
$display("%t I %m pipelineResp: Hit func: update ram: ", $time,
fshow(succ), " ; ", fshow(instResult)
);
@@ -337,9 +345,11 @@ module mkSelfInvIBank#(
endfunction
rule pipelineResp_cRq(pipeOut.cmd matches tagged ICRq .n);
if (verbose)
$display("%t I %m pipelineResp: ", $time, fshow(pipeOut));
procRqT procRq = pipeOutCRq;
if (verbose)
$display("%t I %m pipelineResp: cRq: ", $time, fshow(n), " ; ", fshow(procRq));
// find end of dependency chain
@@ -398,6 +408,7 @@ module mkSelfInvIBank#(
doAssert(isValid(cRqEOC), "cRq hit on another cRq, cRqEOC must be true");
cRqMshr.pipelineResp.setSucc(fromMaybe(?, cRqEOC), Valid (n));
cRqSetDepNoCacheChange;
if (verbose)
$display("%t I %m pipelineResp: cRq: own by other cRq ", $time,
fshow(cOwner), ", depend on cRq ", fshow(cRqEOC)
);
@@ -410,6 +421,7 @@ module mkSelfInvIBank#(
"cRq swapped in by previous cRq, tag must match & cs = S"
);
// Hit
if (verbose)
$display("%t I %m pipelineResp: cRq: own by itself, hit", $time);
cRqHit(n, procRq);
end
@@ -418,16 +430,19 @@ module mkSelfInvIBank#(
// cache has no owner, cRq must just go through tag match
// check for cRqEOC to append to dependency chain
if(cRqEOC matches tagged Valid .k) begin
if (verbose)
$display("%t I %m pipelineResp: cRq: no owner, depend on cRq ", $time, fshow(k));
cRqMshr.pipelineResp.setSucc(k, Valid (n));
cRqSetDepNoCacheChange;
end
else if(ram.info.cs > I && ram.info.tag == getTag(procRq.addr)) begin
if (verbose)
$display("%t I %m pipelineResp: cRq: no owner, hit", $time);
cRqHit(n, procRq);
end
else begin
// can always sliently replace
if (verbose)
$display("%t I %m pipelineResp: cRq: no owner, miss no replace", $time);
cRqMissNoReplacement;
end
@@ -435,8 +450,10 @@ module mkSelfInvIBank#(
endrule
rule pipelineResp_pRs(pipeOut.cmd == IPRs);
if (verbose) begin
$display("%t I %m pipelineResp: ", $time, fshow(pipeOut));
$display("%t I %m pipelineResp: pRs: ", $time);
end
if(ram.info.owner matches tagged Valid .cOwner) begin
procRqT procRq = pipeOutCRq;
@@ -465,6 +482,7 @@ module mkSelfInvIBank#(
rule startReconcile(needReconcile && !waitReconcileDone && cRqMshrEmpty);
pipeline.reconcile;
waitReconcileDone <= True;
if (verbose)
$display("%t I %m startReconcile", $time);
`ifdef PERF_COUNT
if(doStats) begin
@@ -475,6 +493,7 @@ module mkSelfInvIBank#(
rule completeReconcile(needReconcile && waitReconcileDone && pipeline.reconcile_done);
needReconcile <= False;
waitReconcileDone <= False;
if (verbose)
$display("%t I %m completeReconcile", $time);
endrule
@@ -496,6 +515,7 @@ module mkSelfInvIBank#(
);
cRqIndexQ.deq;
cRqMshr.sendRsToC.releaseEntry(cRqIndexQ.first); // release MSHR entry
if (verbose)
$display("%t I %m sendRsToC: ", $time,
fshow(cRqIndexQ.first), " ; ",
fshow(inst)

4
src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv
View File

@@ -237,6 +237,8 @@ module mkSelfInvIPipe(
Add#(indexSz, a__, AddrSz),
Add#(tagSz, b__, AddrSz)
);
Bool verbose = False;
// info RAM
Vector#(wayNum, CacheInfoArray#(indexT, tagT, ownerT, otherT)) infoArray <- replicateM(mkCacheInfoArray);
function RWBramCore#(indexT, infoT) getInfoRam(Integer i) = infoArray[i].ram;
@@ -294,6 +296,7 @@ module mkSelfInvIPipe(
return actionvalue
function tagT getTag(Addr a) = truncateLSB(a);
if (verbose)
$display("%t L1 %m tagMatch: ", $time,
fshow(cmd), " ; ",
fshow(getTag(getAddrFromCmd(cmd))),
@@ -409,6 +412,7 @@ module mkSelfInvIPipe(
needReconcile <= False;
// conflict with deq
conflict_reconcile_deq.wset(?);
if (verbose)
$display("%t I %m doReconcile", $time);
endrule

32
src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
View File

@@ -161,6 +161,8 @@ module mkSelfInvL1Bank#(
Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)
);
Bool verbose = False;
L1CRqMshr#(cRqNum, wayT, tagT, procRqT) cRqMshr <- mkL1CRqMshrLocal;
L1PRqMshr#(pRqNum) pRqMshr <- mkL1PRqMshrLocal;
@@ -262,6 +264,7 @@ module mkSelfInvL1Bank#(
addr: req.addr,
mshrIdx: n
}));
if (verbose)
$display("%t L1 %m cRqTransfer_retry: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -283,6 +286,7 @@ module mkSelfInvL1Bank#(
// performance counter: cRq type
incrReqCnt(r.op);
`endif
if (verbose)
$display("%t L1 %m cRqTransfer_new: ", $time,
fshow(n), " ; ",
fshow(r)
@@ -298,6 +302,7 @@ module mkSelfInvL1Bank#(
addr: req.addr,
mshrIdx: n
}));
if (verbose)
$display("%t L1 %m pRqTransfer: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -315,6 +320,7 @@ module mkSelfInvL1Bank#(
data: resp.data,
way: resp.id
}));
if (verbose)
$display("%t L1 %m pRsTransfer: ", $time, fshow(resp));
// pRs must have data
doAssert(isValid(resp.data), "msut have data");
@@ -348,6 +354,7 @@ module mkSelfInvL1Bank#(
});
// inform processor of line eviction
procResp.evict(getLineAddr(resp.addr));
if (verbose)
$display("%t L1 %m sendRsToP: ", $time,
fshow(rsToPIndexQ.first)," ; ",
fshow(req), " ; ",
@@ -370,6 +377,7 @@ module mkSelfInvL1Bank#(
pRqMshr.sendRsToP_pRq.releaseEntry(n); // mshr entry released
// inform processor of line eviction
procResp.evict(getLineAddr(resp.addr));
if (verbose)
$display("%t L1 %m sendRsToP: ", $time,
fshow(rsToPIndexQ.first), " ; ",
fshow(req), " ; ",
@@ -392,6 +400,7 @@ module mkSelfInvL1Bank#(
child: ?
};
rqToPQ.enq(cRqToP);
if (verbose)
$display("%t L1 %m sendRqToP: ", $time,
fshow(n), " ; ",
fshow(req), " ; ",
@@ -430,6 +439,7 @@ module mkSelfInvL1Bank#(
// function to process cRq hit (MSHR slot may have garbage)
function Action cRqHit(cRqIdxT n, procRqT req, Bool pRsUpgrade);
action
if (verbose)
$display("%t L1 %m pipelineResp: Hit func: ", $time,
fshow(n), " ; ",
fshow(req)
@@ -514,6 +524,7 @@ module mkSelfInvL1Bank#(
},
line: newLine // write new data into cache
}, True); // hit, so update rep info
if (verbose)
$display("%t L1 %m pipelineResp: Hit func: update ram: ", $time,
fshow(newLine), " ; ",
fshow(succ), " ; ",
@@ -534,6 +545,7 @@ module mkSelfInvL1Bank#(
req: req,
succ: succ
});
if (verbose)
$display("%t L1 %m pipelineResp: Hit func: AMO process in next cycle", $time);
end
endaction
@@ -570,6 +582,7 @@ module mkSelfInvL1Bank#(
line: newLine // write new data into cache
}, True); // hit, so update rep info
doAssert(req.toState == M, "AMO must req for M");
if (verbose)
$display("%t L1 %m processAmo: update ram: ", $time,
fshow(newLine), " ; ",
fshow(succ)
@@ -581,9 +594,11 @@ module mkSelfInvL1Bank#(
endrule
rule pipelineResp_cRq(!isValid(processAmo) &&& pipeOut.cmd matches tagged L1CRq .n);
if (verbose)
$display("%t L1 %m pipelineResp: ", $time, fshow(pipeOut));
procRqT procRq = pipeOutCRq;
if (verbose)
$display("%t L1 %m pipelineResp: cRq: ", $time, fshow(n), " ; ", fshow(procRq));
// find end of dependency chain
@@ -615,6 +630,7 @@ module mkSelfInvL1Bank#(
end
// release MSHR entry
cRqMshr.pipelineResp.releaseEntry(n);
if (verbose)
$display("%t L1 %m pipelineResp: Sc early fail func: ", $time,
fshow(resetOwner), " ; ",
fshow(succ)
@@ -726,6 +742,7 @@ module mkSelfInvL1Bank#(
doAssert(isValid(cRqEOC), ("cRq hit on another cRq, cRqEOC must be true"));
cRqMshr.pipelineResp.setSucc(fromMaybe(?, cRqEOC), Valid (n));
cRqSetDepNoCacheChange;
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by other cRq ", $time,
fshow(cOwner), ", depend on cRq ", fshow(cRqEOC)
);
@@ -737,6 +754,7 @@ module mkSelfInvL1Bank#(
doAssert(tag_match, "cRq swapped in by previous cRq, tag must match");
// Hit or Miss (but no replacement)
if(enough_cs) begin
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by itself, hit", $time);
cRqHit(n, procRq, False);
end
@@ -744,12 +762,14 @@ module mkSelfInvL1Bank#(
// Sc already fails, so we don't need to req parent. Since
// Sc is the owner of the line, we need to reset owner to
// Invalid.
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by itself, Sc early fails, ",
$time, fshow(linkAddr)
);
cRqScEarlyFail(True);
end
else begin
if (verbose)
$display("%t L1 %m pipelineResp: cRq: own by itself, miss no replace", $time);
cRqMissNoReplacement;
end
@@ -765,6 +785,7 @@ module mkSelfInvL1Bank#(
// check for cRqEOC to append to dependency chain
// Only append to dep-chain if is in Init state
if(cRqEOC matches tagged Valid .k &&& cState == Init) begin
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, depend on cRq ", $time,
fshow(cState), " ; ", fshow(cRqEOC)
);
@@ -776,6 +797,7 @@ module mkSelfInvL1Bank#(
if(tag_match && enough_cs) begin
// Hit
doAssert(cs_valid, "hit, so cs must > I");
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, hit", $time);
cRqHit(n, procRq, False);
end
@@ -783,6 +805,7 @@ module mkSelfInvL1Bank#(
// Sc already fails, so we don't need to req parent. Since
// there is no owner of the line, we can reset owner to
// Invalid.
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, Sc early fails, ",
$time, fshow(linkAddr)
);
@@ -790,12 +813,14 @@ module mkSelfInvL1Bank#(
end
else if(cs_needs_evict && !tag_match) begin
// Req parent, need replacement
if (verbose)
$display("%t L1 %m pipelineResp: cRq: no owner, replace", $time);
cRqReplacement;
end
else begin
// Req parent, no Replacement necessary, we can silently replace S line
Bool silent_replace = ram.info.cs == S && !tag_match;
if (verbose)
$display("%t L1 %m pipelineResp: cRq: ",
"no owner, miss no replace, silent replace ",
$time, fshow(silent_replace));
@@ -806,8 +831,10 @@ module mkSelfInvL1Bank#(
endrule
rule pipelineResp_pRs(!isValid(processAmo) &&& pipeOut.cmd == L1PRs);
if (verbose) begin
$display("%t L1 %m pipelineResp: ", $time, fshow(pipeOut));
$display("%t L1 %m pipelineResp: pRs: ", $time);
end
if(ram.info.owner matches tagged Valid .cOwner) begin
procRqT procRq = pipeOutCRq;
@@ -827,6 +854,7 @@ module mkSelfInvL1Bank#(
rule pipelineResp_pRq(!isValid(processAmo) &&& pipeOut.cmd matches tagged L1PRq .n);
pRqFromPT pRq = pRqMshr.pipelineResp.getRq(n);
if (verbose)
$display("%t L1 %m pipelineResp: pRq: ", $time, fshow(n), " ; ", fshow(pRq));
// pRq is never in dependency chain, so it is never swapped in
@@ -839,6 +867,7 @@ module mkSelfInvL1Bank#(
doAssert(pRq.toState == S, "must downgrade to S");
if(pipeOut.pRqMiss || ram.info.cs <= pRq.toState || ram.info.tag != getTag(pRq.addr)) begin
if (verbose)
$display("%t L1 %m pipelineResp: pRq: drop", $time);
// pRq can be directly dropped
// must go through tag match, no successor
@@ -852,6 +881,7 @@ module mkSelfInvL1Bank#(
end
end
else begin
if (verbose)
$display("%t L1 %m pipelineResp: pRq: valid process", $time);
// line must NOT be owned
doAssert(ram.info.owner == Invalid,
@@ -905,6 +935,7 @@ module mkSelfInvL1Bank#(
rule startReconcile(needReconcile && !waitReconcileDone && cRqMshrEmpty);
pipeline.reconcile;
waitReconcileDone <= True;
if (verbose)
$display("%t L1 %m startReconcile", $time);
`ifdef PERF_COUNT
if(doStats) begin
@@ -915,6 +946,7 @@ module mkSelfInvL1Bank#(
rule completeReconcile(needReconcile && waitReconcileDone && pipeline.reconcile_done);
needReconcile <= False;
waitReconcileDone <= False;
if (verbose)
$display("%t L1 %m completeReconcile", $time);
endrule

5
src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv
View File

@@ -252,6 +252,9 @@ module mkSelfInvL1Pipe(
Add#(indexSz, a__, AddrSz),
Add#(tagSz, b__, AddrSz)
);
Bool verbose = False;
// info RAM
Vector#(wayNum, CacheInfoArray#(indexT, tagT, ownerT, otherT)) infoArray <- replicateM(mkCacheInfoArray);
function RWBramCore#(indexT, infoT) getInfoRam(Integer i) = infoArray[i].ram;
@@ -310,6 +313,7 @@ module mkSelfInvL1Pipe(
return actionvalue
function tagT getTag(Addr a) = truncateLSB(a);
if (verbose)
$display("%t L1 %m tagMatch: ", $time,
fshow(cmd), " ; ",
fshow(getTag(getAddrFromCmd(cmd))),
@@ -431,6 +435,7 @@ module mkSelfInvL1Pipe(
needReconcile <= False;
// conflict with deq
conflict_reconcile_deq.wset(?);
if (verbose)
$display("%t L1 %m doReconcile", $time);
endrule

4
src_Core/RISCY_OOO/coherence/src/SelfInvLLPipe.bsv
View File

@@ -144,6 +144,9 @@ module mkSelfInvLLPipe(
Add#(indexSz, a__, AddrSz),
Add#(tagSz, b__, AddrSz)
);
Bool verbose = False;
// RAMs
Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCore);
RWBramCore#(indexT, repT) repRam <- mkRandRepRam;
@@ -198,6 +201,7 @@ module mkSelfInvLLPipe(
return actionvalue
function tagT getTag(Addr a) = truncateLSB(a);
if (verbose)
$display("%t LL %m tagMatch: ", $time,
fshow(cmd), " ; ",
fshow(getTag(getAddrFromCmd(cmd))), " ; ",

2
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
View File

@@ -164,7 +164,7 @@ interface AluExePipeline;
endinterface
module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
Bool verbose = True;
Bool verbose = False;
// alu reservation station
ReservationStationAlu rsAlu <- mkReservationStationAlu;

12
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -123,7 +123,7 @@ typedef struct {
} CommitTrap deriving(Bits, Eq, FShow);
module mkCommitStage#(CommitInput inIfc)(CommitStage);
Bool verbose = True;
Integer verbosity = 0;
// func units
ReorderBufferSynth rob = inIfc.robIfc;
@@ -345,7 +345,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
);
rob.deqPort[0].deq;
let x = rob.deqPort[0].deq_data;
if(verbose) $display("[doCommitTrap] ", fshow(x));
if (verbosity > 0) $display("[doCommitTrap] ", fshow(x));
// record trap info
Addr vaddr = ?;
@@ -415,7 +415,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
);
rob.deqPort[0].deq;
let x = rob.deqPort[0].deq_data;
if(verbose) $display("[doCommitKilledLd] ", fshow(x));
if (verbosity > 1) $display("[doCommitKilledLd] ", fshow(x));
// kill everything, redirect, and increment epoch
inIfc.killAll;
@@ -451,7 +451,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
);
rob.deqPort[0].deq;
let x = rob.deqPort[0].deq_data;
if(verbose) $display("[doCommitSystemInst] ", fshow(x));
if (verbosity > 0) $display("[doCommitSystemInst] ", fshow(x));
// we claim a phy reg for every inst, so commit its renaming
regRenamingTable.commit[0].commit;
@@ -553,7 +553,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
);
let x = rob.deqPort[0].deq_data;
let inst_tag = rob.deqPort[0].getDeqInstTag;
if(verbose) $display("[notifyLSQCommit] ", fshow(x), "; ", fshow(inst_tag));
if (verbosity > 1) $display("[notifyLSQCommit] ", fshow(x), "; ", fshow(inst_tag));
// notify LSQ, and record in ROB that notification is done
setLSQAtCommit[0].wset(x.lsqTag);
@@ -605,7 +605,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
stop = True;
end
else begin
if (verbose) $display("[doCommitNormalInst - %d] ", i, fshow(inst_tag), " ; ", fshow(x));
if (verbosity > 0) $display("[doCommitNormalInst - %d] ", i, fshow(inst_tag), " ; ", fshow(x));
// inst can be committed, deq it
rob.deqPort[i].deq;

2
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
View File

@@ -138,7 +138,7 @@ module mkFetchStage(FetchStage);
// rule ordering: Fetch1 (BTB+TLB) < Fetch3 (decode & dir pred) < redirect method
// Fetch1 < Fetch3 to avoid bypassing path on PC and epochs
let verbose = True;
let verbose = False;
// Basic State Elements
Reg#(Bool) started <- mkReg(False);

2
src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
View File

@@ -112,7 +112,7 @@ interface FpuMulDivExePipeline;
endinterface
module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
Bool verbose = True;
Bool verbose = False;
// fpu mul div reservation station
ReservationStationFpuMulDiv rsFpuMulDiv <- mkReservationStationFpuMulDiv;

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -179,7 +179,7 @@ interface MemExePipeline;
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
Bool verbose = True;
Bool verbose = False;
// we change cache request in case of single core, becaues our MSI protocol
// is not good with single core

2
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
View File

@@ -86,7 +86,7 @@ interface RenameStage;
endinterface
module mkRenameStage#(RenameInput inIfc)(RenameStage);
Bool verbose = True;
Bool verbose = False;
// func units
FetchStage fetchStage = inIfc.fetchIfc;

2
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
View File

@@ -122,7 +122,7 @@ typedef union tagged {
module mkDTlb#(
function TlbReq getTlbReq(instT inst)
)(DTlb::DTlb#(instT)) provisos(Bits#(instT, a__));
Bool verbose = True;
Bool verbose = False;
// TLB array
DTlbArray tlb <- mkDTlbArray;

2
src_Core/RISCY_OOO/procs/lib/ITlb.bsv
View File

@@ -82,7 +82,7 @@ endmodule
(* synthesize *)
module mkITlb(ITlb::ITlb);
Bool verbose = True;
Bool verbose = False;
// TLB array
ITlbArray tlb <- mkITlbArray;

2
src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv
View File

@@ -121,7 +121,7 @@ typedef union tagged {
(* synthesize *)
module mkL2Tlb(L2Tlb::L2Tlb);
Bool verbose = True;
Bool verbose = False;
// set associative TLB for 4KB pages
L2SetAssocTlb tlb4KB <- mkL2SetAssocTlb;

2
src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv
View File

@@ -55,7 +55,7 @@ module mkLLCDmaConnect#(
)(Empty) provisos (
Alias#(dmaRqT, DmaRq#(LLCDmaReqId))
);
Bool verbose = True;
Bool verbose = False;
// helper functions for cross bar
function XBarDstInfo#(Bit#(0), Tuple2#(CoreId, TlbMemReq)) getTlbDst(CoreId core, TlbMemReq r);

4
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -436,6 +436,9 @@ module mkSupReorderBuffer#(
Add#(TExp#(TLog#(SupSize)), 0, SupSize), // require SupSize to be power of 2
Add#(1, a__, aluExeNum), Add#(1, b__, fpuMulDivExeNum)
);
Bool verbose = False;
// doCommit rule: deq < wrongSpec (overwrite deq in doCommit) < doRenaming rule: enq
Integer valid_deq_port = 0;
Integer valid_wrongSpec_port = 1;
@@ -665,6 +668,7 @@ module mkSupReorderBuffer#(
function Bool getDepOn(Integer i) = row[w][i].dependsOn_wrongSpec(specTag);
depVec[w] = map(getDepOn, genVector);
end
if (verbose)
$display("[ROB incorrectSpec] ",
fshow(specTag), " ; ",
fshow(killInstTag), " ; ",

4
src_Core/RISCY_OOO/procs/lib/ReservationStationEhr.bsv
View File

@@ -77,6 +77,9 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)(
Bits#(a, aSz), FShow#(a),
Add#(1, b__, size)
);
Bool verbose = False;
Integer valid_wrongSpec_port = 0;
Integer valid_dispatch_port = 0; // write valid
Integer valid_enq_port = 1; // write valid
@@ -213,6 +216,7 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)(
//endrule
method Action enq(ToReservationStation#(a) x) if (enqP matches tagged Valid .idx);
if (verbose)
$display(" [mkReservationStationRow::_write] ", fshow(x));
valid[idx][valid_enq_port] <= True;
data[idx] <= x.data;

2
src_Core/RISCY_OOO/procs/lib/SplitLSQ.bsv
View File

@@ -597,7 +597,7 @@ module mkSplitLSQ(SplitLSQ);
// request faults), we should first copy the MMIO request to a reg, and
// then kill using the info in reg.
Bool verbose = True;
Bool verbose = False;
// we may simplify things in case of single core
Bool multicore = valueof(CoreNum) > 1;