diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index a02320f..6be85e7 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -4018,7 +4018,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; - wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, + wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; wire MUX_commitStage_rg_serial_num$write_1__SEL_1, @@ -4074,20 +4074,14 @@ module mkCore(CLK, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fs_reg$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_1, - MUX_csrf_ie_vec_1$write_1__SEL_2, - MUX_csrf_ie_vec_1$write_1__VAL_1, + MUX_csrf_ie_vec_1$write_1__VAL_2, MUX_csrf_ie_vec_3$write_1__SEL_1, - MUX_csrf_ie_vec_3$write_1__SEL_2, - MUX_csrf_ie_vec_3$write_1__VAL_1, - MUX_csrf_mpp_reg$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__VAL_1, - MUX_csrf_prev_ie_vec_3$write_1__SEL_1, - MUX_csrf_prev_ie_vec_3$write_1__VAL_1, + MUX_csrf_ie_vec_3$write_1__VAL_2, + MUX_csrf_prev_ie_vec_1$write_1__VAL_2, + MUX_csrf_prev_ie_vec_3$write_1__VAL_2, MUX_csrf_prv_reg$write_1__SEL_1, MUX_csrf_software_int_pend_vec_3$write_1__VAL_2, - MUX_csrf_spp_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__VAL_1, + MUX_csrf_spp_reg$write_1__VAL_2, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_flush_reservation$write_1__SEL_1, @@ -4140,8 +4134,8 @@ module mkCore(CLK, reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q207, - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q208, + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q209, + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q210, CASE_guard17337_0b0_theResult___snd25273_BITS__ETC__q211, CASE_guard17337_0b0_theResult___snd25273_BITS__ETC__q212, CASE_guard37809_0b0_theResult___snd45721_BITS__ETC__q197, @@ -4156,8 +4150,8 @@ module mkCore(CLK, CASE_guard86425_0b0_sfdin94645_BITS_56_TO_5_0b_ETC__q216, CASE_guard95494_0b0_theResult___snd03430_BITS__ETC__q217, CASE_guard95494_0b0_theResult___snd03430_BITS__ETC__q218, - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q209, - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q210, + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q207, + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755, @@ -4226,7 +4220,7 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275, - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228, + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229, IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125; reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, @@ -4329,7 +4323,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828, x__h290394, x__h296164; @@ -4360,7 +4354,7 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, @@ -4374,14 +4368,14 @@ module mkCore(CLK, CASE_guard22920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, CASE_guard37809_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, CASE_guard37809_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119, + CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, CASE_guard42142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, CASE_guard47121_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, CASE_guard47121_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, CASE_guard50748_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, CASE_guard50748_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, CASE_guard50849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, - CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, + CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, CASE_guard56190_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, CASE_guard56190_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, CASE_guard59457_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, @@ -4403,7 +4397,7 @@ module mkCore(CLK, CASE_guard96447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, CASE_guard96447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, CASE_guard98956_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233, + CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -5920,7 +5914,7 @@ module mkCore(CLK, NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13952, NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007, NOT_regRenamingTable_rename_1_canRename__3637__ETC___d14065, - NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_RDY_ETC___d15025, + NOT_rob_deqPort_0_canDeq__4986_4987_OR_regRena_ETC___d15025, NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178, NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14778, NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14972, @@ -5991,7 +5985,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo28, + _dfoo26, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -6146,8 +6140,8 @@ module mkCore(CLK, csrf_prv_reg_read__2956_ULE_1___d14597, csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192, fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13541, + fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407, fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13607, - fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14155, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14097, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176, fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14295, @@ -6198,7 +6192,6 @@ module mkCore(CLK, next_deqP___1__h336866, r1__read_BIT_20___h662375, r__h619423, - regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407, regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14027, regRenamingTable_RDY_rename_1_getRename__4083__ETC___d14101, regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588, @@ -6218,6 +6211,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308, regRenamingTable_rename_1_canRename__3637_AND__ETC___d14392, regRenamingTable_rename_1_canRename__3637_AND__ETC___d14402, + rob_RDY_enqPort_1_enq__4147_AND_NOT_fetchStage_ETC___d14155, rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13831, rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13965, rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13982, @@ -9221,8 +9215,8 @@ module mkCore(CLK, // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_first && fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + fetchStage$RDY_iTlbIfc_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; @@ -9258,8 +9252,8 @@ module mkCore(CLK, // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - coreFix_memExe_dTlb$RDY_toParent_flush_response_put && fetchStage$RDY_iTlbIfc_toParent_flush_response_put && + coreFix_memExe_dTlb$RDY_toParent_flush_response_put && l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; @@ -9299,9 +9293,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9650,8 +9644,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && rob$deqPort_0_deq_data[18] ; @@ -9730,7 +9724,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_RDY_ETC___d15025 && + NOT_rob_deqPort_0_canDeq__4986_4987_OR_regRena_ETC___d15025 && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -10356,8 +10350,8 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; @@ -10653,9 +10647,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && @@ -10664,8 +10659,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10749,7 +10744,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -10974,27 +10970,15 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 ; - assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[257:253] == 5'd19 || rob$deqPort_0_deq_data[257:253] == 5'd20) ; - assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -11062,6 +11046,18 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = commitStage_rg_serial_num + y__h723317 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = (k__h674927 == 1'd0 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176) ? { fetchStage$pipelines_0_first[199:195], @@ -11087,18 +11083,6 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11412,7 +11396,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; endcase end - assign MUX_csrf_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd8 || @@ -11420,7 +11404,7 @@ module mkCore(CLK, 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; - assign MUX_csrf_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd18) ? @@ -11431,7 +11415,7 @@ module mkCore(CLK, n__read__h720223 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = n__read__h720223 + { 62'd0, x__h723542 } ; - assign MUX_csrf_mpp_reg$write_1__VAL_1 = + assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd18) ? @@ -11440,14 +11424,14 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__VAL_1 = commitStage_commitTrap[36] ? 64'd0 : trap_val__h709616 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != 6'd8 && IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != 6'd18 || @@ -11465,7 +11449,7 @@ module mkCore(CLK, (mmio_pRqQ_data_0[37:36] == 2'd2) ? mmio_pRqQ_data_0[0] : amoExec___d882[0] ; - assign MUX_csrf_spp_reg$write_1__VAL_1 = + assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd8 || @@ -12028,7 +12012,9 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd0 && @@ -12038,9 +12024,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd1 && @@ -12050,7 +12034,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd2 && @@ -12060,7 +12044,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd3 && @@ -12070,7 +12054,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd4 && @@ -12080,7 +12064,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd5 && @@ -12090,7 +12074,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd6 && @@ -12100,7 +12084,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7 && @@ -12157,7 +12141,12 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN ; + { !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT || + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 || + (EN_dCacheToParent_fromP_enq ? + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]), + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343 } ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 && NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && @@ -12166,12 +12155,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN = - { !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT || - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 || - (EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]), - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343 } ; + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 && NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && @@ -12338,15 +12322,6 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 ; - - // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN = { x_addr__h318727, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : @@ -12359,6 +12334,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ; + assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 && + NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 ; + + // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 + assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 && NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && @@ -12796,25 +12780,25 @@ module mkCore(CLK, // register csrf_ie_vec_1 assign csrf_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_1 ; + !MUX_csrf_ie_vec_1$write_1__SEL_1 && + MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 ; + csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_ie_vec_3 assign csrf_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_1 ; + !MUX_csrf_ie_vec_3$write_1__SEL_1 && + MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? cause_code__h708593 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = @@ -12827,7 +12811,7 @@ module mkCore(CLK, // register csrf_mcause_interrupt_reg assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = @@ -12893,7 +12877,7 @@ module mkCore(CLK, // register csrf_mepc_csr assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = @@ -12945,16 +12929,16 @@ module mkCore(CLK, // register csrf_mpp_reg assign csrf_mpp_reg$D_IN = - MUX_csrf_mpp_reg$write_1__SEL_1 ? - MUX_csrf_mpp_reg$write_1__VAL_1 : - csrf_prv_reg ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_prv_reg : + MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mprv_reg - assign csrf_mprv_reg$D_IN = csrf_mscratch_csr$D_IN[17] ; + assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ; assign csrf_mprv_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && @@ -12971,7 +12955,7 @@ module mkCore(CLK, // register csrf_mtval_csr assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = @@ -13028,23 +13012,23 @@ module mkCore(CLK, // register csrf_prev_ie_vec_1 assign csrf_prev_ie_vec_1$D_IN = - MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : - csrf_ie_vec_1 ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_ie_vec_1 : + MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 ; + csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prev_ie_vec_3 assign csrf_prev_ie_vec_3$D_IN = - MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_3$write_1__VAL_1 : - csrf_ie_vec_3 ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_ie_vec_3 : + MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_prv_reg assign csrf_prv_reg$D_IN = @@ -13099,9 +13083,9 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? cause_code__h708593 : - csrf_rg_tselect$D_IN[3:0] ; + csrf_rg_tdata3$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || @@ -13112,7 +13096,7 @@ module mkCore(CLK, // register csrf_scause_interrupt_reg assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_rg_tselect$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = @@ -13149,7 +13133,7 @@ module mkCore(CLK, // register csrf_sepc_csr assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = @@ -13207,13 +13191,13 @@ module mkCore(CLK, // register csrf_spp_reg assign csrf_spp_reg$D_IN = - MUX_csrf_spp_reg$write_1__SEL_1 ? - MUX_csrf_spp_reg$write_1__VAL_1 : - csrf_prv_reg[0] ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_prv_reg[0] : + MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 ; + csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; @@ -13229,7 +13213,7 @@ module mkCore(CLK, // register csrf_stval_csr assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = @@ -13883,9 +13867,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -22229,10 +22213,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14040 = IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14227 = @@ -22262,10 +22246,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14120 && IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13927 && (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14145 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14155) ; + rob_RDY_enqPort_1_enq__4147_AND_NOT_fetchStage_ETC___d14155) ; assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14441 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && @@ -23574,10 +23558,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || fetchStage_pipelines_1_first__2937_BIT_68_3665_ETC___d14063 ; - assign NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_RDY_ETC___d15025 = + assign NOT_rob_deqPort_0_canDeq__4986_4987_OR_regRena_ETC___d15025 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__4993_BIT_25_4994_4_ETC___d15022) ; @@ -23618,7 +23602,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd15 || rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14086 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13952 || @@ -24059,7 +24043,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14014 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 ; + CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14099 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -24711,7 +24695,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd18 || rob$deqPort_0_deq_data[257:253] == 5'd20 ; - assign _dfoo28 = + assign _dfoo26 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd8 || @@ -26301,7 +26285,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q210 : + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 ; assign _theResult___fst_sfd__h507676 = (_theResult___fst_exp__h506917 == 11'd2047) ? @@ -26312,7 +26296,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 ; assign _theResult___fst_sfd__h517327 = (_theResult___fst_exp__h516494 == 11'd2047) ? @@ -28222,9 +28206,9 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14783 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14778 ; @@ -28375,6 +28359,14 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 ; + assign fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13607 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && @@ -28382,12 +28374,6 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545 ; - assign fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14155 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14151) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14097 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -28580,7 +28566,7 @@ module mkCore(CLK, IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545 ; assign fetchStage_pipelines_1_first__2937_BIT_173_369_ETC___d13775 = { fetchStage$pipelines_1_first[173], - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 } ; + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 } ; assign fetchStage_pipelines_1_first__2937_BIT_68_3665_ETC___d14063 = fetchStage$pipelines_1_first[68] || checkForException___d13797[4] || @@ -29169,17 +29155,9 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign r__h619423 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14027 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; assign regRenamingTable_RDY_rename_1_getRename__4083__ETC___d14101 = @@ -29600,6 +29578,12 @@ module mkCore(CLK, assign result__h653790 = ~x__h653789 ; assign rg_tdata1__read__h619066 = { r1__read__h620942, csrf_rg_tdata1_data } ; + assign rob_RDY_enqPort_1_enq__4147_AND_NOT_fetchStage_ETC___d14155 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14151) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4456_BITS_353_TO_290_4_ETC___d14959 = rob$deqPort_0_deq_data[353:290] + 64'd4 ; assign rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13831 = @@ -30539,23 +30523,23 @@ module mkCore(CLK, default: rVal1__h640779 = 64'b0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h396419 = 8'd255; + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h442114 = 8'd255; 3'd2: - _theResult___fst_exp__h396419 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h442114 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h396419 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + _theResult___fst_exp__h442114 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h396419 = 8'd254; - default: _theResult___fst_exp__h396419 = 8'd0; + 3'd4: _theResult___fst_exp__h442114 = 8'd254; + default: _theResult___fst_exp__h442114 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or @@ -30596,6 +30580,25 @@ module mkCore(CLK, default: _theResult___fst_sfd__h350721 = 23'd0; endcase end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h396419 = 8'd255; + 3'd2: + _theResult___fst_exp__h396419 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h396419 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h396419 = 8'd254; + default: _theResult___fst_exp__h396419 = 8'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -30615,25 +30618,6 @@ module mkCore(CLK, default: _theResult___fst_sfd__h396420 = 23'd0; endcase end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h442114 = 8'd255; - 3'd2: - _theResult___fst_exp__h442114 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h442114 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h442114 = 8'd254; - default: _theResult___fst_exp__h442114 = 8'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -32972,66 +32956,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h442142 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h442142) - 2'b0, 2'b01, 2'b10: - CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = - guard__h442142 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 or - guard__h442142) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h442142 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h442142 != 2'b01 && guard__h442142 != 2'b10 && - guard__h442142 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end always@(guard__h450849 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (guard__h450849) 2'b0, 2'b01, 2'b10: - CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = guard__h450849 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or + CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or guard__h450849) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; + CASE_guard50849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = (guard__h450849 == 2'b0) ? @@ -33048,6 +32994,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end + always@(guard__h442142 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h442142) + 2'b0, 2'b01, 2'b10: + CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h442142 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h442142) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + CASE_guard42142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + (guard__h442142 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h442142 != 2'b01 && guard__h442142 != 2'b10 && + guard__h442142 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end always@(guard__h450849 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -34506,64 +34490,15 @@ module mkCore(CLK, _theResult___exp__h526007; endcase end - always@(guard__h508268 or sfdin__h516488 or _theResult___sfd__h517224) - begin - case (guard__h508268) - 2'b0: - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h516488[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h517224; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h516488 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q207) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - sfdin__h516488[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - 52'd0; - endcase - end - always@(guard__h508268 or - sfdin__h516488 or out_sfd__h517227 or _theResult___sfd__h517224) - begin - case (guard__h508268) - 2'b0, 2'b01: - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h516488[56:5]; - 2'b10: - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h517227; - 2'b11: - CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h517224; - endcase - end always@(guard__h498956 or _theResult___snd__h506868 or _theResult___sfd__h507573) begin case (guard__h498956) 2'b0: - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q209 = + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q207 = _theResult___snd__h506868[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q209 = + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q207 = _theResult___sfd__h507573; endcase end @@ -34571,7 +34506,7 @@ module mkCore(CLK, _theResult___snd__h506868 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 or - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q209) + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -34585,7 +34520,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q209; + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = 52'd0; endcase @@ -34596,16 +34531,65 @@ module mkCore(CLK, begin case (guard__h498956) 2'b0, 2'b01: - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q210 = + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q208 = _theResult___snd__h506868[56:5]; 2'b10: - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q210 = + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q208 = out_sfd__h507576; 2'b11: - CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q210 = + CASE_guard98956_0b0_theResult___snd06868_BITS__ETC__q208 = _theResult___sfd__h507573; endcase end + always@(guard__h508268 or sfdin__h516488 or _theResult___sfd__h517224) + begin + case (guard__h508268) + 2'b0: + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q209 = + sfdin__h516488[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q209 = + _theResult___sfd__h517224; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h516488 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q209) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + sfdin__h516488[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q209; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + 52'd0; + endcase + end + always@(guard__h508268 or + sfdin__h516488 or out_sfd__h517227 or _theResult___sfd__h517224) + begin + case (guard__h508268) + 2'b0, 2'b01: + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q210 = + sfdin__h516488[56:5]; + 2'b10: + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q210 = + out_sfd__h517227; + 2'b11: + CASE_guard08268_0b0_sfdin16488_BITS_56_TO_5_0b_ETC__q210 = + _theResult___sfd__h517224; + endcase + end always@(guard__h517337 or _theResult___snd__h525273 or _theResult___sfd__h526008) begin @@ -35277,6 +35261,33 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_1_first) + begin + case (fetchStage$pipelines_1_first[177:175]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = + fetchStage$pipelines_1_first[177:175]; + default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = 3'd7; + endcase + end + always@(fetchStage$pipelines_1_first or + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228) + begin + case (fetchStage$pipelines_1_first[194:192]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = + fetchStage$pipelines_1_first[194:174]; + 3'd4: + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = + { fetchStage$pipelines_1_first[194:192], + 9'h0AA, + fetchStage$pipelines_1_first[182:178], + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, + fetchStage$pipelines_1_first[174] }; + default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = + 21'd1485482; + endcase + end + always@(fetchStage$pipelines_1_first) begin case (fetchStage$pipelines_1_first[172:161]) 12'd1, @@ -35319,39 +35330,12 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 = fetchStage$pipelines_1_first[172:161]; - default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = + default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 = 12'd2303; endcase end - always@(fetchStage$pipelines_1_first) - begin - case (fetchStage$pipelines_1_first[177:175]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = - fetchStage$pipelines_1_first[177:175]; - default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = 3'd7; - endcase - end - always@(fetchStage$pipelines_1_first or - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229) - begin - case (fetchStage$pipelines_1_first[194:192]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = - fetchStage$pipelines_1_first[194:174]; - 3'd4: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = - { fetchStage$pipelines_1_first[194:192], - 9'h0AA, - fetchStage$pipelines_1_first[182:178], - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, - fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = - 21'd1485482; - endcase - end always@(idx__h690522 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13842 or @@ -35492,29 +35476,29 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13833; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(k__h674927 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin case (k__h674927) 1'd0: - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = + CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 or @@ -35749,10 +35733,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 = + coreFix_memExe_lsq$enqLdTag[4:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 = + coreFix_memExe_lsq$enqStTag[4:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -35760,10 +35744,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 = - coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 = - coreFix_memExe_lsq$enqStTag[4:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_1_first or @@ -35993,15 +35977,6 @@ module mkCore(CLK, 3'd0; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = 3'd7; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -36215,6 +36190,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = 3'd7; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9995 or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285 or diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index 21e4be6..de21a79 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -1904,8 +1904,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163686; - reg [31 : 0] v__h163250; + reg [31 : 0] v__h163702; + reg [31 : 0] v__h163266; reg [31 : 0] v__h5300; reg [31 : 0] v__h5473; reg [31 : 0] v__h5733; @@ -1916,13 +1916,13 @@ module mkProc(CLK, reg [31 : 0] v__h9260; reg [31 : 0] v__h9753; reg [31 : 0] v__h9916; - reg [31 : 0] v__h135207; - reg [31 : 0] v__h135374; - reg [31 : 0] v__h137477; - reg [31 : 0] v__h154821; - reg [31 : 0] v__h134588; - reg [31 : 0] v__h161515; - reg [31 : 0] v__h162023; + reg [31 : 0] v__h135223; + reg [31 : 0] v__h135390; + reg [31 : 0] v__h137493; + reg [31 : 0] v__h154837; + reg [31 : 0] v__h134604; + reg [31 : 0] v__h161531; + reg [31 : 0] v__h162039; reg [31 : 0] v__h2444; reg [31 : 0] v__h4117; reg [31 : 0] v__h5294; @@ -1933,274 +1933,276 @@ module mkProc(CLK, reg [31 : 0] v__h9254; reg [31 : 0] v__h9747; reg [31 : 0] v__h9910; - reg [31 : 0] v__h134582; - reg [31 : 0] v__h135201; - reg [31 : 0] v__h135368; - reg [31 : 0] v__h137471; - reg [31 : 0] v__h154815; - reg [31 : 0] v__h161509; - reg [31 : 0] v__h162017; - reg [31 : 0] v__h163244; - reg [31 : 0] v__h163680; + reg [31 : 0] v__h134598; + reg [31 : 0] v__h135217; + reg [31 : 0] v__h135384; + reg [31 : 0] v__h137487; + reg [31 : 0] v__h154831; + reg [31 : 0] v__h161525; + reg [31 : 0] v__h162033; + reg [31 : 0] v__h163260; + reg [31 : 0] v__h163696; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952, - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, - data64__h148647, - dword__h94449, - ld_data__h132736, - old_dword__h90139, - w1__h48006, - w1__h48011, - w2__h48007, - w2__h48013, - x__h48002; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; - reg [7 : 0] strb8__h148648; - reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; - reg [2 : 0] x__h61720; - reg [1 : 0] CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26, + CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956, + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923, + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891, + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893, + data64__h148663, + dword__h94465, + ld_data__h132752, + old_dword__h90155, + w1__h48022, + w1__h48027, + w2__h48023, + w2__h48029, + x__h48018; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991; + reg [7 : 0] strb8__h148664; + reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; + reg [2 : 0] x__h61736; + reg [1 : 0] CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, - x__h61727, - x__h82707; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - new_cline__h135510; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; - wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - data__h31730, - failed_testnum__h163293, - line_addr__h102513, - line_addr__h102599, - mask__h90136, - mem_req_rd_addr_araddr__h134808, - mem_req_wr_addr_awaddr__h148732, - mmioPlatform_fromHostQ_data_0__h42577, - mmioPlatform_mtime__h37044, - mmioPlatform_reqData__h48598, - n__read_addr__h61588, - n__read_addr__h61673, - n__read_addr__h80469, - n__read_addr__h80548, - n__read_snd_addr__h124040, - newData__h31811, - newData__h34741, - new_dword__h90140, - op_result__h48614, - op_result__h49144, - op_result__h49149, - op_result__h49154, - op_result__h49159, + CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12, + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371, + x__h61743, + x__h82723; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, + new_cline__h135526; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; + wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, + data__h31746, + failed_testnum__h163309, + line_addr__h102529, + line_addr__h102615, + mask__h90152, + mem_req_rd_addr_araddr__h134824, + mem_req_wr_addr_awaddr__h148748, + mmioPlatform_fromHostQ_data_0__h42593, + mmioPlatform_mtime__h37060, + mmioPlatform_reqData__h48614, + n__read_addr__h61604, + n__read_addr__h61689, + n__read_addr__h80485, + n__read_addr__h80564, + n__read_snd_addr__h124056, + newData__h31827, + newData__h34757, + new_dword__h90156, + op_result__h48630, + op_result__h49160, op_result__h49165, - op_result__h49172, - op_result__h49178, - result__h48057, - result__h48181, - result__h48209, - result__h48237, - result__h48265, - result__h48293, - result__h48321, - result__h48349, - result__h48377, - result__h48422, - result__h48450, - result__h48478, - result__h48506, - result__h48547, - result__h48575, - result__h48701, - result__h48728, - result__h48755, - result__h48782, - result__h48809, - result__h48836, - result__h48863, - result__h48890, - result__h48934, - result__h48961, - result__h48988, - result__h49015, - result__h49055, - result__h49082, - result__h49199, - result__h49265, - result__h49331, - result__h49397, - result__h49463, - result__h49529, - result__h49595, - result__h49657, - result__h49702, - result__h49768, - result__h49834, - result__h49892, - result__h49937, - w1___1__h48116, - w2___1__h48117, - x1_avValue_data__h40249, - x1_avValue_data__h44935, - x__h31922, - x__h34832, - x__h37192, - x__h40767, - x__h40778, - x__h42860, - x__h42871, - x__h50114, - x__h91302, - y__h91303, - y__h91304; - wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; - wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995, + op_result__h49170, + op_result__h49175, + op_result__h49181, + op_result__h49188, + op_result__h49194, + result__h48073, + result__h48197, + result__h48225, + result__h48253, + result__h48281, + result__h48309, + result__h48337, + result__h48365, + result__h48393, + result__h48438, + result__h48466, + result__h48494, + result__h48522, + result__h48563, + result__h48591, + result__h48717, + result__h48744, + result__h48771, + result__h48798, + result__h48825, + result__h48852, + result__h48879, + result__h48906, + result__h48950, + result__h48977, + result__h49004, + result__h49031, + result__h49071, + result__h49098, + result__h49215, + result__h49281, + result__h49347, + result__h49413, + result__h49479, + result__h49545, + result__h49611, + result__h49673, + result__h49718, + result__h49784, + result__h49850, + result__h49908, + result__h49953, + w1___1__h48132, + w2___1__h48133, + x1_avValue_data__h40265, + x1_avValue_data__h44951, + x__h31938, + x__h34848, + x__h37208, + x__h40783, + x__h40794, + x__h42876, + x__h42887, + x__h50130, + x__h91318, + y__h91319, + y__h91320; + wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713; + wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999, mmioPlatform_mtime_BITS_31_TO_0__q4, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h31523, - v__h31560, - w18006_BITS_31_TO_0__q7, - w28007_BITS_31_TO_0__q8, - x_data__h30313; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; - wire [5 : 0] x__h134843, x__h148757; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; - wire [3 : 0] b__h134515, b__h2344; - wire [2 : 0] n__read_id__h61592, n__read_id__h61677, x__h7705; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120, - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; - wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, - IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097, - IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471, - IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315, - IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, + v__h31539, + v__h31576, + w18022_BITS_31_TO_0__q7, + w28023_BITS_31_TO_0__q8, + x_data__h30329; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168; + wire [5 : 0] x__h134859, x__h148773; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167; + wire [3 : 0] b__h134531, b__h2344; + wire [2 : 0] n__read_id__h61608, n__read_id__h61693, x__h7705; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120, + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124, + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; + wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, + IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101, + IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475, + IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319, + IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974, + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267, - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012, - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186, - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193, - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019, - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099, - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373, - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271, + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016, + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190, + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197, + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023, + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103, + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377, + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386, - NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388, - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096, - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370, - NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477, - NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530, + NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390, + NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392, + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100, + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374, + NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481, + NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979, + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h29938, - mmioPlatform_reqBE_BIT_4___h29898, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, + mmioPlatform_reqBE_BIT_0___h29954, + mmioPlatform_reqBE_BIT_4___h29914, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61593, - n__read_child__h61678, - n__read_child__h80472, - n__read_child__h80551, - n__read_snd_id__h124041, - propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, - propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, - x__h61406, - x__h75220, - x__h80291; + n__read_child__h61609, + n__read_child__h61694, + n__read_child__h80488, + n__read_child__h80567, + n__read_snd_id__h124057, + propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140, + propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144, + x__h61422, + x__h75236, + x__h80307; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3150,7 +3152,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 ; + IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3178,7 +3180,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 ; + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3339,8 +3341,9 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3357,7 +3360,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3366,7 +3369,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3412,7 +3415,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42860 == 64'd0 || + x__h42876 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3430,7 +3433,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3438,14 +3441,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3455,22 +3458,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 && + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3552,7 +3555,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3570,7 +3573,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3588,7 +3591,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3598,7 +3601,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3618,7 +3621,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3627,7 +3630,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -3659,7 +3662,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3732,13 +3735,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134515 == 4'd0 ; + b__h134531 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134515 != 4'd0 && + b__h134531 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3748,7 +3751,8 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3756,22 +3760,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || + (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -3796,14 +3800,10 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - core_0$mmioToPlatform_cRq_notEmpty) ; + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty ; + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -3838,20 +3838,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30313 } ; + x_data__h30329 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -3865,35 +3865,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31730 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31746 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -3907,10 +3907,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102513, + { line_addr__h102529, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102599, + { line_addr__h102615, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3918,28 +3918,29 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd4194304 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194305) ? @@ -3950,7 +3951,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd4200447) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; + IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -3963,11 +3964,12 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -3978,32 +3980,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4011,29 +4013,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ? + (mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48002 } ; + x__h48018 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50114, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50130, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4041,47 +4043,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42860 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42876 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42860 != 64'd0 ; + x__h42876 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 == 64'd0 ; + x__h40783 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + x__h61422 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, - SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; + CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15, + SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + x__h80307 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; + CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h124040, n__read_snd_id__h124041 } ; + { 1'd1, n__read_snd_addr__h124056, n__read_snd_id__h124057 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4195,11 +4197,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134515 - 4'd1 ; + b__h134531 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134515 ; + b__h134531 ; // register cfg_verbosity assign cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -4208,10 +4210,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, + IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? + (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4219,8 +4221,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, - IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 } ; + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, + IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4259,7 +4261,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134808, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134824, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4270,13 +4272,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148732, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148748, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148647, strb8__h148648, 1'd1 } ; + { data64__h148663, strb8__h148664, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4288,7 +4290,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135510 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135526 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4319,10 +4321,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, + IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4336,15 +4338,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102513 : - line_addr__h102599 ; + line_addr__h102529 : + line_addr__h102615 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4415,10 +4417,11 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4431,11 +4434,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 && + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4444,12 +4447,10 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4495,17 +4496,15 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34741 : + newData__h34757 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4514,7 +4513,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h31811 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h31827 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4524,9 +4523,10 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4596,7 +4596,8 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -4660,7 +4661,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4668,15 +4669,16 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -4762,28 +4764,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, + { IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 } ; + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, + { IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 } ; + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -4796,36 +4798,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 ; + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 ; + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -4926,7 +4928,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132736, llc$dma_respLd_first[3] } ; + { ld_data__h132752, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4947,13 +4949,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || + (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -4964,15 +4966,16 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5011,7 +5014,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5020,7 +5023,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5052,17 +5055,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; + { IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135510, + { new_cline__h135526, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5138,7 +5141,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94449, 3'd1 } ; + { 4'd0, dword__h94465, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5189,7 +5192,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5219,11 +5222,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5441,86 +5444,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29914 && + mmioPlatform_reqBE_BIT_0___h29954, 2'd0 }), - .amoExec_current_data(x__h37192), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h31922)); + .amoExec_current_data(x__h37208), + .amoExec_in_data(mmioPlatform_reqData__h48614), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && + !mmioPlatform_reqBE_BIT_0___h29954), + .amoExec(x__h31938)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29914 && + mmioPlatform_reqBE_BIT_0___h29954, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37044), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h34832)); + .amoExec_current_data(mmioPlatform_mtime__h37060), + .amoExec_in_data(mmioPlatform_reqData__h48614), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && + !mmioPlatform_reqBE_BIT_0___h29954), + .amoExec(x__h34848)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29914 && + mmioPlatform_reqBE_BIT_0___h29954, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42577), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h40778)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42593), + .amoExec_in_data(mmioPlatform_reqData__h48614), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && + !mmioPlatform_reqBE_BIT_0___h29954), + .amoExec(x__h40794)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29898 && - mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29914 && + mmioPlatform_reqBE_BIT_0___h29954, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48598), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && - !mmioPlatform_reqBE_BIT_0___h29938), - .amoExec(x__h42871)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = + .amoExec_in_data(mmioPlatform_reqData__h48614), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && + !mmioPlatform_reqBE_BIT_0___h29954), + .amoExec(x__h42887)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40249 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + x1_avValue_data__h40265 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h31811 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = + newData__h31827 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101 = + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 : + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371 = - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ? + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375 = + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 : + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 = - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; - assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; + assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5528,116 +5531,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? + assign IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 = + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 = + assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - x__h75220 } ; - assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, + x__h75236 } ; + assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, - IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, + IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90140 : + new_dword__h90156 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 } ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q3[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q3 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q4[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q4 } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -5650,23 +5653,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -5679,23 +5682,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -5708,49 +5711,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42860 == 64'd0 : - x__h40767 == 64'd0, + x__h42876 == 64'd0 : + x__h40783 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44935 } ; + x1_avValue_data__h44951 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = + assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -5758,99 +5761,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 = + assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 = + assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 = + assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 = + assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 = + assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 = + assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 = + assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 = + assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120 = + assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130 = + assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 = + assign IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 = + assign IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 = + assign IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 = + assign IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 = + assign NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 || - IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097) ; - assign NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 || + IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101) ; + assign NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5861,7 +5864,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5872,7 +5875,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5884,7 +5887,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5896,7 +5899,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5906,7 +5909,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5926,29 +5929,35 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = + !mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || + core_0$mmioToPlatform_cRq_notEmpty ; + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -5962,57 +5971,57 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 = + assign NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388 = + assign NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 = + assign NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 = + assign NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477 = + assign NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481 = !propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ; - assign NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175 = + assign NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179 = !propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = - { CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, - SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = - { CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - x__h82707 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = - { CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = - { CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, - x__h61720, - x__h61727 } ; - assign b__h134515 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 = + { CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, + SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 = + { CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, + x__h82723 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412 = + { CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 = + { CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12, + x__h61736, + x__h61743 } ; + assign b__h134531 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6020,23 +6029,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31730 = + assign data__h31746 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31523, 32'd0 } ; - assign failed_testnum__h163293 = + { v__h31539, 32'd0 } ; + assign failed_testnum__h163309 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102513 = + assign line_addr__h102529 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102599 = + assign line_addr__h102615 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = - line_addr__h102599 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = - line_addr__h102513 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90136 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 = + line_addr__h102615 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 = + line_addr__h102529 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90152 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6061,14 +6070,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134808 = - { llc$to_mem_toM_first[68:11], x__h134843 } ; - assign mem_req_wr_addr_awaddr__h148732 = - { llc$to_mem_toM_first[639:582], x__h148757 } ; + assign mem_req_rd_addr_araddr__h134824 = + { llc$to_mem_toM_first[68:11], x__h134859 } ; + assign mem_req_wr_addr_awaddr__h148748 = + { llc$to_mem_toM_first[639:582], x__h148773 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = + assign mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42577 = + assign mmioPlatform_fromHostQ_data_0__h42593 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6079,36 +6088,41 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37044 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34741 ; + assign mmioPlatform_mtime__h37060 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = + mmioPlatform_mtimecmp_0 <= newData__h34757 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h29938 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h29898 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48598 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = + assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0) && + core_0$mmioToPlatform_cRq_notEmpty ; + assign mmioPlatform_reqBE_BIT_0___h29954 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h29914 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48614 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6122,235 +6136,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61588 = + assign n__read_addr__h61604 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61673 = + assign n__read_addr__h61689 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80469 = + assign n__read_addr__h80485 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 : 64'd0 ; - assign n__read_addr__h80548 = + assign n__read_addr__h80564 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 : 64'd0 ; - assign n__read_child__h61593 = + assign n__read_child__h61609 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61678 = + assign n__read_child__h61694 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80472 = + assign n__read_child__h80488 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; - assign n__read_child__h80551 = + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 ; + assign n__read_child__h80567 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; - assign n__read_id__h61592 = + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 ; + assign n__read_id__h61608 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61677 = + assign n__read_id__h61693 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h124040 = + assign n__read_snd_addr__h124056 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h124041 = + assign n__read_snd_id__h124057 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h31811 = + assign newData__h31827 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h31922 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34741 = + x__h31938 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; + assign newData__h34757 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h34832 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h135510 = + x__h34848 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; + assign new_cline__h135526 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90140 = x__h91302 | y__h91303 ; - assign op_result__h48614 = - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; - assign op_result__h49144 = w1__h48011 ^ w2__h48013 ; - assign op_result__h49149 = w1__h48011 & w2__h48013 ; - assign op_result__h49154 = w1__h48011 | w2__h48013 ; - assign op_result__h49159 = - (w1__h48011 < w2__h48013) ? w1__h48011 : w2__h48013 ; - assign op_result__h49165 = - (w1__h48011 <= w2__h48013) ? w2__h48013 : w1__h48011 ; - assign op_result__h49172 = - ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ + assign new_dword__h90156 = x__h91318 | y__h91319 ; + assign op_result__h48630 = + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 + + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ; + assign op_result__h49160 = w1__h48027 ^ w2__h48029 ; + assign op_result__h49165 = w1__h48027 & w2__h48029 ; + assign op_result__h49170 = w1__h48027 | w2__h48029 ; + assign op_result__h49175 = + (w1__h48027 < w2__h48029) ? w1__h48027 : w2__h48029 ; + assign op_result__h49181 = + (w1__h48027 <= w2__h48029) ? w2__h48029 : w1__h48027 ; + assign op_result__h49188 = + ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ + (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ 64'h8000000000000000)) ? - w1__h48011 : - w2__h48013 ; - assign op_result__h49178 = - ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ + w1__h48027 : + w2__h48029 ; + assign op_result__h49194 = + ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ + (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ 64'h8000000000000000)) ? - w2__h48013 : - w1__h48011 ; - assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = + w2__h48029 : + w1__h48027 ; + assign propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140 = + assign propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48057 = + assign result__h48073 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; - assign result__h48181 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48209 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48237 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48265 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48293 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48321 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48349 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48377 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48422 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48450 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48478 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48506 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48547 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48575 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48701 = + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0] } ; + assign result__h48197 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48225 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48253 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48281 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48309 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48337 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48365 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48393 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48438 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48466 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48494 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48522 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48563 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48591 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48717 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48728 = + assign result__h48744 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48755 = + assign result__h48771 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48782 = + assign result__h48798 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48809 = + assign result__h48825 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48836 = + assign result__h48852 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48863 = + assign result__h48879 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48890 = + assign result__h48906 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48934 = + assign result__h48950 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48961 = + assign result__h48977 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48988 = + assign result__h49004 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49015 = + assign result__h49031 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49055 = + assign result__h49071 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49082 = + assign result__h49098 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49199 = + assign result__h49215 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49265 = + assign result__h49281 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49331 = + assign result__h49347 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49397 = + assign result__h49413 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49463 = + assign result__h49479 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49529 = + assign result__h49545 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49595 = - { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + assign result__h49611 = + { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49657 = + assign result__h49673 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; - assign result__h49702 = + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0] } ; + assign result__h49718 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49768 = + assign result__h49784 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49834 = - { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], + assign result__h49850 = + { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49892 = + assign result__h49908 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; - assign result__h49937 = - { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0] } ; + assign result__h49953 = + { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31523 = mmioPlatform_waitUpperMSIPCRs ? v__h31560 : 32'd0 ; - assign v__h31560 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18006_BITS_31_TO_0__q7 = w1__h48006[31:0] ; - assign w1___1__h48116 = { 32'd0, w1__h48006[31:0] } ; - assign w28007_BITS_31_TO_0__q8 = w2__h48007[31:0] ; - assign w2___1__h48117 = { 32'd0, w2__h48007[31:0] } ; - assign x1_avValue_data__h40249 = + assign v__h31539 = mmioPlatform_waitUpperMSIPCRs ? v__h31576 : 32'd0 ; + assign v__h31576 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18022_BITS_31_TO_0__q7 = w1__h48022[31:0] ; + assign w1___1__h48132 = { 32'd0, w1__h48022[31:0] } ; + assign w28023_BITS_31_TO_0__q8 = w2__h48023[31:0] ; + assign w2___1__h48133 = { 32'd0, w2__h48023[31:0] } ; + assign x1_avValue_data__h40265 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44935 = + assign x1_avValue_data__h44951 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134843 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148757 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37192 = mmioPlatform_mtimecmp_0 ; - assign x__h40767 = + assign x__h134859 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148773 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37208 = mmioPlatform_mtimecmp_0 ; + assign x__h40783 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40778 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; - assign x__h42860 = + x__h40794 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 ; + assign x__h42876 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42871 : + x__h42887 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6359,29 +6373,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50114 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61406 = - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? + assign x__h50130 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61422 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; - assign x__h75220 = + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ; + assign x__h75236 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 ; assign x__h7705 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80291 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? + assign x__h80307 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; - assign x__h91302 = old_dword__h90139 & y__h91304 ; - assign x_data__h30313 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91303 = + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ; + assign x__h91318 = old_dword__h90155 & y__h91320 ; + assign x_data__h30329 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91319 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90136 ; - assign y__h91304 = + mask__h90152 ; + assign y__h91320 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -6410,466 +6424,466 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132736 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132736 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132736 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132736 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132736 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132736 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132736 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132736 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132752 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132752 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132752 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132752 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132752 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132752 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132752 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132752 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148647 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148647 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148647 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148647 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148647 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148647 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148647 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148647 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h148663 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148663 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148663 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148663 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148663 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148663 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148663 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148663 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148648 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148648 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148648 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148648 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148648 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148648 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148648 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148648 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148664 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148664 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148664 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148664 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148664 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148664 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148664 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148664 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48181 or - result__h48209 or - result__h48237 or - result__h48265 or - result__h48293 or - result__h48321 or result__h48349 or result__h48377) + result__h48197 or + result__h48225 or + result__h48253 or + result__h48281 or + result__h48309 or + result__h48337 or result__h48365 or result__h48393) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48181; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48197; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48209; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48225; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48237; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48253; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48265; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48281; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48293; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48309; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48321; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48337; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48349; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48365; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48377; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48393; endcase end always@(mmioPlatform_curReq or - result__h48422 or - result__h48450 or result__h48478 or result__h48506) + result__h48438 or + result__h48466 or result__h48494 or result__h48522) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48422; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48438; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48450; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48466; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48478; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48494; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48506; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48522; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48547 or result__h48575) + always@(mmioPlatform_curReq or result__h48563 or result__h48591) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48547; + result__h48563; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48575; + result__h48591; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48007 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; + w2__h48023 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; 2'b01: - w2__h48007 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; + w2__h48023 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; 2'b10: - w2__h48007 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h48023 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h48007 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + w2__h48023 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w2___1__h48117 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or + w2___1__h48133 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48013 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; + w2__h48029 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; 2'b01: - w2__h48013 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; - 2'b10: w2__h48013 = w2___1__h48117; + w2__h48029 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; + 2'b10: w2__h48029 = w2___1__h48133; 2'b11: - w2__h48013 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + w2__h48029 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_curReq or - result__h48934 or - result__h48961 or result__h48988 or result__h49015) + result__h48950 or + result__h48977 or result__h49004 or result__h49031) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48934; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h48950; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48961; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h48977; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h48988; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h49004; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49015; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h49031; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48701 or - result__h48728 or - result__h48755 or - result__h48782 or - result__h48809 or - result__h48836 or result__h48863 or result__h48890) + result__h48717 or + result__h48744 or + result__h48771 or + result__h48798 or + result__h48825 or + result__h48852 or result__h48879 or result__h48906) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48701; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48717; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48728; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48744; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48755; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48771; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48782; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48798; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48809; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48825; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48836; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48852; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48863; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48879; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48890; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48906; endcase end - always@(mmioPlatform_curReq or result__h49055 or result__h49082) + always@(mmioPlatform_curReq or result__h49071 or result__h49098) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49055; + result__h49071; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49082; + result__h49098; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48006 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; + w1__h48022 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; 2'b01: - w1__h48006 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; + w1__h48022 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; 2'b10: - w1__h48006 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h48022 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h48006 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; + w1__h48022 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w1___1__h48116 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or + w1___1__h48132 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48011 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; + w1__h48027 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; 2'b01: - w1__h48011 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; - 2'b10: w1__h48011 = w1___1__h48116; + w1__h48027 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; + 2'b10: w1__h48027 = w1___1__h48132; 2'b11: - w1__h48011 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; + w1__h48027 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w18006_BITS_31_TO_0__q7 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or + w18022_BITS_31_TO_0__q7 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; 2'b01: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; 2'b10: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - { {32{w18006_BITS_31_TO_0__q7[31]}}, w18006_BITS_31_TO_0__q7 }; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + { {32{w18022_BITS_31_TO_0__q7[31]}}, w18022_BITS_31_TO_0__q7 }; 2'b11: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w28007_BITS_31_TO_0__q8 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or + w28023_BITS_31_TO_0__q8 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; 2'b01: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; 2'b10: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - { {32{w28007_BITS_31_TO_0__q8[31]}}, w28007_BITS_31_TO_0__q8 }; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + { {32{w28023_BITS_31_TO_0__q8[31]}}, w28023_BITS_31_TO_0__q8 }; 2'b11: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49178 or - w2__h48013 or - op_result__h48614 or - op_result__h49144 or - op_result__h49149 or - op_result__h49154 or - op_result__h49172 or op_result__h49159 or op_result__h49165) + op_result__h49194 or + w2__h48029 or + op_result__h48630 or + op_result__h49160 or + op_result__h49165 or + op_result__h49170 or + op_result__h49188 or op_result__h49175 or op_result__h49181) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - w2__h48013; + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + w2__h48029; 4'd1: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h48614; + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h48630; 4'd2: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49144; + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49160; 4'd3: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49149; - 4'd4: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49154; - 4'd5: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49172; - 4'd7: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49159; - 4'd8: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = op_result__h49165; - default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49178; + 4'd4: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49170; + 4'd5: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49188; + 4'd7: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49175; + 4'd8: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49181; + default: IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49194; endcase end always@(mmioPlatform_curReq or - result__h49657 or - result__h49702 or result__h49768 or result__h49834) + result__h49673 or + result__h49718 or result__h49784 or result__h49850) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49657; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49673; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49702; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49718; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49768; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49784; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49834; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49850; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48057 or - result__h49199 or - result__h49265 or - result__h49331 or - result__h49397 or - result__h49463 or result__h49529 or result__h49595) + result__h48073 or + result__h49215 or + result__h49281 or + result__h49347 or + result__h49413 or + result__h49479 or result__h49545 or result__h49611) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h48057; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h48073; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49199; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49215; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49265; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49281; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49331; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49347; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49397; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49413; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49463; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49479; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49529; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49545; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49595; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49611; endcase end - always@(mmioPlatform_curReq or result__h49892 or result__h49937) + always@(mmioPlatform_curReq or result__h49908 or result__h49953) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49892; + result__h49908; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49937; + result__h49953; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - x__h48002 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; + x__h48018 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947; 2'b01: - x__h48002 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; + x__h48018 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956; 2'b10: - x__h48002 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h48018 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h48002 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + x__h48018 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6877,15 +6891,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6893,11 +6907,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6905,315 +6919,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 or + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019) + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012; + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019; + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 or + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193) + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186; + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197; endcase end - always@(x__h61406 or n__read_id__h61592 or n__read_id__h61677) + always@(x__h61422 or n__read_id__h61608 or n__read_id__h61693) begin - case (x__h61406) - 1'd0: x__h61720 = n__read_id__h61592; - 1'd1: x__h61720 = n__read_id__h61677; + case (x__h61422) + 1'd0: x__h61736 = n__read_id__h61608; + 1'd1: x__h61736 = n__read_id__h61693; endcase end - always@(x__h61406 or n__read_child__h61593 or n__read_child__h61678) + always@(x__h61422 or n__read_child__h61609 or n__read_child__h61694) begin - case (x__h61406) - 1'd0: x__h61727 = n__read_child__h61593; - 1'd1: x__h61727 = n__read_child__h61678; + case (x__h61422) + 1'd0: x__h61743 = n__read_child__h61609; + 1'd1: x__h61743 = n__read_child__h61694; endcase end - always@(x__h61406 or - propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or - propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) + always@(x__h61422 or + propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 or + propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144) begin - case (x__h61406) + case (x__h61422) 1'd0: - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = - propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; + CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12 = + propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140; 1'd1: - CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = - propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; + CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12 = + propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144; endcase end - always@(x__h61406 or - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) + always@(x__h61422 or + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 or + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124) begin - case (x__h61406) + case (x__h61422) 1'd0: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; + CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120; 1'd1: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; + CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124; endcase end - always@(x__h61406 or - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) + always@(x__h61422 or + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 or + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134) begin - case (x__h61406) + case (x__h61422) 1'd0: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; + CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130; 1'd1: - CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; + CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; endcase end - always@(x__h61406 or n__read_addr__h61588 or n__read_addr__h61673) + always@(x__h61422 or n__read_addr__h61604 or n__read_addr__h61689) begin - case (x__h61406) + case (x__h61422) 1'd0: - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = - n__read_addr__h61588; + CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15 = + n__read_addr__h61604; 1'd1: - CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = - n__read_addr__h61673; + CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15 = + n__read_addr__h61689; endcase end - always@(x__h80291 or n__read_child__h80472 or n__read_child__h80551) + always@(x__h80307 or n__read_child__h80488 or n__read_child__h80567) begin - case (x__h80291) - 1'd0: x__h82707 = n__read_child__h80472; - 1'd1: x__h82707 = n__read_child__h80551; + case (x__h80307) + 1'd0: x__h82723 = n__read_child__h80488; + 1'd1: x__h82723 = n__read_child__h80567; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80291 or + always@(x__h80307 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80291 or + always@(x__h80307 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 : 2'd0; 1'd1: - CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 : 2'd0; endcase end - always@(x__h80291 or - NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or - NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) + always@(x__h80307 or + NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 or + NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; + CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390; 1'd1: - CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; + CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392; endcase end - always@(x__h80291 or n__read_addr__h80469 or n__read_addr__h80548) + always@(x__h80307 or n__read_addr__h80485 or n__read_addr__h80564) begin - case (x__h80291) + case (x__h80307) 1'd0: - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = - n__read_addr__h80469; + CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26 = + n__read_addr__h80485; 1'd1: - CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = - n__read_addr__h80548; + CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26 = + n__read_addr__h80564; endcase end @@ -7629,76 +7643,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163686 = $stime; + v__h163702 = $stime; #0; end - v__h163680 = v__h163686 / 32'd10; + v__h163696 = v__h163702 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163680, + v__h163696, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && - NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + x__h61422 && + NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && - NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + x__h61422 && + NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61406 && - NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + x__h61422 && + NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && - NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + x__h80307 && + NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && - NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + x__h80307 && + NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80291 && - NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + x__h80307 && + NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (core_0$RDY_coreIndInv_terminate) @@ -7706,14 +7720,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163250 = $stime; + v__h163266 = $stime; #0; end - v__h163244 = v__h163250 / 32'd10; + v__h163260 = v__h163266 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163244, + v__h163260, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7723,7 +7737,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163293); + $display("FAIL %0d", failed_testnum__h163309); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9295,7 +9309,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_toHostQ_empty) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 797, column 30\nCannot write tohost when toHostQ not empty"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 800, column 30\nCannot write tohost when toHostQ not empty"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && @@ -9312,7 +9326,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd2 && mmioPlatform_reqFunc[5:4] != 2'd1) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 819, column 33\nCannot do AMO on toHost"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 822, column 33\nCannot do AMO on toHost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -9323,37 +9337,37 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42876 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 855, column 41\nCan only write 0 to fromhost"); + x__h42876 != 64'd0) + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 858, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42860 != 64'd0) + x__h42876 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40783 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 847, column 41\nCan only write 0 to fromhost"); + x__h40783 != 64'd0) + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 850, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40767 != 64'd0) + x__h40783 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9366,7 +9380,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd2 && mmioPlatform_reqFunc[5:4] != 2'd1) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 870, column 33\nCannot do AMO on fromHost"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 873, column 33\nCannot do AMO on fromHost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -9374,7 +9388,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9388,85 +9402,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) begin - v__h135207 = $stime; + v__h135223 = $stime; #0; end - v__h135201 = v__h135207 / 32'd10; + v__h135217 = v__h135223 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135201, + v__h135217, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135374 = $stime; + v__h135390 = $stime; #0; end - v__h135368 = v__h135374 / 32'd10; + v__h135384 = v__h135390 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135368); + v__h135384); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9528,135 +9542,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137477 = $stime; + v__h137493 = $stime; #0; end - v__h137471 = v__h137477 / 32'd10; + v__h137487 = v__h137493 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137471); + v__h137487); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -10854,169 +10868,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154821 = $stime; + v__h154837 = $stime; #0; end - v__h154815 = v__h154821 / 32'd10; + v__h154831 = v__h154837 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154815); + $display("%0d: ERROR: CreditCounter: overflow", v__h154831); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_wr_addr_awaddr__h148732); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", mem_req_wr_addr_awaddr__h148748); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", data64__h148647); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", data64__h148663); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", strb8__h148648); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", strb8__h148664); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134588 = $stime; + v__h134604 = $stime; #0; end - v__h134582 = v__h134588 / 32'd10; + v__h134598 = v__h134604 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134582, + v__h134598, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11087,159 +11101,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_rd_addr_araddr__h134808); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", mem_req_rd_addr_araddr__h134824); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) begin - v__h161515 = $stime; + v__h161531 = $stime; #0; end - v__h161509 = v__h161515 / 32'd10; + v__h161525 = v__h161531 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161509, + v__h161525, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h162023 = $stime; + v__h162039 = $stime; #0; end - v__h162017 = v__h162023 / 32'd10; + v__h162033 = v__h162039 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h162017); + v__h162033); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv index b9126d2..259825e 100644 --- a/src_Core/CPU/MMIOPlatform.bsv +++ b/src_Core/CPU/MMIOPlatform.bsv @@ -321,15 +321,18 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, // check for timer interrupt Vector#(CoreNum, Bool) needTimerInt = replicate(False); for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin - if(!mtip[i] && mtimecmp[i] <= mtime) begin - cores[i].pRq.enq(MMIOPRq { - target: MTIP, - func: St, - data: 1 - }); - mtip[i] <= True; - needTimerInt[i] = True; - end + if(!mtip[i] + && (mtimecmp[i] <= mtime) + && (mtimecmp [i] != 0)) // Avoid interrupt until mtimecmp has actually been written + begin + cores[i].pRq.enq(MMIOPRq { + target: MTIP, + func: St, + data: 1 + }); + mtip[i] <= True; + needTimerInt[i] = True; + end end if(needTimerInt != replicate(False)) begin state <= WaitResp; diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 0ed7460..7bcc820 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -4465,7 +4465,7 @@ module mkCore(CLK, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, - MUX_flush_reservation$write_1__SEL_2, + MUX_flush_reservation$write_1__SEL_1, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -4489,7 +4489,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_started$write_1__SEL_1, MUX_v_f_to_TV_0$enq_1__SEL_2; // remaining internal signals @@ -4525,7 +4524,7 @@ module mkCore(CLK, trap_val__h711388, x__h197129, x__h723943; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, CASE_guard02883_0b0_sfdin11103_BITS_56_TO_5_0b_ETC__q217, @@ -4561,8 +4560,8 @@ module mkCore(CLK, CASE_guard00505_0b0_theResult___snd08504_BITS__ETC__q83, CASE_guard09435_0b0_sfdin17657_BITS_56_TO_34_0_ETC__q86, CASE_guard09435_0b0_sfdin17657_BITS_56_TO_34_0_ETC__q87, + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88, CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89, - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90, CASE_guard37493_0b0_sfdin45586_BITS_56_TO_34_0_ETC__q119, CASE_guard37493_0b0_sfdin45586_BITS_56_TO_34_0_ETC__q120, CASE_guard46099_0b0_sfdin54194_BITS_56_TO_34_0_ETC__q49, @@ -4577,8 +4576,8 @@ module mkCore(CLK, CASE_guard63738_0b0_sfdin71960_BITS_56_TO_34_0_ETC__q52, CASE_guard63966_0b0_theResult___snd71989_BITS__ETC__q123, CASE_guard63966_0b0_theResult___snd71989_BITS__ETC__q124, + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53, CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54, - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55, CASE_guard91798_0b0_sfdin99891_BITS_56_TO_34_0_ETC__q84, CASE_guard91798_0b0_sfdin99891_BITS_56_TO_34_0_ETC__q85, _theResult___fst_sfd__h346072, @@ -4621,8 +4620,8 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, CASE_guard02883_0b0_theResult___fst_exp11109_0_ETC__q211, CASE_guard02883_0b0_theResult___fst_exp11109_0_ETC__q212, @@ -4632,12 +4631,12 @@ module mkCore(CLK, CASE_guard32424_0b0_theResult___fst_exp40385_0_ETC__q184, CASE_guard41736_0b0_theResult___fst_exp49962_0_ETC__q185, CASE_guard41736_0b0_theResult___fst_exp49962_0_ETC__q186, - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189, - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190, + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187, + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188, CASE_guard71728_0b0_theResult___fst_exp79689_0_ETC__q160, CASE_guard71728_0b0_theResult___fst_exp79689_0_ETC__q161, - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187, - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188, + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189, + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190, CASE_guard90109_0b0_theResult___fst_exp98099_0_ETC__q191, CASE_guard90109_0b0_theResult___fst_exp98099_0_ETC__q192, CASE_guard93571_0b0_theResult___fst_exp01532_0_ETC__q143, @@ -4770,22 +4769,22 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, CASE_guard00505_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, CASE_guard00505_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, CASE_guard09435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, CASE_guard09435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, CASE_guard18271_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, CASE_guard18271_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, CASE_guard32424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, CASE_guard32424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, CASE_guard37493_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, CASE_guard41736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, CASE_guard41736_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard46099_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53, + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, CASE_guard46200_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, CASE_guard50805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard50805_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard54808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, @@ -4796,16 +4795,16 @@ module mkCore(CLK, CASE_guard63738_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, CASE_guard63966_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, CASE_guard63966_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, CASE_guard71728_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard72574_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, CASE_guard72574_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, CASE_guard81040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, CASE_guard81040_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard90109_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard91798_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, CASE_guard93571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, @@ -5393,7 +5392,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data75286_BITS_31_TO_0__q14, + data75286_BITS_31_TO_0__q13, imm__h655334, r1__read__h613079, r1__read__h614262, @@ -6326,7 +6325,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901, - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_RDY_ETC___d15380, + NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380, NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659, NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998, NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377, @@ -6396,7 +6395,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo20, + _dfoo22, _dfoo24, _dfoo26, _dfoo32, @@ -6541,7 +6540,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899, f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894, - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14083, + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181, @@ -6592,7 +6591,7 @@ module mkCore(CLK, next_deqP___1__h328991, next_deqP___1__h332216, r1__read_BIT_20___h655898, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946, regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027, regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434, @@ -6617,7 +6616,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925, rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730, - rob_RDY_deqPort_0_deq__4341_AND_rob_RDY_deqPor_ETC___d15003, + rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, @@ -9835,8 +9834,8 @@ module mkCore(CLK, // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_first && fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + fetchStage$RDY_iTlbIfc_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; @@ -9872,8 +9871,8 @@ module mkCore(CLK, // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - coreFix_memExe_dTlb$RDY_toParent_flush_response_put && fetchStage$RDY_iTlbIfc_toParent_flush_response_put && + coreFix_memExe_dTlb$RDY_toParent_flush_response_put && l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; @@ -10015,9 +10014,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -10377,8 +10376,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10414,7 +10413,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4341_AND_rob_RDY_deqPor_ETC___d15003 && + regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 && NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10449,7 +10448,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_RDY_ETC___d15380 && + NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 && NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11127,16 +11126,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush && + commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -11144,7 +11143,9 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_debug_resume = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -11416,9 +11417,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11430,8 +11432,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11532,7 +11534,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11963,7 +11966,7 @@ module mkCore(CLK, assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; - assign MUX_flush_reservation$write_1__SEL_2 = + assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -12020,9 +12023,6 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[89] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ; - assign MUX_started$write_1__SEL_1 = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -12041,6 +12041,18 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = commitStage_rg_serial_num + y__h734147 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = (k__h670531 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105) ? { fetchStage$pipelines_0_first[199:195], @@ -12066,18 +12078,6 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -13877,13 +13877,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -13899,12 +13899,12 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or @@ -14142,12 +14142,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -14277,13 +14277,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -14300,12 +14300,12 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or @@ -14323,11 +14323,11 @@ module mkCore(CLK, default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -14675,13 +14675,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14883,10 +14883,10 @@ module mkCore(CLK, WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15231,8 +15231,8 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data @@ -15490,9 +15490,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -16749,7 +16749,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN = 1'd1 ; assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN = - MUX_flush_reservation$write_1__SEL_2 ; + MUX_flush_reservation$write_1__SEL_1 ; // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = @@ -20942,8 +20942,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 = (_theResult___fst_exp__h589266 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == @@ -21536,8 +21536,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 = (_theResult___fst_exp__h598099 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == @@ -21558,8 +21558,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 = (_theResult___fst_exp__h598099 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21569,8 +21569,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 = (_theResult____h651123 == 16'd0 && (csrf_prv_reg == 2'd0 || @@ -23780,12 +23780,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], x__h302154 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 = - !MUX_flush_reservation$write_1__SEL_2 && + !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 = - MUX_flush_reservation$write_1__SEL_2 ? + MUX_flush_reservation$write_1__SEL_1 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -24241,10 +24241,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139 = @@ -24258,10 +24258,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 && IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14083) ; + rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && @@ -25549,9 +25549,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 ; - assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_RDY_ETC___d15380 = + assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25590,7 +25590,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012 = !specTagManager$canClaim || @@ -26691,7 +26691,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo20 = + assign _dfoo22 = commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 ; assign _dfoo24 = @@ -27719,7 +27719,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; assign _theResult___fst_exp__h501523 = 11'd897 - { 5'd0, @@ -27875,7 +27875,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; assign _theResult___fst_exp__h540376 = 11'd897 - { 5'd0, @@ -28008,7 +28008,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 : + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ; assign _theResult___fst_exp__h559578 = (_theResult___fst_exp__h558795 == 11'd2047) ? @@ -28134,7 +28134,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 : + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ; assign _theResult___fst_exp__h590098 = (_theResult___fst_exp__h589266 == 11'd2047) ? @@ -28289,7 +28289,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; assign _theResult___fst_sfd__h502288 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && @@ -30193,13 +30193,13 @@ module mkCore(CLK, csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440 ; - assign data75286_BITS_31_TO_0__q14 = data__h475286[31:0] ; + assign data75286_BITS_31_TO_0__q13 = data__h475286[31:0] ; assign data___1__h475012 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; assign data___1__h475820 = - { {32{data75286_BITS_31_TO_0__q14[31]}}, - data75286_BITS_31_TO_0__q14 } ; + { {32{data75286_BITS_31_TO_0__q13[31]}}, + data75286_BITS_31_TO_0__q13 } ; assign data__h475286 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? @@ -30306,12 +30306,14 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609380 = { 56'd0, x__h613038 } ; - assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14083 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31100,14 +31102,13 @@ module mkCore(CLK, assign r___1__h475911 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31605,13 +31606,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612210 = { r1__read__h614604, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4341_AND_rob_RDY_deqPor_ETC___d15003 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 ; + assign rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -32900,27 +32900,6 @@ module mkCore(CLK, default: rVal1__h633783 = 64'b0; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -33038,45 +33017,66 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33232,17 +33232,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[31:0]; - 1'd1: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[63:32]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:18]) 2'd0: @@ -33260,6 +33249,17 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19]) + 1'd0: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[31:0]; + 1'd1: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[63:32]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33759,28 +33759,80 @@ module mkCore(CLK, default: _theResult___fst_sfd__h372561 = 23'd0; endcase end + always@(guard__h372574 or + _theResult___snd__h380597 or + out_sfd__h381122 or _theResult___sfd__h381119) + begin + case (guard__h372574) + 2'b0, 2'b01: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 = + _theResult___snd__h380597[56:34]; + 2'b10: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 = + out_sfd__h381122; + 2'b11: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 = + _theResult___sfd__h381119; + endcase + end + always@(guard__h372574 or + _theResult___snd__h380597 or _theResult___sfd__h381119) + begin + case (guard__h372574) + 2'b0: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = + _theResult___snd__h380597[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = + _theResult___sfd__h381119; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 or + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or + _theResult___snd__h380597) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h381197 = + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53; + 3'd1: + _theResult___fst_sfd__h381197 = + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54; + 3'd2: + _theResult___fst_sfd__h381197 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; + 3'd3: + _theResult___fst_sfd__h381197 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; + 3'd4: _theResult___fst_sfd__h381197 = _theResult___snd__h380597[56:34]; + default: _theResult___fst_sfd__h381197 = 23'd0; + endcase + end always@(guard__h346099 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h346099) 2'b0, 2'b01, 2'b10: - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = guard__h346099 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or guard__h346099) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53; + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = (guard__h346099 == 2'b0) ? @@ -33797,58 +33849,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372574 or - _theResult___snd__h380597 or - out_sfd__h381122 or _theResult___sfd__h381119) - begin - case (guard__h372574) - 2'b0, 2'b01: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = - _theResult___snd__h380597[56:34]; - 2'b10: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = - out_sfd__h381122; - 2'b11: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = - _theResult___sfd__h381119; - endcase - end - always@(guard__h372574 or - _theResult___snd__h380597 or _theResult___sfd__h381119) - begin - case (guard__h372574) - 2'b0: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55 = - _theResult___snd__h380597[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55 = - _theResult___sfd__h381119; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 or - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___snd__h380597) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h381197 = - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54; - 3'd1: - _theResult___fst_sfd__h381197 = - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55; - 3'd2: - _theResult___fst_sfd__h381197 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; - 3'd3: - _theResult___fst_sfd__h381197 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_sfd__h381197 = _theResult___snd__h380597[56:34]; - default: _theResult___fst_sfd__h381197 = 23'd0; - endcase - end always@(guard__h346099 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34501,28 +34501,80 @@ module mkCore(CLK, default: _theResult___fst_sfd__h418258 = 23'd0; endcase end + always@(guard__h418271 or + _theResult___snd__h426294 or + out_sfd__h426819 or _theResult___sfd__h426816) + begin + case (guard__h418271) + 2'b0, 2'b01: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 = + _theResult___snd__h426294[56:34]; + 2'b10: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 = + out_sfd__h426819; + 2'b11: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 = + _theResult___sfd__h426816; + endcase + end + always@(guard__h418271 or + _theResult___snd__h426294 or _theResult___sfd__h426816) + begin + case (guard__h418271) + 2'b0: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = + _theResult___snd__h426294[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = + _theResult___sfd__h426816; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 or + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or + _theResult___snd__h426294) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h426894 = + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88; + 3'd1: + _theResult___fst_sfd__h426894 = + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89; + 3'd2: + _theResult___fst_sfd__h426894 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; + 3'd3: + _theResult___fst_sfd__h426894 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; + 3'd4: _theResult___fst_sfd__h426894 = _theResult___snd__h426294[56:34]; + default: _theResult___fst_sfd__h426894 = 23'd0; + endcase + end always@(guard__h391798 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (guard__h391798) 2'b0, 2'b01, 2'b10: - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = guard__h391798 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or guard__h391798) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = (guard__h391798 == 2'b0) ? @@ -34539,58 +34591,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418271 or - _theResult___snd__h426294 or - out_sfd__h426819 or _theResult___sfd__h426816) - begin - case (guard__h418271) - 2'b0, 2'b01: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = - _theResult___snd__h426294[56:34]; - 2'b10: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = - out_sfd__h426819; - 2'b11: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = - _theResult___sfd__h426816; - endcase - end - always@(guard__h418271 or - _theResult___snd__h426294 or _theResult___sfd__h426816) - begin - case (guard__h418271) - 2'b0: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90 = - _theResult___snd__h426294[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90 = - _theResult___sfd__h426816; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 or - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___snd__h426294) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h426894 = - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89; - 3'd1: - _theResult___fst_sfd__h426894 = - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90; - 3'd2: - _theResult___fst_sfd__h426894 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; - 3'd3: - _theResult___fst_sfd__h426894 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_sfd__h426894 = _theResult___snd__h426294[56:34]; - default: _theResult___fst_sfd__h426894 = 23'd0; - endcase - end always@(guard__h391798 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -35333,66 +35333,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h437493 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h437493) - 2'b0, 2'b01, 2'b10: - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h437493 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h437493) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - (guard__h437493 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h437493 != 2'b01 && guard__h437493 != 2'b10 && - guard__h437493 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end always@(guard__h446200 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (guard__h446200) 2'b0, 2'b01, 2'b10: - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = guard__h446200 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or guard__h446200) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = (guard__h446200 == 2'b0) ? @@ -35409,6 +35371,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end + always@(guard__h437493 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h437493) + 2'b0, 2'b01, 2'b10: + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h437493 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h437493) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + (guard__h437493 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h437493 != 2'b01 && guard__h437493 != 2'b10 && + guard__h437493 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end always@(guard__h446200 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -35738,58 +35738,16 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h502883 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h502883) - 2'b0, 2'b01, 2'b10: - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 2'd3: - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h502883 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502883) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h502883 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h502883 == 2'b01 || guard__h502883 == 2'b10 || - guard__h502883 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end always@(guard__h511952 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h511952) 2'b0, 2'b01, 2'b10: - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = guard__h511952 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && @@ -35800,12 +35758,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = (guard__h511952 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && @@ -35815,6 +35773,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(guard__h502883 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h502883) + 2'b0, 2'b01, 2'b10: + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 2'd3: + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h502883 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502883) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + (guard__h502883 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171] : + (guard__h502883 == 2'b01 || guard__h502883 == 2'b10 || + guard__h502883 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -36029,21 +36029,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571728 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590109 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571728) + case (guard__h590109) 2'b0, 2'b01, 2'b10: - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h571728 != 2'b11 || + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h590109 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571728) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590109) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36052,12 +36052,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h571728 == 2'b0) ? + (guard__h590109 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h571728 != 2'b01 && guard__h571728 != 2'b10 && - guard__h571728 != 2'b11 || + guard__h590109 != 2'b01 && guard__h590109 != 2'b10 && + guard__h590109 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36068,21 +36068,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590109 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571728 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590109) + case (guard__h571728) 2'b0, 2'b01, 2'b10: - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h590109 != 2'b11 || + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h571728 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590109) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571728) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36091,12 +36091,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h590109 == 2'b0) ? + (guard__h571728 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h590109 != 2'b01 && guard__h590109 != 2'b10 && - guard__h590109 != 2'b11 || + guard__h571728 != 2'b01 && guard__h571728 != 2'b10 && + guard__h571728 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36209,66 +36209,15 @@ module mkCore(CLK, _theResult___exp__h550691; endcase end - always@(guard__h581040 or - _theResult___fst_exp__h589266 or _theResult___exp__h589995) - begin - case (guard__h581040) - 2'b0: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187 = - _theResult___fst_exp__h589266; - 2'b01, 2'b10, 2'b11: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187 = - _theResult___exp__h589995; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h589266 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - _theResult___fst_exp__h589266; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - 11'd0; - endcase - end - always@(guard__h581040 or - _theResult___fst_exp__h589266 or - out_exp__h589998 or _theResult___exp__h589995) - begin - case (guard__h581040) - 2'b0, 2'b01: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 = - _theResult___fst_exp__h589266; - 2'b10: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 = - out_exp__h589998; - 2'b11: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 = - _theResult___exp__h589995; - endcase - end always@(guard__h550805 or _theResult___fst_exp__h558795 or _theResult___exp__h559475) begin case (guard__h550805) 2'b0: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187 = _theResult___fst_exp__h558795; 2'b01, 2'b10, 2'b11: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187 = _theResult___exp__h559475; endcase end @@ -36276,7 +36225,7 @@ module mkCore(CLK, _theResult___fst_exp__h558795 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189) + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36290,7 +36239,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189; + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = 11'd0; endcase @@ -36301,16 +36250,67 @@ module mkCore(CLK, begin case (guard__h550805) 2'b0, 2'b01: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 = _theResult___fst_exp__h558795; 2'b10: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 = out_exp__h559478; 2'b11: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 = _theResult___exp__h559475; endcase end + always@(guard__h581040 or + _theResult___fst_exp__h589266 or _theResult___exp__h589995) + begin + case (guard__h581040) + 2'b0: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189 = + _theResult___fst_exp__h589266; + 2'b01, 2'b10, 2'b11: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189 = + _theResult___exp__h589995; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h589266 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + _theResult___fst_exp__h589266; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + 11'd0; + endcase + end + always@(guard__h581040 or + _theResult___fst_exp__h589266 or + out_exp__h589998 or _theResult___exp__h589995) + begin + case (guard__h581040) + 2'b0, 2'b01: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 = + _theResult___fst_exp__h589266; + 2'b10: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 = + out_exp__h589998; + 2'b11: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 = + _theResult___exp__h589995; + endcase + end always@(guard__h590109 or _theResult___fst_exp__h598099 or _theResult___exp__h598779) begin @@ -37849,17 +37849,6 @@ module mkCore(CLK, coreFix_aluExe_1_rsAlu$RDY_enq; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or @@ -37879,6 +37868,17 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or @@ -38083,10 +38083,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -38094,10 +38094,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = - coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -38390,16 +38390,6 @@ module mkCore(CLK, default: data_warl_xformed__h723335 = rob$deqPort_0_deq_data[95:32]; endcase end - always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196) - begin - case (rob$deqPort_0_deq_data[329:325]) - 5'd19, 5'd20: - x__h723943 = - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196; - default: x__h723943 = rob$deqPort_0_deq_data[425:362]; - endcase - end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) @@ -38453,6 +38443,16 @@ module mkCore(CLK, 12'd2303; endcase end + always@(rob$deqPort_0_deq_data or + IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196) + begin + case (rob$deqPort_0_deq_data[329:325]) + 5'd19, 5'd20: + x__h723943 = + IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196; + default: x__h723943 = rob$deqPort_0_deq_data[425:362]; + endcase + end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[165:162]) diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index a353d3a..bb0d3be 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -2716,22 +2716,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - debug_module$RDY_hart0_reset_client_response_put && - proc$RDY_start) && + proc$RDY_start && + debug_module$RDY_hart0_reset_client_response_put) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - debug_module$RDY_hart0_client_run_halt_request_get && - proc$RDY_hart0_run_halt_server_request_put ; + proc$RDY_hart0_run_halt_server_request_put && + debug_module$RDY_hart0_client_run_halt_request_get ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - debug_module$RDY_hart0_client_run_halt_response_put && - proc$RDY_hart0_run_halt_server_response_get ; + proc$RDY_hart0_run_halt_server_response_get && + debug_module$RDY_hart0_client_run_halt_response_put ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2743,25 +2743,25 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - v_td2_to_td_0$RDY_in_put && proc$RDY_v_to_TV_0_get ; + proc$RDY_v_to_TV_0_get && v_td2_to_td_0$RDY_in_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_mkConnectionGetPut_2 assign CAN_FIRE_RL_mkConnectionGetPut_2 = - v_td2_to_td_0$RDY_out_get && tv_encode$RDY_v_cpu_in_0_put ; + tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0$RDY_out_get ; assign WILL_FIRE_RL_mkConnectionGetPut_2 = CAN_FIRE_RL_mkConnectionGetPut_2 ; // rule RL_mkConnectionGetPut_3 assign CAN_FIRE_RL_mkConnectionGetPut_3 = - v_td2_to_td_1$RDY_in_put && proc$RDY_v_to_TV_1_get ; + proc$RDY_v_to_TV_1_get && v_td2_to_td_1$RDY_in_put ; assign WILL_FIRE_RL_mkConnectionGetPut_3 = CAN_FIRE_RL_mkConnectionGetPut_3 ; // rule RL_mkConnectionGetPut_4 assign CAN_FIRE_RL_mkConnectionGetPut_4 = - v_td2_to_td_1$RDY_out_get && tv_encode$RDY_v_cpu_in_1_put ; + tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1$RDY_out_get ; assign WILL_FIRE_RL_mkConnectionGetPut_4 = CAN_FIRE_RL_mkConnectionGetPut_4 ; @@ -2787,22 +2787,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - dm_gpr_tap_ifc$RDY_client_response_put && - proc$RDY_hart0_gpr_mem_server_response_get ; + proc$RDY_hart0_gpr_mem_server_response_get && + dm_gpr_tap_ifc$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -2815,22 +2815,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; // rule RL_ClientServerResponse_4 assign CAN_FIRE_RL_ClientServerResponse_4 = - dm_csr_tap$RDY_client_response_put && - proc$RDY_hart0_csr_mem_server_response_get ; + proc$RDY_hart0_csr_mem_server_response_get && + dm_csr_tap$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_4 = CAN_FIRE_RL_ClientServerResponse_4 ; @@ -2935,15 +2935,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - dm_gpr_tap_ifc$RDY_client_request_get && - proc$RDY_hart0_gpr_mem_server_request_put ; + proc$RDY_hart0_gpr_mem_server_request_put && + dm_gpr_tap_ifc$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ClientServerRequest_4 assign CAN_FIRE_RL_ClientServerRequest_4 = - dm_csr_tap$RDY_client_request_get && - proc$RDY_hart0_csr_mem_server_request_put ; + proc$RDY_hart0_csr_mem_server_request_put && + dm_csr_tap$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_4 = CAN_FIRE_RL_ClientServerRequest_4 ; diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index 1b6b7c2..b1f7022 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1434,7 +1434,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && + corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 5c9ceee..8e3867b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -2104,8 +2104,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162844; - reg [31 : 0] v__h162380; + reg [31 : 0] v__h162860; + reg [31 : 0] v__h162396; reg [31 : 0] v__h5520; reg [31 : 0] v__h5693; reg [31 : 0] v__h5953; @@ -2116,13 +2116,13 @@ module mkProc(CLK, reg [31 : 0] v__h9480; reg [31 : 0] v__h9973; reg [31 : 0] v__h10136; - reg [31 : 0] v__h134337; - reg [31 : 0] v__h134504; - reg [31 : 0] v__h136607; - reg [31 : 0] v__h153951; - reg [31 : 0] v__h133718; - reg [31 : 0] v__h160645; - reg [31 : 0] v__h161153; + reg [31 : 0] v__h134353; + reg [31 : 0] v__h134520; + reg [31 : 0] v__h136623; + reg [31 : 0] v__h153967; + reg [31 : 0] v__h133734; + reg [31 : 0] v__h160661; + reg [31 : 0] v__h161169; reg [31 : 0] v__h2664; reg [31 : 0] v__h4337; reg [31 : 0] v__h5514; @@ -2133,280 +2133,282 @@ module mkProc(CLK, reg [31 : 0] v__h9474; reg [31 : 0] v__h9967; reg [31 : 0] v__h10130; - reg [31 : 0] v__h133712; - reg [31 : 0] v__h134331; - reg [31 : 0] v__h134498; - reg [31 : 0] v__h136601; - reg [31 : 0] v__h153945; - reg [31 : 0] v__h160639; - reg [31 : 0] v__h161147; - reg [31 : 0] v__h162374; - reg [31 : 0] v__h162838; + reg [31 : 0] v__h133728; + reg [31 : 0] v__h134347; + reg [31 : 0] v__h134514; + reg [31 : 0] v__h136617; + reg [31 : 0] v__h153961; + reg [31 : 0] v__h160655; + reg [31 : 0] v__h161163; + reg [31 : 0] v__h162390; + reg [31 : 0] v__h162854; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944, - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, - data64__h147777, - dword__h93782, - ld_data__h131939, - old_dword__h89472, - w1__h47861, - w1__h47866, - w2__h47862, - w2__h47868, - x__h47857; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948, + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915, + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883, + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885, + data64__h147793, + dword__h93798, + ld_data__h131955, + old_dword__h89488, + w1__h47877, + w1__h47882, + w2__h47878, + w2__h47884, + x__h47873; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147778; - reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; + reg [7 : 0] strb8__h147794; + reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61575; + reg [2 : 0] x__h61591; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, - x__h61582, - x__h82300; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - new_cline__h134640; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; - wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - data__h31950, - failed_testnum__h162423, - line_addr__h101846, - line_addr__h101932, - mask__h89469, - mem_req_rd_addr_araddr__h133938, - mem_req_wr_addr_awaddr__h147862, - mmioPlatform_fromHostQ_data_0__h42651, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48453, - n__read_addr__h61443, - n__read_addr__h61528, - n__read_addr__h80062, - n__read_addr__h80141, - n__read_snd_addr__h123373, - newData__h32031, - newData__h34961, - new_dword__h89473, - op_result__h48469, - op_result__h48999, - op_result__h49004, - op_result__h49009, - op_result__h49014, + CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, + CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358, + x__h61598, + x__h82316; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, + new_cline__h134656; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; + wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, + data__h31966, + failed_testnum__h162439, + line_addr__h101862, + line_addr__h101948, + mask__h89485, + mem_req_rd_addr_araddr__h133954, + mem_req_wr_addr_awaddr__h147878, + mmioPlatform_fromHostQ_data_0__h42667, + mmioPlatform_mtime__h37280, + mmioPlatform_reqData__h48469, + n__read_addr__h61459, + n__read_addr__h61544, + n__read_addr__h80078, + n__read_addr__h80157, + n__read_snd_addr__h123389, + newData__h32047, + newData__h34977, + new_dword__h89489, + op_result__h48485, + op_result__h49015, op_result__h49020, - op_result__h49027, - op_result__h49033, - result__h47912, - result__h48036, - result__h48064, - result__h48092, - result__h48120, - result__h48148, - result__h48176, - result__h48204, - result__h48232, - result__h48277, - result__h48305, - result__h48333, - result__h48361, - result__h48402, - result__h48430, - result__h48556, - result__h48583, - result__h48610, - result__h48637, - result__h48664, - result__h48691, - result__h48718, - result__h48745, - result__h48789, - result__h48816, - result__h48843, - result__h48870, - result__h48910, - result__h48937, - result__h49054, - result__h49120, - result__h49186, - result__h49252, - result__h49318, - result__h49384, - result__h49450, - result__h49512, - result__h49557, - result__h49623, - result__h49689, - result__h49747, - result__h49792, - w1___1__h47971, - w2___1__h47972, - x1_avValue_data__h40323, - x1_avValue_data__h44790, - x__h32142, - x__h35052, - x__h37412, - x__h40841, - x__h40852, - x__h42861, - x__h42872, - x__h49969, - x__h90635, - y__h90636, - y__h90637; - wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; - wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987, + op_result__h49025, + op_result__h49030, + op_result__h49036, + op_result__h49043, + op_result__h49049, + result__h47928, + result__h48052, + result__h48080, + result__h48108, + result__h48136, + result__h48164, + result__h48192, + result__h48220, + result__h48248, + result__h48293, + result__h48321, + result__h48349, + result__h48377, + result__h48418, + result__h48446, + result__h48572, + result__h48599, + result__h48626, + result__h48653, + result__h48680, + result__h48707, + result__h48734, + result__h48761, + result__h48805, + result__h48832, + result__h48859, + result__h48886, + result__h48926, + result__h48953, + result__h49070, + result__h49136, + result__h49202, + result__h49268, + result__h49334, + result__h49400, + result__h49466, + result__h49528, + result__h49573, + result__h49639, + result__h49705, + result__h49763, + result__h49808, + w1___1__h47987, + w2___1__h47988, + x1_avValue_data__h40339, + x1_avValue_data__h44806, + x__h32158, + x__h35068, + x__h37428, + x__h40857, + x__h40868, + x__h42877, + x__h42888, + x__h49985, + x__h90651, + y__h90652, + y__h90653; + wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710; + wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w17861_BITS_31_TO_0__q15, - w27862_BITS_31_TO_0__q16, - x_data__h30533; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; - wire [5 : 0] x__h133973, x__h147887; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; - wire [3 : 0] b__h133645, b__h2564; - wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112, - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; - wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, - IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089, - IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458, - IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302, - IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, + v__h31759, + v__h31796, + w17877_BITS_31_TO_0__q15, + w27878_BITS_31_TO_0__q16, + x_data__h30549; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160; + wire [5 : 0] x__h133989, x__h147903; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159; + wire [3 : 0] b__h133661, b__h2564; + wire [2 : 0] n__read_id__h61463, n__read_id__h61548, x__h7925; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112, + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116, + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; + wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, + IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093, + IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462, + IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306, + IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966, + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254, - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004, - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173, - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180, - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011, - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091, - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360, - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258, + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008, + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177, + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184, + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015, + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095, + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364, + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373, - NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375, - NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088, - NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512, + NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377, + NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379, + NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092, + NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971, + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, + mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30134, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61448, - n__read_child__h61533, - n__read_child__h80065, - n__read_child__h80144, - n__read_snd_id__h123374, - propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, - propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, - x__h61261, - x__h74813, - x__h79884; + n__read_child__h61464, + n__read_child__h61549, + n__read_child__h80081, + n__read_child__h80160, + n__read_snd_id__h123390, + propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132, + propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136, + x__h61277, + x__h74829, + x__h79900; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3534,7 +3536,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 ; + IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3562,7 +3564,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 ; + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3723,8 +3725,9 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3741,7 +3744,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3750,7 +3753,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3796,7 +3799,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42861 == 64'd0 || + x__h42877 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3814,7 +3817,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3822,14 +3825,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3839,22 +3842,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 && + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3936,7 +3939,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3954,7 +3957,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3972,7 +3975,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3982,7 +3985,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -4002,7 +4005,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -4011,7 +4014,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4043,7 +4046,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4116,13 +4119,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133645 == 4'd0 ; + b__h133661 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133645 != 4'd0 && + b__h133661 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4132,7 +4135,8 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4140,22 +4144,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || + (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4180,14 +4184,10 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - core_0$mmioToPlatform_cRq_notEmpty) ; + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty ; + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -4222,20 +4222,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30549 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4249,35 +4249,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31966 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4291,10 +4291,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101846, + { line_addr__h101862, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101932, + { line_addr__h101948, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4302,28 +4302,29 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4334,7 +4335,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; + IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4347,11 +4348,12 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4362,32 +4364,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4395,29 +4397,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ? + (mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47857 } ; + x__h47873 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49985, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4427,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42877 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42861 != 64'd0 ; + x__h42877 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40841 == 64'd0 ; + x__h40857 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - x__h61261 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && + x__h61277 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - x__h79884 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && + x__h79900 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; + { 1'd1, n__read_snd_addr__h123389, n__read_snd_id__h123390 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4579,11 +4581,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133645 - 4'd1 ; + b__h133661 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133645 ; + b__h133661 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4595,10 +4597,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, + IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? + (NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4606,8 +4608,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, - IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 } ; + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, + IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4646,7 +4648,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133954, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4659,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147878, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147777, strb8__h147778, 1'd1 } ; + { data64__h147793, strb8__h147794, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4677,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134656 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4706,10 +4708,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, + IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4723,15 +4725,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101846 : - line_addr__h101932 ; + line_addr__h101862 : + line_addr__h101948 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4802,10 +4804,11 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4818,11 +4821,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 && + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4831,12 +4834,10 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4882,17 +4883,15 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34977 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4900,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32047 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4911,9 +4910,10 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4983,7 +4983,8 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -5047,7 +5048,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5055,15 +5056,16 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5149,28 +5151,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, + { IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 } ; + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, + { IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 } ; + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5183,36 +5185,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 ; + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 ; + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5321,7 +5323,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131939, llc$dma_respLd_first[3] } ; + { ld_data__h131955, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5342,13 +5344,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || + (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5359,15 +5361,16 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5424,7 +5427,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5433,7 +5436,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5465,17 +5468,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; + { IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134640, + { new_cline__h134656, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5554,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93782, 3'd1 } ; + { 4'd0, dword__h93798, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5602,7 +5605,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5632,11 +5635,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5854,86 +5857,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37428), + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h32158)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37280), + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h35068)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40852)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42667), + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h40868)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h42872)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h42888)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40323 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + x1_avValue_data__h40339 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = - NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = + newData__h32047 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093 = + NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 : + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358 = - NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ? + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362 = + NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 : + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 = - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; - assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; + assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5941,116 +5944,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? + assign IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 = + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 = + assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - x__h74813 } ; - assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, + x__h74829 } ; + assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, - IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, + IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -6063,23 +6066,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -6092,23 +6095,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6121,49 +6124,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42861 == 64'd0 : - x__h40841 == 64'd0, + x__h42877 == 64'd0 : + x__h40857 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44790 } ; + x1_avValue_data__h44806 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = + assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6171,99 +6174,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 = + assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 = + assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 = + assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 = + assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 = + assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 = + assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 = + assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 = + assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112 = + assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122 = + assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 = + assign IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 = + assign IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 = + assign IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 = + assign IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 = + assign NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 || - IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089) ; - assign NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 || + IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093) ; + assign NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6274,7 +6277,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6285,7 +6288,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6297,7 +6300,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6309,7 +6312,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6319,7 +6322,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6339,29 +6342,35 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = + !mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || + core_0$mmioToPlatform_cRq_notEmpty ; + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -6375,51 +6384,51 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 = + assign NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375 = + assign NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 = + assign NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 = + assign NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = - { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = - { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - x__h82300 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = - { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = - { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - x__h61575, - x__h61582 } ; - assign b__h133645 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 = + { CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 = + { CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, + x__h82316 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399 = + { CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 = + { CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, + x__h61591, + x__h61598 } ; + assign b__h133661 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6427,23 +6436,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31966 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h162423 = + { v__h31759, 32'd0 } ; + assign failed_testnum__h162439 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101846 = + assign line_addr__h101862 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101932 = + assign line_addr__h101948 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = - line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = - line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89469 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 = + line_addr__h101948 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 = + line_addr__h101862 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89485 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6477,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133938 = - { llc$to_mem_toM_first[68:11], x__h133973 } ; - assign mem_req_wr_addr_awaddr__h147862 = - { llc$to_mem_toM_first[639:582], x__h147887 } ; + assign mem_req_rd_addr_araddr__h133954 = + { llc$to_mem_toM_first[68:11], x__h133989 } ; + assign mem_req_wr_addr_awaddr__h147878 = + { llc$to_mem_toM_first[639:582], x__h147903 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = + assign mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42651 = + assign mmioPlatform_fromHostQ_data_0__h42667 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,36 +6495,41 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + assign mmioPlatform_mtime__h37280 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = + mmioPlatform_mtimecmp_0 <= newData__h34977 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = + assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0) && + core_0$mmioToPlatform_cRq_notEmpty ; + assign mmioPlatform_reqBE_BIT_0___h30174 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30134 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48469 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6529,235 +6543,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61443 = + assign n__read_addr__h61459 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61528 = + assign n__read_addr__h61544 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80062 = + assign n__read_addr__h80078 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 : 64'd0 ; - assign n__read_addr__h80141 = + assign n__read_addr__h80157 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 : 64'd0 ; - assign n__read_child__h61448 = + assign n__read_child__h61464 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61533 = + assign n__read_child__h61549 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80065 = + assign n__read_child__h80081 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; - assign n__read_child__h80144 = + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 ; + assign n__read_child__h80160 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; - assign n__read_id__h61447 = + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 ; + assign n__read_id__h61463 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61532 = + assign n__read_id__h61548 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123373 = + assign n__read_snd_addr__h123389 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123374 = + assign n__read_snd_id__h123390 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32047 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + x__h32158 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; + assign newData__h34977 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h134640 = + x__h35068 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; + assign new_cline__h134656 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89473 = x__h90635 | y__h90636 ; - assign op_result__h48469 = - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; - assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; - assign op_result__h49004 = w1__h47866 & w2__h47868 ; - assign op_result__h49009 = w1__h47866 | w2__h47868 ; - assign op_result__h49014 = - (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; - assign op_result__h49020 = - (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; - assign op_result__h49027 = - ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ + assign new_dword__h89489 = x__h90651 | y__h90652 ; + assign op_result__h48485 = + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 + + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ; + assign op_result__h49015 = w1__h47882 ^ w2__h47884 ; + assign op_result__h49020 = w1__h47882 & w2__h47884 ; + assign op_result__h49025 = w1__h47882 | w2__h47884 ; + assign op_result__h49030 = + (w1__h47882 < w2__h47884) ? w1__h47882 : w2__h47884 ; + assign op_result__h49036 = + (w1__h47882 <= w2__h47884) ? w2__h47884 : w1__h47882 ; + assign op_result__h49043 = + ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ + (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ 64'h8000000000000000)) ? - w1__h47866 : - w2__h47868 ; - assign op_result__h49033 = - ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ + w1__h47882 : + w2__h47884 ; + assign op_result__h49049 = + ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ + (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ 64'h8000000000000000)) ? - w2__h47868 : - w1__h47866 ; - assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = + w2__h47884 : + w1__h47882 ; + assign propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132 = + assign propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47912 = + assign result__h47928 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; - assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48556 = + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0] } ; + assign result__h48052 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48080 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48108 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48136 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48164 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48192 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48220 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48248 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48293 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48321 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48349 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48377 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48418 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48446 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48572 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48583 = + assign result__h48599 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48610 = + assign result__h48626 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48637 = + assign result__h48653 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48664 = + assign result__h48680 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48691 = + assign result__h48707 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48718 = + assign result__h48734 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48745 = + assign result__h48761 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48789 = + assign result__h48805 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48816 = + assign result__h48832 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48843 = + assign result__h48859 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48870 = + assign result__h48886 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48910 = + assign result__h48926 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48937 = + assign result__h48953 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49054 = + assign result__h49070 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49120 = + assign result__h49136 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49186 = + assign result__h49202 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49252 = + assign result__h49268 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49318 = + assign result__h49334 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49384 = + assign result__h49400 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49450 = - { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + assign result__h49466 = + { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49512 = + assign result__h49528 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; - assign result__h49557 = + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0] } ; + assign result__h49573 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49623 = + assign result__h49639 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49689 = - { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], + assign result__h49705 = + { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49747 = + assign result__h49763 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; - assign result__h49792 = - { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0] } ; + assign result__h49808 = + { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; - assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; - assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; - assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; - assign x1_avValue_data__h40323 = + assign v__h31759 = mmioPlatform_waitUpperMSIPCRs ? v__h31796 : 32'd0 ; + assign v__h31796 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17877_BITS_31_TO_0__q15 = w1__h47877[31:0] ; + assign w1___1__h47987 = { 32'd0, w1__h47877[31:0] } ; + assign w27878_BITS_31_TO_0__q16 = w2__h47878[31:0] ; + assign w2___1__h47988 = { 32'd0, w2__h47878[31:0] } ; + assign x1_avValue_data__h40339 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44790 = + assign x1_avValue_data__h44806 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40841 = + assign x__h133989 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147903 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37428 = mmioPlatform_mtimecmp_0 ; + assign x__h40857 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40852 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; - assign x__h42861 = + x__h40868 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 ; + assign x__h42877 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42872 : + x__h42888 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6780,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61261 = - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? + assign x__h49985 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61277 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; - assign x__h74813 = + NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ; + assign x__h74829 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 ; assign x__h7925 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79884 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? + assign x__h79900 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; - assign x__h90635 = old_dword__h89472 & y__h90637 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90636 = + NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ; + assign x__h90651 = old_dword__h89488 & y__h90653 ; + assign x_data__h30549 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90652 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89469 ; - assign y__h90637 = + mask__h89485 ; + assign y__h90653 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,473 +7015,473 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[511:448]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat) + 3'd0: data64__h147793 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147793 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147793 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147793 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147793 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147793 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147793 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147793 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131955 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131955 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131955 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131955 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131955 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131955 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131955 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131955 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; - endcase - end - always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) - begin - case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147794 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147794 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147794 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147794 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147794 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147794 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147794 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147794 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48036 or - result__h48064 or - result__h48092 or - result__h48120 or - result__h48148 or - result__h48176 or result__h48204 or result__h48232) + result__h48052 or + result__h48080 or + result__h48108 or + result__h48136 or + result__h48164 or + result__h48192 or result__h48220 or result__h48248) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48036; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48052; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48064; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48080; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48092; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48108; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48120; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48136; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48148; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48164; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48176; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48192; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48204; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48220; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48232; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48248; endcase end always@(mmioPlatform_curReq or - result__h48277 or - result__h48305 or result__h48333 or result__h48361) + result__h48293 or + result__h48321 or result__h48349 or result__h48377) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48277; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48293; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48305; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48321; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48333; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48349; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48361; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48377; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48402 or result__h48430) + always@(mmioPlatform_curReq or result__h48418 or result__h48446) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48402; + result__h48418; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48430; + result__h48446; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47862 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; + w2__h47878 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; 2'b01: - w2__h47862 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; + w2__h47878 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; 2'b10: - w2__h47862 = + w2__h47878 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47862 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + w2__h47878 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w2___1__h47972 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or + w2___1__h47988 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47868 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; + w2__h47884 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; 2'b01: - w2__h47868 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; - 2'b10: w2__h47868 = w2___1__h47972; + w2__h47884 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; + 2'b10: w2__h47884 = w2___1__h47988; 2'b11: - w2__h47868 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + w2__h47884 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_curReq or - result__h48789 or - result__h48816 or result__h48843 or result__h48870) + result__h48572 or + result__h48599 or + result__h48626 or + result__h48653 or + result__h48680 or + result__h48707 or result__h48734 or result__h48761) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48789; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48572; + 3'h1: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48599; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48816; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48626; + 3'h3: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48653; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48843; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48680; + 3'h5: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48707; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48870; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48734; + 3'h7: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48761; + endcase + end + always@(mmioPlatform_curReq or + result__h48805 or + result__h48832 or result__h48859 or result__h48886) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48805; + 3'h2: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48832; + 3'h4: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48859; + 3'h6: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48886; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h48556 or - result__h48583 or - result__h48610 or - result__h48637 or - result__h48664 or - result__h48691 or result__h48718 or result__h48745) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48556; - 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48583; - 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48610; - 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48637; - 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48664; - 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48691; - 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48718; - 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48745; - endcase - end - always@(mmioPlatform_curReq or result__h48910 or result__h48937) + always@(mmioPlatform_curReq or result__h48926 or result__h48953) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48910; + result__h48926; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48937; + result__h48953; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47861 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; + w1__h47877 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; 2'b01: - w1__h47861 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; + w1__h47877 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; 2'b10: - w1__h47861 = + w1__h47877 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47861 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; + w1__h47877 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w1___1__h47971 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or + w1___1__h47987 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47866 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; + w1__h47882 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; 2'b01: - w1__h47866 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; - 2'b10: w1__h47866 = w1___1__h47971; + w1__h47882 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; + 2'b10: w1__h47882 = w1___1__h47987; 2'b11: - w1__h47866 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; + w1__h47882 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w17861_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or + w17877_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; 2'b01: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; 2'b10: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - { {32{w17861_BITS_31_TO_0__q15[31]}}, - w17861_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + { {32{w17877_BITS_31_TO_0__q15[31]}}, + w17877_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w27862_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or + w27878_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; 2'b01: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; 2'b10: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - { {32{w27862_BITS_31_TO_0__q16[31]}}, - w27862_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + { {32{w27878_BITS_31_TO_0__q16[31]}}, + w27878_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49033 or - w2__h47868 or - op_result__h48469 or - op_result__h48999 or - op_result__h49004 or - op_result__h49009 or - op_result__h49027 or op_result__h49014 or op_result__h49020) + op_result__h49049 or + w2__h47884 or + op_result__h48485 or + op_result__h49015 or + op_result__h49020 or + op_result__h49025 or + op_result__h49043 or op_result__h49030 or op_result__h49036) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - w2__h47868; + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + w2__h47884; 4'd1: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48469; + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h48485; 4'd2: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48999; + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49015; 4'd3: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49004; - 4'd4: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49009; - 4'd5: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49027; - 4'd7: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49014; - 4'd8: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = op_result__h49020; - default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49033; + 4'd4: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49025; + 4'd5: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49043; + 4'd7: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49030; + 4'd8: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49036; + default: IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49049; endcase end always@(mmioPlatform_curReq or - result__h49512 or - result__h49557 or result__h49623 or result__h49689) + result__h49528 or + result__h49573 or result__h49639 or result__h49705) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49512; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49528; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49557; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49573; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49623; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49639; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49689; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49705; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47912 or - result__h49054 or - result__h49120 or - result__h49186 or - result__h49252 or - result__h49318 or result__h49384 or result__h49450) + result__h47928 or + result__h49070 or + result__h49136 or + result__h49202 or + result__h49268 or + result__h49334 or result__h49400 or result__h49466) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h47912; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h47928; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49054; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49070; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49120; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49136; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49186; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49202; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49252; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49268; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49318; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49334; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49384; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49400; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49450; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49466; endcase end - always@(mmioPlatform_curReq or result__h49747 or result__h49792) + always@(mmioPlatform_curReq or result__h49763 or result__h49808) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49747; + result__h49763; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49792; + result__h49808; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - x__h47857 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; + x__h47873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939; 2'b01: - x__h47857 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; + x__h47873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948; 2'b10: - x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47873 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47857 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + x__h47873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7475,15 +7489,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7491,11 +7505,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7503,315 +7517,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 or + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011) + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004; + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011; + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 or + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180) + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173; + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184; endcase end - always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) + always@(x__h61277 or n__read_id__h61463 or n__read_id__h61548) begin - case (x__h61261) - 1'd0: x__h61575 = n__read_id__h61447; - 1'd1: x__h61575 = n__read_id__h61532; + case (x__h61277) + 1'd0: x__h61591 = n__read_id__h61463; + 1'd1: x__h61591 = n__read_id__h61548; endcase end - always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) + always@(x__h61277 or n__read_child__h61464 or n__read_child__h61549) begin - case (x__h61261) - 1'd0: x__h61582 = n__read_child__h61448; - 1'd1: x__h61582 = n__read_child__h61533; + case (x__h61277) + 1'd0: x__h61598 = n__read_child__h61464; + 1'd1: x__h61598 = n__read_child__h61549; endcase end - always@(x__h61261 or - propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or - propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) + always@(x__h61277 or + propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 or + propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = - propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; + CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = + propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132; 1'd1: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = - propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; + CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = + propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136; endcase end - always@(x__h61261 or - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) + always@(x__h61277 or + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 or + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116; endcase end - always@(x__h61261 or - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) + always@(x__h61277 or + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 or + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; endcase end - always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) + always@(x__h61277 or n__read_addr__h61459 or n__read_addr__h61544) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61443; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = + n__read_addr__h61459; 1'd1: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61528; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = + n__read_addr__h61544; endcase end - always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) - begin - case (x__h79884) - 1'd0: x__h82300 = n__read_child__h80065; - 1'd1: x__h82300 = n__read_child__h80144; - endcase - end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79884 or + always@(x__h79900 or n__read_child__h80081 or n__read_child__h80160) + begin + case (x__h79900) + 1'd0: x__h82316 = n__read_child__h80081; + 1'd1: x__h82316 = n__read_child__h80160; + endcase + end + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79884 or + always@(x__h79900 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 : 2'd0; 1'd1: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 : 2'd0; endcase end - always@(x__h79884 or - NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or - NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) + always@(x__h79900 or + NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 or + NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; + CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377; 1'd1: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; + CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379; endcase end - always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) + always@(x__h79900 or n__read_addr__h80078 or n__read_addr__h80157) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80062; + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = + n__read_addr__h80078; 1'd1: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80141; + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = + n__read_addr__h80157; endcase end @@ -8227,14 +8241,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162844 = $stime; + v__h162860 = $stime; #0; end - v__h162838 = v__h162844 / 32'd10; + v__h162854 = v__h162860 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162838, + v__h162854, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8244,14 +8258,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162380 = $stime; + v__h162396 = $stime; #0; end - v__h162374 = v__h162380 / 32'd10; + v__h162390 = v__h162396 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162374, + v__h162390, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8261,7 +8275,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162423); + $display("FAIL %0d", failed_testnum__h162439); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9826,85 +9840,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) begin - v__h134337 = $stime; + v__h134353 = $stime; #0; end - v__h134331 = v__h134337 / 32'd10; + v__h134347 = v__h134353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134331, + v__h134347, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134504 = $stime; + v__h134520 = $stime; #0; end - v__h134498 = v__h134504 / 32'd10; + v__h134514 = v__h134520 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134498); + v__h134514); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9966,135 +9980,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136607 = $stime; + v__h136623 = $stime; #0; end - v__h136601 = v__h136607 / 32'd10; + v__h136617 = v__h136623 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136601); + v__h136617); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11292,169 +11306,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153951 = $stime; + v__h153967 = $stime; #0; end - v__h153945 = v__h153951 / 32'd10; + v__h153961 = v__h153967 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153945); + $display("%0d: ERROR: CreditCounter: overflow", v__h153961); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_wr_addr_awaddr__h147862); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", mem_req_wr_addr_awaddr__h147878); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", data64__h147777); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", data64__h147793); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", strb8__h147778); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", strb8__h147794); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133718 = $stime; + v__h133734 = $stime; #0; end - v__h133712 = v__h133718 / 32'd10; + v__h133728 = v__h133734 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133712, + v__h133728, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11525,159 +11539,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_rd_addr_araddr__h133938); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", mem_req_rd_addr_araddr__h133954); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) begin - v__h160645 = $stime; + v__h160661 = $stime; #0; end - v__h160639 = v__h160645 / 32'd10; + v__h160655 = v__h160661 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160639, + v__h160655, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161153 = $stime; + v__h161169 = $stime; #0; end - v__h161147 = v__h161153 / 32'd10; + v__h161163 = v__h161169 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161147); + v__h161163); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index dc1eedb..f251e7c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -4375,7 +4375,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2, - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1, MUX_rob$setExecuted_deqLSQ_2__VAL_2, @@ -4511,7 +4511,7 @@ module mkCore(CLK, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, - MUX_flush_reservation$write_1__SEL_2, + MUX_flush_reservation$write_1__SEL_1, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -4535,7 +4535,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_started$write_1__SEL_1, MUX_v_f_to_TV_0$enq_1__SEL_2; // remaining internal signals @@ -4571,7 +4570,7 @@ module mkCore(CLK, trap_val__h720333, x__h200595, x__h733185; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20, CASE_guard07812_0b0_sfdin16032_BITS_56_TO_5_0b_ETC__q217, @@ -4667,8 +4666,8 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, CASE_guard07812_0b0_theResult___fst_exp16038_0_ETC__q211, CASE_guard07812_0b0_theResult___fst_exp16038_0_ETC__q212, @@ -4817,20 +4816,20 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, CASE_guard04926_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94, CASE_guard04926_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93, - CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, CASE_guard13856_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, CASE_guard13856_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95, CASE_guard16881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, CASE_guard22692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98, CASE_guard22692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, CASE_guard37353_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard41914_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, CASE_guard41914_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, CASE_guard46665_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, + CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, + CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, CASE_guard50621_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, CASE_guard50621_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, CASE_guard55734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, @@ -4839,21 +4838,21 @@ module mkCore(CLK, CASE_guard59229_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58, CASE_guard59551_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, CASE_guard59551_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, - CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, + CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61, CASE_guard68159_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, CASE_guard68387_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, CASE_guard68387_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, CASE_guard76657_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, CASE_guard76657_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard76995_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, - CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, + CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, CASE_guard85969_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard95038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, - CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, - CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, + CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, + CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, CASE_k78117_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -5452,7 +5451,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, data78998_BITS_31_TO_0__q11, - data79892_BITS_31_TO_0__q15, + data79892_BITS_31_TO_0__q14, imm__h662592, r1__read__h619416, r1__read__h620599, @@ -6393,7 +6392,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13986, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14128, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14146, - NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_RDY_ETC___d15696, + NOT_rob_deqPort_0_canDeq__5654_5655_OR_regRena_ETC___d15696, NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_deq_ETC___d15980, NOT_rob_deqPort_0_deq_data__4651_BITS_329_TO_3_ETC___d15310, NOT_rob_deqPort_1_deq_data__5662_BIT_25_5663_5_ETC___d15693, @@ -6624,7 +6623,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14126, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14144, f_csr_rsps_i_notFull__6112_AND_f_csr_reqs_firs_ETC___d16215, - fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14328, + fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14268, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14457, @@ -6675,7 +6674,7 @@ module mkCore(CLK, next_deqP___1__h333412, next_deqP___1__h336637, r1__read_BIT_20___h663156, - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544, + regRenamingTable_RDY_commit_0_commit__5255_AND_ETC___d15315, regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14191, regRenamingTable_RDY_rename_1_getRename__4254__ETC___d14272, regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680, @@ -6704,7 +6703,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170, rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16051, - rob_RDY_deqPort_0_deq__4648_AND_rob_RDY_deqPor_ETC___d15315, + rob_RDY_enqPort_1_enq__4320_AND_NOT_fetchStage_ETC___d14328, tsr_val__h736420, tvm_val__h736422, v__h303710, @@ -9918,8 +9917,8 @@ module mkCore(CLK, // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_first && fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + fetchStage$RDY_iTlbIfc_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; @@ -9955,8 +9954,8 @@ module mkCore(CLK, // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - coreFix_memExe_dTlb$RDY_toParent_flush_response_put && fetchStage$RDY_iTlbIfc_toParent_flush_response_put && + coreFix_memExe_dTlb$RDY_toParent_flush_response_put && l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; @@ -10098,9 +10097,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -10450,8 +10449,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10505,7 +10504,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4648_AND_rob_RDY_deqPor_ETC___d15315 && + regRenamingTable_RDY_commit_0_commit__5255_AND_ETC___d15315 && NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15332 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10540,7 +10539,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_RDY_ETC___d15696 && + NOT_rob_deqPort_0_canDeq__5654_5655_OR_regRena_ETC___d15696 && NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15708 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11222,16 +11221,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush && + commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -11239,7 +11238,9 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_debug_resume = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -11532,9 +11533,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13290 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11546,8 +11548,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13600 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11648,7 +11650,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -12079,7 +12082,7 @@ module mkCore(CLK, assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; - assign MUX_flush_reservation$write_1__SEL_2 = + assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -12136,9 +12139,6 @@ module mkCore(CLK, assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && coreFix_memExe_lsq$firstLd[89] ; - assign MUX_started$write_1__SEL_1 = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -12157,6 +12157,18 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = commitStage_rg_serial_num + y__h743778 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = (k__h678117 == 1'd0 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350) ? { fetchStage$pipelines_0_first[199:195], @@ -12182,18 +12194,6 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -12213,7 +12213,7 @@ module mkCore(CLK, { 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 = { 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 = { 1'd1, coreFix_memExe_lsq$getHit[7:1] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? @@ -14052,13 +14052,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -14074,12 +14074,12 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 ; + NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or @@ -14317,12 +14317,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 ; + NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -14452,13 +14452,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -14475,12 +14475,12 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 ; + NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or @@ -14498,11 +14498,11 @@ module mkCore(CLK, default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -14850,13 +14850,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -15058,10 +15058,10 @@ module mkCore(CLK, WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15406,8 +15406,8 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data @@ -15619,7 +15619,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -15631,10 +15631,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_aluExe_0_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_aluExe_0_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; default: coreFix_aluExe_0_rsAlu$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -15665,9 +15665,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -15932,7 +15932,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -15944,10 +15944,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_aluExe_1_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_aluExe_1_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; default: coreFix_aluExe_1_rsAlu$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -16579,7 +16579,7 @@ module mkCore(CLK, MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -16591,10 +16591,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -16927,7 +16927,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN = 1'd1 ; assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN = - MUX_flush_reservation$write_1__SEL_2 ; + MUX_flush_reservation$write_1__SEL_1 ; // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = @@ -18014,7 +18014,7 @@ module mkCore(CLK, MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -18026,10 +18026,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_memExe_rsMem$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_memExe_rsMem$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; default: coreFix_memExe_rsMem$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -21108,8 +21108,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10806 = (_theResult___fst_exp__h554891 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21130,8 +21130,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; + CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9769 = (_theResult___fst_exp__h594195 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == @@ -21141,8 +21141,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410 = (guard__h350520 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? @@ -21746,8 +21746,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; + CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059 = (_theResult____h658381 == 16'd0 && (csrf_prv_reg == 2'd0 || @@ -22384,8 +22384,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; + CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8759 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 || @@ -22397,8 +22397,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9474 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 || @@ -23945,12 +23945,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], x__h306575 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3104 = - !MUX_flush_reservation$write_1__SEL_2 && + !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3112 = - MUX_flush_reservation$write_1__SEL_2 ? + MUX_flush_reservation$write_1__SEL_1 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -24406,10 +24406,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14204 = IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14401 = @@ -24423,10 +24423,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14291 && IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14083 && (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14318 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14328) ; + rob_RDY_enqPort_1_enq__4320_AND_NOT_fetchStage_ETC___d14328) ; assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14618 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && @@ -25769,9 +25769,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13975 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14144 ; - assign NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_RDY_ETC___d15696 = + assign NOT_rob_deqPort_0_canDeq__5654_5655_OR_regRena_ETC___d15696 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25810,7 +25810,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14257 = !specTagManager$canClaim || @@ -27945,7 +27945,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; assign _theResult___fst_exp__h506452 = 11'd897 - { 5'd0, @@ -28101,7 +28101,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; assign _theResult___fst_exp__h545305 = 11'd897 - { 5'd0, @@ -28515,7 +28515,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; assign _theResult___fst_sfd__h507217 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && @@ -30518,13 +30518,13 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13686 ; assign data78998_BITS_31_TO_0__q11 = data__h478998[31:0] ; - assign data79892_BITS_31_TO_0__q15 = data__h479892[31:0] ; + assign data79892_BITS_31_TO_0__q14 = data__h479892[31:0] ; assign data___1__h479510 = { {32{data78998_BITS_31_TO_0__q11[31]}}, data78998_BITS_31_TO_0__q11 } ; assign data___1__h480404 = - { {32{data79892_BITS_31_TO_0__q15[31]}}, - data79892_BITS_31_TO_0__q15 } ; + { {32{data79892_BITS_31_TO_0__q14[31]}}, + data79892_BITS_31_TO_0__q14 } ; assign data__h478998 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? @@ -30644,12 +30644,14 @@ module mkCore(CLK, fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; assign fcsr_csr__read__h615717 = { 56'd0, x__h619375 } ; - assign fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14328 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14324) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14268 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31438,14 +31440,13 @@ module mkCore(CLK, assign r___1__h480506 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__5255_AND_ETC___d15315 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4651_BITS_329_TO_3_ETC___d15310 ; assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14191 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31974,13 +31975,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h618547 = { r1__read__h620941, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4648_AND_rob_RDY_deqPor_ETC___d15315 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4651_BITS_329_TO_3_ETC___d15310 ; + assign rob_RDY_enqPort_1_enq__4320_AND_NOT_fetchStage_ETC___d14328 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14324) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4651_BITS_161_TO_98_46_ETC___d15630 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -33265,27 +33265,6 @@ module mkCore(CLK, default: rVal1__h640618 = 64'b0; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -33403,45 +33382,66 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -34181,61 +34181,23 @@ module mkCore(CLK, begin case (guard__h350520) 2'b0, 2'b01, 2'b10: - CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - guard__h350520 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or - guard__h350520) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - (guard__h350520 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h350520 != 2'b01 && guard__h350520 != 2'b10 && - guard__h350520 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(guard__h350520 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h350520) - 2'b0, 2'b01, 2'b10: - CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = guard__h350520 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or guard__h350520) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = - CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + CASE_guard50520_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = (guard__h350520 == 2'b0) ? @@ -34252,6 +34214,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h350520 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h350520) + 2'b0, 2'b01, 2'b10: + CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + guard__h350520 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or + guard__h350520) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = + CASE_guard50520_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = + (guard__h350520 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + guard__h350520 != 2'b01 && guard__h350520 != 2'b10 && + guard__h350520 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h359229 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34366,66 +34366,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376995 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h376995) - 2'b0, 2'b01, 2'b10: - CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - guard__h376995 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or - guard__h376995) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - (guard__h376995 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h376995 == 2'b01 || guard__h376995 == 2'b10 || - guard__h376995 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h368159 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h368159) 2'b0, 2'b01, 2'b10: - CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = guard__h368159 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or + CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 or guard__h368159) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = - CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; + CASE_guard68159_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = (guard__h368159 == 2'b0) ? @@ -34442,6 +34404,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h376995 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h376995) + 2'b0, 2'b01, 2'b10: + CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = + guard__h376995 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 or + guard__h376995) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = + CASE_guard76995_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = + (guard__h376995 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h376995 == 2'b01 || guard__h376995 == 2'b10 || + guard__h376995 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h376995 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34923,61 +34923,23 @@ module mkCore(CLK, begin case (guard__h396219) 2'b0, 2'b01, 2'b10: - CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = - guard__h396219 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or - guard__h396219) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - (guard__h396219 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h396219 != 2'b01 && guard__h396219 != 2'b10 && - guard__h396219 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h396219 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h396219) - 2'b0, 2'b01, 2'b10: - CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = guard__h396219 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or + CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or guard__h396219) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = - CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; + CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = (guard__h396219 == 2'b0) ? @@ -34994,6 +34956,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end + always@(guard__h396219 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h396219) + 2'b0, 2'b01, 2'b10: + CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + guard__h396219 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or + guard__h396219) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = + CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = + (guard__h396219 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h396219 != 2'b01 && guard__h396219 != 2'b10 && + guard__h396219 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end always@(guard__h404926 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -36061,58 +36061,16 @@ module mkCore(CLK, _theResult___exp__h507116; endcase end - always@(guard__h507812 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h507812) - 2'b0, 2'b01, 2'b10: - CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 2'd3: - CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h507812 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507812) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h507812 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h507812 == 2'b01 || guard__h507812 == 2'b10 || - guard__h507812 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end always@(guard__h498500 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h498500) 2'b0, 2'b01, 2'b10: - CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = guard__h498500 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && @@ -36123,12 +36081,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = (guard__h498500 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && @@ -36138,6 +36096,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(guard__h507812 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h507812) + 2'b0, 2'b01, 2'b10: + CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 2'd3: + CASE_guard07812_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h507812 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507812) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + (guard__h507812 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171] : + (guard__h507812 == 2'b01 || guard__h507812 == 2'b10 || + guard__h507812 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -36277,21 +36277,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h585969 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h585969) + case (guard__h595038) 2'b0, 2'b01, 2'b10: - CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h585969 == 2'b11 && + CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h595038 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585969) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36300,12 +36300,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h585969 == 2'b0) ? + (guard__h595038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h585969 == 2'b01 || guard__h585969 == 2'b10 || - guard__h585969 == 2'b11) && + (guard__h595038 == 2'b01 || guard__h595038 == 2'b10 || + guard__h595038 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36316,21 +36316,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595038 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h585969 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595038) + case (guard__h585969) 2'b0, 2'b01, 2'b10: - CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h595038 == 2'b11 && + CASE_guard85969_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h585969 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595038) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585969) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36339,12 +36339,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h595038 == 2'b0) ? + (guard__h585969 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h595038 == 2'b01 || guard__h595038 == 2'b10 || - guard__h595038 == 2'b11) && + (guard__h585969 == 2'b01 || guard__h585969 == 2'b10 || + guard__h585969 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36727,58 +36727,16 @@ module mkCore(CLK, _theResult___exp__h603708; endcase end - always@(guard__h537353 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h537353) - 2'b0, 2'b01, 2'b10: - CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h537353 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537353) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h537353 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h537353 == 2'b01 || guard__h537353 == 2'b10 || - guard__h537353 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end always@(guard__h546665 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h546665) 2'b0, 2'b01, 2'b10: - CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard46665_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = guard__h546665 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36789,12 +36747,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = (guard__h546665 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && @@ -36804,6 +36762,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h537353 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h537353) + 2'b0, 2'b01, 2'b10: + CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard37353_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h537353 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537353) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h537353 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h537353 == 2'b01 || guard__h537353 == 2'b10 || + guard__h537353 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == @@ -38214,17 +38214,6 @@ module mkCore(CLK, coreFix_aluExe_1_rsAlu$RDY_enq; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or @@ -38244,6 +38233,17 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769); endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or @@ -38356,6 +38356,21 @@ module mkCore(CLK, coreFix_memExe_lsq$RDY_enqSt; endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769); + endcase + end always@(fetchStage$pipelines_0_first or IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 or @@ -38373,21 +38388,6 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769); - endcase - end always@(fetchStage$pipelines_1_first or fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14315 or SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022 or @@ -38979,6 +38979,15 @@ module mkCore(CLK, endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd0: @@ -39209,15 +39218,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9999 or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9289 or diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index a353d3a..bb0d3be 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -2716,22 +2716,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - debug_module$RDY_hart0_reset_client_response_put && - proc$RDY_start) && + proc$RDY_start && + debug_module$RDY_hart0_reset_client_response_put) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - debug_module$RDY_hart0_client_run_halt_request_get && - proc$RDY_hart0_run_halt_server_request_put ; + proc$RDY_hart0_run_halt_server_request_put && + debug_module$RDY_hart0_client_run_halt_request_get ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - debug_module$RDY_hart0_client_run_halt_response_put && - proc$RDY_hart0_run_halt_server_response_get ; + proc$RDY_hart0_run_halt_server_response_get && + debug_module$RDY_hart0_client_run_halt_response_put ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2743,25 +2743,25 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - v_td2_to_td_0$RDY_in_put && proc$RDY_v_to_TV_0_get ; + proc$RDY_v_to_TV_0_get && v_td2_to_td_0$RDY_in_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_mkConnectionGetPut_2 assign CAN_FIRE_RL_mkConnectionGetPut_2 = - v_td2_to_td_0$RDY_out_get && tv_encode$RDY_v_cpu_in_0_put ; + tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0$RDY_out_get ; assign WILL_FIRE_RL_mkConnectionGetPut_2 = CAN_FIRE_RL_mkConnectionGetPut_2 ; // rule RL_mkConnectionGetPut_3 assign CAN_FIRE_RL_mkConnectionGetPut_3 = - v_td2_to_td_1$RDY_in_put && proc$RDY_v_to_TV_1_get ; + proc$RDY_v_to_TV_1_get && v_td2_to_td_1$RDY_in_put ; assign WILL_FIRE_RL_mkConnectionGetPut_3 = CAN_FIRE_RL_mkConnectionGetPut_3 ; // rule RL_mkConnectionGetPut_4 assign CAN_FIRE_RL_mkConnectionGetPut_4 = - v_td2_to_td_1$RDY_out_get && tv_encode$RDY_v_cpu_in_1_put ; + tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1$RDY_out_get ; assign WILL_FIRE_RL_mkConnectionGetPut_4 = CAN_FIRE_RL_mkConnectionGetPut_4 ; @@ -2787,22 +2787,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - dm_gpr_tap_ifc$RDY_client_response_put && - proc$RDY_hart0_gpr_mem_server_response_get ; + proc$RDY_hart0_gpr_mem_server_response_get && + dm_gpr_tap_ifc$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -2815,22 +2815,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; // rule RL_ClientServerResponse_4 assign CAN_FIRE_RL_ClientServerResponse_4 = - dm_csr_tap$RDY_client_response_put && - proc$RDY_hart0_csr_mem_server_response_get ; + proc$RDY_hart0_csr_mem_server_response_get && + dm_csr_tap$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_4 = CAN_FIRE_RL_ClientServerResponse_4 ; @@ -2935,15 +2935,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - dm_gpr_tap_ifc$RDY_client_request_get && - proc$RDY_hart0_gpr_mem_server_request_put ; + proc$RDY_hart0_gpr_mem_server_request_put && + dm_gpr_tap_ifc$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ClientServerRequest_4 assign CAN_FIRE_RL_ClientServerRequest_4 = - dm_csr_tap$RDY_client_request_get && - proc$RDY_hart0_csr_mem_server_request_put ; + proc$RDY_hart0_csr_mem_server_request_put && + dm_csr_tap$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_4 = CAN_FIRE_RL_ClientServerRequest_4 ; diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v index 1b6b7c2..b1f7022 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v @@ -1434,7 +1434,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && + corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index b4e5c4f..73ce8a6 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -2104,8 +2104,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163582; - reg [31 : 0] v__h163118; + reg [31 : 0] v__h163598; + reg [31 : 0] v__h163134; reg [31 : 0] v__h5520; reg [31 : 0] v__h5693; reg [31 : 0] v__h5953; @@ -2116,13 +2116,13 @@ module mkProc(CLK, reg [31 : 0] v__h9480; reg [31 : 0] v__h9973; reg [31 : 0] v__h10136; - reg [31 : 0] v__h135075; - reg [31 : 0] v__h135242; - reg [31 : 0] v__h137345; - reg [31 : 0] v__h154689; - reg [31 : 0] v__h134456; - reg [31 : 0] v__h161383; - reg [31 : 0] v__h161891; + reg [31 : 0] v__h135091; + reg [31 : 0] v__h135258; + reg [31 : 0] v__h137361; + reg [31 : 0] v__h154705; + reg [31 : 0] v__h134472; + reg [31 : 0] v__h161399; + reg [31 : 0] v__h161907; reg [31 : 0] v__h2664; reg [31 : 0] v__h4337; reg [31 : 0] v__h5514; @@ -2133,280 +2133,282 @@ module mkProc(CLK, reg [31 : 0] v__h9474; reg [31 : 0] v__h9967; reg [31 : 0] v__h10130; - reg [31 : 0] v__h134450; - reg [31 : 0] v__h135069; - reg [31 : 0] v__h135236; - reg [31 : 0] v__h137339; - reg [31 : 0] v__h154683; - reg [31 : 0] v__h161377; - reg [31 : 0] v__h161885; - reg [31 : 0] v__h163112; - reg [31 : 0] v__h163576; + reg [31 : 0] v__h134466; + reg [31 : 0] v__h135085; + reg [31 : 0] v__h135252; + reg [31 : 0] v__h137355; + reg [31 : 0] v__h154699; + reg [31 : 0] v__h161393; + reg [31 : 0] v__h161901; + reg [31 : 0] v__h163128; + reg [31 : 0] v__h163592; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952, - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, - data64__h148515, - dword__h94382, - ld_data__h132631, - old_dword__h90072, - w1__h48093, - w1__h48098, - w2__h48094, - w2__h48100, - x__h48089; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34, + CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956, + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923, + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891, + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893, + data64__h148531, + dword__h94398, + ld_data__h132647, + old_dword__h90088, + w1__h48109, + w1__h48114, + w2__h48110, + w2__h48116, + x__h48105; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h148516; - reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; + reg [7 : 0] strb8__h148532; + reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61807; + reg [2 : 0] x__h61823; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; + CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, - x__h61814, - x__h82716; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - new_cline__h135378; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; - wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - data__h31950, - failed_testnum__h163161, - line_addr__h102446, - line_addr__h102532, - mask__h90069, - mem_req_rd_addr_araddr__h134676, - mem_req_wr_addr_awaddr__h148600, - mmioPlatform_fromHostQ_data_0__h42745, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48685, - n__read_addr__h61675, - n__read_addr__h61760, - n__read_addr__h80478, - n__read_addr__h80557, - n__read_snd_addr__h123973, - newData__h32031, - newData__h34961, - new_dword__h90073, - op_result__h48701, - op_result__h49231, - op_result__h49236, - op_result__h49241, - op_result__h49246, + CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20, + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371, + x__h61830, + x__h82732; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, + new_cline__h135394; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; + wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, + data__h31966, + failed_testnum__h163177, + line_addr__h102462, + line_addr__h102548, + mask__h90085, + mem_req_rd_addr_araddr__h134692, + mem_req_wr_addr_awaddr__h148616, + mmioPlatform_fromHostQ_data_0__h42761, + mmioPlatform_mtime__h37280, + mmioPlatform_reqData__h48701, + n__read_addr__h61691, + n__read_addr__h61776, + n__read_addr__h80494, + n__read_addr__h80573, + n__read_snd_addr__h123989, + newData__h32047, + newData__h34977, + new_dword__h90089, + op_result__h48717, + op_result__h49247, op_result__h49252, - op_result__h49259, - op_result__h49265, - result__h48144, - result__h48268, - result__h48296, - result__h48324, - result__h48352, - result__h48380, - result__h48408, - result__h48436, - result__h48464, - result__h48509, - result__h48537, - result__h48565, - result__h48593, - result__h48634, - result__h48662, - result__h48788, - result__h48815, - result__h48842, - result__h48869, - result__h48896, - result__h48923, - result__h48950, - result__h48977, - result__h49021, - result__h49048, - result__h49075, - result__h49102, - result__h49142, - result__h49169, - result__h49286, - result__h49352, - result__h49418, - result__h49484, - result__h49550, - result__h49616, - result__h49682, - result__h49744, - result__h49789, - result__h49855, - result__h49921, - result__h49979, - result__h50024, - w1___1__h48203, - w2___1__h48204, - x1_avValue_data__h40417, - x1_avValue_data__h45022, - x__h32142, - x__h35052, - x__h37412, - x__h40935, - x__h40946, - x__h43001, - x__h43012, - x__h50201, - x__h91235, - y__h91236, - y__h91237; - wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; - wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995, + op_result__h49257, + op_result__h49262, + op_result__h49268, + op_result__h49275, + op_result__h49281, + result__h48160, + result__h48284, + result__h48312, + result__h48340, + result__h48368, + result__h48396, + result__h48424, + result__h48452, + result__h48480, + result__h48525, + result__h48553, + result__h48581, + result__h48609, + result__h48650, + result__h48678, + result__h48804, + result__h48831, + result__h48858, + result__h48885, + result__h48912, + result__h48939, + result__h48966, + result__h48993, + result__h49037, + result__h49064, + result__h49091, + result__h49118, + result__h49158, + result__h49185, + result__h49302, + result__h49368, + result__h49434, + result__h49500, + result__h49566, + result__h49632, + result__h49698, + result__h49760, + result__h49805, + result__h49871, + result__h49937, + result__h49995, + result__h50040, + w1___1__h48219, + w2___1__h48220, + x1_avValue_data__h40433, + x1_avValue_data__h45038, + x__h32158, + x__h35068, + x__h37428, + x__h40951, + x__h40962, + x__h43017, + x__h43028, + x__h50217, + x__h91251, + y__h91252, + y__h91253; + wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713; + wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w18093_BITS_31_TO_0__q15, - w28094_BITS_31_TO_0__q16, - x_data__h30533; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; - wire [5 : 0] x__h134711, x__h148625; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; - wire [3 : 0] b__h134383, b__h2564; - wire [2 : 0] n__read_id__h61679, n__read_id__h61764, x__h7925; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120, - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; - wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, - IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097, - IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471, - IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315, - IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, + v__h31759, + v__h31796, + w18109_BITS_31_TO_0__q15, + w28110_BITS_31_TO_0__q16, + x_data__h30549; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168; + wire [5 : 0] x__h134727, x__h148641; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167; + wire [3 : 0] b__h134399, b__h2564; + wire [2 : 0] n__read_id__h61695, n__read_id__h61780, x__h7925; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120, + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124, + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; + wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, + IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101, + IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475, + IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319, + IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974, + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267, - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012, - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186, - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193, - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019, - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099, - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373, - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271, + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016, + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190, + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197, + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023, + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103, + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377, + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386, - NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388, - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096, - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530, + NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390, + NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392, + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100, + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979, + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, + mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30134, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61680, - n__read_child__h61765, - n__read_child__h80481, - n__read_child__h80560, - n__read_snd_id__h123974, - propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, - propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, - x__h61493, - x__h75229, - x__h80300; + n__read_child__h61696, + n__read_child__h61781, + n__read_child__h80497, + n__read_child__h80576, + n__read_snd_id__h123990, + propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140, + propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144, + x__h61509, + x__h75245, + x__h80316; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3534,7 +3536,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 ; + IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3562,7 +3564,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 ; + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3723,8 +3725,9 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3741,7 +3744,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3750,7 +3753,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3796,7 +3799,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h43001 == 64'd0 || + x__h43017 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3814,7 +3817,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3822,14 +3825,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3839,22 +3842,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 && + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3936,7 +3939,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3954,7 +3957,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3972,7 +3975,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3982,7 +3985,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -4002,7 +4005,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -4011,7 +4014,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4043,7 +4046,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4116,13 +4119,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134383 == 4'd0 ; + b__h134399 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134383 != 4'd0 && + b__h134399 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4132,7 +4135,8 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4140,22 +4144,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || + (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4180,14 +4184,10 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - core_0$mmioToPlatform_cRq_notEmpty) ; + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty ; + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -4222,20 +4222,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30549 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4249,35 +4249,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31966 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4291,10 +4291,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102446, + { line_addr__h102462, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102532, + { line_addr__h102548, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4302,28 +4302,29 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4334,7 +4335,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; + IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4347,11 +4348,12 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4362,32 +4364,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4395,29 +4397,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ? + (mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48089 } ; + x__h48105 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50201, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50217, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4427,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43001 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43017 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h43001 != 64'd0 ; + x__h43017 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40935 == 64'd0 ; + x__h40951 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61493 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + x__h61509 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; + CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80300 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + x__h80316 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; + CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123973, n__read_snd_id__h123974 } ; + { 1'd1, n__read_snd_addr__h123989, n__read_snd_id__h123990 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4579,11 +4581,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134383 - 4'd1 ; + b__h134399 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134383 ; + b__h134399 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4595,10 +4597,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, + IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? + (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4606,8 +4608,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, - IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 } ; + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, + IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4646,7 +4648,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134676, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134692, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4659,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148600, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148616, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148515, strb8__h148516, 1'd1 } ; + { data64__h148531, strb8__h148532, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4677,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135378 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135394 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4706,10 +4708,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, + IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4723,15 +4725,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102446 : - line_addr__h102532 ; + line_addr__h102462 : + line_addr__h102548 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4802,10 +4804,11 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4818,11 +4821,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 && + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4831,12 +4834,10 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4882,17 +4883,15 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; + mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34977 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4900,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32047 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4911,9 +4910,10 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4983,7 +4983,8 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -5047,7 +5048,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5055,15 +5056,16 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5149,28 +5151,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, + { IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 } ; + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, + { IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 } ; + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5183,36 +5185,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 ; + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 ; + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5321,7 +5323,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132631, llc$dma_respLd_first[3] } ; + { ld_data__h132647, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5342,13 +5344,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || + (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5359,15 +5361,16 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5424,7 +5427,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5433,7 +5436,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5465,17 +5468,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; + { IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135378, + { new_cline__h135394, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5554,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94382, 3'd1 } ; + { 4'd0, dword__h94398, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5602,7 +5605,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5632,11 +5635,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5854,86 +5857,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37428), + .amoExec_in_data(mmioPlatform_reqData__h48701), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h32158)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37280), + .amoExec_in_data(mmioPlatform_reqData__h48701), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h35068)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42745), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40946)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42761), + .amoExec_in_data(mmioPlatform_reqData__h48701), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h40962)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48685), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h43012)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = + .amoExec_in_data(mmioPlatform_reqData__h48701), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h43028)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40417 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + x1_avValue_data__h40433 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = + newData__h32047 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101 = + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 : + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371 = - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ? + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375 = + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 : + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 = - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; - assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; + assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5941,116 +5944,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 = - NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? + assign IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 = + NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 = - NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? + assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 = + NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 = + assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, - x__h75229 } ; - assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, + x__h75245 } ; + assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, - IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, + IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90073 : + new_dword__h90089 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -6063,23 +6066,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -6092,23 +6095,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6121,49 +6124,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h43001 == 64'd0 : - x__h40935 == 64'd0, + x__h43017 == 64'd0 : + x__h40951 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h45022 } ; + x1_avValue_data__h45038 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = + assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6171,99 +6174,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 = + assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 = + assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 = + assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 = + assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 = + assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 = + assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 = + assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 = + assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120 = + assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130 = + assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 = + assign IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 = + assign IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 = + assign IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 = + assign IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 = + assign NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 || - IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097) ; - assign NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 || + IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101) ; + assign NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6274,7 +6277,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6285,7 +6288,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6297,7 +6300,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6309,7 +6312,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6319,7 +6322,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6339,29 +6342,35 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = + !mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || + core_0$mmioToPlatform_cRq_notEmpty ; + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -6375,51 +6384,51 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 = + assign NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388 = + assign NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 = + assign NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 = + assign NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = - { CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = - { CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, - x__h82716 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = - { CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = - { CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, - x__h61807, - x__h61814 } ; - assign b__h134383 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 = + { CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 = + { CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, + x__h82732 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412 = + { CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 = + { CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20, + x__h61823, + x__h61830 } ; + assign b__h134399 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6427,23 +6436,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31966 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h163161 = + { v__h31759, 32'd0 } ; + assign failed_testnum__h163177 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102446 = + assign line_addr__h102462 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102532 = + assign line_addr__h102548 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = - line_addr__h102532 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = - line_addr__h102446 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90069 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 = + line_addr__h102548 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 = + line_addr__h102462 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90085 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6477,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134676 = - { llc$to_mem_toM_first[68:11], x__h134711 } ; - assign mem_req_wr_addr_awaddr__h148600 = - { llc$to_mem_toM_first[639:582], x__h148625 } ; + assign mem_req_rd_addr_araddr__h134692 = + { llc$to_mem_toM_first[68:11], x__h134727 } ; + assign mem_req_wr_addr_awaddr__h148616 = + { llc$to_mem_toM_first[639:582], x__h148641 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = + assign mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42745 = + assign mmioPlatform_fromHostQ_data_0__h42761 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,36 +6495,41 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + assign mmioPlatform_mtime__h37280 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = + mmioPlatform_mtimecmp_0 <= newData__h34977 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48685 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = + assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0) && + core_0$mmioToPlatform_cRq_notEmpty ; + assign mmioPlatform_reqBE_BIT_0___h30174 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30134 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48701 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6529,235 +6543,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61675 = + assign n__read_addr__h61691 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61760 = + assign n__read_addr__h61776 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80478 = + assign n__read_addr__h80494 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 : 64'd0 ; - assign n__read_addr__h80557 = + assign n__read_addr__h80573 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 : 64'd0 ; - assign n__read_child__h61680 = + assign n__read_child__h61696 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61765 = + assign n__read_child__h61781 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80481 = + assign n__read_child__h80497 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; - assign n__read_child__h80560 = + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 ; + assign n__read_child__h80576 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; - assign n__read_id__h61679 = + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 ; + assign n__read_id__h61695 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61764 = + assign n__read_id__h61780 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123973 = + assign n__read_snd_addr__h123989 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123974 = + assign n__read_snd_id__h123990 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32047 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + x__h32158 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; + assign newData__h34977 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h135378 = + x__h35068 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; + assign new_cline__h135394 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90073 = x__h91235 | y__h91236 ; - assign op_result__h48701 = - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; - assign op_result__h49231 = w1__h48098 ^ w2__h48100 ; - assign op_result__h49236 = w1__h48098 & w2__h48100 ; - assign op_result__h49241 = w1__h48098 | w2__h48100 ; - assign op_result__h49246 = - (w1__h48098 < w2__h48100) ? w1__h48098 : w2__h48100 ; - assign op_result__h49252 = - (w1__h48098 <= w2__h48100) ? w2__h48100 : w1__h48098 ; - assign op_result__h49259 = - ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ + assign new_dword__h90089 = x__h91251 | y__h91252 ; + assign op_result__h48717 = + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 + + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ; + assign op_result__h49247 = w1__h48114 ^ w2__h48116 ; + assign op_result__h49252 = w1__h48114 & w2__h48116 ; + assign op_result__h49257 = w1__h48114 | w2__h48116 ; + assign op_result__h49262 = + (w1__h48114 < w2__h48116) ? w1__h48114 : w2__h48116 ; + assign op_result__h49268 = + (w1__h48114 <= w2__h48116) ? w2__h48116 : w1__h48114 ; + assign op_result__h49275 = + ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ + (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ 64'h8000000000000000)) ? - w1__h48098 : - w2__h48100 ; - assign op_result__h49265 = - ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ + w1__h48114 : + w2__h48116 ; + assign op_result__h49281 = + ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ + (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ 64'h8000000000000000)) ? - w2__h48100 : - w1__h48098 ; - assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = + w2__h48116 : + w1__h48114 ; + assign propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140 = + assign propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48144 = + assign result__h48160 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; - assign result__h48268 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48296 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48324 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48352 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48380 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48408 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48436 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48464 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48509 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48537 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48565 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48593 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48634 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48662 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48788 = + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0] } ; + assign result__h48284 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48312 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48340 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48368 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48396 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48424 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48452 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48480 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48525 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48553 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48581 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48609 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48650 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48678 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48804 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48815 = + assign result__h48831 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48842 = + assign result__h48858 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48869 = + assign result__h48885 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48896 = + assign result__h48912 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48923 = + assign result__h48939 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48950 = + assign result__h48966 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48977 = + assign result__h48993 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h49021 = + assign result__h49037 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h49048 = + assign result__h49064 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h49075 = + assign result__h49091 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49102 = + assign result__h49118 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49142 = + assign result__h49158 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49169 = + assign result__h49185 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49286 = + assign result__h49302 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49352 = + assign result__h49368 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49418 = + assign result__h49434 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49484 = + assign result__h49500 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49550 = + assign result__h49566 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49616 = + assign result__h49632 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49682 = - { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], + assign result__h49698 = + { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49744 = + assign result__h49760 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; - assign result__h49789 = + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0] } ; + assign result__h49805 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49855 = + assign result__h49871 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49921 = - { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], + assign result__h49937 = + { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49979 = + assign result__h49995 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; - assign result__h50024 = - { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0] } ; + assign result__h50040 = + { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18093_BITS_31_TO_0__q15 = w1__h48093[31:0] ; - assign w1___1__h48203 = { 32'd0, w1__h48093[31:0] } ; - assign w28094_BITS_31_TO_0__q16 = w2__h48094[31:0] ; - assign w2___1__h48204 = { 32'd0, w2__h48094[31:0] } ; - assign x1_avValue_data__h40417 = + assign v__h31759 = mmioPlatform_waitUpperMSIPCRs ? v__h31796 : 32'd0 ; + assign v__h31796 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18109_BITS_31_TO_0__q15 = w1__h48109[31:0] ; + assign w1___1__h48219 = { 32'd0, w1__h48109[31:0] } ; + assign w28110_BITS_31_TO_0__q16 = w2__h48110[31:0] ; + assign w2___1__h48220 = { 32'd0, w2__h48110[31:0] } ; + assign x1_avValue_data__h40433 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h45022 = + assign x1_avValue_data__h45038 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134711 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148625 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40935 = + assign x__h134727 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148641 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37428 = mmioPlatform_mtimecmp_0 ; + assign x__h40951 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40946 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; - assign x__h43001 = + x__h40962 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 ; + assign x__h43017 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h43012 : + x__h43028 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6780,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50201 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61493 = - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? + assign x__h50217 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61509 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; - assign x__h75229 = + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ; + assign x__h75245 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; + IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 ; assign x__h7925 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80300 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? + assign x__h80316 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; - assign x__h91235 = old_dword__h90072 & y__h91237 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91236 = + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ; + assign x__h91251 = old_dword__h90088 & y__h91253 ; + assign x_data__h30549 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91252 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90069 ; - assign y__h91237 = + mask__h90085 ; + assign y__h91253 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,473 +7015,473 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[511:448]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat) + 3'd0: data64__h148531 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148531 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148531 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148531 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148531 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148531 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148531 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148531 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132631 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132631 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132631 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132631 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132631 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132631 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132631 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132631 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132647 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132647 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132647 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132647 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132647 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132647 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132647 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132647 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148515 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148515 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148515 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148515 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148515 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148515 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148515 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148515 = llc$to_mem_toM_first[511:448]; - endcase - end - always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) - begin - case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148516 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148516 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148516 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148516 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148516 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148516 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148516 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148516 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148532 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148532 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148532 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148532 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148532 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148532 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148532 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148532 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48268 or - result__h48296 or - result__h48324 or - result__h48352 or - result__h48380 or - result__h48408 or result__h48436 or result__h48464) + result__h48284 or + result__h48312 or + result__h48340 or + result__h48368 or + result__h48396 or + result__h48424 or result__h48452 or result__h48480) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48268; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48284; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48296; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48312; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48324; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48340; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48352; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48368; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48380; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48396; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48408; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48424; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48436; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48452; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = - result__h48464; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = + result__h48480; endcase end always@(mmioPlatform_curReq or - result__h48509 or - result__h48537 or result__h48565 or result__h48593) + result__h48525 or + result__h48553 or result__h48581 or result__h48609) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48509; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48525; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48537; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48553; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48565; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48581; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = - result__h48593; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + result__h48609; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48634 or result__h48662) + always@(mmioPlatform_curReq or result__h48650 or result__h48678) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48634; + result__h48650; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48662; + result__h48678; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48094 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; + w2__h48110 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; 2'b01: - w2__h48094 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; + w2__h48110 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; 2'b10: - w2__h48094 = + w2__h48110 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h48094 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + w2__h48110 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w2___1__h48204 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or + w2___1__h48220 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48100 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; + w2__h48116 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; 2'b01: - w2__h48100 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; - 2'b10: w2__h48100 = w2___1__h48204; + w2__h48116 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; + 2'b10: w2__h48116 = w2___1__h48220; 2'b11: - w2__h48100 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + w2__h48116 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_curReq or - result__h49021 or - result__h49048 or result__h49075 or result__h49102) + result__h48804 or + result__h48831 or + result__h48858 or + result__h48885 or + result__h48912 or + result__h48939 or result__h48966 or result__h48993) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49021; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48804; + 3'h1: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48831; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49048; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48858; + 3'h3: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48885; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49075; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48912; + 3'h5: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48939; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = - result__h49102; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48966; + 3'h7: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = + result__h48993; + endcase + end + always@(mmioPlatform_curReq or + result__h49037 or + result__h49064 or result__h49091 or result__h49118) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h49037; + 3'h2: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h49064; + 3'h4: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h49091; + 3'h6: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + result__h49118; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h48788 or - result__h48815 or - result__h48842 or - result__h48869 or - result__h48896 or - result__h48923 or result__h48950 or result__h48977) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48788; - 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48815; - 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48842; - 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48869; - 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48896; - 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48923; - 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48950; - 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = - result__h48977; - endcase - end - always@(mmioPlatform_curReq or result__h49142 or result__h49169) + always@(mmioPlatform_curReq or result__h49158 or result__h49185) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49142; + result__h49158; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49169; + result__h49185; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48093 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; + w1__h48109 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; 2'b01: - w1__h48093 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; + w1__h48109 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; 2'b10: - w1__h48093 = + w1__h48109 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h48093 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; + w1__h48109 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w1___1__h48203 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or + w1___1__h48219 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48098 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; + w1__h48114 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; 2'b01: - w1__h48098 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; - 2'b10: w1__h48098 = w1___1__h48203; + w1__h48114 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; + 2'b10: w1__h48114 = w1___1__h48219; 2'b11: - w1__h48098 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; + w1__h48114 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or - w18093_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or + w18109_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; 2'b01: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; 2'b10: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - { {32{w18093_BITS_31_TO_0__q15[31]}}, - w18093_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + { {32{w18109_BITS_31_TO_0__q15[31]}}, + w18109_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or - w28094_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or + w28110_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; 2'b01: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; 2'b10: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - { {32{w28094_BITS_31_TO_0__q16[31]}}, - w28094_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + { {32{w28110_BITS_31_TO_0__q16[31]}}, + w28110_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49265 or - w2__h48100 or - op_result__h48701 or - op_result__h49231 or - op_result__h49236 or - op_result__h49241 or - op_result__h49259 or op_result__h49246 or op_result__h49252) + op_result__h49281 or + w2__h48116 or + op_result__h48717 or + op_result__h49247 or + op_result__h49252 or + op_result__h49257 or + op_result__h49275 or op_result__h49262 or op_result__h49268) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - w2__h48100; + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + w2__h48116; 4'd1: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h48701; + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h48717; 4'd2: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49231; + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49247; 4'd3: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49236; - 4'd4: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49241; - 4'd5: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49259; - 4'd7: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49246; - 4'd8: - IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = op_result__h49252; - default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = - op_result__h49265; + 4'd4: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49257; + 4'd5: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49275; + 4'd7: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49262; + 4'd8: + IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49268; + default: IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = + op_result__h49281; endcase end always@(mmioPlatform_curReq or - result__h49744 or - result__h49789 or result__h49855 or result__h49921) + result__h49760 or + result__h49805 or result__h49871 or result__h49937) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49744; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49760; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49789; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49805; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49855; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49871; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = - result__h49921; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + result__h49937; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48144 or - result__h49286 or - result__h49352 or - result__h49418 or - result__h49484 or - result__h49550 or result__h49616 or result__h49682) + result__h48160 or + result__h49302 or + result__h49368 or + result__h49434 or + result__h49500 or + result__h49566 or result__h49632 or result__h49698) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h48144; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h48160; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49286; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49302; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49352; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49368; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49418; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49434; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49484; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49500; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49550; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49566; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49616; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49632; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = - result__h49682; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = + result__h49698; endcase end - always@(mmioPlatform_curReq or result__h49979 or result__h50024) + always@(mmioPlatform_curReq or result__h49995 or result__h50040) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49979; + result__h49995; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h50024; + result__h50040; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) begin case (mmioPlatform_reqSz) 2'b0: - x__h48089 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; + x__h48105 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947; 2'b01: - x__h48089 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; + x__h48105 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956; 2'b10: - x__h48089 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h48105 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h48089 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; + x__h48105 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7475,15 +7489,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7491,11 +7505,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7503,315 +7517,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 or + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019) + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012; + IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = + SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019; + IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 or + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193) + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186; + IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; + IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197; endcase end - always@(x__h61493 or n__read_id__h61679 or n__read_id__h61764) + always@(x__h61509 or n__read_id__h61695 or n__read_id__h61780) begin - case (x__h61493) - 1'd0: x__h61807 = n__read_id__h61679; - 1'd1: x__h61807 = n__read_id__h61764; + case (x__h61509) + 1'd0: x__h61823 = n__read_id__h61695; + 1'd1: x__h61823 = n__read_id__h61780; endcase end - always@(x__h61493 or n__read_child__h61680 or n__read_child__h61765) + always@(x__h61509 or n__read_child__h61696 or n__read_child__h61781) begin - case (x__h61493) - 1'd0: x__h61814 = n__read_child__h61680; - 1'd1: x__h61814 = n__read_child__h61765; + case (x__h61509) + 1'd0: x__h61830 = n__read_child__h61696; + 1'd1: x__h61830 = n__read_child__h61781; endcase end - always@(x__h61493 or - propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or - propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) + always@(x__h61509 or + propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 or + propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144) begin - case (x__h61493) + case (x__h61509) 1'd0: - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = - propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; + CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20 = + propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140; 1'd1: - CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = - propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; + CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20 = + propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144; endcase end - always@(x__h61493 or - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) + always@(x__h61509 or + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 or + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124) begin - case (x__h61493) + case (x__h61509) 1'd0: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; + CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120; 1'd1: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; + CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124; endcase end - always@(x__h61493 or - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) + always@(x__h61509 or + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 or + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134) begin - case (x__h61493) + case (x__h61509) 1'd0: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = - IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; + CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130; 1'd1: - CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = - IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; + CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; endcase end - always@(x__h61493 or n__read_addr__h61675 or n__read_addr__h61760) + always@(x__h61509 or n__read_addr__h61691 or n__read_addr__h61776) begin - case (x__h61493) + case (x__h61509) 1'd0: - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = - n__read_addr__h61675; + CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23 = + n__read_addr__h61691; 1'd1: - CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = - n__read_addr__h61760; + CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23 = + n__read_addr__h61776; endcase end - always@(x__h80300 or n__read_child__h80481 or n__read_child__h80560) - begin - case (x__h80300) - 1'd0: x__h82716 = n__read_child__h80481; - 1'd1: x__h82716 = n__read_child__h80560; - endcase - end - always@(x__h80300 or + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80300 or + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80300 or + always@(x__h80316 or n__read_child__h80497 or n__read_child__h80576) + begin + case (x__h80316) + 1'd0: x__h82732 = n__read_child__h80497; + 1'd1: x__h82732 = n__read_child__h80576; + endcase + end + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80300 or + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80300 or + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80300 or + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80300 or + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80300 or + always@(x__h80316 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80300 or + always@(x__h80316 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : + IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 : 2'd0; 1'd1: - CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : + IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 : 2'd0; endcase end - always@(x__h80300 or - NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or - NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) + always@(x__h80316 or + NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 or + NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; + CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390; 1'd1: - CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; + CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392; endcase end - always@(x__h80300 or n__read_addr__h80478 or n__read_addr__h80557) + always@(x__h80316 or n__read_addr__h80494 or n__read_addr__h80573) begin - case (x__h80300) + case (x__h80316) 1'd0: - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = - n__read_addr__h80478; + CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34 = + n__read_addr__h80494; 1'd1: - CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = - n__read_addr__h80557; + CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34 = + n__read_addr__h80573; endcase end @@ -8227,36 +8241,36 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163582 = $stime; + v__h163598 = $stime; #0; end - v__h163576 = v__h163582 / 32'd10; + v__h163592 = v__h163598 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163576, + v__h163592, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && - NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && + NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && - x__h61493 && + if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && + x__h61509 && (!propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && - NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && + NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && - x__h80300 && + if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && + x__h80316 && (!propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8266,14 +8280,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163118 = $stime; + v__h163134 = $stime; #0; end - v__h163112 = v__h163118 / 32'd10; + v__h163128 = v__h163134 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163112, + v__h163128, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8283,7 +8297,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163161); + $display("FAIL %0d", failed_testnum__h163177); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9861,13 +9875,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43001 != 64'd0) + x__h43017 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40935 != 64'd0) + x__h40951 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9876,7 +9890,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9885,85 +9899,85 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) begin - v__h135075 = $stime; + v__h135091 = $stime; #0; end - v__h135069 = v__h135075 / 32'd10; + v__h135085 = v__h135091 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135069, + v__h135085, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135242 = $stime; + v__h135258 = $stime; #0; end - v__h135236 = v__h135242 / 32'd10; + v__h135252 = v__h135258 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135236); + v__h135252); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10025,135 +10039,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137345 = $stime; + v__h137361 = $stime; #0; end - v__h137339 = v__h137345 / 32'd10; + v__h137355 = v__h137361 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137339); + v__h137355); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11351,169 +11365,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154689 = $stime; + v__h154705 = $stime; #0; end - v__h154683 = v__h154689 / 32'd10; + v__h154699 = v__h154705 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154683); + $display("%0d: ERROR: CreditCounter: overflow", v__h154699); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_wr_addr_awaddr__h148600); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", mem_req_wr_addr_awaddr__h148616); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", data64__h148515); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", data64__h148531); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", strb8__h148516); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", strb8__h148532); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134456 = $stime; + v__h134472 = $stime; #0; end - v__h134450 = v__h134456 / 32'd10; + v__h134466 = v__h134472 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134450, + v__h134466, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11584,159 +11598,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) - $write("'h%h", mem_req_rd_addr_araddr__h134676); + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + $write("'h%h", mem_req_rd_addr_araddr__h134692); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) begin - v__h161383 = $stime; + v__h161399 = $stime; #0; end - v__h161377 = v__h161383 / 32'd10; + v__h161393 = v__h161399 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161377, + v__h161393, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161891 = $stime; + v__h161907 = $stime; #0; end - v__h161885 = v__h161891 / 32'd10; + v__h161901 = v__h161907 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161885); + v__h161901); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 0ed7460..7bcc820 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -4465,7 +4465,7 @@ module mkCore(CLK, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, - MUX_flush_reservation$write_1__SEL_2, + MUX_flush_reservation$write_1__SEL_1, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -4489,7 +4489,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_started$write_1__SEL_1, MUX_v_f_to_TV_0$enq_1__SEL_2; // remaining internal signals @@ -4525,7 +4524,7 @@ module mkCore(CLK, trap_val__h711388, x__h197129, x__h723943; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, CASE_guard02883_0b0_sfdin11103_BITS_56_TO_5_0b_ETC__q217, @@ -4561,8 +4560,8 @@ module mkCore(CLK, CASE_guard00505_0b0_theResult___snd08504_BITS__ETC__q83, CASE_guard09435_0b0_sfdin17657_BITS_56_TO_34_0_ETC__q86, CASE_guard09435_0b0_sfdin17657_BITS_56_TO_34_0_ETC__q87, + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88, CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89, - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90, CASE_guard37493_0b0_sfdin45586_BITS_56_TO_34_0_ETC__q119, CASE_guard37493_0b0_sfdin45586_BITS_56_TO_34_0_ETC__q120, CASE_guard46099_0b0_sfdin54194_BITS_56_TO_34_0_ETC__q49, @@ -4577,8 +4576,8 @@ module mkCore(CLK, CASE_guard63738_0b0_sfdin71960_BITS_56_TO_34_0_ETC__q52, CASE_guard63966_0b0_theResult___snd71989_BITS__ETC__q123, CASE_guard63966_0b0_theResult___snd71989_BITS__ETC__q124, + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53, CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54, - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55, CASE_guard91798_0b0_sfdin99891_BITS_56_TO_34_0_ETC__q84, CASE_guard91798_0b0_sfdin99891_BITS_56_TO_34_0_ETC__q85, _theResult___fst_sfd__h346072, @@ -4621,8 +4620,8 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, CASE_guard02883_0b0_theResult___fst_exp11109_0_ETC__q211, CASE_guard02883_0b0_theResult___fst_exp11109_0_ETC__q212, @@ -4632,12 +4631,12 @@ module mkCore(CLK, CASE_guard32424_0b0_theResult___fst_exp40385_0_ETC__q184, CASE_guard41736_0b0_theResult___fst_exp49962_0_ETC__q185, CASE_guard41736_0b0_theResult___fst_exp49962_0_ETC__q186, - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189, - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190, + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187, + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188, CASE_guard71728_0b0_theResult___fst_exp79689_0_ETC__q160, CASE_guard71728_0b0_theResult___fst_exp79689_0_ETC__q161, - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187, - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188, + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189, + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190, CASE_guard90109_0b0_theResult___fst_exp98099_0_ETC__q191, CASE_guard90109_0b0_theResult___fst_exp98099_0_ETC__q192, CASE_guard93571_0b0_theResult___fst_exp01532_0_ETC__q143, @@ -4770,22 +4769,22 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, CASE_guard00505_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, CASE_guard00505_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, CASE_guard09435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, CASE_guard09435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, CASE_guard18271_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, CASE_guard18271_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, CASE_guard32424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, CASE_guard32424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, CASE_guard37493_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, CASE_guard41736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, CASE_guard41736_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, CASE_guard46099_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53, + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, CASE_guard46200_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, CASE_guard50805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, CASE_guard50805_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, CASE_guard54808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, @@ -4796,16 +4795,16 @@ module mkCore(CLK, CASE_guard63738_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, CASE_guard63966_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, CASE_guard63966_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, CASE_guard71728_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, CASE_guard72574_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, CASE_guard72574_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, CASE_guard81040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, CASE_guard81040_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, CASE_guard90109_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, CASE_guard91798_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, CASE_guard93571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, @@ -5393,7 +5392,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data75286_BITS_31_TO_0__q14, + data75286_BITS_31_TO_0__q13, imm__h655334, r1__read__h613079, r1__read__h614262, @@ -6326,7 +6325,7 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901, - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_RDY_ETC___d15380, + NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380, NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659, NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998, NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377, @@ -6396,7 +6395,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo20, + _dfoo22, _dfoo24, _dfoo26, _dfoo32, @@ -6541,7 +6540,7 @@ module mkCore(CLK, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899, f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894, - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14083, + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181, @@ -6592,7 +6591,7 @@ module mkCore(CLK, next_deqP___1__h328991, next_deqP___1__h332216, r1__read_BIT_20___h655898, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946, regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027, regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434, @@ -6617,7 +6616,7 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925, rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730, - rob_RDY_deqPort_0_deq__4341_AND_rob_RDY_deqPor_ETC___d15003, + rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, @@ -9835,8 +9834,8 @@ module mkCore(CLK, // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_first && fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + fetchStage$RDY_iTlbIfc_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; @@ -9872,8 +9871,8 @@ module mkCore(CLK, // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - coreFix_memExe_dTlb$RDY_toParent_flush_response_put && fetchStage$RDY_iTlbIfc_toParent_flush_response_put && + coreFix_memExe_dTlb$RDY_toParent_flush_response_put && l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; @@ -10015,9 +10014,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -10377,8 +10376,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10414,7 +10413,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq__4341_AND_rob_RDY_deqPor_ETC___d15003 && + regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 && NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && @@ -10449,7 +10448,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_RDY_ETC___d15380 && + NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 && NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && @@ -11127,16 +11126,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush && + commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -11144,7 +11143,9 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_debug_resume = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -11416,9 +11417,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11430,8 +11432,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && + fetchStage$RDY_pipelines_0_deq && + fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11532,7 +11534,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11963,7 +11966,7 @@ module mkCore(CLK, assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; - assign MUX_flush_reservation$write_1__SEL_2 = + assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -12020,9 +12023,6 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[89] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ; - assign MUX_started$write_1__SEL_1 = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -12041,6 +12041,18 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = commitStage_rg_serial_num + y__h734147 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = (k__h670531 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105) ? { fetchStage$pipelines_0_first[199:195], @@ -12066,18 +12078,6 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -13877,13 +13877,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -13899,12 +13899,12 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or @@ -14142,12 +14142,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -14277,13 +14277,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -14300,12 +14300,12 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or @@ -14323,11 +14323,11 @@ module mkCore(CLK, default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -14675,13 +14675,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14883,10 +14883,10 @@ module mkCore(CLK, WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15231,8 +15231,8 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data @@ -15490,9 +15490,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -16749,7 +16749,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN = 1'd1 ; assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN = - MUX_flush_reservation$write_1__SEL_2 ; + MUX_flush_reservation$write_1__SEL_1 ; // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = @@ -20942,8 +20942,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 = (_theResult___fst_exp__h589266 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == @@ -21536,8 +21536,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 = (_theResult___fst_exp__h598099 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == @@ -21558,8 +21558,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 = (_theResult___fst_exp__h598099 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21569,8 +21569,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 = (_theResult____h651123 == 16'd0 && (csrf_prv_reg == 2'd0 || @@ -23780,12 +23780,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], x__h302154 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 = - !MUX_flush_reservation$write_1__SEL_2 && + !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 = - MUX_flush_reservation$write_1__SEL_2 ? + MUX_flush_reservation$write_1__SEL_1 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -24241,10 +24241,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139 = @@ -24258,10 +24258,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 && IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 || - rob$RDY_enqPort_1_enq && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14083) ; + rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && @@ -25549,9 +25549,9 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 ; - assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_RDY_ETC___d15380 = + assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && @@ -25590,7 +25590,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && v_f_to_TV_1$FULL_N ; assign NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012 = !specTagManager$canClaim || @@ -26691,7 +26691,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo20 = + assign _dfoo22 = commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 ; assign _dfoo24 = @@ -27719,7 +27719,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; assign _theResult___fst_exp__h501523 = 11'd897 - { 5'd0, @@ -27875,7 +27875,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; assign _theResult___fst_exp__h540376 = 11'd897 - { 5'd0, @@ -28008,7 +28008,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 : + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ; assign _theResult___fst_exp__h559578 = (_theResult___fst_exp__h558795 == 11'd2047) ? @@ -28134,7 +28134,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 : + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ; assign _theResult___fst_exp__h590098 = (_theResult___fst_exp__h589266 == 11'd2047) ? @@ -28289,7 +28289,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; assign _theResult___fst_sfd__h502288 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && @@ -30193,13 +30193,13 @@ module mkCore(CLK, csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440 ; - assign data75286_BITS_31_TO_0__q14 = data__h475286[31:0] ; + assign data75286_BITS_31_TO_0__q13 = data__h475286[31:0] ; assign data___1__h475012 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; assign data___1__h475820 = - { {32{data75286_BITS_31_TO_0__q14[31]}}, - data75286_BITS_31_TO_0__q14 } ; + { {32{data75286_BITS_31_TO_0__q13[31]}}, + data75286_BITS_31_TO_0__q13 } ; assign data__h475286 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? @@ -30306,12 +30306,14 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609380 = { 56'd0, x__h613038 } ; - assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14083 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; + assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -31100,14 +31102,13 @@ module mkCore(CLK, assign r___1__h475911 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - epochManager$RDY_incrementEpoch && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 = + regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && @@ -31605,13 +31606,12 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612210 = { r1__read__h614604, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq__4341_AND_rob_RDY_deqPor_ETC___d15003 = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 ; + assign rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && @@ -32900,27 +32900,6 @@ module mkCore(CLK, default: rVal1__h633783 = 64'b0; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -33038,45 +33017,66 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33232,17 +33232,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[31:0]; - 1'd1: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[63:32]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:18]) 2'd0: @@ -33260,6 +33249,17 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19]) + 1'd0: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[31:0]; + 1'd1: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[63:32]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33759,28 +33759,80 @@ module mkCore(CLK, default: _theResult___fst_sfd__h372561 = 23'd0; endcase end + always@(guard__h372574 or + _theResult___snd__h380597 or + out_sfd__h381122 or _theResult___sfd__h381119) + begin + case (guard__h372574) + 2'b0, 2'b01: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 = + _theResult___snd__h380597[56:34]; + 2'b10: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 = + out_sfd__h381122; + 2'b11: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 = + _theResult___sfd__h381119; + endcase + end + always@(guard__h372574 or + _theResult___snd__h380597 or _theResult___sfd__h381119) + begin + case (guard__h372574) + 2'b0: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = + _theResult___snd__h380597[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = + _theResult___sfd__h381119; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53 or + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or + _theResult___snd__h380597) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h381197 = + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q53; + 3'd1: + _theResult___fst_sfd__h381197 = + CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54; + 3'd2: + _theResult___fst_sfd__h381197 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; + 3'd3: + _theResult___fst_sfd__h381197 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; + 3'd4: _theResult___fst_sfd__h381197 = _theResult___snd__h380597[56:34]; + default: _theResult___fst_sfd__h381197 = 23'd0; + endcase + end always@(guard__h346099 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h346099) 2'b0, 2'b01, 2'b10: - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 = + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = guard__h346099 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or guard__h346099) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53; + CASE_guard46099_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = (guard__h346099 == 2'b0) ? @@ -33797,58 +33849,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372574 or - _theResult___snd__h380597 or - out_sfd__h381122 or _theResult___sfd__h381119) - begin - case (guard__h372574) - 2'b0, 2'b01: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = - _theResult___snd__h380597[56:34]; - 2'b10: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = - out_sfd__h381122; - 2'b11: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 = - _theResult___sfd__h381119; - endcase - end - always@(guard__h372574 or - _theResult___snd__h380597 or _theResult___sfd__h381119) - begin - case (guard__h372574) - 2'b0: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55 = - _theResult___snd__h380597[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55 = - _theResult___sfd__h381119; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54 or - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___snd__h380597) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h381197 = - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q54; - 3'd1: - _theResult___fst_sfd__h381197 = - CASE_guard72574_0b0_theResult___snd80597_BITS__ETC__q55; - 3'd2: - _theResult___fst_sfd__h381197 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; - 3'd3: - _theResult___fst_sfd__h381197 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_sfd__h381197 = _theResult___snd__h380597[56:34]; - default: _theResult___fst_sfd__h381197 = 23'd0; - endcase - end always@(guard__h346099 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -34501,28 +34501,80 @@ module mkCore(CLK, default: _theResult___fst_sfd__h418258 = 23'd0; endcase end + always@(guard__h418271 or + _theResult___snd__h426294 or + out_sfd__h426819 or _theResult___sfd__h426816) + begin + case (guard__h418271) + 2'b0, 2'b01: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 = + _theResult___snd__h426294[56:34]; + 2'b10: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 = + out_sfd__h426819; + 2'b11: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 = + _theResult___sfd__h426816; + endcase + end + always@(guard__h418271 or + _theResult___snd__h426294 or _theResult___sfd__h426816) + begin + case (guard__h418271) + 2'b0: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = + _theResult___snd__h426294[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = + _theResult___sfd__h426816; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88 or + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or + _theResult___snd__h426294) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h426894 = + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q88; + 3'd1: + _theResult___fst_sfd__h426894 = + CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89; + 3'd2: + _theResult___fst_sfd__h426894 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; + 3'd3: + _theResult___fst_sfd__h426894 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; + 3'd4: _theResult___fst_sfd__h426894 = _theResult___snd__h426294[56:34]; + default: _theResult___fst_sfd__h426894 = 23'd0; + endcase + end always@(guard__h391798 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (guard__h391798) 2'b0, 2'b01, 2'b10: - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = guard__h391798 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or guard__h391798) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; + CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = (guard__h391798 == 2'b0) ? @@ -34539,58 +34591,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418271 or - _theResult___snd__h426294 or - out_sfd__h426819 or _theResult___sfd__h426816) - begin - case (guard__h418271) - 2'b0, 2'b01: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = - _theResult___snd__h426294[56:34]; - 2'b10: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = - out_sfd__h426819; - 2'b11: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 = - _theResult___sfd__h426816; - endcase - end - always@(guard__h418271 or - _theResult___snd__h426294 or _theResult___sfd__h426816) - begin - case (guard__h418271) - 2'b0: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90 = - _theResult___snd__h426294[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90 = - _theResult___sfd__h426816; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89 or - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___snd__h426294) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h426894 = - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q89; - 3'd1: - _theResult___fst_sfd__h426894 = - CASE_guard18271_0b0_theResult___snd26294_BITS__ETC__q90; - 3'd2: - _theResult___fst_sfd__h426894 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; - 3'd3: - _theResult___fst_sfd__h426894 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_sfd__h426894 = _theResult___snd__h426294[56:34]; - default: _theResult___fst_sfd__h426894 = 23'd0; - endcase - end always@(guard__h391798 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin @@ -35333,66 +35333,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h437493 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h437493) - 2'b0, 2'b01, 2'b10: - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h437493 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h437493) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - (guard__h437493 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h437493 != 2'b01 && guard__h437493 != 2'b10 && - guard__h437493 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end always@(guard__h446200 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (guard__h446200) 2'b0, 2'b01, 2'b10: - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = guard__h446200 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or guard__h446200) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard46200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = (guard__h446200 == 2'b0) ? @@ -35409,6 +35371,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end + always@(guard__h437493 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h437493) + 2'b0, 2'b01, 2'b10: + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h437493 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h437493) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + CASE_guard37493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + (guard__h437493 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h437493 != 2'b01 && guard__h437493 != 2'b10 && + guard__h437493 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end always@(guard__h446200 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin @@ -35738,58 +35738,16 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h502883 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h502883) - 2'b0, 2'b01, 2'b10: - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 2'd3: - CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h502883 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502883) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h502883 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h502883 == 2'b01 || guard__h502883 == 2'b10 || - guard__h502883 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - endcase - end always@(guard__h511952 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (guard__h511952) 2'b0, 2'b01, 2'b10: - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard11952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = guard__h511952 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && @@ -35800,12 +35758,12 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = (guard__h511952 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && @@ -35815,6 +35773,48 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(guard__h502883 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h502883) + 2'b0, 2'b01, 2'b10: + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 2'd3: + CASE_guard02883_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h502883 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502883) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + (guard__h502883 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171] : + (guard__h502883 == 2'b01 || guard__h502883 == 2'b10 || + guard__h502883 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -36029,21 +36029,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571728 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590109 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571728) + case (guard__h590109) 2'b0, 2'b01, 2'b10: - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h571728 != 2'b11 || + CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h590109 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571728) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590109) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36052,12 +36052,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h571728 == 2'b0) ? + (guard__h590109 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h571728 != 2'b01 && guard__h571728 != 2'b10 && - guard__h571728 != 2'b11 || + guard__h590109 != 2'b01 && guard__h590109 != 2'b10 && + guard__h590109 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36068,21 +36068,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590109 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571728 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590109) + case (guard__h571728) 2'b0, 2'b01, 2'b10: - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h590109 != 2'b11 || + CASE_guard71728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h571728 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590109) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571728) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36091,12 +36091,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h590109 == 2'b0) ? + (guard__h571728 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h590109 != 2'b01 && guard__h590109 != 2'b10 && - guard__h590109 != 2'b11 || + guard__h571728 != 2'b01 && guard__h571728 != 2'b10 && + guard__h571728 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36209,66 +36209,15 @@ module mkCore(CLK, _theResult___exp__h550691; endcase end - always@(guard__h581040 or - _theResult___fst_exp__h589266 or _theResult___exp__h589995) - begin - case (guard__h581040) - 2'b0: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187 = - _theResult___fst_exp__h589266; - 2'b01, 2'b10, 2'b11: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187 = - _theResult___exp__h589995; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h589266 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - _theResult___fst_exp__h589266; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q187; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - 11'd0; - endcase - end - always@(guard__h581040 or - _theResult___fst_exp__h589266 or - out_exp__h589998 or _theResult___exp__h589995) - begin - case (guard__h581040) - 2'b0, 2'b01: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 = - _theResult___fst_exp__h589266; - 2'b10: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 = - out_exp__h589998; - 2'b11: - CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q188 = - _theResult___exp__h589995; - endcase - end always@(guard__h550805 or _theResult___fst_exp__h558795 or _theResult___exp__h559475) begin case (guard__h550805) 2'b0: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187 = _theResult___fst_exp__h558795; 2'b01, 2'b10, 2'b11: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187 = _theResult___exp__h559475; endcase end @@ -36276,7 +36225,7 @@ module mkCore(CLK, _theResult___fst_exp__h558795 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189) + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: @@ -36290,7 +36239,7 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q189; + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = 11'd0; endcase @@ -36301,16 +36250,67 @@ module mkCore(CLK, begin case (guard__h550805) 2'b0, 2'b01: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 = _theResult___fst_exp__h558795; 2'b10: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 = out_exp__h559478; 2'b11: - CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q190 = + CASE_guard50805_0b0_theResult___fst_exp58795_0_ETC__q188 = _theResult___exp__h559475; endcase end + always@(guard__h581040 or + _theResult___fst_exp__h589266 or _theResult___exp__h589995) + begin + case (guard__h581040) + 2'b0: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189 = + _theResult___fst_exp__h589266; + 2'b01, 2'b10, 2'b11: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189 = + _theResult___exp__h589995; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h589266 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + _theResult___fst_exp__h589266; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q189; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = + 11'd0; + endcase + end + always@(guard__h581040 or + _theResult___fst_exp__h589266 or + out_exp__h589998 or _theResult___exp__h589995) + begin + case (guard__h581040) + 2'b0, 2'b01: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 = + _theResult___fst_exp__h589266; + 2'b10: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 = + out_exp__h589998; + 2'b11: + CASE_guard81040_0b0_theResult___fst_exp89266_0_ETC__q190 = + _theResult___exp__h589995; + endcase + end always@(guard__h590109 or _theResult___fst_exp__h598099 or _theResult___exp__h598779) begin @@ -37849,17 +37849,6 @@ module mkCore(CLK, coreFix_aluExe_1_rsAlu$RDY_enq; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or @@ -37879,6 +37868,17 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or @@ -38083,10 +38083,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -38094,10 +38094,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = - coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = - coreFix_memExe_lsq$enqStTag[5]; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -38390,16 +38390,6 @@ module mkCore(CLK, default: data_warl_xformed__h723335 = rob$deqPort_0_deq_data[95:32]; endcase end - always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196) - begin - case (rob$deqPort_0_deq_data[329:325]) - 5'd19, 5'd20: - x__h723943 = - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196; - default: x__h723943 = rob$deqPort_0_deq_data[425:362]; - endcase - end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) @@ -38453,6 +38443,16 @@ module mkCore(CLK, 12'd2303; endcase end + always@(rob$deqPort_0_deq_data or + IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196) + begin + case (rob$deqPort_0_deq_data[329:325]) + 5'd19, 5'd20: + x__h723943 = + IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196; + default: x__h723943 = rob$deqPort_0_deq_data[425:362]; + endcase + end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[165:162]) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index a353d3a..bb0d3be 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -2716,22 +2716,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - debug_module$RDY_hart0_reset_client_response_put && - proc$RDY_start) && + proc$RDY_start && + debug_module$RDY_hart0_reset_client_response_put) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - debug_module$RDY_hart0_client_run_halt_request_get && - proc$RDY_hart0_run_halt_server_request_put ; + proc$RDY_hart0_run_halt_server_request_put && + debug_module$RDY_hart0_client_run_halt_request_get ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - debug_module$RDY_hart0_client_run_halt_response_put && - proc$RDY_hart0_run_halt_server_response_get ; + proc$RDY_hart0_run_halt_server_response_get && + debug_module$RDY_hart0_client_run_halt_response_put ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2743,25 +2743,25 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - v_td2_to_td_0$RDY_in_put && proc$RDY_v_to_TV_0_get ; + proc$RDY_v_to_TV_0_get && v_td2_to_td_0$RDY_in_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_mkConnectionGetPut_2 assign CAN_FIRE_RL_mkConnectionGetPut_2 = - v_td2_to_td_0$RDY_out_get && tv_encode$RDY_v_cpu_in_0_put ; + tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0$RDY_out_get ; assign WILL_FIRE_RL_mkConnectionGetPut_2 = CAN_FIRE_RL_mkConnectionGetPut_2 ; // rule RL_mkConnectionGetPut_3 assign CAN_FIRE_RL_mkConnectionGetPut_3 = - v_td2_to_td_1$RDY_in_put && proc$RDY_v_to_TV_1_get ; + proc$RDY_v_to_TV_1_get && v_td2_to_td_1$RDY_in_put ; assign WILL_FIRE_RL_mkConnectionGetPut_3 = CAN_FIRE_RL_mkConnectionGetPut_3 ; // rule RL_mkConnectionGetPut_4 assign CAN_FIRE_RL_mkConnectionGetPut_4 = - v_td2_to_td_1$RDY_out_get && tv_encode$RDY_v_cpu_in_1_put ; + tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1$RDY_out_get ; assign WILL_FIRE_RL_mkConnectionGetPut_4 = CAN_FIRE_RL_mkConnectionGetPut_4 ; @@ -2787,22 +2787,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - dm_gpr_tap_ifc$RDY_client_response_put && - proc$RDY_hart0_gpr_mem_server_response_get ; + proc$RDY_hart0_gpr_mem_server_response_get && + dm_gpr_tap_ifc$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -2815,22 +2815,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; // rule RL_ClientServerResponse_4 assign CAN_FIRE_RL_ClientServerResponse_4 = - dm_csr_tap$RDY_client_response_put && - proc$RDY_hart0_csr_mem_server_response_get ; + proc$RDY_hart0_csr_mem_server_response_get && + dm_csr_tap$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_4 = CAN_FIRE_RL_ClientServerResponse_4 ; @@ -2935,15 +2935,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - dm_gpr_tap_ifc$RDY_client_request_get && - proc$RDY_hart0_gpr_mem_server_request_put ; + proc$RDY_hart0_gpr_mem_server_request_put && + dm_gpr_tap_ifc$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ClientServerRequest_4 assign CAN_FIRE_RL_ClientServerRequest_4 = - dm_csr_tap$RDY_client_request_get && - proc$RDY_hart0_csr_mem_server_request_put ; + proc$RDY_hart0_csr_mem_server_request_put && + dm_csr_tap$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_4 = CAN_FIRE_RL_ClientServerRequest_4 ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index 1b6b7c2..b1f7022 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -1434,7 +1434,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && + corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 5c9ceee..8e3867b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -2104,8 +2104,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162844; - reg [31 : 0] v__h162380; + reg [31 : 0] v__h162860; + reg [31 : 0] v__h162396; reg [31 : 0] v__h5520; reg [31 : 0] v__h5693; reg [31 : 0] v__h5953; @@ -2116,13 +2116,13 @@ module mkProc(CLK, reg [31 : 0] v__h9480; reg [31 : 0] v__h9973; reg [31 : 0] v__h10136; - reg [31 : 0] v__h134337; - reg [31 : 0] v__h134504; - reg [31 : 0] v__h136607; - reg [31 : 0] v__h153951; - reg [31 : 0] v__h133718; - reg [31 : 0] v__h160645; - reg [31 : 0] v__h161153; + reg [31 : 0] v__h134353; + reg [31 : 0] v__h134520; + reg [31 : 0] v__h136623; + reg [31 : 0] v__h153967; + reg [31 : 0] v__h133734; + reg [31 : 0] v__h160661; + reg [31 : 0] v__h161169; reg [31 : 0] v__h2664; reg [31 : 0] v__h4337; reg [31 : 0] v__h5514; @@ -2133,280 +2133,282 @@ module mkProc(CLK, reg [31 : 0] v__h9474; reg [31 : 0] v__h9967; reg [31 : 0] v__h10130; - reg [31 : 0] v__h133712; - reg [31 : 0] v__h134331; - reg [31 : 0] v__h134498; - reg [31 : 0] v__h136601; - reg [31 : 0] v__h153945; - reg [31 : 0] v__h160639; - reg [31 : 0] v__h161147; - reg [31 : 0] v__h162374; - reg [31 : 0] v__h162838; + reg [31 : 0] v__h133728; + reg [31 : 0] v__h134347; + reg [31 : 0] v__h134514; + reg [31 : 0] v__h136617; + reg [31 : 0] v__h153961; + reg [31 : 0] v__h160655; + reg [31 : 0] v__h161163; + reg [31 : 0] v__h162390; + reg [31 : 0] v__h162854; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944, - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, - data64__h147777, - dword__h93782, - ld_data__h131939, - old_dword__h89472, - w1__h47861, - w1__h47866, - w2__h47862, - w2__h47868, - x__h47857; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948, + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915, + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883, + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885, + data64__h147793, + dword__h93798, + ld_data__h131955, + old_dword__h89488, + w1__h47877, + w1__h47882, + w2__h47878, + w2__h47884, + x__h47873; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147778; - reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; + reg [7 : 0] strb8__h147794; + reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61575; + reg [2 : 0] x__h61591; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, - x__h61582, - x__h82300; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - new_cline__h134640; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; - wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821, - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - data__h31950, - failed_testnum__h162423, - line_addr__h101846, - line_addr__h101932, - mask__h89469, - mem_req_rd_addr_araddr__h133938, - mem_req_wr_addr_awaddr__h147862, - mmioPlatform_fromHostQ_data_0__h42651, - mmioPlatform_mtime__h37264, - mmioPlatform_reqData__h48453, - n__read_addr__h61443, - n__read_addr__h61528, - n__read_addr__h80062, - n__read_addr__h80141, - n__read_snd_addr__h123373, - newData__h32031, - newData__h34961, - new_dword__h89473, - op_result__h48469, - op_result__h48999, - op_result__h49004, - op_result__h49009, - op_result__h49014, + CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, + CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358, + x__h61598, + x__h82316; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, + new_cline__h134656; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; + wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825, + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, + data__h31966, + failed_testnum__h162439, + line_addr__h101862, + line_addr__h101948, + mask__h89485, + mem_req_rd_addr_araddr__h133954, + mem_req_wr_addr_awaddr__h147878, + mmioPlatform_fromHostQ_data_0__h42667, + mmioPlatform_mtime__h37280, + mmioPlatform_reqData__h48469, + n__read_addr__h61459, + n__read_addr__h61544, + n__read_addr__h80078, + n__read_addr__h80157, + n__read_snd_addr__h123389, + newData__h32047, + newData__h34977, + new_dword__h89489, + op_result__h48485, + op_result__h49015, op_result__h49020, - op_result__h49027, - op_result__h49033, - result__h47912, - result__h48036, - result__h48064, - result__h48092, - result__h48120, - result__h48148, - result__h48176, - result__h48204, - result__h48232, - result__h48277, - result__h48305, - result__h48333, - result__h48361, - result__h48402, - result__h48430, - result__h48556, - result__h48583, - result__h48610, - result__h48637, - result__h48664, - result__h48691, - result__h48718, - result__h48745, - result__h48789, - result__h48816, - result__h48843, - result__h48870, - result__h48910, - result__h48937, - result__h49054, - result__h49120, - result__h49186, - result__h49252, - result__h49318, - result__h49384, - result__h49450, - result__h49512, - result__h49557, - result__h49623, - result__h49689, - result__h49747, - result__h49792, - w1___1__h47971, - w2___1__h47972, - x1_avValue_data__h40323, - x1_avValue_data__h44790, - x__h32142, - x__h35052, - x__h37412, - x__h40841, - x__h40852, - x__h42861, - x__h42872, - x__h49969, - x__h90635, - y__h90636, - y__h90637; - wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; - wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987, + op_result__h49025, + op_result__h49030, + op_result__h49036, + op_result__h49043, + op_result__h49049, + result__h47928, + result__h48052, + result__h48080, + result__h48108, + result__h48136, + result__h48164, + result__h48192, + result__h48220, + result__h48248, + result__h48293, + result__h48321, + result__h48349, + result__h48377, + result__h48418, + result__h48446, + result__h48572, + result__h48599, + result__h48626, + result__h48653, + result__h48680, + result__h48707, + result__h48734, + result__h48761, + result__h48805, + result__h48832, + result__h48859, + result__h48886, + result__h48926, + result__h48953, + result__h49070, + result__h49136, + result__h49202, + result__h49268, + result__h49334, + result__h49400, + result__h49466, + result__h49528, + result__h49573, + result__h49639, + result__h49705, + result__h49763, + result__h49808, + w1___1__h47987, + w2___1__h47988, + x1_avValue_data__h40339, + x1_avValue_data__h44806, + x__h32158, + x__h35068, + x__h37428, + x__h40857, + x__h40868, + x__h42877, + x__h42888, + x__h49985, + x__h90651, + y__h90652, + y__h90653; + wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710; + wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31743, - v__h31780, - w17861_BITS_31_TO_0__q15, - w27862_BITS_31_TO_0__q16, - x_data__h30533; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; - wire [5 : 0] x__h133973, x__h147887; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; - wire [3 : 0] b__h133645, b__h2564; - wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112, - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; - wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, - IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089, - IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458, - IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302, - IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, + v__h31759, + v__h31796, + w17877_BITS_31_TO_0__q15, + w27878_BITS_31_TO_0__q16, + x_data__h30549; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160; + wire [5 : 0] x__h133989, x__h147903; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159; + wire [3 : 0] b__h133661, b__h2564; + wire [2 : 0] n__read_id__h61463, n__read_id__h61548, x__h7925; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112, + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116, + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; + wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, + IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093, + IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462, + IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306, + IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966, + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254, - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004, - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173, - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180, - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011, - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091, - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360, - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956, - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258, + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008, + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177, + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184, + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015, + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095, + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364, + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960, + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373, - NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375, - NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088, - NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512, + NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377, + NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379, + NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092, + NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971, + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_reqBE_BIT_0___h30158, - mmioPlatform_reqBE_BIT_4___h30118, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, + mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30134, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61448, - n__read_child__h61533, - n__read_child__h80065, - n__read_child__h80144, - n__read_snd_id__h123374, - propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, - propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, - x__h61261, - x__h74813, - x__h79884; + n__read_child__h61464, + n__read_child__h61549, + n__read_child__h80081, + n__read_child__h80160, + n__read_snd_id__h123390, + propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132, + propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136, + x__h61277, + x__h74829, + x__h79900; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3534,7 +3536,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 ; + IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3562,7 +3564,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 ; + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3723,8 +3725,9 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3741,7 +3744,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3750,7 +3753,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && + IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3796,7 +3799,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42861 == 64'd0 || + x__h42877 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3814,7 +3817,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3822,14 +3825,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3839,22 +3842,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 ; + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 && - NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 && + NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3936,7 +3939,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3954,7 +3957,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3972,7 +3975,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3982,7 +3985,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -4002,7 +4005,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -4011,7 +4014,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4043,7 +4046,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4116,13 +4119,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133645 == 4'd0 ; + b__h133661 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133645 != 4'd0 && + b__h133661 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4132,7 +4135,8 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4140,22 +4144,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || + (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4180,14 +4184,10 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - core_0$mmioToPlatform_cRq_notEmpty) ; + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty ; + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -4222,20 +4222,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30533 } ; + x_data__h30549 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4249,35 +4249,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31966 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 } } ; + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4291,10 +4291,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101846, + { line_addr__h101862, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101932, + { line_addr__h101948, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4302,28 +4302,29 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4334,7 +4335,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; + IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4347,11 +4348,12 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4362,32 +4364,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4395,29 +4397,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ? + (mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47857 } ; + x__h47873 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49985, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4425,47 +4427,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42877 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42861 != 64'd0 ; + x__h42877 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40841 == 64'd0 ; + x__h40857 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && - x__h61261 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && + x__h61277 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && - x__h79884 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && + x__h79900 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; + { 1'd1, n__read_snd_addr__h123389, n__read_snd_id__h123390 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4579,11 +4581,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133645 - 4'd1 ; + b__h133661 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133645 ; + b__h133661 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4595,10 +4597,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, + IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? + (NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4606,8 +4608,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, - IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 } ; + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, + IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4646,7 +4648,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133954, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4657,13 +4659,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147878, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147777, strb8__h147778, 1'd1 } ; + { data64__h147793, strb8__h147794, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4675,7 +4677,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134656 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4706,10 +4708,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, + IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4723,15 +4725,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101846 : - line_addr__h101932 ; + line_addr__h101862 : + line_addr__h101948 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4802,10 +4804,11 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4818,11 +4821,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 && + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4831,12 +4834,10 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4882,17 +4883,15 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && - core_0$mmioToPlatform_cRq_notEmpty || + mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; + mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34961 : + newData__h34977 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4901,7 +4900,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32047 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4911,9 +4910,10 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4983,7 +4983,8 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - MUX_mmioPlatform_curReq$write_1__SEL_1 || + WILL_FIRE_RL_mmioPlatform_selectReq && + NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -5047,7 +5048,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5055,15 +5056,16 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5149,28 +5151,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, + { IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 } ; + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, + { IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 } ; + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5183,36 +5185,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 ; + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 ; + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5321,7 +5323,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131939, llc$dma_respLd_first[3] } ; + { ld_data__h131955, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5342,13 +5344,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || + mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || + (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5359,15 +5361,16 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; + NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5424,7 +5427,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5433,7 +5436,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5465,17 +5468,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; + { IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134640, + { new_cline__h134656, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5551,7 +5554,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93782, 3'd1 } ; + { 4'd0, dword__h93798, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5602,7 +5605,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5632,11 +5635,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5854,86 +5857,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(x__h37412), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h32142)); + .amoExec_current_data(x__h37428), + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h32158)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37264), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h35052)); + .amoExec_current_data(mmioPlatform_mtime__h37280), + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h35068)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h40852)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42667), + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h40868)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30118 && - mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30134 && + mmioPlatform_reqBE_BIT_0___h30174, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48453), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && - !mmioPlatform_reqBE_BIT_0___h30158), - .amoExec(x__h42872)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = + .amoExec_in_data(mmioPlatform_reqData__h48469), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && + !mmioPlatform_reqBE_BIT_0___h30174), + .amoExec(x__h42888)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40323 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + x1_avValue_data__h40339 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = - newData__h32031 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = - NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? + assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = + newData__h32047 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093 = + NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 : + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358 = - NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ? + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362 = + NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 : + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 = - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; - assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; + assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5941,116 +5944,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 = - NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? + assign IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 = + NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 = - NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? + assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 = + NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 = + assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, - x__h74813 } ; - assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, + x__h74829 } ; + assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, - IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, + IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89473 : + new_dword__h89489 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872 = + assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = + assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -6063,23 +6066,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -6092,23 +6095,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701 = + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6121,49 +6124,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 = - { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706, + assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 = + { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = + IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; - assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = + IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42861 == 64'd0 : - x__h40841 == 64'd0, + x__h42877 == 64'd0 : + x__h40857 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44790 } ; + x1_avValue_data__h44806 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = + assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6171,99 +6174,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 = + assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 = + assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 = + assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 = + assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 = + assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 = + assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 = + assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 = + assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112 = + assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122 = + assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 = + assign IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 = + assign IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 = + assign IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 = + assign IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 = + assign NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 || - IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089) ; - assign NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 || + IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093) ; + assign NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6274,7 +6277,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6285,7 +6288,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6297,7 +6300,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6309,7 +6312,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6319,7 +6322,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 = + assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6339,29 +6342,35 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = + assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = + !mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && + mmioPlatform_mtimecmp_0 != 64'd0 || + core_0$mmioToPlatform_cRq_notEmpty ; + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && + !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = + assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -6375,51 +6384,51 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 = + assign NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375 = + assign NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 = + assign NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 = + assign NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = - { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = - { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, - x__h82300 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = - { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = - { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, - x__h61575, - x__h61582 } ; - assign b__h133645 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 = + { CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 = + { CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, + x__h82316 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399 = + { CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 = + { CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, + x__h61591, + x__h61598 } ; + assign b__h133661 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6427,23 +6436,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31950 = + assign data__h31966 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31743, 32'd0 } ; - assign failed_testnum__h162423 = + { v__h31759, 32'd0 } ; + assign failed_testnum__h162439 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101846 = + assign line_addr__h101862 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101932 = + assign line_addr__h101948 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = - line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = - line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89469 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 = + line_addr__h101948 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 = + line_addr__h101862 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89485 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6468,14 +6477,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133938 = - { llc$to_mem_toM_first[68:11], x__h133973 } ; - assign mem_req_wr_addr_awaddr__h147862 = - { llc$to_mem_toM_first[639:582], x__h147887 } ; + assign mem_req_rd_addr_araddr__h133954 = + { llc$to_mem_toM_first[68:11], x__h133989 } ; + assign mem_req_wr_addr_awaddr__h147878 = + { llc$to_mem_toM_first[639:582], x__h147903 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = + assign mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42651 = + assign mmioPlatform_fromHostQ_data_0__h42667 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6486,36 +6495,41 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = - mmioPlatform_mtimecmp_0 <= newData__h34961 ; + assign mmioPlatform_mtime__h37280 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = + mmioPlatform_mtimecmp_0 <= newData__h34977 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = + assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + mmioPlatform_mtimecmp_0 == 64'd0) && + core_0$mmioToPlatform_cRq_notEmpty ; + assign mmioPlatform_reqBE_BIT_0___h30174 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30134 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48469 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || + (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = + assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6529,235 +6543,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61443 = + assign n__read_addr__h61459 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61528 = + assign n__read_addr__h61544 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80062 = + assign n__read_addr__h80078 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 : 64'd0 ; - assign n__read_addr__h80141 = + assign n__read_addr__h80157 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 : 64'd0 ; - assign n__read_child__h61448 = + assign n__read_child__h61464 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61533 = + assign n__read_child__h61549 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80065 = + assign n__read_child__h80081 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; - assign n__read_child__h80144 = + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 ; + assign n__read_child__h80160 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; - assign n__read_id__h61447 = + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 ; + assign n__read_id__h61463 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61532 = + assign n__read_id__h61548 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123373 = + assign n__read_snd_addr__h123389 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123374 = + assign n__read_snd_id__h123390 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32031 = + assign newData__h32047 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32142 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; - assign newData__h34961 = + x__h32158 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; + assign newData__h34977 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35052 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; - assign new_cline__h134640 = + x__h35068 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; + assign new_cline__h134656 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89473 = x__h90635 | y__h90636 ; - assign op_result__h48469 = - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; - assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; - assign op_result__h49004 = w1__h47866 & w2__h47868 ; - assign op_result__h49009 = w1__h47866 | w2__h47868 ; - assign op_result__h49014 = - (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; - assign op_result__h49020 = - (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; - assign op_result__h49027 = - ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ + assign new_dword__h89489 = x__h90651 | y__h90652 ; + assign op_result__h48485 = + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 + + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ; + assign op_result__h49015 = w1__h47882 ^ w2__h47884 ; + assign op_result__h49020 = w1__h47882 & w2__h47884 ; + assign op_result__h49025 = w1__h47882 | w2__h47884 ; + assign op_result__h49030 = + (w1__h47882 < w2__h47884) ? w1__h47882 : w2__h47884 ; + assign op_result__h49036 = + (w1__h47882 <= w2__h47884) ? w2__h47884 : w1__h47882 ; + assign op_result__h49043 = + ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ + (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ 64'h8000000000000000)) ? - w1__h47866 : - w2__h47868 ; - assign op_result__h49033 = - ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ + w1__h47882 : + w2__h47884 ; + assign op_result__h49049 = + ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ + (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ 64'h8000000000000000)) ? - w2__h47868 : - w1__h47866 ; - assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = + w2__h47884 : + w1__h47882 ; + assign propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132 = + assign propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47912 = + assign result__h47928 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; - assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48556 = + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0] } ; + assign result__h48052 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48080 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48108 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48136 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48164 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48192 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48220 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48248 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48293 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48321 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48349 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48377 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48418 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48446 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48572 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48583 = + assign result__h48599 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48610 = + assign result__h48626 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48637 = + assign result__h48653 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48664 = + assign result__h48680 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48691 = + assign result__h48707 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48718 = + assign result__h48734 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48745 = + assign result__h48761 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48789 = + assign result__h48805 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48816 = + assign result__h48832 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48843 = + assign result__h48859 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48870 = + assign result__h48886 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48910 = + assign result__h48926 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48937 = + assign result__h48953 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49054 = + assign result__h49070 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49120 = + assign result__h49136 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49186 = + assign result__h49202 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49252 = + assign result__h49268 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49318 = + assign result__h49334 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49384 = + assign result__h49400 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49450 = - { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], + assign result__h49466 = + { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49512 = + assign result__h49528 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; - assign result__h49557 = + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0] } ; + assign result__h49573 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49623 = + assign result__h49639 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49689 = - { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], + assign result__h49705 = + { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49747 = + assign result__h49763 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; - assign result__h49792 = - { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0] } ; + assign result__h49808 = + { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; - assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; - assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; - assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; - assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; - assign x1_avValue_data__h40323 = + assign v__h31759 = mmioPlatform_waitUpperMSIPCRs ? v__h31796 : 32'd0 ; + assign v__h31796 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17877_BITS_31_TO_0__q15 = w1__h47877[31:0] ; + assign w1___1__h47987 = { 32'd0, w1__h47877[31:0] } ; + assign w27878_BITS_31_TO_0__q16 = w2__h47878[31:0] ; + assign w2___1__h47988 = { 32'd0, w2__h47878[31:0] } ; + assign x1_avValue_data__h40339 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44790 = + assign x1_avValue_data__h44806 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37412 = mmioPlatform_mtimecmp_0 ; - assign x__h40841 = + assign x__h133989 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147903 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37428 = mmioPlatform_mtimecmp_0 ; + assign x__h40857 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40852 : - IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; - assign x__h42861 = + x__h40868 : + IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 ; + assign x__h42877 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42872 : + x__h42888 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6766,29 +6780,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61261 = - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? + assign x__h49985 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61277 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; - assign x__h74813 = + NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ; + assign x__h74829 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; + IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 ; assign x__h7925 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79884 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? + assign x__h79900 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; - assign x__h90635 = old_dword__h89472 & y__h90637 ; - assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90636 = + NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ; + assign x__h90651 = old_dword__h89488 & y__h90653 ; + assign x_data__h30549 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90652 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89469 ; - assign y__h90637 = + mask__h89485 ; + assign y__h90653 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7001,473 +7015,473 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[511:448]; + endcase + end + always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) + begin + case (llc_axi4_adapter_rg_wr_req_beat) + 3'd0: data64__h147793 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147793 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147793 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147793 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147793 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147793 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147793 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147793 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131955 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131955 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131955 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131955 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131955 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131955 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131955 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131955 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; - endcase - end - always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) - begin - case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147794 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147794 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147794 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147794 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147794 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147794 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147794 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147794 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48036 or - result__h48064 or - result__h48092 or - result__h48120 or - result__h48148 or - result__h48176 or result__h48204 or result__h48232) + result__h48052 or + result__h48080 or + result__h48108 or + result__h48136 or + result__h48164 or + result__h48192 or result__h48220 or result__h48248) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48036; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48052; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48064; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48080; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48092; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48108; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48120; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48136; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48148; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48164; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48176; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48192; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48204; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48220; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = - result__h48232; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = + result__h48248; endcase end always@(mmioPlatform_curReq or - result__h48277 or - result__h48305 or result__h48333 or result__h48361) + result__h48293 or + result__h48321 or result__h48349 or result__h48377) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48277; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48293; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48305; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48321; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48333; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48349; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = - result__h48361; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + result__h48377; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48402 or result__h48430) + always@(mmioPlatform_curReq or result__h48418 or result__h48446) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48402; + result__h48418; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48430; + result__h48446; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47862 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; + w2__h47878 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; 2'b01: - w2__h47862 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; + w2__h47878 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; 2'b10: - w2__h47862 = + w2__h47878 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47862 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + w2__h47878 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w2___1__h47972 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or + w2___1__h47988 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47868 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; + w2__h47884 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; 2'b01: - w2__h47868 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; - 2'b10: w2__h47868 = w2___1__h47972; + w2__h47884 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; + 2'b10: w2__h47884 = w2___1__h47988; 2'b11: - w2__h47868 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + w2__h47884 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_curReq or - result__h48789 or - result__h48816 or result__h48843 or result__h48870) + result__h48572 or + result__h48599 or + result__h48626 or + result__h48653 or + result__h48680 or + result__h48707 or result__h48734 or result__h48761) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48789; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48572; + 3'h1: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48599; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48816; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48626; + 3'h3: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48653; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48843; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48680; + 3'h5: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48707; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = - result__h48870; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48734; + 3'h7: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = + result__h48761; + endcase + end + always@(mmioPlatform_curReq or + result__h48805 or + result__h48832 or result__h48859 or result__h48886) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48805; + 3'h2: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48832; + 3'h4: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48859; + 3'h6: + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + result__h48886; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h48556 or - result__h48583 or - result__h48610 or - result__h48637 or - result__h48664 or - result__h48691 or result__h48718 or result__h48745) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48556; - 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48583; - 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48610; - 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48637; - 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48664; - 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48691; - 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48718; - 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = - result__h48745; - endcase - end - always@(mmioPlatform_curReq or result__h48910 or result__h48937) + always@(mmioPlatform_curReq or result__h48926 or result__h48953) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48910; + result__h48926; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48937; + result__h48953; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47861 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; + w1__h47877 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; 2'b01: - w1__h47861 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; + w1__h47877 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; 2'b10: - w1__h47861 = + w1__h47877 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47861 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; + w1__h47877 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w1___1__h47971 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or + w1___1__h47987 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47866 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; + w1__h47882 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; 2'b01: - w1__h47866 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; - 2'b10: w1__h47866 = w1___1__h47971; + w1__h47882 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; + 2'b10: w1__h47882 = w1___1__h47987; 2'b11: - w1__h47866 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; + w1__h47882 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or - w17861_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or + w17877_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; 2'b01: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; 2'b10: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - { {32{w17861_BITS_31_TO_0__q15[31]}}, - w17861_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + { {32{w17877_BITS_31_TO_0__q15[31]}}, + w17877_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or - w27862_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or + w27878_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; 2'b01: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; 2'b10: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - { {32{w27862_BITS_31_TO_0__q16[31]}}, - w27862_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + { {32{w27878_BITS_31_TO_0__q16[31]}}, + w27878_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49033 or - w2__h47868 or - op_result__h48469 or - op_result__h48999 or - op_result__h49004 or - op_result__h49009 or - op_result__h49027 or op_result__h49014 or op_result__h49020) + op_result__h49049 or + w2__h47884 or + op_result__h48485 or + op_result__h49015 or + op_result__h49020 or + op_result__h49025 or + op_result__h49043 or op_result__h49030 or op_result__h49036) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - w2__h47868; + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + w2__h47884; 4'd1: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48469; + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h48485; 4'd2: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h48999; + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49015; 4'd3: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49004; - 4'd4: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49009; - 4'd5: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49027; - 4'd7: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49014; - 4'd8: - IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = op_result__h49020; - default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = - op_result__h49033; + 4'd4: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49025; + 4'd5: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49043; + 4'd7: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49030; + 4'd8: + IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49036; + default: IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = + op_result__h49049; endcase end always@(mmioPlatform_curReq or - result__h49512 or - result__h49557 or result__h49623 or result__h49689) + result__h49528 or + result__h49573 or result__h49639 or result__h49705) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49512; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49528; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49557; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49573; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49623; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49639; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = - result__h49689; - default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + result__h49705; + default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47912 or - result__h49054 or - result__h49120 or - result__h49186 or - result__h49252 or - result__h49318 or result__h49384 or result__h49450) + result__h47928 or + result__h49070 or + result__h49136 or + result__h49202 or + result__h49268 or + result__h49334 or result__h49400 or result__h49466) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h47912; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h47928; 3'h1: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49054; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49070; 3'h2: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49120; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49136; 3'h3: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49186; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49202; 3'h4: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49252; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49268; 3'h5: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49318; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49334; 3'h6: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49384; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49400; 3'h7: - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = - result__h49450; + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = + result__h49466; endcase end - always@(mmioPlatform_curReq or result__h49747 or result__h49792) + always@(mmioPlatform_curReq or result__h49763 or result__h49808) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49747; + result__h49763; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49792; + result__h49808; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 or + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) begin case (mmioPlatform_reqSz) 2'b0: - x__h47857 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; + x__h47873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939; 2'b01: - x__h47857 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; + x__h47873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948; 2'b10: - x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47873 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47857 = - IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; + x__h47873 = + IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = + IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7475,15 +7489,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7491,11 +7505,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; + IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7503,315 +7517,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 or + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011) + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004; + IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = + SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011; + IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 or + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180) + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173; + IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; + IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184; endcase end - always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) + always@(x__h61277 or n__read_id__h61463 or n__read_id__h61548) begin - case (x__h61261) - 1'd0: x__h61575 = n__read_id__h61447; - 1'd1: x__h61575 = n__read_id__h61532; + case (x__h61277) + 1'd0: x__h61591 = n__read_id__h61463; + 1'd1: x__h61591 = n__read_id__h61548; endcase end - always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) + always@(x__h61277 or n__read_child__h61464 or n__read_child__h61549) begin - case (x__h61261) - 1'd0: x__h61582 = n__read_child__h61448; - 1'd1: x__h61582 = n__read_child__h61533; + case (x__h61277) + 1'd0: x__h61598 = n__read_child__h61464; + 1'd1: x__h61598 = n__read_child__h61549; endcase end - always@(x__h61261 or - propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or - propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) + always@(x__h61277 or + propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 or + propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = - propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; + CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = + propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132; 1'd1: - CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = - propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; + CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = + propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136; endcase end - always@(x__h61261 or - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) + always@(x__h61277 or + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 or + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116; endcase end - always@(x__h61261 or - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) + always@(x__h61277 or + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 or + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122; 1'd1: - CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; + CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; endcase end - always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) + always@(x__h61277 or n__read_addr__h61459 or n__read_addr__h61544) begin - case (x__h61261) + case (x__h61277) 1'd0: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61443; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = + n__read_addr__h61459; 1'd1: - CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = - n__read_addr__h61528; + CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = + n__read_addr__h61544; endcase end - always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) - begin - case (x__h79884) - 1'd0: x__h82300 = n__read_child__h80065; - 1'd1: x__h82300 = n__read_child__h80144; - endcase - end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79884 or + always@(x__h79900 or n__read_child__h80081 or n__read_child__h80160) + begin + case (x__h79900) + 1'd0: x__h82316 = n__read_child__h80081; + 1'd1: x__h82316 = n__read_child__h80160; + endcase + end + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79884 or + always@(x__h79900 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79884 or + always@(x__h79900 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : + IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 : 2'd0; 1'd1: - CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : + IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 : 2'd0; endcase end - always@(x__h79884 or - NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or - NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) + always@(x__h79900 or + NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 or + NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; + CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377; 1'd1: - CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; + CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379; endcase end - always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) + always@(x__h79900 or n__read_addr__h80078 or n__read_addr__h80157) begin - case (x__h79884) + case (x__h79900) 1'd0: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80062; + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = + n__read_addr__h80078; 1'd1: - CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = - n__read_addr__h80141; + CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = + n__read_addr__h80157; endcase end @@ -8227,14 +8241,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162844 = $stime; + v__h162860 = $stime; #0; end - v__h162838 = v__h162844 / 32'd10; + v__h162854 = v__h162860 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162838, + v__h162854, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8244,14 +8258,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162380 = $stime; + v__h162396 = $stime; #0; end - v__h162374 = v__h162380 / 32'd10; + v__h162390 = v__h162396 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162374, + v__h162390, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8261,7 +8275,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162423); + $display("FAIL %0d", failed_testnum__h162439); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9826,85 +9840,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) begin - v__h134337 = $stime; + v__h134353 = $stime; #0; end - v__h134331 = v__h134337 / 32'd10; + v__h134347 = v__h134353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134331, + v__h134347, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134504 = $stime; + v__h134520 = $stime; #0; end - v__h134498 = v__h134504 / 32'd10; + v__h134514 = v__h134520 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134498); + v__h134514); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9966,135 +9980,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136607 = $stime; + v__h136623 = $stime; #0; end - v__h136601 = v__h136607 / 32'd10; + v__h136617 = v__h136623 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136601); + v__h136617); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11292,169 +11306,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153951 = $stime; + v__h153967 = $stime; #0; end - v__h153945 = v__h153951 / 32'd10; + v__h153961 = v__h153967 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153945); + $display("%0d: ERROR: CreditCounter: overflow", v__h153961); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_wr_addr_awaddr__h147862); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", mem_req_wr_addr_awaddr__h147878); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", data64__h147777); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", data64__h147793); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", strb8__h147778); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", strb8__h147794); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133718 = $stime; + v__h133734 = $stime; #0; end - v__h133712 = v__h133718 / 32'd10; + v__h133728 = v__h133734 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133712, + v__h133728, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11525,159 +11539,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) - $write("'h%h", mem_req_rd_addr_araddr__h133938); + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + $write("'h%h", mem_req_rd_addr_araddr__h133954); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) begin - v__h160645 = $stime; + v__h160661 = $stime; #0; end - v__h160639 = v__h160645 / 32'd10; + v__h160655 = v__h160661 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160639, + v__h160655, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161153 = $stime; + v__h161169 = $stime; #0; end - v__h161147 = v__h161153 / 32'd10; + v__h161163 = v__h161169 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161147); + v__h161163); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)