diff --git a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile b/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile index 08f784a..57ffcbf 100644 --- a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile +++ b/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile @@ -12,8 +12,10 @@ CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$ RVFI_DII_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII +CHERI_DIRS = $(RISCY_HOME)/../CHERI:$(RISCY_HOME)/../../libs/cheri-cap-lib + # ALL_RISCY_DIRS = $(RISCY_DIRS) -ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(RVFI_DII_DIRS) +ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(RVFI_DII_DIRS):$(CHERI_DIRS) # ================================================================ @@ -24,6 +26,7 @@ ARCH ?= RV64ACDFIMSU # RISC-V config macros passed into Bluespec 'bsc' compiler BSC_COMPILATION_FLAGS += \ + -D RISCV \ -D RV64 \ -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ -D SV39 \ diff --git a/src_Core/CHERI/ScrFile.bsv b/src_Core/CHERI/ScrFile.bsv index b28356e..d10f599 100644 --- a/src_Core/CHERI/ScrFile.bsv +++ b/src_Core/CHERI/ScrFile.bsv @@ -34,45 +34,40 @@ import Types::*; import ProcTypes::*; import DefaultValue::*; -import ConcatReg::*; import ConfigReg::*; import Ehr::*; -import Fifo::*; -import Vector::*; -import FIFO::*; import GetPut::*; -import BuildVector::*; -import CHERICap :: *; -import CHERICC_Fat :: *; -import ISA_Decls_CHERI :: *; +import CHERICap::*; +import CHERICC_Fat::*; +import ISA_Decls_CHERI::*; // ================================================================ // BSV additional libs -import Cur_Cycle :: *; +import Cur_Cycle::*; // ================================================================ // Project imports from Toooba -import SoC_Map :: *; +import SoC_Map::*; // ================================================================ // Information returned on traps and mret/sret/uret typedef struct { Addr new_pc; - } Trap_Updates + } Scr_Trap_Updates deriving (Bits, FShow); typedef struct { Addr new_pc; - } RET_Updates + } Scr_RET_Updates deriving (Bits, FShow); typedef struct { Addr top; Addr base; - Perms perms; + HardPerms perms; } ScrVMInfo deriving (Bits, FShow); @@ -83,19 +78,19 @@ deriving (Bits, FShow); // ================================================================ -interface CsrFile; +interface ScrFile; // Read method CapReg rd(SCR csr); // normal write by CSRXXX inst to any CSR - method Action csrInstWr(SCR csr, CapReg x); + method Action scrInstWr(SCR csr, CapReg x); // The WARL transform performed during CSRRx writes to a CSR method CapReg warl_xform (SCR csr, CapReg x); // Methods for handling traps - method ActionValue#(Trap_Updates) trap(Trap t, Addr pc, Addr faultAddr, Bit #(32) orig_inst); - method ActionValue#(RET_Updates) sret; - method ActionValue#(RET_Updates) mret; + method ActionValue#(Scr_Trap_Updates) trap(Trap t, Addr pc, Addr faultAddr, Bit #(32) orig_inst); + method ActionValue#(Scr_RET_Updates) sret; + method ActionValue#(Scr_RET_Updates) mret; // Outputs for CSRs that the rest of the processor needs to know about method ScrVMInfo vmI; @@ -132,7 +127,7 @@ module mkConfigEhr#(t init)(Ehr#(n, t)) provisos(Bits#(t, w)); return ifc; endmodule -module mkCsrFile #(Data hartid)(CsrFile); +module mkScrFile (ScrFile); RiscVISASubset isa = defaultValue; // To save from bypassing logic, CSR reads will get stale value @@ -145,25 +140,25 @@ module mkCsrFile #(Data hartid)(CsrFile); // User level SCRs with accessSysRegs Reg#(CapReg) utcc_reg <- mkCsrReg(defaultValue); - Reg#(CapReg) utdc_reg <- mkCsrReg(null_cap); - Reg#(CapReg) uScratchC_reg <- mkCsrReg(null_cap); + Reg#(CapReg) utdc_reg <- mkCsrReg(nullCap); + Reg#(CapReg) uScratchC_reg <- mkCsrReg(nullCap); Reg#(CapReg) uepcc_reg <- mkCsrReg(defaultValue); // System level SCRs with accessSysRegs Reg#(CapReg) stcc_reg <- mkCsrReg(defaultValue); - Reg#(CapReg) stdc_reg <- mkCsrReg(null_cap); - Reg#(CapReg) sScratchC_reg <- mkCsrReg(null_cap); + Reg#(CapReg) stdc_reg <- mkCsrReg(nullCap); + Reg#(CapReg) sScratchC_reg <- mkCsrReg(nullCap); Reg#(CapReg) sepcc_reg <- mkCsrReg(defaultValue); // Machine level SCRs with accessSysRegs Reg#(CapReg) mtcc_reg <- mkCsrReg(defaultValue); - Reg#(CapReg) mtdc_reg <- mkCsrReg(null_cap); - Reg#(CapReg) mScratchC_reg <- mkCsrReg(null_cap); + Reg#(CapReg) mtdc_reg <- mkCsrReg(nullCap); + Reg#(CapReg) mScratchC_reg <- mkCsrReg(nullCap); Reg#(CapReg) mepcc_reg <- mkCsrReg(defaultValue); // Function for getting a csr given an index - function Reg#(Data) get_csr(CSR csr); - return (case (csr) + function Reg#(CapReg) get_scr(SCR scr); + return (case (scr) // User SCRs SCR_PCC: pcc_reg; SCR_DDC: ddc_reg; @@ -188,41 +183,44 @@ module mkCsrFile #(Data hartid)(CsrFile); // ================================================================ // INTERFACE - method Data rd(CSR csr); - return get_csr(csr)._read; + method CapReg rd(SCR scr); + return get_scr(scr)._read; endmethod - method Action csrInstWr(CSR csr, Data x); - get_csr(csr)._write(x); + method Action scrInstWr(SCR csr, CapReg x); + get_scr(csr)._write(x); endmethod - method ActionValue#(Trap_Updates) trap(Trap t, Addr pc, Addr addr, Bit #(32) orig_inst); - + method ActionValue#(Scr_Trap_Updates) trap(Trap t, Addr pc, Addr addr, Bit #(32) orig_inst); + return ?; endmethod - method ActionValue#(RET_Updates) mret; - + method ActionValue#(Scr_RET_Updates) mret; + return ?; endmethod - method ActionValue#(RET_Updates) sret; - + method ActionValue#(Scr_RET_Updates) sret; + return ?; endmethod - method VMInfo vmI; - return VMInfo { - top: getTop(pcc_reg), - base: getBase(pcc_reg), + method ScrVMInfo vmI; + return ScrVMInfo { + top: truncate(getTop(pcc_reg)), + base: truncate(getBase(pcc_reg)), perms: getHardPerms(pcc_reg) }; endmethod - method VMInfo vmD; + method ScrVMInfo vmD; // for load/store, need to consider MPRV - return VMInfo { - top: getTop(pcc_reg), - base: getBase(pcc_reg), + return ScrVMInfo { + top: truncate(getTop(pcc_reg)), + base: truncate(getBase(pcc_reg)), perms: getHardPerms(pcc_reg) }; endmethod + method ScrDecodeInfo decodeInfo = + ScrDecodeInfo{cap_mode: getFlags(pcc_reg)==1'b1}; + endmodule diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 3f23186..df5a971 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -1,7 +1,7 @@ // Copyright (c) 2017 Massachusetts Institute of Technology // Portions Copyright (c) 2019-2020 Bluespec, Inc. -// +// // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without @@ -9,10 +9,10 @@ // modify, merge, publish, distribute, sublicense, and/or sell copies // of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: -// +// // The above copyright notice and this permission notice shall be // included in all copies or substantial portions of the Software. -// +// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND @@ -86,6 +86,7 @@ import Toooba_RVFI_DII_Bridge::*; `endif import CsrFile :: *; +import ScrFile :: *; // ================================================================ // Toooba @@ -161,7 +162,7 @@ interface Core; // Bluespec: external interrupt requests targeting Machine and Supervisor modes method Action setMEIP (Bit #(1) v); method Action setSEIP (Bit #(1) v); - + `ifdef RVFI_DII interface Toooba_RVFI_DII_Server rvfi_dii_server; `endif @@ -235,7 +236,7 @@ module mkCore#(CoreId coreId)(Core); FetchStage fetchStage <- mkFetchStage; ITlb iTlb = fetchStage.iTlbIfc; ICoCache iMem = fetchStage.iMemIfc; - + // ================================================================ // If using Direct Instruction Injection then make a // bridge that can insert instructions. @@ -250,8 +251,10 @@ module mkCore#(CoreId coreId)(Core); // back end RFileSynth rf <- mkRFileSynth; - // Bluespec: CsrFile including external interrupt request methods + // Bluespec: CsrFile including external interrupt request methods CsrFile csrf <- mkCsrFile(zeroExtend(coreId)); // hartid in CSRF should be core id + // Special Capability register file + ScrFile scaprf <- mkScrFile(); RegRenamingTable regRenamingTable <- mkRegRenamingTable; EpochManager epochManager <- mkEpochManager; @@ -305,7 +308,7 @@ module mkCore#(CoreId coreId)(Core); ); // whether perf data is collected - Reg#(Bool) doStatsReg <- mkConfigReg(False); + Reg#(Bool) doStatsReg <- mkConfigReg(False); // write aggressive elements + wakupe reservation stations function Action writeAggr(Integer wrAggrPort, PhyRIndx dst); @@ -353,6 +356,7 @@ module mkCore#(CoreId coreId)(Core); method rf_rd1 = rf.read[aluRdPort(i)].rd1; method rf_rd2 = rf.read[aluRdPort(i)].rd2; method csrf_rd = csrf.rd; + method scaprf_rd = scaprf.rd; method rob_getPC = rob.getOrigPC[i].get; method rob_getPredPC = rob.getOrigPredPC[i].get; method rob_getOrig_Inst = rob.getOrig_Inst[i].get; @@ -396,6 +400,7 @@ module mkCore#(CoreId coreId)(Core); method rf_rd2 = rf.read[fpuMulDivRdPort(i)].rd2; method rf_rd3 = rf.read[fpuMulDivRdPort(i)].rd3; method csrf_rd = csrf.rd; + method scaprf_rd = scaprf.rd; method rob_setExecuted = rob.setExecuted_doFinishFpuMulDiv[i].set; method Action writeRegFile(PhyRIndx dst, Data data); writeAggr(fpuMulDivWrAggrPort(i), dst); @@ -412,6 +417,7 @@ module mkCore#(CoreId coreId)(Core); method rf_rd1 = rf.read[memRdPort].rd1; method rf_rd2 = rf.read[memRdPort].rd2; method csrf_rd = csrf.rd; + method scaprf_rd = scaprf.rd; method rob_getPC = rob.getOrigPC[valueof(AluExeNum)].get; // last getPC port method rob_setExecuted_doFinishMem = rob.setExecuted_doFinishMem; `ifdef INCLUDE_TANDEM_VERIF @@ -540,6 +546,7 @@ module mkCore#(CoreId coreId)(Core); interface sbConsIfc = sbCons; interface sbAggrIfc = sbAggr; interface csrfIfc = csrf; + interface scaprfIfc = scaprf; interface emIfc = epochManager; interface smIfc = specTagManager; interface rsAluIfc = reservationStationAlu; @@ -567,6 +574,7 @@ module mkCore#(CoreId coreId)(Core); interface robIfc = rob; interface rtIfc = regRenamingTable; interface csrfIfc = csrf; + interface scaprfIfc = scaprf; method stbEmpty = stb.isEmpty; method stqEmpty = lsq.stqEmpty; method lsqSetAtCommit = lsq.setAtCommit; @@ -1392,7 +1400,7 @@ module mkCore#(CoreId coreId)(Core); interface checkStarted = nullGet; `endif endinterface - + `ifdef RVFI_DII interface Toooba_RVFI_DII_Server rvfi_dii_server = rvfi_bridge.rvfi_dii_server; `endif diff --git a/src_Core/ISA/ISA_Decls_CHERI.bsv b/src_Core/ISA/ISA_Decls_CHERI.bsv index 43918ce..e60129a 100644 --- a/src_Core/ISA/ISA_Decls_CHERI.bsv +++ b/src_Core/ISA/ISA_Decls_CHERI.bsv @@ -25,9 +25,9 @@ * * @BERI_LICENSE_HEADER_END@ */ - - -`ifdef ISA_CHERI +import ISA_Decls::*; +import CHERICap::*; +import CHERICC_Fat::*; typedef TMul#(XLEN, 2) CLEN; @@ -196,13 +196,11 @@ Bit #(3) f3_LQ = 3'h2; Bit #(3) f3_SQ = 3'b100; `ifdef RV64 -Bit #(3) w_SIZE_CAP = w_SIZE_Q; -Bit #(3) w_SIZE_MAX = w_SIZE_Q; +Bit #(3) w_SIZE_CAP = f3_SQ; +Bit #(3) w_SIZE_MAX = f3_SQ; `else //RV32 -Bit #(3) w_SIZE_CAP = w_SIZE_D; -Bit #(3) w_SIZE_MAX = w_SIZE_D; +Bit #(3) w_SIZE_CAP = f3_SD; +Bit #(3) w_SIZE_MAX = f3_SD; `endif Bit #(3) f3_AMO_CAP = w_SIZE_CAP; - -`endif diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 327c324..f02373c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -1,6 +1,6 @@ // Copyright (c) 2017 Massachusetts Institute of Technology -// +// // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without @@ -8,10 +8,10 @@ // modify, merge, publish, distribute, sublicense, and/or sell copies // of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: -// +// // The above copyright notice and this permission notice shall be // included in all copies or substantial portions of the Software. -// +// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND @@ -40,6 +40,9 @@ import ReorderBuffer::*; import SpecFifo::*; import HasSpecBits::*; import Bypass::*; +import CHERICap::*; +import CHERICC_Fat::*; +import ISA_Decls_CHERI::*; import Cur_Cycle :: *; @@ -140,6 +143,8 @@ interface AluExeInput; method Data rf_rd2(PhyRIndx rindx); // CSR file method Data csrf_rd(CSR csr); + // Special Capability Register file. + method CapReg scaprf_rd(SCR csr); // ROB method Addr rob_getPC(InstTag t); method Addr rob_getPredPC(InstTag t); @@ -212,7 +217,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); if(x.regs.dst matches tagged Valid .dst) begin inIfc.setRegReadyAggr(dst.indx); end - + // go to next stage dispToRegQ.enq(ToSpecFifo { data: AluDispatchToRegRead { @@ -378,7 +383,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); if (x.spec_tag matches tagged Valid .valid_spec_tag) begin inIfc.correctSpec(valid_spec_tag); end - // train branch predictor if needed + // train branch predictor if needed // since we can only do 1 training in a cycle, split the rule // XXX not training JAL, reduce chance of conflicts if(x.iType == Jr || x.iType == Br) begin @@ -417,4 +422,3 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); endcase); endmethod endmodule - diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index a9430e3..c5bd413 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -1,7 +1,7 @@ // Copyright (c) 2017 Massachusetts Institute of Technology // Portions Copyright (c) 2019-2020 Bluespec, Inc. -// +// // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without @@ -9,10 +9,10 @@ // modify, merge, publish, distribute, sublicense, and/or sell copies // of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: -// +// // The above copyright notice and this permission notice shall be // included in all copies or substantial portions of the Software. -// +// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND @@ -37,6 +37,7 @@ import ReorderBuffer::*; import ReorderBufferSynth::*; import RenamingTable::*; import CsrFile::*; +import ScrFile::*; import StoreBuffer::*; import VerificationPacket::*; import RenameDebugIF::*; @@ -78,6 +79,7 @@ interface CommitInput; interface ReorderBufferSynth robIfc; interface RegRenamingTable rtIfc; interface CsrFile csrfIfc; + interface ScrFile scaprfIfc; // no stores method Bool stbEmpty; method Bool stqEmpty; @@ -127,7 +129,7 @@ typedef struct { interface CommitStage; // performance - method Data getPerf(ComStagePerfType t); + method Data getPerf(ComStagePerfType t); // deadlock check interface Get#(CommitStuck) commitInstStuck; interface Get#(CommitStuck) commitUserInstStuck; @@ -336,6 +338,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); ReorderBufferSynth rob = inIfc.robIfc; RegRenamingTable regRenamingTable = inIfc.rtIfc; CsrFile csrf = inIfc.csrfIfc; + ScrFile scaprf = inIfc.scaprfIfc; // FIXME FIXME FIXME wires to set atCommit in LSQ: avoid scheduling cycle. // Using wire should be fine, because LSQ does not need to see atCommit @@ -387,7 +390,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); // RVFI trace report. Not an input? FIFO#(Rvfi_Traces) rvfiQ <- mkFIFO; Reg#(Dii_Id) traceCnt <- mkReg(0); - + function TraceStateBundle getTSB(); return TraceStateBundle{ sepc: csrf.rd(CSRsepc), @@ -736,7 +739,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); if (! debugger_halt) begin // trap handling & redirect - let trap_updates <- csrf.trap(trap.trap, trap.pc, trap.addr, trap.orig_inst); + let trap_updates <- csrf.trap(trap.trap, trap.pc, trap.addr, trap.orig_inst); + let cap_trap_updates <- scaprf.trap(trap.trap, trap.pc, trap.addr, trap.orig_inst); inIfc.redirectPc(trap_updates.new_pc `ifdef RVFI_DII , trap.x.diid + 1 @@ -874,17 +878,18 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); Maybe #(RET_Updates) m_ret_updates = no_ret_updates; `endif if(x.iType == Sret) begin - RET_Updates ret_updates <- csrf.sret; + RET_Updates ret_updates <- csrf.sret; next_pc = ret_updates.new_pc; + Scr_RET_Updates scr_ret_updates <- scaprf.sret; `ifdef INCLUDE_TANDEM_VERIF - m_ret_updates = tagged Valid ret_updates; + m_ret_updates = tagged Valid ret_updates; `endif end else if(x.iType == Mret) begin - RET_Updates ret_updates <- csrf.mret; + RET_Updates ret_updates <- csrf.mret; next_pc = ret_updates.new_pc; `ifdef INCLUDE_TANDEM_VERIF - m_ret_updates = tagged Valid ret_updates; + m_ret_updates = tagged Valid ret_updates; `endif end inIfc.redirectPc(next_pc diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv index 3da8829..90ed88d 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv @@ -1,6 +1,6 @@ // Copyright (c) 2017 Massachusetts Institute of Technology -// +// // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without @@ -8,10 +8,10 @@ // modify, merge, publish, distribute, sublicense, and/or sell copies // of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: -// +// // The above copyright notice and this permission notice shall be // included in all copies or substantial portions of the Software. -// +// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND @@ -39,6 +39,9 @@ import SpecFifo::*; import MulDiv::*; import Fpu::*; import Bypass::*; +import CHERICap::*; +import CHERICC_Fat::*; +import ISA_Decls_CHERI::*; typedef struct { // inst info @@ -90,6 +93,8 @@ interface FpuMulDivExeInput; method Data rf_rd3(PhyRIndx rindx); // CSR file method Data csrf_rd(CSR csr); + // Special Capability Register file. + method CapReg scaprf_rd(SCR csr); // ROB method Action rob_setExecuted(InstTag t, Data dst_data, Bit#(5) fflags); @@ -120,7 +125,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); // pipeline fifos let dispToRegQ <- mkFpuMulDivDispToRegFifo; let regToExeQ <- mkFpuMulDivRegToExeFifo; - + // wire to recv bypass Vector#(TMul#(2, AluExeNum), RWire#(Tuple2#(PhyRIndx, Data))) bypassWire <- replicateM(mkRWire); @@ -144,7 +149,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); // FPU MUL DIV never have exception or misprecition, so no spec tag doAssert(!isValid(x.spec_tag), "FpuMulDiv should not carry any spec tag"); - + // go to next stage dispToRegQ.enq(ToSpecFifo { data: FpuMulDivDispatchToRegRead { diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index 02a0cdb..6828987 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -50,6 +50,9 @@ import CCTypes::*; import L1CoCache::*; import Bypass::*; import LatencyTimer::*; +import CHERICap::*; +import CHERICC_Fat::*; +import ISA_Decls_CHERI::*; import Cur_Cycle :: *; @@ -150,6 +153,8 @@ interface MemExeInput; method Data rf_rd2(PhyRIndx rindx); // CSR file method Data csrf_rd(CSR csr); + // Special Capability Register file. + method CapReg scaprf_rd(SCR csr); // ROB method Addr rob_getPC(InstTag t); method Action rob_setExecuted_doFinishMem(InstTag t, diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 0c15ace..8968fa0 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -1,7 +1,7 @@ // Copyright (c) 2017 Massachusetts Institute of Technology // Portions Copyright (c) 2019-2020 Bluespec, Inc. -// +// // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without @@ -9,10 +9,10 @@ // modify, merge, publish, distribute, sublicense, and/or sell copies // of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: -// +// // The above copyright notice and this permission notice shall be // included in all copies or substantial portions of the Software. -// +// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND @@ -41,6 +41,7 @@ import ReorderBufferSynth::*; import Scoreboard::*; import ScoreboardSynth::*; import CsrFile::*; +import ScrFile::*; import SpecTagManager::*; import EpochManager::*; import ReservationStationEhr::*; @@ -64,6 +65,7 @@ interface RenameInput; interface ScoreboardCons sbConsIfc; interface ScoreboardAggr sbAggrIfc; interface CsrFile csrfIfc; + interface ScrFile scaprfIfc; interface EpochManager emIfc; interface SpecTagManager smIfc; interface Vector#(AluExeNum, ReservationStationAlu) rsAluIfc; @@ -107,6 +109,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); ScoreboardCons sbCons = inIfc.sbConsIfc; ScoreboardAggr sbAggr = inIfc.sbAggrIfc; CsrFile csrf = inIfc.csrfIfc; + ScrFile scaprf = inIfc.scaprfIfc; EpochManager epochManager = inIfc.emIfc; SpecTagManager specTagManager = inIfc.smIfc; Vector#(AluExeNum, ReservationStationAlu) reservationStationAlu = inIfc.rsAluIfc; @@ -1059,7 +1062,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); // deq fetch & update epochs match fetchStage.pipelines[i].deq; epochManager.updatePrevEpoch[i].update(main_epoch); - + // Claim a speculation tag if (new_speculation) begin specTagClaimed = True; // mark resource used @@ -1097,7 +1100,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); csr: dInst.csr, claimed_phy_reg: True, // XXX we always claim a free reg in rename trap: Invalid, // no trap - tval: 0, + tval: 0, // default values of FullResult ppc_vaddr_csrData: PPC (ppc), // default use PPC fflags: 0,