diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk
index fa3edb1..9646934 100644
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -48,7 +48,7 @@ RENAME_DEBUG ?= false
 INSTR_PREFETCHER_LOCATION ?= NONE
 INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW
 DATA_PREFETCHER_LOCATION ?= L1
-DATA_PREFETCHER_TYPE ?= STRIDE
+DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT
 
 # clk frequency depends on core size
 ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))
diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
index d2a9c0d..cc1e694 100644
--- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
@@ -774,8 +774,8 @@ endmodule
 
 module mkBRAMMarkovOnHitPrefetcher(Prefetcher) provisos
 (
-    NumAlias#(maxChainLength, 2),
-    NumAlias#(numLastRequests, 16),
+    NumAlias#(maxChainLength, 1),
+    NumAlias#(numLastRequests, 32),
     Alias#(chainLengthT, Bit#(TLog#(TAdd#(maxChainLength,1))))
 );
     Reg#(LineAddr) lastLastChildRequest <- mkReg(0);